JP6996589B2 - Pachinko machine - Google Patents

Description

The present invention relates to a gaming machine.

Pachinko gaming machines, slot machines, and the like are known as a type of gaming machine. These gaming machines include a control element such as a CPU, a read-only storage element such as a ROM, and a read / write storage element such as a RAM. The control element executes the process according to the program read from the read-only storage element while writing the information to the read / write storage element and reading the information from the storage element. In executing this process, information is input from a sensor or the like to the control element, and information is output from the control element to the electric actuator, the light emitting element, or the like (see, for example, Patent Document 1). It is also known that a control element, a read-only storage element, a read / write storage element, and the like are integrated into a single chip.

Japanese Unexamined Patent Publication No. 2009-261415

Here, in a gaming machine such as the above example, there is a demand for a configuration capable of suitably performing control, and there is still room for improvement in this respect.

The present invention has been made in view of the above-exemplified circumstances and the like, and an object of the present invention is to provide a gaming machine capable of suitably performing control.

The invention according to claim 1 in order to solve the above problems includes a storage means for storing an instruction in advance and a storage means.
A control execution means for executing the instruction read from the storage means, and a control execution means.
In a gaming machine equipped with
The control execution means is
A first signal output means for outputting a signal corresponding to the first instruction when the first instruction is executed, and
A second signal output means for outputting a signal corresponding to the second instruction when the second instruction having a different amount of information from the first instruction is executed.
Equipped with
This gaming machine is
A specific output means for outputting a specific signal regardless of whether the signal corresponding to the first command is output or the signal corresponding to the second command is output.
An operating means that, when the specific signal is output, is in a specific operating state at least one of the input and output of information.
Equipped with
A plurality of the operating means are provided, and a plurality of the specific output means are provided corresponding to the plurality of the operating means .

According to the present invention, control can be preferably performed.

It is a perspective view which shows the pachinko machine in 1st Embodiment. It is a perspective view which shows the main structure of a pachinko machine by disassembling. It is a front view which shows the structure of a game board. It is a block diagram which shows the electric structure of a pachinko machine. It is explanatory drawing for demonstrating the contents of various counters used for a winning or failing lottery. It is a flowchart which shows the main process executed by MPU of a main control unit. It is a flowchart which shows the timer interrupt processing executed by the MPU of a main control unit. It is a block diagram for demonstrating the electric structure of the CPU provided in the MPU. (A) is a block diagram of an input latch circuit, and (b) is a block diagram of an output latch circuit. It is explanatory drawing for demonstrating the area where an instruction is stored in ROM. (A) It is an explanatory diagram for explaining an in instruction and an out instruction which is a 2-byte instruction, and (b) is an explanatory diagram for explaining a load instruction which is a 3-byte instruction. It is a block diagram for demonstrating an IO space and a memory space. It is explanatory drawing for demonstrating the memory space. It is a block diagram which shows the electric structure for outputting a chip select signal from a chip select terminal corresponding to an input latch circuit which inputs data from an input port. (A)-(h) It is a time chart which shows a mode that a chip select signal is output from a chip select terminal. It is a flowchart which shows the instruction execution process which is executed in the CPU core. It is a flowchart which shows the process for 3 byte instruction executed in the CPU core. It is explanatory drawing for demonstrating the electric structure of the CPU in 2nd Embodiment. It is a block diagram which shows the output circuit for outputting a chip select signal to an output latch circuit in a CPU, and the input circuit for outputting a chip select signal to an input latch circuit in a CPU. (A) It is a front view of the special figure display part, and (b) is explanatory drawing for explaining an output area. It is explanatory drawing for demonstrating the content of the data set in the output area (a1)-(a8), and the description for demonstrating the light emitting mode of the 1st-eighth light emitting part of (b1)-(b8). It is a figure. It is a flowchart which shows the control process of the special figure display part executed by MPU of a main control device. It is a block diagram which shows the electric structure of the CPU in 3rd Embodiment. FIG. 3 is a block diagram showing an electrical configuration for outputting a chip select signal to a corresponding input latch circuit when reading data from a RAM.

<First Embodiment>
Hereinafter, a first embodiment of a pachinko gaming machine (hereinafter referred to as “pachinko machine”), which is a type of gaming machine, will be described in detail with reference to the drawings. FIG. 1 is a perspective view of the pachinko machine 10, and FIG. 2 is a perspective view showing the main configurations of the pachinko machine 10 in an exploded manner. Note that, in FIG. 2, for convenience, the configuration in the gaming area of the pachinko machine 10 is omitted.

As shown in FIG. 1, the pachinko machine 10 has an outer frame 11 forming an outer shell of the pachinko machine 10 and a gaming machine main body 12 rotatably attached to the outer frame 11 in the forward direction. .. The outer frame 11 is formed by connecting wooden plates on all four sides and has a rectangular frame shape. The pachinko machine 10 is installed in the game hall by attaching and fixing the outer frame 11 to the island equipment. The outer frame 11 is not an indispensable configuration for the pachinko machine 10, and the outer frame 11 may be provided in the island equipment of the game hall.

As shown in FIG. 2, the gaming machine main body 12 includes an inner frame 13, a front door frame 14 arranged in front of the inner frame 13, and a back pack unit 15 arranged behind the inner frame 13. ing. The inner frame 13 of the gaming machine main body 12 is rotatably supported with respect to the outer frame 11. Specifically, the inner frame 13 can rotate forward with the left side as the rotation base end side and the right side as the rotation tip side in front view.

The front door frame 14 is rotatably supported by the inner frame 13, and is rotatable forward with the left side as the rotation base end side and the right side as the rotation tip side in front view. Further, the back pack unit 15 is rotatably supported on the inner frame 13, and is rotatable rearward with the left side as the rotation base end side and the right side as the rotation tip side in front view.

The gaming machine main body 12 is provided with a locking device at the rotating tip portion thereof, and has a function of locking the gaming machine main body 12 with respect to the outer frame 11 so as to be in a locked state. It has a function of locking the door frame 14 to the inner frame 13 so that it cannot be opened. Each of these locked states is released by performing an unlocking operation using the unlocking key on the cylinder lock 17 exposed on the front surface of the pachinko machine 10.

Next, the configuration of the front side of the gaming machine main body 12 will be described.

The inner frame 13 is mainly composed of a resin base 21 having an outer shape substantially the same as that of the outer frame 11. A substantially elliptical window hole 23 is formed in the central portion of the resin base 21. A game board 24 is detachably attached to the resin base 21. The game board 24 is made of plywood, and the game area PA formed on the front surface of the game board 24 is exposed to the front side of the inner frame 13 through the window hole 23 of the resin base 21.

Here, the configuration of the game board 24 will be described with reference to FIG. FIG. 3 is a front view of the game board 24.

An inner rail portion 25 and an outer rail portion 26 are attached to the game board 24 so as to partition a part of the outer edge of the game area PA, and the guiding means is provided by the inner rail portion 25 and the outer rail portion 26. As a guide rail is configured. The game ball launched from the game ball launching mechanism 27 (see FIG. 2) attached below the window hole 23 in the resin base 21 is guided to the upper part of the game area PA by the guide rail.

By the way, the game ball launch mechanism 27 has a launch rail 27a extending toward the guide rail, a ball feeding device 27b for supplying the game ball stored in the precision plate 55a described later on the launch rail 27a, and the launch rail 27a. It is equipped with a solenoid 27c, which is an electric actuator that launches the game ball supplied to the guide rail toward the guide rail. The solenoid 27c is driven and controlled by the rotation operation of the launch operation device (or operation handle) 28 provided on the front door frame 14, and the game ball is launched.

The game board 24 is formed with a plurality of large and small openings penetrating in the front-rear direction. Each opening is provided with a general winning opening 31, a special electric winning device 32, a first operating port 33, a second operating port 34, a through gate 35, a variable display unit 36, a special drawing unit 37, a normal drawing unit 38, and the like. ing.

Even if a ball enters the through gate 35, the game ball is not paid out. On the other hand, when a ball enters the general winning opening 31, the special electric winning device 32, the first operating opening 33, and the second operating opening 34, a predetermined number of game balls are paid out. Specifically, regarding the number of prize balls, when a ball enters the first operating port 33 or a ball enters the second operating port 34, three prize balls are paid out. , When a ball is entered into the general winning opening 31, 10 prize balls are paid out, and when a ball is entered into the special electric winning device 32, 15 prize balls are paid out. Will be executed.

The number of prize balls is arbitrary. For example, the number of prize balls in the second operating port 34 may be smaller than that in the first operating port 33, and the second operating port 34 is the first operating port. The number of prize balls may be larger than 33.

In addition, an out opening 24a is provided at the lowermost portion of the game board 24, and a game ball that has not entered various winning openings or the like is discharged from the game area PA through the out opening 24a. Further, a large number of nails 24b are planted on the game board 24 in order to appropriately disperse and adjust the falling direction of the game ball, and various members such as a windmill are arranged.

Here, the entry ball means that the game ball passes through a predetermined opening, and not only is the ball discharged from the game area PA after passing through the opening, but also from the game area PA after passing through the opening. A mode in which the flow of the game area PA is continued without being discharged is also included. However, in the following description, in order to clearly distinguish the ball from entering the game ball into the out opening 24a, the general winning opening 31, the special electric winning device 32, the first operating port 33, the second operating port 34, and the through gate 35 The entry of a game ball into a game is also referred to as a prize.

The first operating port 33 and the second operating port 34 are unitized as an operating port device and installed on the game board 24. Both the first actuating port 33 and the second actuating port 34 are open upward. Further, both the operating ports 33 and 34 are arranged in the vertical direction so that the first operating port 33 faces upward. The second actuating port 34 is provided with a universal electric accessory 34a as a guide piece made of a pair of left and right movable pieces. In the closed state of the general electric accessory 34a, the game ball cannot win the prize in the second operating port 34, and when the general electric accessory 34a is in the open state, the prize can be won in the second operating port 34.

A through gate 35 is provided on the upstream side of the second operating port 34 in the flow direction of the game ball. The through gate 35 has a through hole (not shown) penetrating in the vertical direction, and the game ball winning the through gate 35 flows down the game area PA after winning. As a result, the game ball that has won the through gate 35 can win the second operating port 34.

Based on the winning of the through gate 35, the universal electric accessory 34a of the second operating port 34 is switched from the closed state to the open state. Specifically, an internal lottery is performed triggered by winning a prize in the through gate 35, and a normal map display of the normal map unit 38 provided in the lower right corner, which is an area where the game ball does not pass in the game area PA. The variable display of the pattern is performed in the part 38a. Then, when the result of the internal lottery is the winning of the electric service opening, the stop result corresponding to the result is displayed, and the variable display of the general map display unit 38a is completed, the state shifts to the general electric opening state. In the open state of the normal electric power, the public electric accessory 34a is in the open state in a predetermined manner.

The cathode ray display unit 38a is composed of a segment display device in which a plurality of segment light emitting units are arranged in a predetermined manner, but the present invention is not limited to this, and the liquid crystal display device and the organic EL display device are not limited thereto. , CRT or other types of display devices such as dot matrix displays. Further, as the pattern to be variablely displayed on the general map display unit 38a, a configuration in which a plurality of types of characters are variablely displayed, a configuration in which a plurality of types of symbols are variablely displayed, a configuration in which a plurality of types of characters are variablely displayed, or a configuration in which a plurality of types of characters are variablely displayed. A configuration in which multiple types of colors are switched and displayed can be considered.

In the normal drawing unit 38, a normal drawing holding display unit 38b is provided at a position adjacent to the normal drawing display unit 38a. The number of game balls that have won a prize in the through gate 35 is reserved up to a maximum of four, and the reserved number is displayed by lighting the normal figure reservation display unit 38b.

A winning lottery is performed with a prize in the first operating port 33 or the second operating port 34 as a trigger. Then, the lottery result is clearly shown through the display effect in the symbol display device 41 of the special figure unit 37 and the variable display unit 36.

More specifically, the special figure unit 37 is provided with a special figure display unit 37a. The display area of the special figure display unit 37a is narrower than the display surface 41a of the symbol display device 41. In the special figure display unit 37a, a winning lottery is performed triggered by a prize in the first operating port 33 or a winning in the second operating port 34, so that a variable display or a predetermined display of the pattern is performed. Then, the result corresponding to the lottery result is displayed. The special figure display unit 37a is composed of a segment display device in which a plurality of segment light emitting units are arranged in a predetermined manner, but the present invention is not limited to this, and the liquid crystal display device and the organic EL display device are not limited thereto. , CRT or other types of display devices such as dot matrix displays. Further, as the pattern displayed on the special figure display unit 37a, a configuration in which a plurality of types of characters are displayed, a configuration in which a plurality of types of symbols are displayed, a configuration in which a plurality of types of characters are displayed, or a configuration in which a plurality of types of colors are displayed. Is displayed.

In the special figure unit 37, a special figure hold display unit 37b is provided at a position adjacent to the special figure display unit 37a. The number of game balls that have won a prize in the first operating port 33 or the second operating port 34 is reserved up to four, and the reserved number is displayed by lighting the special figure reservation display unit 37b.

About the symbol display device 41 In detail, the symbol display device 41 is configured as a liquid crystal display device provided with a liquid crystal display, and the display content is controlled by a display control device described later. The symbol display device 41 is not limited to the liquid crystal display device, and may be another display device having a display screen such as a plasma display device, an organic EL display device, or a CRT, and is a dot matrix display device. You may.

In the symbol display device 41, when the special symbol display unit 37a performs a variable display or a predetermined display of the symbol based on the winning of the first operating port 33 or the winning of the second operating port 34, the symbol is displayed accordingly. A variable display or a predetermined display is performed. For example, on the display surface 41a of the symbol display device 41, three symbol rows of upper, middle, and lower rows are set as a plurality of display areas, and the numbers "1" to "9" are added to each symbol row. The symbols are scrolled and displayed in ascending or descending order. In this scroll display, the scroll display in all the symbol columns is started first, the scroll display is switched to the standby display in the order of the upper symbol column → the lower symbol column → the middle symbol column, and finally the predetermined symbol display is specified in each symbol column. It ends with the symbol still displayed. Then, for example, in a game round in which the game result is a big hit result, a predetermined combination of symbols is stopped and displayed on a preset effective line on the display surface 41a of the symbol display device 41.

In the symbol display device 41, not only the display effect triggered by winning a prize in the first actuating port 33 or the second actuating port 34, but also the display effect in the open / close execution mode that shifts after winning is performed. Will be. Further, based on the winning of any of the operating ports 33 and 34, the display is started on the special figure display unit 37a and the symbol display device 41, and the game times 1 until the predetermined result is displayed and ended. Equivalent to times. Further, the mode of variable display of symbols in the symbol display device 41 is not limited to the above, and is arbitrary, such as the number of symbol rows, the direction of variable display of symbols in the symbol row, the number of symbols in each symbol row, and the like. Can be changed as appropriate. Further, the pattern to be variablely displayed by the symbol display device 41 is not limited to the above-mentioned symbol, and may be configured such that only numbers are variablely displayed as the symbol, for example.

If a big hit is won in the winning lottery based on the winning of the first operating port 33 or the winning of the second operating port 34, the mode shifts to the opening / closing execution mode in which the special electric winning device 32 can be won. The special electric winning device 32 is provided with a large winning opening (not shown) leading to the back side of the game board 24, and is provided with an opening / closing door 32a for opening and closing the large winning opening. The opening / closing door 32a is arranged in either a closed state or an open state. Specifically, the opening / closing door 32a is normally in a closed state in which the game ball cannot win a prize, and is switched to an open state in which the game ball can win a prize when the transition to the open / close execution mode is won in the internal lottery. It has become. By the way, the open / close execution mode is a mode in which the transition is made when a hit result is obtained. It should be noted that although it is not impossible to win a prize in the closed state, it may be configured in a state in which it is more difficult for the prize to occur than in the open state.

As shown in FIG. 2, the front door frame 14 is provided so as to cover the entire front surface side of the inner frame 13 in which the game board 24 having the above configuration is attached to the resin base 21. As shown in FIG. 1, the front door frame 14 is formed with a window portion 51 so that almost the entire area of the game area PA can be visually recognized from the front. The window portion 51 has a substantially elliptical shape, and the window panel 52 is fitted therein. The window panel 52 is colorless and transparently formed by glass, but is not limited to this, and may be colorless and transparent by synthetic resin, and the gaming area PA is formed from the front of the pachinko machine 10 through the window panel 52. It may be colored and transparent as long as it is visible.

A display light emitting unit 53 is provided above the window unit 51. Further, a pair of left and right speaker units 54 for outputting sound effects and the like according to the game state are provided. Further, below the window portion 51, an upper bulging portion 55 bulging toward the front side and a lower bulging portion 56 are vertically arranged side by side. An upper plate 55a opened upward is provided inside the upper bulging portion 55, and a lower plate 56a also opened upward is provided inside the lower bulging portion 56. The upper plate 55a has a function of temporarily storing the game balls paid out from the payout device described later and guiding them to the game ball launching mechanism 27 side while arranging them in a row. Further, the lower plate 56a has a function of storing excess game balls in the upper plate 55a.

Next, the configuration of the back side of the gaming machine main body 12 will be described.

As shown in FIG. 2, a main control device 60 that controls the main control of the game is mounted on the back surface of the inner frame 13 (specifically, the game board 24). The main control device 60 has a main control board housed in a board box. The substrate box may be provided with a trace means for leaving a trace of its opening, or may be provided with a trace structure for leaving a trace of its opening. As the trace means, a plurality of case bodies constituting the substrate box are inseparably bonded, and a bonding portion that requires destruction of a predetermined portion at the time of separation is configured, or an adhesive layer remains on the bonding target at the time of peeling. It is conceivable that a sealing sticker that leaves a trace of what has been done is attached so as to straddle the boundary between a plurality of case bodies. Further, as the trace structure, a configuration in which an adhesive is applied to the boundary between a plurality of case bodies constituting the substrate box can be considered.

The back pack unit 15 is installed so as to cover the back side of the inner frame 13 including the main control device 60. The back pack unit 15 includes a back pack 72 formed of a transparent synthetic resin, and a payout mechanism unit 73 and a control device collective unit 74 are attached to the back pack 72.

The payout mechanism unit 73 includes a tank 75 in which game balls supplied from the island equipment of the game hall are sequentially replenished, and a payout device 76 for paying out the game balls stored in the tank 75. The game ball paid out from the payout device 76 is discharged to the upper plate 55a or the lower plate 56a through the payout passage provided on the downstream side of the payout device 76. The payout mechanism unit 73 is provided with, for example, a back pack board having a power switch for turning on and off the power supply while supplying a main power supply of AC 24 volts.

The control device collective unit 74 generates and outputs predetermined electric power required by the payout control device 77 having a function of controlling the payout device 76 and various control devices, and is accompanied by the operation of the launch operation device 28 by the player. It is equipped with a power supply / launch control device 78 for controlling the launch of a game ball. The payout control device 77 and the power supply / launch control device 78 are arranged so as to be stacked in the front-rear direction so that the payout control device 77 is behind the pachinko machine 10.

<Electrical configuration of pachinko machine 10>
FIG. 4 is a block diagram showing an electrical configuration of the pachinko machine 10.

The main control device 60 includes a main control board 61 that controls the main control of the game, and a power failure monitoring board 65 that monitors the power supply. The MPU 62 is mounted on the main control board 61. The MPU 62 is a ROM 63 that stores various control programs and fixed value data executed by the MPU 62, and a memory for temporarily storing various data and the like when the control program stored in the ROM 63 is executed. A certain RAM 64, an interrupt circuit, a timer circuit, a data input / output circuit, various counter circuits as a random number generator, and the like are built-in. It is not essential that the ROM 63 and the RAM 64 are integrated into one chip with respect to the MPU 62, and each may be individually chipped. This also applies to MPUs of control devices other than the main control device 60.

The MPU 62 is provided with an input port 62a and an output port 62b, respectively. The input port 62a is provided with 24 connection terminals, and the output port 62b is provided with 40 connection terminals. The power failure monitoring board 65 and the payout control device 77 provided in the main control device 60 are connected to the input port 62a of the MPU 62. A power supply / emission control device 78 having a function of supplying operating power is connected to the power failure monitoring board 65, and power is supplied to the MPU 62 via the power failure monitoring board 65.

Further, various sensors such as various winning detection sensors 66a to 66e are connected to the input port 62a of the MPU 62. The various prize detection sensors 66a to 66e are provided on a one-to-one basis with respect to the winning portion corresponding to winning such as the general winning opening 31, the special electric winning device 32, the first operating port 33, the second operating port 34, and the through gate 35. The detection sensor is included, and the MPU 62 determines the winning of each ball entry portion. Further, in the MPU 62, various lottery is executed based on the winning of the first operating port 33, and various lottery is executed based on the winning of the second operating port 34.

A power failure monitoring board 65, a payout control device 77, and a voice emission control device 80 are connected to the output port 62b of the MPU 62. A prize ball command is output to the payout control device 77, for example, based on a winning determination result for the winning ball unit corresponding to the winning. Various commands such as fluctuation commands, type commands, and opening commands are output to the voice emission control device 80. Details of these various commands will be described later. The MPU 62 transmits a command to the voice emission control device 80 by parallel communication.

Further, in the output port 62b of the MPU 62, a drive unit for special electric power 32b for opening and closing the opening / closing door 32a of the special electric winning device 32, and a drive unit for general electric power for opening and closing the general electric accessory 34a of the second operating port 34. 34b, the special drawing unit 37 and the normal drawing unit 38 are connected. Incidentally, the special figure unit 37 is provided with a special figure display unit 37a and a special figure hold display unit 37b, all of which are connected to the output side of the MPU 62. Similarly, the normal map unit 38 is provided with a normal map display unit 38a and a normal map hold display unit 38b, all of which are connected to the output side of the MPU 62. Various driver circuits are provided on the main control board 61, and the MPU 62 executes drive control of various drive units and various display units through the driver circuits.

That is, in the open / close execution mode, the drive control of the special electric drive unit 32b is executed in the MPU 62 so that the special electric winning device 32 is opened / closed. Further, when the open state of the utility accessory 34a is won, the drive control of the drive unit 34b for the utility is executed in the MPU 62 so that the utility accessory 34a is opened and closed. Further, at each game round, the display control of the special figure display unit 37a is executed in the MPU 62. Further, when the lottery result of whether or not to open the general electric accessory 34a is clearly shown, the display control of the general drawing display unit 38a is executed in the MPU 62. Further, when a prize is awarded to the first operating port 33 or the second operating port 34, or when the variable display is started in the special figure display unit 37a, the display control of the special figure hold display unit 37b is executed in the MPU 62. Then, when a prize is won in the through gate 35, or when the variable display is started in the normal figure display unit 38a, the display control of the normal figure hold display unit 38b is executed in the MPU 62.

The power failure monitoring board 65 relays between the main control board 61 and the power supply / emission control device 78, and monitors the DC stable 24 volt voltage, which is the maximum voltage output from the power supply / emission control device 78. The payout control device 77 controls the payout of prize balls and rental balls by the payout device 76 based on the prize ball command received from the main control device 60.

The power supply / launch control device 78 is connected to, for example, a commercial power supply (external power supply) in a game hall or the like. Then, based on the external power supplied from the commercial power source, the operating power required for each of the main control board 61, the payout control device 77, and the like is generated, and the generated operating power is supplied. By the way, the power supply / emission control device 78 is provided with a power supply unit for power failure such as a backup capacitor, and even when the power of the pachinko machine 10 is in the OFF state, the power supply unit for power failure is mainly used. Power for storage retention is supplied to the RAM 64 of the control device 60. Further, the power supply / launch control device 78 is responsible for launch control of the game ball launch mechanism 27, and the game ball launch mechanism 27 is driven when predetermined launch conditions are met.

The voice emission control device 80 drives and controls the display light emission unit 53 and the speaker unit 54 provided on the front door frame 14 based on various commands received from the main control device 60, and also controls the display control device 90. Is. The display control device 90 executes the display control of the symbol display device 41 based on the command received from the voice emission control device 80.

<Electrical configuration for performing various lottery with MPU 62 of the main control device 60>
Next, an electrical configuration for performing various lottery in the MPU 62 of the main control device 60 will be described with reference to FIG.

The MPU 62 uses various counter information during the game to perform a winning lottery, a setting of the display of the special figure display unit 37a, a setting of the symbol display of the symbol display device 41, a setting of the display of the normal figure display unit 38a, and the like. Specifically, as shown in FIG. 5, when the hit random number counter C1 used for the lottery for hit occurrence, the jackpot type counter C2 used for determining the jackpot type, and the symbol display device 41 are displaced and fluctuate. The reach random number counter C3 used for the reach generation lottery, the random number initial value counter CINI used for setting the initial value of the winning random number counter C1, and the variation type for determining the display duration in the special figure display unit 37a and the symbol display device 41. The counter CS is used. Further, it is decided to use the general electric accessory opening counter C4 used for the lottery as to whether or not the general electric accessory 34a of the second operating port 34 is set to the ordinary electric accessory open state. The counters C1 to C3, CINI, CS, and C4 are provided in various counter areas 64b of the RAM 64.

Each of the counters C1 to C3, CINI, CS, and C4 is a loop counter in which 1 is added to the previous value each time the update is made, and the value returns to "0" after reaching the maximum value. Each counter is updated at short intervals. The information corresponding to the hit random number counter C1, the jackpot type counter C2, and the reach random number counter C3 is provided in the RAM 64 as an acquisition information storage means when a prize is won in the first operating port 33 or the second operating port 34. It is stored in the hold storage area 64a.

The hold storage area 64a includes a hold area RE and an execution area AE. The holding area RE includes a first holding area RE1, a second holding area RE2, a third holding area RE3, and a fourth holding area RE4, and is recorded in the winning history of the first operating port 33 or the second operating port 34. At the same time, the combination of the numerical information of the hit random number counter C1, the jackpot type counter C2, and the reach random number counter C3 is stored as the hold information in any of the hold areas RE1 to RE4.

In this case, in the first holding area RE1 to the fourth holding area RE4, when the first operating port 33 or the second operating port 34 is awarded a plurality of times in succession, the first holding area RE1 → the second Each numerical information is stored in the order of the holding area RE2 → the third holding area RE3 → the fourth holding area RE4 in chronological order. By providing the four holding areas RE1 to RE4 in this way, up to four winning histories of the game balls to the first operating port 33 or the second operating port 34 can be reserved and stored. ..

The number that can be stored on hold is not limited to four, and may be any other, such as two, three, or five or more, or may be a single number.

The execution area AE is an area for moving each numerical information stored in the first holding area RE1 of the holding area RE when starting the variable display of the special figure display unit 37a, and is the start of one game. At that time, a hit / fail judgment or the like is performed based on various numerical information stored in the execution area AE.

Each of the above counters will be described in detail.

First, the general electric utility opening counter C4 will be described. The general electric utility opening counter C4 is configured to, for example, add 1 in order within the range of 0 to 250 and return to "0" after reaching the maximum value. The general electric accessory opening counter C4 is periodically updated, and is stored in the general electric holding area 64c of the RAM 64 at the timing when the game ball wins the through gate 35. Then, at a predetermined timing, a lottery is performed as to whether or not to control the utility accessory 34a to the open state by the value of the stored utility accessory opening counter C4.

In the pachinko machine 10, a plurality of types of support modes are set so that the modes of support by the general electric accessory 34a are different from each other. Specifically, in the support mode, when the game ball is continuously launched to the game area PA in the same manner, the general electric accessory 34a of the second operating port 34 is per unit time. A high-frequency support mode and a low-frequency support mode are set so that the frequency of opening is relatively high or low.

In the high-frequency support mode and the low-frequency support mode, the probability of winning the normal-electricity open state in the general-purpose electric power opening lottery using the general-purpose electric goods opening counter C4 is the same (for example, both are 4/5). In the high-frequency support mode, the number of times the general-purpose accessory 34a is opened when the general-purpose electric accessory 34a is won is set more than in the low-frequency support mode, and one opening time is set longer. Has been done. In this case, in the high-frequency support mode, when the open state of the general electric power is won and the open state of the public electric accessory 34a occurs multiple times, from the end of one open state to the start of the next open state. The closing time is set shorter than the one-time opening time. Furthermore, in the high-frequency support mode, the minimum secured time for the next public-electric open lottery to be held after one public-electric open lottery is performed (that is, the general-purpose map), compared to the low-frequency support mode. The duration of one display on the display unit 38a) is set short.

As described above, in the high frequency support mode, the probability of winning the second operating port 34 is higher than in the low frequency support mode. In other words, in the low frequency support mode, the probability of winning the first operating port 33 is higher than that of the second operating port 34, but in the high frequency support mode, the second operation is higher than that of the first operating port 33. The probability that a prize will be awarded to the mouth 34 increases. Then, when a prize is won in the second operating port 34, a predetermined number of game balls are paid out. Therefore, in the high frequency support mode, the player plays a game while not reducing the number of balls held so much. It can be carried out.

The configuration for increasing the frequency of the high-frequency support mode to be in the open state per unit time is not limited to the above, for example, in the general open lottery. It may be configured to increase the probability of winning the open state. In addition, the secured time secured for the next Fuden opening lottery after one Fuden opening lottery is performed (for example, is executed by the Fuzu display unit 38a based on the winning of the through gate 35). In a configuration in which multiple types of variable display times are prepared, the high frequency support mode is set so that a shorter reservation time is easier to select or the average reservation time is shorter than the low frequency support mode. May be good. Furthermore, the number of times of opening is increased, the opening time is lengthened, and the securing time secured for the next public power opening lottery after one public power opening lottery is held is shortened. By applying any one of the conditions or any combination of the conditions of shortening the average time and increasing the winning probability, the advantage of the high frequency support mode over the low frequency support mode may be enhanced.

Next, the winning random number counter C1 will be described. The winning random number counter C1 is configured to be incremented by 1 in order within the range of, for example, 0 to 599, and return to "0" after reaching the maximum value. In particular, when the hit random number counter C1 makes one round, the value of the random number initial value counter CINI at that time is read as the initial value of the hit random number counter C1. The random number initial value counter CINI is a loop counter similar to the hit random number counter C1 (value = 0 to 599). The winning random number counter C1 is periodically updated and stored in the hold storage area 64a of the RAM 64 at the timing when the game ball wins the first operating port 33 or the second operating port 34.

The value of the random number that wins the jackpot is stored in the ROM 63 as a winning / failing table. As the pass / fail table, a pass / fail table for the low probability mode and a pass / fail table for the high probability mode are set. That is, in the pachinko machine 10, a low probability mode and a high probability mode are set as the lottery mode in the winning / failing lottery means.

In the gaming state in which the winning / failing table for the low probability mode is referred to at the time of the lottery, the number of random numbers that win the big hit is two. On the other hand, in the gaming state in which the winning / failing table for the high probability mode is referred to in the lottery, the number of random numbers that win the big hit is 20. If the winning probability in the high probability mode is higher than that in the low probability mode, the number of random numbers to be won is arbitrary.

The jackpot type counter C2 is configured to add 1 in order within the range of 0 to 29 and return to "0" after reaching the maximum value. The jackpot type counter C2 is periodically updated and stored in the hold storage area 64a at the timing when the game ball wins the first operating port 33 or the second operating port 34.

In this pachinko machine 10, a plurality of jackpot results are set. These plurality of big hit results are (1) the mode of opening / closing control of the special electric winning device 32 in the opening / closing execution mode, (2) the lottery mode in the winning / failing lottery means after the opening / closing execution mode ends, and (3) the first after the opening / closing execution mode ends. A plurality of jackpot results are set by providing differences in the three conditions of the support mode in the general electric accessory 34a of the two operating ports 34.

As an aspect of opening / closing control of the special electric winning device 32 in the opening / closing execution mode, the frequency of winning the special electric winning device 32 from the start to the end of the opening / closing execution mode is relatively high and low. A frequency winning mode and a low frequency winning mode are set. Specifically, in either the high-frequency winning mode or the low-frequency winning mode, the game is executed up to a predetermined number of round games.

Here, the round game continues until either the predetermined upper limit duration elapses or the predetermined upper limit number of game balls wins the special electric winning device 32. It is a game to play. Further, the number of round games in the open / close execution mode triggered by the jackpot result is the same as the fixed number of rounds regardless of the type of jackpot result triggered by the transition. Specifically, the maximum number of round games is set to 15 rounds regardless of which jackpot result is obtained.

Further, in the pachinko machine 10, a plurality of types of one-time opening mode of the special electric winning device 32 are set with different opening durations from the opening to the closing of the special electric winning device 32. Specifically, a long-time mode in which the opening duration is set to 29 sec, which is a long time, and a short-time mode in which the opening duration is set to 0.06 sec, which is shorter than the long time, are set. Has been done.

In the pachinko machine 10, when the launch operation device 28 is operated by the player, the game ball launch mechanism 27 is driven and controlled so that one game ball is launched toward the game area every 0.6 sec. To. In addition, the maximum number of end conditions for round games is set to nine. Then, in the long-time mode among the above-mentioned opening modes, the opening duration is set to be longer than the product of the firing cycle of the game ball and one round game. On the other hand, in the short-time mode, the opening duration is set to be shorter than the product of the firing cycle of the game ball and one round game, and more specifically, the opening duration is shorter than the firing cycle of the game ball. Therefore, when the opening is performed once in the long-time mode, it is expected that the special electric winning device 32 will be awarded the maximum number of prizes in one round game, and 1 in the short-time mode. When the number of times is opened, it is expected that the special electric winning device 32 will not be awarded, or even if the winning is generated, the number will be about one.

In the high-frequency winning mode, the special electric winning device 32 is opened once for a long time in each round game. On the other hand, in the low-frequency winning mode, the special electric winning device 32 is opened once in each round game in a short-time mode.

In addition, the number of times the special electric winning device 32 is opened and closed in the high-frequency winning mode and the low-frequency winning mode, the number of round games, the opening duration for one opening, and the upper limit number in one round game are those in the high-frequency winning mode. Is not limited to the above values and is arbitrary as long as the frequency of winning the special electric winning device 32 from the start to the end of the opening / closing execution mode is higher than that of the low frequency winning mode. Is.

The distribution destination of the game result for the jackpot type counter C2 is stored in the ROM 63 as a distribution table. Then, a low probability jackpot result, a low winning high probability jackpot result, and a most advantageous jackpot result are set as such distribution destinations.

The low-probability jackpot result is a jackpot result in which the open / close execution mode becomes the high-frequency winning mode, and after the open / close execution mode ends, the win / fail lottery mode becomes the low-probability mode and the support mode becomes the high-frequency support mode. However, this high-frequency support mode shifts to the low-frequency support mode when the number of games reaches the end reference number (specifically, 100 times) after the transition.

The low-winning high-probability jackpot result is a jackpot result in which the open / close execution mode becomes the low-frequency winning mode, and after the opening / closing execution mode ends, the winning / fail lottery mode becomes the high-probability mode and the support mode becomes the high-frequency support mode. be. These high-probability mode and high-frequency support mode continue until the lottery result in the winning / losing lottery becomes a big hit and the mode shifts to the opening / closing execution mode.

The most advantageous jackpot result is a jackpot result in which the open / close execution mode becomes the high-frequency winning mode, and after the open / close execution mode ends, the win / fail lottery mode becomes the high-probability mode and the support mode becomes the high-frequency support mode. These high-probability mode and high-frequency support mode continue until the lottery result in the winning / losing lottery becomes a big hit and the mode shifts to the opening / closing execution mode.

In relation to each of the above game states, the normal game state is not an open / close execution mode, but a state in which the winning / failing lottery mode is a low probability mode and the support mode is a low frequency support mode. Further, as a game result, a configuration in which a low winning high probability jackpot result is not set may be used.

In the distribution table, among the values of the jackpot type counter C2 of "0 to 29", "0 to 9" corresponds to the low accuracy jackpot result, and "10 to 14" corresponds to the low winning high accuracy jackpot result. "15-29" corresponds to the most advantageous jackpot result.

Next, the reach random number counter C3 will be described. The reach random number counter C3 is configured to be incremented by 1 in order within the range of, for example, 0 to 238, and return to "0" after reaching the maximum value. Here, in the pachinko machine 10, an expected effect is set as a kind of display effect in the symbol display device 41. The expected effect is a symbol display device 41 that is provided with a symbol display device 41 capable of displaying variable symbols, and in a gaming machine in which a final stop result is given as a result of a game that results in a predetermined jackpot. In the stage before the stop result is derived and displayed after the variable display of the symbol in the above is started, it means a display state for making the player think that the variable display state is likely to be the grant correspondence result. Specifically, regarding the grant correspondence result, the combination of symbols with the same number on any of the effective lines is stopped and displayed.

Two types of expected effects are set: a reach display and a notice display for expecting the occurrence of the reach display and the occurrence of the grant response result in the stage before the reach display occurs.

In the reach display, a combination of reach symbols consisting of the same symbol is displayed by stopping and displaying a part of the symbol rows among the plurality of symbol rows displayed on the display surface 41a of the symbol display device 41. In the state, the display state in which the fluctuation display of the symbol is performed in the remaining symbol rows is included. In addition, in the state where the combination of reach symbols is displayed as described above, the variation display of the symbols is performed in the remaining symbol rows, and the reach effect is performed by displaying a predetermined character or the like as a moving image on the background screen. , A combination of reach symbols is reduced or hidden, and a predetermined character or the like is displayed as a moving image on substantially the entire display surface 41a to perform a reach effect.

In the notice display, after the variable display of the symbol is started on the display surface 41a of the symbol display device 41, the symbol is variablely displayed in all the symbol rows, or a plurality of symbol rows. In the situation where the symbols are displayed in a variable manner in the symbol row, the mode in which the character is displayed separately from the symbols on the symbol row is included. Further, a background screen having a predetermined mode different from the previous mode and a symbol on the symbol row having a predetermined mode different from the previous mode are also included. Such a notice display may occur in any of the game times when the reach display is performed and when the reach display is not performed, but the case where the reach display is performed is higher than the case where the reach display is not performed. It is set to occur with a probability.

The reach display is executed regardless of the value of the reach random number counter C3 in the game times when the combination of the same symbols is finally stopped and displayed. Further, in the game times corresponding to the jackpot result in which the combination of the same symbols is not stopped and displayed, the game is not executed regardless of the value of the reach random number counter C3. Further, in the game times corresponding to the deviation result, the game is executed when the reach random number counter C3 acquired at a predetermined timing by referring to the reach table stored in the ROM 63 corresponds to the occurrence of the reach display.

On the other hand, the determination of whether or not to display the advance notice is not performed by the main control device 60, but by the voice emission control device 80. In this case, in the voice emission control device 80, the notice display is more likely to occur in the game times corresponding to any of the jackpot results than in the game times corresponding to the missed result, and the notice display having a low appearance rate is displayed. A lottery process for displaying a notice is executed so as to satisfy at least one of the conditions that are likely to occur. Incidentally, this lottery result is reflected when the effect for the game round is executed on the symbol display device 41.

Next, the variable type counter CS will be described. The variation type counter CS is configured to be incremented by 1 in order within the range of 0 to 198, and returns to "0" after reaching the maximum value. The variation type counter CS is used in the MPU 62 to determine the display duration on the special symbol display unit 37a and the symbol display duration on the symbol display device 41. The variation type counter CS is updated once every time the normal processing described later is executed once, and is repeatedly updated even within the remaining time in the normal processing. Then, the buffer value of the variation type counter CS is acquired when the variation pattern is determined at the start of the variation display on the special symbol display unit 37a and at the start of the variation of the symbol by the symbol display device 41.

<Processing configuration of main control device 60>
Next, each process executed for advancing the game by the MPU 62 of the main control device 60 will be described. The processing of the MPU 62 is roughly divided into a main processing that is started when the power is turned on and a timer interrupt processing that is started periodically (in this embodiment, at a cycle of 4 msec).

<Main processing>
First, the main process will be described with reference to the flowchart of FIG.

In step S101, the power-on wait process is executed. In the power-on wait process, for example, the process waits without proceeding to the next process until a predetermined time for waiting (specifically, 1 sec) elapses after the main process is started. During the execution period of the power-on wait process, the operation start and initial setting of the symbol display device 41 are completed. In the following step S102, access to the RAM 64 is permitted, and in step S103, the internal function register of the MPU 62 is set.

After that, in step S104, it is determined whether or not the RAM erasing switch provided in the power supply / emission control device 78 is manually operated, and in the following step S105, whether or not "1" is set in the power failure flag of the RAM 64. Is determined. Further, in step S106, a checksum calculation process for calculating a checksum is executed, and in the following step S107, whether or not the checksum matches the checksum saved when the power is turned off, that is, the validity of the stored data is determined. judge.

In the pachinko machine 10, when the RAM data is initialized at the time of turning on the power, for example, at the start of business of the game hall, the power is turned on while pressing the RAM erasing switch. Therefore, if the RAM erase switch is pressed, the process proceeds to step S108. Further, when the power cutoff occurrence information is not set or when an abnormality in the stored data is confirmed by the checksum, the process proceeds to step S108 in the same manner. In step S108, the RAM 64 is cleared. Then, the process proceeds to step S109.

On the other hand, when the RAM erase switch is not pressed, step S109 without executing the process of step S108, provided that the power failure flag is set to "1" and the checksum is normal. Proceed to. In step S109, the power-on setting process is executed. In the power-on setting process, a predetermined area of the RAM 64 such as initialization of the power failure flag is set as an initial value, and a command corresponding to the current gaming state is transmitted to the voice emission control device 80 in order to recognize the current gaming state. do.

After that, the process proceeds to the residual processing of steps S110 to S113. That is, although the MPU 62 is configured to periodically execute the timer interrupt processing, a residual time is generated between the timer interrupt processing of one and the next timer interrupt processing. This residual time varies depending on the processing completion time of each timer interrupt process, and the residual process of steps S110 to S113 is repeatedly executed by utilizing the irregular time. In this respect, it can be said that the residual processing in steps S110 to S113 is an irregular process that is executed irregularly.

In the residual processing, first, in step S110, interrupt prohibition is set in order to prohibit the occurrence of timer interrupt processing. In the following step S111, the random number initial value update process for updating the random number initial value counter CINI is executed, and the variation counter update process for updating the variation type counter CS is executed in step S112. In these update processes, the current numerical information is read from the corresponding counter of the RAM 64, a process of adding 1 to the read numerical information is executed, and then a process of overwriting the read source counter is executed. In this case, when the counter value reaches the maximum value, it is cleared to "0" respectively. After that, in step S113, the interrupt enable setting for switching from the state in which the occurrence of the timer interrupt process is prohibited to the state in which the timer interrupt process is permitted is set. After executing the process of step S113, the process returns to step S110, and the processes of steps S110 to S113 are repeated.

<Timer interrupt processing>
Next, the timer interrupt process will be described with reference to the flowchart of FIG. 7. The timer interrupt process is executed periodically (for example, in a 4 msec cycle).

First, the power failure information storage process is executed in step S201. In the power failure information storage process, it is monitored whether or not a power failure signal corresponding to the occurrence of a power failure is received from the power failure monitoring board 65, and if the occurrence of a power failure is specified, the power failure processing is executed.

In the following step S202, the lottery random number update process is executed. In the lottery random number update process, the hit random number counter C1, the jackpot type counter C2, the reach random number counter C3, and the general electric accessory release counter C4 are updated. Specifically, the current numerical information was sequentially read from the hit random number counter C1, the jackpot type counter C2, the reach random number counter C3, and the general electric utility release counter C4, and the read numerical information was added by 1 to each. Later, a process of overwriting the read source counter is executed. In this case, when the counter value reaches the maximum value, it is cleared to "0" respectively.

After that, in step S203, the random number initial value update process is executed in the same manner as in step S111, and in step S204, the fluctuation counter update process is executed in the same manner as in step S112.

In the following step S205, fraud detection processing for monitoring whether or not a predetermined event set as a monitoring target for fraud has occurred is executed. In the fraud detection process, "1" is set in the game stop flag provided in the RAM 64 by monitoring the occurrence of a plurality of types of events and confirming that a predetermined event has occurred.

In the following step S206, it is determined whether or not the progress of the game is stopped by determining whether or not "1" is set in the game stop flag. If a negative determination is made in step S206, the processes after step S207 are executed.

In step S207, the port output process is executed. In the port output processing, when the output information is set in the previous timer interrupt processing, the processing for outputting the output corresponding to the output information to the various drive units 32b and 34b through the output port 62b of the MPU 62 is performed. Execute. For example, when the information to switch the special electric winning device 32 to the open state is set, the output of the drive signal to the drive unit 32b for the special electric is started, and when the information to switch to the closed state is set. Stops the output of the drive signal. Further, when the information for switching the utility accessory 34a of the second operating port 34 to the open state is set, the output of the drive signal to the drive unit 34b for the utility should be started and the state should be switched to the closed state. If the information is set, the output of the drive signal is stopped.

In the following step S208, the reading process is executed. In the reading process, signals other than the power failure signal and the winning signal are read through the input port 62a of the MPU 62, and the read information is stored for use in future processing.

In the following step S209, the winning detection process is executed. In the winning detection process, the signals received from the winning detection sensors 66a to 66e are read through the input port 62a of the MPU 62, and the general winning opening 31, the special electric winning device 32, the first operating port 33, and the second operating port are used. A process for specifying whether or not a prize has been won in the 34 and the through gate 35 is executed.

In the following step S210, a timer update process for collectively updating the numerical information of a plurality of types of timer counters provided in the RAM 64 is executed. In this case, the timer counters to which the stored numerical information is subtracted and updated are collectively handled, but both the subtraction type timer counter update and the addition type timer counter update are collectively performed. It may be configured.

In the following step S211, a launch control process for controlling the launch of the game ball is executed. In the situation where the firing operation to the firing operation device 28 is continued, one game ball is launched every 0.6 sec, which is a predetermined firing cycle, as described above.

In the following step S212, as the input state monitoring process, the disconnection confirmation of the winning detection sensors 66a to 66e and the opening confirmation of the gaming machine main body 12 and the front door frame 14 are confirmed based on the information read in the reading process of step S208. conduct.

In the following step S213, the special figure special electric control process for performing the execution control of the game times and the execution control of the open / close execution mode is executed. In the special figure special electric control process, when a prize is generated in the first operating port 33 or the second operating port 34 in a situation where the number of reserved information stored in the holding storage area 64a is less than the upper limit number, the prize is awarded. The processing of storing the numerical information of the hit random number counter C1, the jackpot type counter C2, and the reach random number counter C3 at the time point in the hold storage area 64a in time series is executed as the hold information. Further, in the special figure special electric control process, it is determined whether or not the hold information corresponds to the jackpot winning on the condition that the hold information is stored and not during the game rotation or the open / close execution mode. Processing, and if it corresponds to the jackpot winning, the distribution determination processing for determining which jackpot result the pending information corresponds to is executed. In addition, in the special figure special electric control process, not only the hit / fail determination process and the distribution determination process, but also whether or not the hold information corresponds to the reach occurrence when the hold information does not correspond to the big hit winning. The determination reach determination process is executed, and the process of selecting the duration of the game round is executed by using the numerical information of the variation type counter CS at that time. Then, a variable command including information on the duration according to the result of each of these processes and a type command including information on the game result are transmitted to the voice emission control device 80, and the pattern on the special figure display unit 37a is displayed. Start variable display. As a result, one game round is started, and the special figure display unit 37a and the symbol display device 41 start the effect for the game round.

Further, in the special figure special electric control process, it is determined whether or not it is the end timing of the game round during the execution of one game round, and if it is the end timing, the display corresponding to the game result is performed. , Executes the process of ending the game. In this case, a final stop command indicating that the game round should be ended is transmitted to the voice emission control device 80. Further, in the special figure special electric control process, when the result of the game round is the result corresponding to the transition to the open / close execution mode, the process for starting the open / close execution mode is executed. At the time of this start, an opening command indicating that the open / close execution mode is started is transmitted to the voice emission control device 80. Further, in the special figure special electric control process, a process for starting each round game and a process for ending each round game are executed. In each of these processes, an open command indicating that the round game is started is transmitted to the voice emission control device 80, and a closing command indicating that the round game is ended is transmitted to the voice emission control device 80. Further, in the special figure special electric control process, an ending command indicating that the opening / closing execution mode is terminated is transmitted to the voice emission control device 80, and a winning / failing lottery mode or a support mode after the opening / closing execution mode is set. Execute the process.

After executing the special figure special electric control process of step S213 in the timer interrupt process, the normal figure general electric control process is executed in step S214. In the Fuzu Fuden control process, when a prize has been won in the through gate 35, a process for acquiring the hold information on the Fuzu side is executed, and the hold information on the Fuzu side is stored. In addition, a release determination is made for the reserved information, and further, a process for performing an effect for a normal drawing is executed with the opening determination as an opportunity. Further, based on the result of the opening determination, a process of opening and closing the general electric accessory 34a of the second operating port 34 is executed.

In the following step S215, based on the processing results of the immediately preceding steps S213 and S214, the output information for reflecting the increase / decrease number of the reserved information related to the special figure display unit 37a on the special figure reservation display unit 37b is set. , The output information for reflecting the increase / decrease number of the reserved information related to the normal figure display unit 38a in the normal figure hold display unit 38b is set. Further, in step S215, output information for updating the display contents of the special figure display unit 37a is set based on the processing results of the immediately preceding steps S213 and S214, and the display contents of the normal figure display unit 38a are set. Set the output information for updating. The output information is set in step S215 through the output port 62b of the MPU 62.

In the following step S216, the contents of the command and the signal received from the payout control device 77 are confirmed, and the payout state reception process for performing the process corresponding to the check result is executed. Further, in step S217, a payout output process for setting the prize ball command as an output target is executed. In the following step S218, the external information setting process for controlling the start and end of the output of the external signal according to the processing result of the various processes executed in the timer interrupt process this time is executed. After that, the timer interrupt processing is terminated.

<Electrical configuration for reading data in MPU62>
Next, an electrical configuration for performing instructions, reading data, and writing data in the MPU 62 will be described. FIG. 8 is a block diagram for explaining the electrical configuration of the CPU 101 provided in the MPU 62.

The MPU 62 has a built-in CPU 101. The CPU core 102 built in the CPU 101 reads various instructions from the ROM 83 built in the MPU 62, and executes arithmetic processing, input data analysis processing, and data output processing according to a program corresponding to the instruction. Specifically, the CPU core 102 reads an instruction from the area of the address corresponding to the value of the program counter built in the CPU core 102 and updated as the processing of the CPU core 102 progresses, and the processing corresponding to the instruction. By executing, various processes according to the program are executed.

The CPU core 102 includes a Vcc terminal, a GND terminal, an INT terminal, an NMI terminal, a data terminal D0 to D7, an address terminal A0 to A15, an RD terminal, a WR terminal, an IRQ terminal, an MRQ terminal, and the like. Hereinafter, the data terminals D0 to D7, the address terminals A0 to A15, the RD terminal, the WR terminal, the IRQ terminal, and the MRQ terminal will be described in detail. The description of the Vcc terminal, the GND terminal, the INT terminal, and the NMI terminal will be omitted. Further, these Vcc terminal, GND terminal, INT terminal and NMI terminal are also provided in the CPU 101, but the description thereof will be omitted.

The data terminals D0 to D7 read the instruction in the CPU core 102, read the data referred to when executing the process in the CPU core 102 according to the program corresponding to the instruction, and the CPU core 102 according to the program corresponding to the instruction. It is a terminal for writing the data derived as a result of the processing in. A plurality of data terminals D0 to D7 are provided, and are electrically connected to the data terminals D10 to D17 provided in the CPU 101. Specifically, eight data terminals D0 to D7 of the CPU core 102 are provided, and eight data terminals D10 to D17 of the CPU 101 are also associated with the data terminals D0 to D7 of the CPU core 102 on a one-to-one basis. It is provided. The data terminals D0 to D7 of the CPU core 102 are electrically connected to the data terminals D10 to D17 of the CPU 101 through the data bus DB built in the CPU 101, and the data terminals D10 to D17 of the CPU 101 are provided inside the MPU 62. It is electrically connected to the data bus DB. With such a configuration, the CPU core 102 can collectively read 8-bit (that is, 1 byte) data through the data bus DB, and can read 8-bit (that is, 1 byte) data for the data bus DB. Can be written together.

The address terminals A0 to A15 are for designating the address of the area where the instruction or data exists when reading the instruction from the ROM 63 in the CPU core 102 and reading the data from the ROM 63 or the RAM 64 in the CPU core 102. It is a terminal. Further, the address terminals A0 to A15 are terminals for designating the address of the area for writing the data when writing the data to the ROM 63 or the RAM 64 in the CPU core 102. A plurality of address terminals A0 to A15 are provided, and are electrically connected to the address terminals A20 to A35 provided in the CPU 101. Specifically, 16 address terminals A0 to A15 of the CPU core 102 are provided, and 16 address terminals A20 to A35 of the CPU 101 are also associated with the address terminals A0 to A15 of the CPU core 102 on a one-to-one basis. It is provided. The address terminals A0 to A15 of the CPU core 102 are electrically connected to the address terminals A20 to A35 of the CPU 101 through the address bus AB built in the CPU 101, and the address terminals A20 to A35 of the CPU 101 are provided inside the MPU 62. It is electrically connected to the address bus AB. With such a configuration, the CPU core 102 can specify addresses to the ROM 63 and the RAM 64.

The address terminals A0 to A15 are used not only when addressing the ROM 63 and RAM 64, but also when outputting chip select signals from the chip select terminals CS0 to CS12 provided in the CPU 101. Here, the chip select terminals CS0 to CS12 specify the input latch circuit 103 (see FIG. 9A) to be operated when reading the instruction in the CPU core 102 and reading the data in the CPU core 102, and also specify the operation target. This is a terminal for designating an output latch circuit 104 (see FIG. 9B) to be operated when writing data in the CPU core 102.

A plurality of input latch circuits 103 are built in the MPU 62. As the plurality of input latch circuits 103, an input latch circuit for designating the ROM 63 as a read target when reading instructions and data, an input latch circuit for designating the RAM 64 as a read target when reading data, and the like. And, when reading the data input to the input port 62a of the MPU 62, an input latch circuit for designating an area in which the input data is stored as a reading target is provided. When reading the data input to the input port 62a of the MPU 62, the input latch circuit for designating the area where the input data is stored as the read target differs the area designated as the read target in the input port 62a. There are multiple.

A plurality of output latch circuits 104 are built in the MPU 62. As the plurality of output latch circuits 104, an output latch circuit for designating the RAM 64 as a write target when writing data, and an area for storing the output data when outputting data to the output port 62b of the MPU 62 are write targets. An output latch circuit is provided to specify as. When outputting data to the output port 62b of the MPU 62, a plurality of output latch circuits for designating an area for storing the output data as a write target are provided in the output port 62b with different areas designated as a read target. There is.

A plurality of chip select terminals CS0 to CS12 are provided, and each of the chip select terminals CS0 to CS12 is electrically connected to a select signal line provided inside the MPU 62. Specifically, 13 chip select terminals CS0 to CS12 are provided, and 13 select signal lines are provided so as to correspond one-to-one with the chip select terminals CS0 to CS12. The plurality of chip select terminals CS0 to CS4, which are a part of the chip select terminals CS0 to CS12, are for outputting the CS0 signal to CS4 signal as the chip select signal to the input latch circuit 103, and the remaining plurality of chips. The select terminals CS5 to CS12 are for outputting CS5 signals to CS12 signals as chip select signals to the output latch circuit 104.

The input latch circuit 103 will be described by taking as an example what is used in the CPU 101 when inputting predetermined data from the input port 62a of the MPU 62. FIG. 9A is a block diagram of the input latch circuit 103. As shown in FIG. 9A, the input latch circuit 103 collects data stored in the input latch circuit 103 through the input terminals Q0 to Q7 and the input terminals Q0 to Q7 for receiving data from the input port 62a. It includes data terminals D20 to D27 for supplying to the bus DB, a CK terminal to which a CS0 signal output from the chip select terminal CS0 of the CPU 101 is input, and the like. When the CS0 signal is input from the chip select terminal CS0 of the CPU 101 to the CK terminal, the input latch circuit 103 transfers the data stored in the input latch circuit 103 through the input terminals Q0 to Q7 to the data terminals D20 to D20. It is supplied to the data bus DB through D27. In addition to these terminals, the input latch circuit 103 includes a Vcc terminal, a GND terminal, a CLR terminal, and the like.

The output latch circuit 104 will be described by taking as an example what is used in the CPU 101 when outputting predetermined data to the output port 62b of the MPU 62. FIG. 9B is a block diagram of the output latch circuit 104. As shown in FIG. 9B, the output latch circuit 104 outputs the data stored in the output latch circuit 104 through the data terminals D30 to D37 and the data terminals D30 to D37 for receiving data from the data bus DB. It is provided with output terminals Q10 to Q17 for supplying to the port 62b, a CK terminal to which a CS5 signal output from the chip select terminal CS5 of the CPU 101 is input, and the like. The output latch circuit 104 inputs data provided to the data bus DB through the data terminals D30 to D37 into the output latch circuit 104 by inputting a CS5 signal from the chip select terminal CS5 of the CPU 101 to the CK terminal. The data is captured, and then the captured data is output from the output terminals Q10 to Q17 to the output port 62b. In addition to these terminals, the output latch circuit 104 includes a Vcc terminal, a GND terminal, a CLR terminal, and the like.

While the chip select terminals CS0 to CS12 of the CPU 101 have the above functions, the address data output from the address terminals A0 to A15 (see FIG. 8) of the CPU core 102 is a chip select for outputting a chip select signal. It is used when selecting terminals CS0 to CS12. Further, when selecting the chip select terminals CS0 to CS12 for outputting the chip select signal, the signals output from the RD terminal, the WR terminal, the IRQ terminal and the MRQ terminal of the CPU core 102 are used.

The RD terminal is a terminal for outputting an RD signal that specifies that the CPU core 102 reads an instruction or reads data. The WR terminal is a terminal for outputting a WR signal that specifies that data is written in the CPU core 102. The IREQ terminal sends an IREQ signal that specifies that the CPU core 102 is in a situation where an in instruction for inputting data from the input port 62a or an out instruction for outputting data to the output port 62b is executed in the CPU core 102. It is a terminal for output. The MRQ terminal outputs an MEQU signal that specifies that the CPU core 102 is in a situation to execute a load instruction for reading an instruction or data from the ROM 63, writing data to the RAM 64, reading data from the RAM 64, or the like. It is a terminal for output.

Next, various instructions executed in the CPU core 102 will be described. FIG. 10 is an explanatory diagram for explaining an area in which instructions are stored in the ROM 63.

The ROM 63 stores in advance a 1-byte instruction, a 2-byte instruction, and a 3-byte instruction as instructions. Of these instructions, the in and out instructions already described correspond to 2-byte instructions, and the load instruction corresponds to a 3-byte instruction. Incidentally, the 2-byte instruction includes instructions other than the in instruction and the out instruction, and the 3-byte instruction includes instructions other than the load instruction. Further, the number of bytes of the instruction is not limited to these, and a 4-byte instruction may be stored in advance in addition to or in place of the instruction having the number of bytes.

FIG. 11A is an explanatory diagram for explaining an in instruction and an out instruction which are 2-byte instructions. The in instruction and the out instruction include the address code shown in FIG. 11 (a1) and the IO identification code shown in FIG. 11 (a2). The address code has a 1-byte data structure and is set as the first byte in the in instruction and the out instruction. Depending on the content set in the address code, the type of input latch circuit 103 to be operated when data is input from the input port 62a and the operation target when data is output to the output port 62b. The type of output latch circuit 104 is specified. In this case, since the address code has a 1-byte data structure, it is possible to specify 256 addresses as addresses for specifying the types of the latch circuits 103 and 104 to be operated. However, in the pachinko machine 10, since the number of chip select terminals CS0 to CS12 of the CPU 101 is 13 as already described, the type of address actually specified is 13 or less.

The IO identification code has a 1-byte data structure, and the content set in the IO identification code specifies whether the type of the 2-byte instruction is an in instruction or an out instruction. By the way, in the case of an out instruction, the value next to the value of the program counter corresponding to the out instruction corresponds to the 1-byte instruction, and the 1-byte instruction corresponds to the 1-byte output data for output to the output port 62b. Is set.

FIG. 11B is an explanatory diagram for explaining a load instruction which is a 3-byte instruction. The load instruction includes a first address code shown in FIG. 11 (b1), a second address code shown in FIG. 11 (b2), and an execution code shown in FIG. 11 (b3). Both the first address code and the second address code have a 1-byte data structure, the first address code is set to the first byte in the load instruction, and the second address code is the second in the load instruction. It is set to the byte of. Depending on the contents set in the first address code and the second address code, the type of area to be read when reading instructions and data, and the type of area to be written when writing data. Is identified.

The execution code has a 1-byte data structure, and the type of the instruction to be executed is specified by the contents set in the execution code. As the instruction to be executed, a transfer instruction, an arithmetic operation instruction, a logical operation instruction, a bit operation instruction, a rotate instruction, a shift instruction, and the like are set. In the case of a transfer command, the process of reading the data of the address specified by the first address code and the second address code to the CPU core 102, or the predetermined data at the address specified by the first address code and the second address code. Is executed. Further, in the case of an arithmetic operation instruction, a process of adding or subtracting predetermined data to the data is executed. Further, in the case of a logical operation instruction, a process of performing a predetermined logical operation on the data is executed. Further, in the case of a bit manipulation instruction, a process of switching a predetermined bit of data between "0" and "1" is executed. Further, in the case of a rotate instruction, a process of shifting the bits included in the data so as to circulate in a predetermined direction is executed. Further, in the case of a shift instruction, a process of shifting the bits included in the data in a predetermined direction without rotating the bits is executed.

Next, the IO space 105 and the memory space 106, which are virtual spaces accessed by the CPU core 102, will be described. FIG. 12 is a block diagram for explaining the IO space 105 and the memory space 106.

The IO space 105 is a virtual space accessed by the CPU core 102 when an in instruction or an out instruction is executed in the CPU core 102. The situation where the CPU core 102 is accessing the IO space 105 is actually a chip select from the corresponding chip select terminal of the CPU 101 to the corresponding input latch circuit 103 in order to input data from the input port 62a. A signal is being output, or a chip select signal is being output from the corresponding chip select terminal of the CPU 101 to the corresponding output latch circuit 104 in order to output data to the output port 62b.

As described above, the address code is 1 byte in the in instruction and the out instruction that access the IO space 105. Therefore, the number of addresses that can be specified as the IO space 105 in the CPU core 102 is 256 corresponding to 1 byte. Corresponding to this, when accessing the IO space 105, only eight address terminals A0 to A7, which are a part of the 16 address terminals A0 to A15 of the CPU core 102 and are plural, are used. The address is specified. That is, when accessing the IO space 105, the same number of address terminals A0 to A7 as the number of bits of the address code set in the in instruction and the out instruction are used. As a result, the contents of the address code set in the in command and the out command can be used as they are as data to be set in the address terminals A0 to A7. The address data set in the first byte in the in instruction and the out instruction is the eight address terminals A0 that are continuous from the 0th address terminal A0 of the address terminals A0 to A15 of the CPU core 102 toward the lower level. It corresponds to ~ A7.

The memory space 106 is a virtual access by the CPU core 102 when reading an instruction from the area of ROM 63 having an address corresponding to the value of the program counter in the CPU core 102 and when executing a load instruction in the CPU core 102. It is a space. The situation where the CPU core 102 is accessing the memory space 106 is actually the corresponding chip select terminals CS0 to CS4 of the CPU 101 for reading instructions or data from the ROM 63 or reading data from the RAM 64. Corresponds to the situation where the chip select signal is output to the corresponding input latch circuit 103, and the corresponding output latch circuit from the corresponding chip select terminals CS5 to CS12 of the CPU 101 in order to write data to the RAM 64. The situation where the chip select signal is output to 104 corresponds to this.

As already described in the load instruction for accessing the memory space 106, the address code is a total of 2 bytes of the first address code and the second address code. Therefore, the number of addresses that can be specified as the memory space 106 in the CPU core 102 is 65536 corresponding to 2 bytes. Corresponding to this, when accessing the memory space 106, address designation is performed using all 16 address terminals A0 to A15 of the CPU core 102. That is, when accessing the memory space 106, the same number of address terminals A0 to A15 as the total number of bits of the first address code and the second address code set in the load instruction is used. As a result, the contents of the first address code and the second address code set in the load instruction can be used as they are as data to be set in the address terminals A0 to A15.

The first address data set in the first byte in the load instruction is eight consecutive address terminals A0 to lower from the 0th address terminal A0 among the address terminals A0 to A15 of the CPU core 102. It corresponds to A7. Further, the second address data set in the second byte in the load instruction is eight consecutive address terminals from the eighth address terminal A8 of the address terminals A0 to A15 of the CPU core 102 toward the lower level. It corresponds to A8 to A15.

Here, as already described, in the in instruction and the out instruction, the address data is set in the first byte, and the data corresponding to the address terminals A0 to A7 is set in the address data as the address code. .. That is, in any of the in instruction, the out instruction, and the load instruction, the data corresponding to the address terminals A0 to A7 is set in the first byte. As a result, the data set in the first byte may be set in the address terminals A0 to A7 regardless of whether the instruction is an in instruction, an out instruction, or a load instruction, and the data setting may be performed. By making it possible to standardize the processing configuration of the above, it is possible to simplify the processing configuration.

Next, the contents that the CPU core 102 can execute the load instruction will be described even when the data is input from the input port 62a and the data is output to the output port 62b.

As described above, the in instruction and the out instruction have a 2-byte configuration of an address code and an IO identification code, and an address for specifying the type of the latch circuits 103 and 104 to be operated is set in the address code. The IO identification code is set with data indicating whether it corresponds to an in instruction or an out instruction. In this configuration, the execution code cannot be set in the in instruction and the out instruction like the load instruction. Further, since the total number of bits of a 2-byte instruction is smaller than that of a 3-byte instruction, the number of usable 2-byte instructions is naturally limited.

On the other hand, the CPU core 102 can execute the load instruction even when the data is input from the input port 62a and when the data is output to the output port 62b. This makes it possible to use the execution code even when inputting / outputting these data. For example, by executing a load instruction when inputting data from the input port 62a, the data in the state after changing the array of a plurality of bits can be read, or the data set in a plurality of bits can be read. It is possible to read the data in the state after inverting each of them. Further, for example, by executing a load instruction when outputting data to the output port 62b, the data output to the output port 62b is held as it is on the CPU core 102 side, and the data is stored in a predetermined order of bits. It is possible to output the data in the state after changing the array to the output port 62b.

However, in the load instruction, as described above, the first address code is set in the first byte and the second address code is set in the second byte, and the CPU core 102 executes the load instruction. Whether it accesses the ROM 63 or the RAM 64, or the input port 62a or the output port 62b, the address can be specified by using all of the 16 address terminals A0 to A15. The memory space 106 is being accessed. If the handling of the load instruction in the CPU core 102 is to be different between the case of accessing the ROM 63 or the RAM 64 and the case of accessing the input port 62a or the output port 62b, the data for identifying the access target is used as the address code. This is because it becomes necessary to set separately, and in this case, the load instruction cannot be set as a 3-byte instruction. Further, with the above configuration, when the CPU core 102 accesses the input port 62a or the output port 62b, the in instruction or the out instruction is executed (that is, the IO space 105 is accessed), and the load instruction is executed. The address is specified differently depending on the case (that is, when accessing the memory space 106).

When executing the load instruction in the CPU core 102 in this way, it is necessary that different addresses are set for accessing the ROM 63 or RAM 64 and accessing the input port 62a or the output port 62b. Therefore, as shown in the explanatory diagram of the memory space 106 of FIG. 13, the memory space 106 includes not only the ROM space 106a corresponding to the ROM 63 and the RAM space 106b corresponding to the RAM 64, but also the input corresponding to the input port 62a. The output port space 106d corresponding to the port space 106c and the output port 62b exists. The addresses set in each of the ROM space 106a, the RAM space 106b, the input port space 106c, and the output port space 106d are different from each other.

ROM 63 has the largest number of areas that require addressing, RAM 64 has the second largest, the output latch circuit 104 corresponding to the output port 62b has the next largest number, and the input latch circuit 103 corresponding to the input port 62a has the smallest number. .. Therefore, the type of address set in the ROM space 106a is the most, the type of the address set in the RAM space 106b is the second most, and the type of the address set in the output port space 106d is next. The number of types of addresses set in the input port space 106c is the smallest.

Next, regardless of whether the CPU core 102 executes an in instruction or an out instruction or a load instruction, data is input from the input port 62a or data is output to the output port 62b. The configuration for doing this will be described. FIG. 14 is a block diagram showing an electrical configuration for outputting a chip select signal from the chip select terminal CS0 corresponding to the input latch circuit 103 for inputting data from the input port 62a. An electrical configuration for outputting a chip select signal from another chip select terminal corresponding to the input latch circuit 103 for inputting data from the input port 62a, and an output for outputting data to the output port 62b. The electrical configuration for outputting the chip select signal from the chip select terminal corresponding to the latch circuit 104 is the same as the electrical configuration shown in FIG.

Both the RD terminal and the WR terminal of the CPU core 102 are electrically connected to the operation selection circuit 111 built in the CPU 101. Specifically, the operation selection circuit 111 is provided with an input terminal corresponding to the RD terminal, and a signal path is formed by electrically connecting the RD terminal and the input terminal. Further, the operation selection circuit 111 is provided with an input terminal corresponding to the WR terminal, and a signal path is formed so as to electrically connect these WR terminals and the input terminal.

The operation selection circuit 111 is for selecting whether the signal that triggers the output of the operation selection signal from the operation selection terminal 111a is the RD signal output from the RD terminal or the WR signal output from the WR terminal. It is a circuit of. An initialization signal is input to the operation selection circuit 111 when the supply of operating power to the CPU 101 is started from the initialization circuit 112 built in the CPU 101, and the initialization signal is input. As a result, the signal on the side defined in the design stage of the pachinko machine 10 is selected from the RD signal and the WR signal as the signal that triggers the output of the operation selection signal. Specifically, the operation selection circuit 111 is provided with a switch circuit 111b, and when an initialization signal is input from the initialization circuit 112, the RD terminal and the operation selection terminal 111a are made conductive, and the WR. Of the states in which the terminal and the operation selection terminal 111a are made conductive, the state is set to the side determined in the design stage of the pachinko machine 10. Since the RD signal is a LOW level signal, when the switch circuit 111b is in a state of conducting the RD terminal and the operation selection terminal 111a, or when the RD signal is not output (that is, the HI level signal is output from the RD terminal). If), the HI level signal is output as a non-operation selection signal from the operation selection terminal 111a of the operation selection circuit 111, and if the RD signal is output, the operation is operated from the operation selection terminal 111a of the operation selection circuit 111. A LOW level signal is output as a selection signal. Similarly, since the WR signal is a LOW level signal, when the switch circuit 111b is in a state of conducting the WR terminal and the operation selection terminal 111a, when the WR signal is not output (that is, the HI level signal is output from the WR terminal). (When output), the HI level signal is output as a non-operation selection signal from the operation selection terminal 111a of the operation selection circuit 111, and when the WR signal is output, the operation selection terminal 111a of the operation selection circuit 111 is output. A LOW level signal is output as an operation selection signal.

Since FIG. 14 is a chip select terminal CS0 for outputting a chip select signal to the input latch circuit 103, the operation selection circuit 111 is in a state of conducting the RD terminal and the operation selection terminal 111a. As a result, the RD signal is output from the RD terminal of the CPU core 102, so that the operation selection circuit 111 outputs the operation selection signal from the operation selection terminal 111a.

In the case of the operation selection circuit 111 corresponding to the chip select terminals CS5 to CS12 for outputting the chip select signal to the output latch circuit 104, the initialization signal is input from the initialization circuit 112, so that the WR terminal is used. And the operation selection terminal 111a are connected to each other, and the WR signal is output from the WR terminal of the CPU core 102, so that the operation selection signal is output from the operation selection terminal 111a of the operation selection circuit 111. Although the details will be described later, it is a necessary condition for the chip select signal to be output from the chip select terminal CS0 that the operation selection signal is output from the operation selection circuit 111.

Both the IRQ terminal and the MRQ terminal of the CPU core 102 are electrically connected to the target selection circuit 113 built in the CPU 101. Specifically, the target selection circuit 113 is provided with an input terminal corresponding to the IREQ terminal, and a signal path is formed so as to electrically connect these IREQ terminals and the input terminal. Further, the target selection circuit 113 is provided with an input terminal corresponding to the MRQ terminal, and a signal path is formed so as to electrically connect these MEQU terminals and the input terminal.

The target selection circuit 113 is provided with a target selection logic circuit 113a. Each of the signal output from the IRQ terminal and the signal output from the MREF terminal is input to the NOR circuit in the target selection logic circuit 113a through each NOT circuit in the target selection logic circuit 113a. Since the IRQ signal is a LOW level signal and the MRQ signal is a LOW level signal, the LOW level signal is output from the target selection logic circuit 113a in a situation where either the IRQ signal or the MRQ signal is output. To. Then, in the situation where the LOW level signal is output from the target selection logic circuit 113a, the LOW level signal is output as the target selection signal from the target selection terminal 113b of the target selection circuit 113. That is, the target selection signal is output from the target selection circuit 113 regardless of whether the IRQ signal is output from the IRQ terminal or the MRQ signal is output from the MRQ terminal. As a result, in any case in the configuration where the CPU core 102 accesses the input port 62a or the output port 62b not only when the in instruction or the out instruction is executed but also when the load instruction is executed. Even so, it is possible to output the target selection signal from the target selection circuit 113. Although the details will be described later, it is a necessary condition for the chip select signal to be output from the chip select terminal CS0 that the target selection signal is output from the target selection circuit 113. The target selection circuit 113 outputs the HI level signal as the non-target selection signal in the situation where the IRQ signal is not output and the MCHECK signal is not output.

Of the address terminals A0 to A15 of the CPU core 102, eight address terminals A0 to A7 that are continuous from the 0th address terminal A0 toward the lower side are electrically connected to the IO address decoder 114. Specifically, the IO address decoder 114 is provided with eight input terminals corresponding to the eight address terminals A0 to A7 on a one-to-one basis, and the corresponding address terminals A0 to A7 and the input terminal are provided. The signal path is formed so as to electrically connect the two. Further, all 16 address terminals A0 to A15 are electrically connected to the memory address decoder 115. Specifically, the memory address decoder 115 is provided with 16 input terminals corresponding to 16 address terminals A0 to A15 on a one-to-one basis, and the corresponding address terminals A0 to A15 and the input terminal are provided. The signal path is formed so as to electrically connect the two. The signal path from the address terminals A0 to A7 to each input terminal of the IO address decoder 114 is an intermediate position of the signal path that electrically connects the address terminals A0 to A7 and each input terminal of the memory address decoder 115. It is provided by branching from.

The IO address decoder 114 has an electric circuit so as to output a LOW level signal as an IO address signal from the IO address output terminal 114a when the 1-byte address data corresponding to the chip select terminal CS0 is output from the CPU core 102. It is formed. Further, when the CPU core 102 outputs the chip select signal from the chip select terminals CS1 to CS12 different from the chip select terminals CS0, the address data is output from the address terminals A0 to A7, but the chip select terminal CS0 is used. The corresponding IO address decoder 114 does not output the IO address signal from the IO address output terminal 114a even if the address data different from the address data corresponding to the circuit provided in itself is input. That is, the HI level signal is output from the IO address output terminal 114a as a non-IO address signal.

The memory address decoder 115 has an electric circuit so as to output a LOW level signal as a memory address signal from the memory address output terminal 115a when 2-byte address data corresponding to the chip select terminal CS0 is output from the CPU core 102. It is formed. Further, when the CPU core 102 outputs the chip select signal from the chip select terminals CS1 to CS12 different from the chip select terminals CS0, the address data is output from the address terminals A0 to A15, but the chip select terminal CS0 is used. The corresponding memory address decoder 115 does not output a memory address signal from the memory address output terminal 115a even if address data different from the address data corresponding to the circuit provided in itself is input. That is, the HI level signal is output from the memory address output terminal 115a as a non-memory address signal.

Although the details will be described later, it is a necessary condition for the chip select signal to be output from the chip select terminal CS0 that the corresponding address signal is output from the IO address decoder 114 or the memory address decoder 115.

Here, the first of the 1-byte address data that triggers the output of the IO address signal from the IO address decoder 114 and the 2-byte address data that triggers the output of the memory address signal from the memory address decoder 115. The 1-byte address data set in the bytes is the same data. For example, while the 1-byte address data that triggers the output of the IO address signal from the IO address decoder 114 is set to "A5" in hexadecimal, the memory address signal is output from the memory address decoder 115. Of the two-byte address data that triggers, the address data of the first byte is set to "A5" in hexadecimal, and the address data of the second byte is set to "00" in hexadecimal.

In the electric circuit for outputting the chip select signal to the input latch circuit 103 for inputting data from the input port 62a and the output latch circuit 104 for outputting data to the output port 62b, as described above, the IREQ The target selection signal is output from the target selection circuit 113 regardless of whether the signal or the MCHECK signal is output. Then, if the 1-byte address data output from the upper address terminals A0 to A7 is the address data corresponding to the address signal output from the IO address decoder 114, the lower address terminals A8 to A15 Regardless of which data is the 1-byte address data output from, the IO address signal is output from the IO address decoder 114. In this case, the 2-byte address data whose address data of the upper address terminals A0 to A7 corresponds to the IO address decoder 114 is a chip select different from the chip select terminal corresponding to the IO address decoder 114. It cannot be used as address data corresponding to the IO address decoder and the memory address decoder in the terminal electric circuit. Under such circumstances, the 1-byte address data set in the first byte of the 2-byte address data for outputting the memory address signal from the memory address decoder 115 is the IO address decoder 114 to IO. By matching the 1-byte address data for outputting the address signal, it is possible to suppress the number of types of address data that cannot be used as an electric circuit of another chip select terminal.

Both the IO address output terminal 114a of the IO address decoder 114 and the memory address output terminal 115a of the memory address decoder 115 are electrically connected to the address circuit 116 built in the CPU 101. Specifically, the address circuit 116 is provided with an input terminal corresponding to the IO address output terminal 114a, and the signal path is provided by electrically connecting the IO address output terminal 114a and the input terminal. It is formed. Further, the address circuit 116 is provided with an input terminal corresponding to the memory address output terminal 115a, and a signal path is formed so as to electrically connect these memory address output terminals 115a and the input terminal. There is.

The address circuit 116 is provided with an address logic circuit 116a. Each of the signal output from the IO address output terminal 114a and the signal output from the memory address output terminal 115a are input to the NOR circuit in the address logic circuit 116a through each NOT circuit in the address logic circuit 116a. ing. Since the IO address signal is a LOW level signal and the memory address signal is a LOW level signal, the LOW level signal is output from the address logic circuit 116a in a situation where at least one of the address signals is output. Then, in the situation where the LOW level signal is output from the address logic circuit 116a, the LOW level signal is output as a combined address signal from the address output terminal 116b of the address circuit 116. That is, the composite address signal is output from the address circuit 116 regardless of whether the IO address signal is output from the IO address output terminal 114a or the memory address signal is output from the memory address output terminal 115a. .. Although the details will be described later, it is a necessary condition for the chip select signal to be output from the chip select terminal CS0 that the combined address signal is output from the address circuit 116. The address circuit 116 outputs an HI level signal as a non-synthesized address signal when the IO address signal is not output and the memory address signal is not output.

The address output terminal 116b of the address circuit 116, the operation selection terminal 111a of the operation selection circuit 111, and the target selection terminal 113b of the target selection circuit 113 are all electrically connected to the synthesis circuit 117 built in the CPU 101. .. Specifically, the synthesis circuit 117 is provided with an input terminal corresponding to the address output terminal 116b, and a signal path is formed so as to electrically connect these address output terminals 116b and the input terminal. There is. Further, the synthesis circuit 117 is provided with an input terminal corresponding to the operation selection terminal 111a, and a signal path is formed so as to electrically connect these operation selection terminals 111a and the input terminal. Further, the synthesis circuit 117 is provided with an input terminal corresponding to the target selection terminal 113b, and a signal path is formed so as to electrically connect the target selection terminal 113b and the input terminal.

The synthesis circuit 117 is provided with a synthesis logic circuit 117a. The signal output from the address output terminal 116b, the signal output from the operation selection terminal 111a, and the signal output from the target selection terminal 113b each pass through each NOT circuit in the synthesis logic circuit 117a, and are NAND in the synthesis logic circuit 117a. It is designed to be input to the circuit. Since the composite address signal, the operation selection signal, and the target selection signal are all LOW level signals, the LOW level is output from the synthesis circuit 117 in the situation where all of the composite address signal, the operation selection signal, and the target selection signal are output. A signal is output. Then, in the situation where the LOW level signal is output from the synthesis logic circuit 117a, the LOW level signal is output as the chip select signal from the chip select terminal CS0. That is, when the combined address signal is output from the address circuit 116, the operation selection signal is output from the operation selection circuit 111, and the target selection signal is output from the target selection circuit 113, the chip select terminal CS0 outputs the chip select. A signal is output. By outputting the chip select signal from the chip select terminal CS0, the data latched in the input latch circuit 103 corresponding to the chip select terminal CS0 is supplied to the data bus DB.

The synthesis circuit 117 outputs an HI level signal as a non-chip select signal when none of the composite address signal, the operation selection signal, and the target selection signal is output. In this case, the data latched in the input latch circuit 103 corresponding to the chip select terminal CS0 is not supplied to the data bus DB.

Next, a state in which the chip select signal is output from the chip select terminal CS0 will be described with reference to the time chart of FIG. FIG. 15 (a) shows a period during which 1-byte address data is output from the CPU core 102, and FIG. 15 (b) shows a period during which 2-byte address data is output from the CPU core 102. FIG. 15 (c). ) Indicates the period during which the combined address signal is output from the address circuit 116, FIG. 15 (d) indicates the period during which the operation selection signal is output from the operation selection circuit 111, and FIG. 15 (e) shows the period during which the operation selection signal is output from the CPU core 102. FIG. 15 (f) shows the period during which the IRQ signal is output, FIG. 15 (f) shows the period during which the MEQU signal is output from the CPU core 102, and FIG. 15 (g) shows the period during which the target selection signal is output from the target selection circuit 113. FIG. 15 (h) shows a period during which a chip select signal is output from the chip select terminal CS0.

First, a case where a chip select signal is output from the chip select terminal CS0 when an in instruction is executed in the CPU core 102 will be described.

At the timing of t1, the output of 1-byte address data is started from the CPU core 102 as shown in FIG. 15 (a), and the output of the IREC signal is started from the CPU core 102 as shown in FIG. 15 (e). Will be done. The output of the RD signal is started from the CPU core 102 at the timing of t1. Further, the address data output at the timing of t1 is the address data corresponding to the IO address decoder 114.

When the output of 1-byte address data is started at the timing of t1, the output of the IO address signal is started from the IO address decoder 114. Then, when the output of the IO address signal is started, the output of the combined address signal from the address circuit 116 is started at the timing of t2, as shown in FIG. 15 (c).

Further, since the output of the RD signal is started at the timing of t1, the output of the operation selection signal from the operation selection circuit 111 is started at the timing of t2 as shown in FIG. 15 (d). Further, when the output of the IRQ signal is started at the timing of t1, the output of the target selection signal from the target selection circuit 113 is started at the timing of t2, as shown in FIG. 15 (g).

By starting the output of all the combined address signal, operation selection signal and target selection signal at the timing of t2, the output of the chip select signal from the chip select terminal CS0 at the timing of t3 as shown in FIG. 15 (h). Is started. As a result, the data latched in the input latch circuit 103 corresponding to the chip select terminal CS0 is supplied to the data bus DB.

After that, at the timing of t4, the output of 1-byte address data from the CPU core 102 is stopped as shown in FIG. 15 (a), and the IREQ signal from the CPU core 102 is stopped as shown in FIG. 15 (e). Output is stopped. The output of the RD signal from the CPU core 102 is also stopped at the timing of t4. As a result, at the timing of t5, the output of the composite address signal is stopped as shown in FIG. 15 (c), the output of the operation selection signal is stopped as shown in FIG. 15 (d), and the output of the operation selection signal is stopped as shown in FIG. 15 (g). As shown, the output of the target selection signal is stopped. Then, when the output of these signals is stopped, the output of the chip select signal from the chip select terminal CS0 is stopped at the timing of t6 as shown in FIG. 15 (h). When the output of the chip select signal is stopped, the supply of the data latched in the input latch circuit 103 corresponding to the chip select terminal CS0 to the data bus DB is stopped.

The above operation flow is the same even when an out instruction is executed in the CPU core 102 when data is output to the output port 62b by using the output latch circuit 104.

Next, a case where a chip select signal is output from the chip select terminal CS0 when a load instruction is executed in the CPU core 102 will be described.

At the timing of t7, the output of 2-byte address data is started from the CPU core 102 as shown in FIG. 15 (b), and the output of the MRQ signal is started from the CPU core 102 as shown in FIG. 15 (f). Will be done. The output of the RD signal is started from the CPU core 102 at the timing of t7. Further, the address data output at the timing of t7 is the address data corresponding to the memory address decoder 115.

When the output of the 2-byte address data is started at the timing of t7, the output of the memory address signal is started from the memory address decoder 115. Then, when the output of the memory address signal is started, the output of the combined address signal from the address circuit 116 is started at the timing of t8, as shown in FIG. 15 (c).

Further, since the output of the RD signal is started at the timing of t7, the output of the operation selection signal from the operation selection circuit 111 is started at the timing of t8 as shown in FIG. 15 (d). Further, when the output of the MRQ signal is started at the timing of t7, the output of the target selection signal from the target selection circuit 113 is started at the timing of t8, as shown in FIG. 15 (g).

By starting the output of all the combined address signal, operation selection signal and target selection signal at the timing of t8, the output of the chip select signal from the chip select terminal CS0 at the timing of t9 as shown in FIG. 15 (h). Is started. As a result, the data latched in the input latch circuit 103 corresponding to the chip select terminal CS0 is supplied to the data bus DB.

After that, at the timing of t10, the output of the 2-byte address data from the CPU core 102 is stopped as shown in FIG. 15 (b), and the MRQ signal from the CPU core 102 is stopped as shown in FIG. 15 (f). Output is stopped. The output of the RD signal from the CPU core 102 is also stopped at the timing of t10. As a result, at the timing of t11, the output of the composite address signal is stopped as shown in FIG. 15 (c), the output of the operation selection signal is stopped as shown in FIG. 15 (d), and the output of the operation selection signal is stopped as shown in FIG. 15 (g). As shown, the output of the target selection signal is stopped. Then, when the output of these signals is stopped, the output of the chip select signal from the chip select terminal CS0 is stopped at the timing of t12 as shown in FIG. 15 (h). When the output of the chip select signal is stopped, the supply of the data latched in the input latch circuit 103 corresponding to the chip select terminal CS0 to the data bus DB is stopped.

As described above, the target selection circuit 113 is provided with a negative logic OR circuit in which each of the signal output from the IRQ terminal of the CPU core 102 and the signal output from the MCHECK terminal of the CPU core 102 are input signals. As a result, the target selection signal is output from the target selection circuit 113 regardless of whether the IRQ signal or the MREF signal is output from the CPU core 102. In this case, when data is input from the input port 62a using the input latch circuit 103 corresponding to the chip select terminal CS0, either the in command or the load command is executed by the CPU core 102. That is, regardless of whether the IRQ signal or the MRQ signal is output from the CPU core 102, it is possible to output the target selection signal from the target selection circuit 113 without switching the state of the target selection circuit 113. It becomes. This makes it possible to output a chip select signal from the chip select terminal CS0 regardless of whether the in instruction or the load instruction is executed while simplifying the processing configuration.

Further, the electric circuit corresponding to the chip select terminal CS0 is provided with an IO address decoder 114 corresponding to 1-byte address data and a memory address decoder 115 corresponding to 2-byte address data, and is provided with a CPU core. When 1 byte of address data is output from 102, an IO address signal is output from the IO address decoder 114, and when 2 bytes of address data is output from the CPU core 102, memory is output from the memory address decoder 115. The address signal is output. Then, when at least one of the IO address signal and the memory address signal is output, the combined address signal is output from the address circuit 116. In this case, when data is input from the input port 62a using the input latch circuit 103 corresponding to the chip select terminal CS0, either the in instruction or the load instruction is executed by the CPU core 102. That is, regardless of whether 1 byte of address data or 2 bytes of address data is output from the CPU core 102, the address circuit 116 does not switch the state of the circuit for outputting the address signal. It is possible to output a composite address signal from. This makes it possible to output a chip select signal from the chip select terminal CS0 regardless of whether the in instruction or the load instruction is executed while simplifying the processing configuration.

Next, the contents of the instruction execution process repeatedly executed in the CPU core 102 at a short cycle will be described with reference to the flowchart of FIG. The processing of FIG. 16 is executed by the CPU core 102, and as a result, the main processing (FIG. 6) and the timer interrupt processing (FIG. 7) already described in the MPU 62 of the main control device 60 are executed. ..

First, the instruction is read from the area of ROM 63 corresponding to the address specified by the current value of the program counter (step S301). When the read instruction is a 2-byte instruction (step S302: YES), it is determined whether or not the IO identification code is set for the instruction (step S303). When the IO identification code is not set (step S303: NO), it means that the current instruction is neither an in instruction nor an out instruction. Therefore, in the other processing of step S304, the processing corresponding to the current instruction is performed. To execute.

When the IO identification code is set in the current instruction (step S303: YES), it means that the current instruction is an in instruction or an out instruction, so the process proceeds to step S305. In step S305, the address code set in the first byte of the instruction read this time is set for the eight upper address terminals A0 to A7 to set the output of 1-byte address data. .. As a result, 1-byte address data is output from the address terminals A0 to A7. In this case, the output states of the remaining eight address terminals A8 to A15 are maintained in the previous output states. Further, in step S306, the output of the IRQ signal is started from the IRQ terminal of the CPU core 102.

After that, when the IO identification code in this instruction corresponds to the input of data from the input port 62a (step S307: YES), the output of the RD signal is started from the RD terminal of the CPU core 102 (step S308). On the other hand, when the IO identification code in this instruction corresponds to the output of data from the output port 62b (step S307: NO), the output of the WR signal is started from the WR terminal of the CPU core 102 (step S309). After that, 1 byte of output data is read from the area of ROM 63 corresponding to the address specified in the next value of the program counter referred to in step S301, and the output data is set in the data bus DB (step S310). ).

If the current instruction is not a 2-byte instruction (step S302: NO), it is determined whether or not the current instruction is a 3-byte instruction (step S311). If it is not a 3-byte instruction, it means that the instruction this time is a 1-byte instruction or an instruction of 4 bytes or more. Therefore, the processing corresponding to the instruction this time is executed in the other processing of step S304. When it is a 3-byte instruction (step S311: YES), the process for the 3-byte instruction is executed (step S312).

FIG. 17 is a flowchart showing a process for a 3-byte instruction.

When the 3-byte instruction this time is an input instruction to the input port 62a (step S401: YES), the first address code set in the first byte of the instruction read this time is set to the upper eight address terminals A0. By setting the 2nd address code set for the 2nd byte of the instruction read this time for the 8 lower address terminals A8 to A15, the 2 bytes are set. Set the output of address data. As a result, 2-byte address data is output from the address terminals A0 to A15.

After that, the output of the MRQ signal is started from the MRQ terminal of the CPU core 102 (step S403), and the output of the RD signal is started from the RD terminal of the CPU core 102 (step S404). After that, if the input instruction this time includes a logical operation instruction (step S405: YES), the logical operation process specified in this instruction is executed for the data input this time from the input port 62a. (Step S406). For example, when it is specified as an instruction to execute the AND process of the data stored and held in the register of the MPU 62 and the data input this time from the input port 62a, the AND process is executed.

When the 3-byte instruction this time is an output instruction for the output port 62b (step S407: YES), the output setting of the 2-byte address data is performed in the same manner as in step S402 (step S408). As a result, 2-byte address data is output from the address terminals A0 to A15.

After that, the output of the MRQ signal is started from the MRQ terminal of the CPU core 102 (step S409), and the output of the WR signal is started from the WR terminal of the CPU core 102 (step S410). After that, if the output instruction this time includes a shift instruction (step S411: YES), a process of shifting the bits of the data that is the source of the output this time to the output port 62b in a predetermined direction is executed (step S412). ). After that, the data to be output this time is set in the data bus DB (step S413).

When the 3-byte instruction this time is a read instruction (step S414: YES), the output setting of the 2-byte address data is performed in the same manner as in step S402 (step S415). As a result, 2-byte address data is output from the address terminals A0 to A15. After that, the output of the MRQ signal is started from the MRQ terminal of the CPU core 102 (step S416), and the output of the RD signal is started from the RD terminal of the CPU core 102 (step S417). As a result, data is read from the area corresponding to the current address data in the ROM 63 or the RAM 64.

When the 3-byte instruction this time is a write instruction (step S418: YES), the output setting of the 2-byte address data is performed in the same manner as in step S402 (step S419). As a result, 2-byte address data is output from the address terminals A0 to A15. After that, the output of the MRQ signal is started from the MRQ terminal of the CPU core 102 (step S420), and the output of the WR signal is started from the WR terminal of the CPU core 102 (step S421). After that, the data to be output this time is set in the data bus DB (step S422).

If the 3-byte instruction this time is not a write instruction (step S418: NO), other processing is executed (step S423). In other processing, for example, a calculation operation instruction or a bit manipulation instruction is executed.

According to the present embodiment described in detail above, the following excellent effects are obtained.

The CPU core 102 outputs an MEQU signal from the MEQU terminal when executing a load instruction, and outputs an IRQ signal from the IEQU terminal when executing an in instruction or an out instruction. This makes it possible to prevent data reading, data writing, and data input / output from being performed in a situation where none of the load instruction, the in instruction, and the out instruction is executed, and the load instruction can be prevented. It is possible to distinguish the operation target between the case where is executed and the case where the in instruction or the out instruction is executed. In this case, even if either the MRQ signal or the IRQ signal is output from the CPU core 102 from the synthesis circuit 117 for outputting the chip select signal to the input latch circuit 103 corresponding to the input port 62a. A chip select signal is output. This also applies to the configuration for outputting the chip select signal to the output latch circuit 104 corresponding to the output port 62b. As a result, it is possible to receive data from the input port 62a or set data to the output port 62b not only when the in instruction or the out instruction is executed but also when the load instruction is executed. It will be possible. Therefore, it is possible to widen the range of types of instructions executed when receiving data from the input port 62a or setting data to the output port 62b.

In a configuration in which the chip select signal is output from the synthesis circuit 117 on the condition that the target selection signal is output from the target selection circuit 113, the target selection circuit 113 outputs the IRQ signal or the MRQ signal. Since the configuration outputs the target selection signal, it is possible to achieve the above-mentioned excellent effect while diverting the configuration other than the target selection circuit 113 as it is.

The target selection circuit 113 is provided with a negative logic OR circuit in which each of the signal output from the IRQ terminal of the CPU core 102 and the signal output from the MCHECK terminal of the CPU core 102 is used as an input signal. The target selection signal is output from the target selection circuit 113 regardless of whether the IRQ signal or the MRQ signal is output from the core 102. In this case, when data is input from the input port 62a using the input latch circuit 103 corresponding to the chip select terminal CS0, either the in command or the load command is executed by the CPU core 102. That is, regardless of whether the IRQ signal or the MRQ signal is output from the CPU core 102, it is possible to output the target selection signal from the target selection circuit 113 without switching the state of the target selection circuit 113. It becomes. This makes it possible to output a chip select signal from the chip select terminal CS0 regardless of whether the in instruction or the load instruction is executed while simplifying the processing configuration.

When an in instruction or an out instruction is executed, 1 byte of address data is output from the CPU core 102, and when a load instruction is executed, 2 bytes of address data is output from the CPU core 102. This makes it possible to output the address data in a mode corresponding to each of the case of executing the in instruction or the out instruction and the case of executing the load instruction. Further, even if the configuration is such that 1 byte of address data is output when the in instruction or the out instruction is executed and 2 bytes of address data is output when the load instruction is executed, 1 byte is output. The chip select signal is output from the synthesis circuit 117 regardless of whether the address data of the above is output or the 2-byte address data is output. As a result, it is possible to receive data from the input port 62a or set data to the output port 62b not only when the in instruction or the out instruction is executed but also when the load instruction is executed. It will be possible.

The electric circuit corresponding to the chip select terminal CS0 is provided with an IO address decoder 114 corresponding to 1-byte address data and a memory address decoder 115 corresponding to 2-byte address data, from the CPU core 102. When 1-byte address data is output, the IO address signal is output from the IO address decoder 114, and when 2-byte address data is output from the CPU core 102, the memory address signal is output from the memory address decoder 115. Is output. Then, when at least one of the IO address signal and the memory address signal is output, the combined address signal is output from the address circuit 116. In this case, when data is input from the input port 62a using the input latch circuit 103 corresponding to the chip select terminal CS0, either the in instruction or the load instruction is executed by the CPU core 102. That is, regardless of whether 1 byte of address data or 2 bytes of address data is output from the CPU core 102, the address circuit 116 does not switch the state of the circuit for outputting the address signal. It is possible to output a composite address signal from. This makes it possible to output a chip select signal from the chip select terminal CS0 regardless of whether the in instruction or the load instruction is executed while simplifying the processing configuration.

<Second embodiment>
In this embodiment, it is possible to process the already output data and output the processed data without executing the process for separately storing the output data in the CPU core 102. It differs from the first embodiment in that it has a configuration. The different configurations will be described below. The description of the same configuration as that of the first embodiment is basically omitted.

FIG. 18 is an explanatory diagram for explaining the electrical configuration of the CPU 101 in the present embodiment.

The CPU 101 includes chip select terminals CS0 to CS12 as in the first embodiment. However, in the present embodiment, the chip select terminal CS0, the chip select terminal CS2, the chip select terminal CS4 and the chip select terminal CS6 are for outputting the chip select signal to the output latch circuits 121a to 121d. Other chip select terminals CS1, CS3, CS5, CS7 to CS12 are for outputting chip select signals to the input latch circuits 122a to 122i.

The chip select terminals CS0, CS2, CS4, CS6 corresponding to the output latch circuits 121a to 121d form a signal path between the corresponding output latch circuits 121a to 121d, and the input latch circuits 122a to 122i have a signal path. The corresponding chip select terminals CS1, CS3, CS5, CS7 to CS12 form a signal path with the corresponding input latch circuits 122a to 122i. Further, each of the output latch circuits 121a to 121d has a signal path formed between the data terminals D10 to D17 of the CPU 101 and the electrically connected data bus DB, and the data bus is formed from the data terminals D10 to D17. The data supplied to the DB can be latched by the output latch circuits 121a to 121d. Further, each of the input latch circuits 122a to 122i has a signal path formed between the data bus DB and the data bus DB, and temporarily stores and holds the data supplied from the output source of the corresponding data. It is possible to supply the data to the data bus DB as needed.

A plurality of (specifically, three) chip select terminals CS0, CS2, CS4, which are a part of the chip select terminals CS0, CS2, CS4, CS6 corresponding to the output latch circuits 121a to 121d, are connected to the output port 62b. The chip select signal is output to the output latch circuits 121a to 121c for outputting the data of the above, and the remaining chip select terminal CS6 is a chip to the output latch circuit 121d for outputting the data to the RAM 64. It is for outputting a select signal. In this case, the input latch circuits 122a to 122c are provided in a one-to-one correspondence with the output latch circuits 121a to 121c for outputting data to the output port 62b, and these output latch circuits 121a to 121a to The data output from the output port 62b from the 121c is latched by the input latch circuits 122a to 122c corresponding to the output latch circuits 121a to 121c of the output source. Specifically, the data paths L1 to L3 that electrically connect the output latch circuits 121a to 121c and the output port 62b are branched in the middle, and the branch paths L4 to L6 correspond to the input latch circuits. It is electrically connected to 122a to 122c. Then, the data latched in the input latch circuits 122a to 122c is output as a chip select signal from the chip select terminals CS1, CS3, CS5 provided in a one-to-one correspondence with the input latch circuits 122a to 122c. By doing so, the data is supplied to the data bus DB and input to the data terminals D10 to D17 of the CPU 101. As a result, when data is output to the output port 62b, the data to be output is read out and processed by the CPU core 102 without executing a process for separately storing the data to be output in the register of the CPU core 102 or the RAM 64. The processed data can be output to the output port 62b.

Next, a configuration for processing the data already output to the output port 62b in the CPU core 102 and outputting the processed data to the output port 62b will be described in detail. FIG. 19 is a block diagram showing an output circuit 131 for outputting a chip select signal to the output latch circuit 121a in the CPU 101, and an input circuit 141 for outputting a chip select signal to the input latch circuit 122a in the CPU 101. Is. Note that FIG. 19 shows an electrical configuration for outputting a chip select signal to a combination of other output latch circuits 121b and 121c for circulating output data to the output port 62b and input latch circuits 122b and 122c. It is the same as the electrical configuration shown.

The output circuit 131 is electrically connected to the operation selection circuit 132 electrically connected to the RD terminal and the WR terminal, and the IRQ terminal and the MRQ terminal, as in the electrical configuration shown in FIG. 14 in the first embodiment. When the target selection circuit 133 connected to the CPU core 102, the IO address decoder 134 in which 1 byte of address data is input when the out instruction is executed, and the load instruction are executed in the CPU core 102. The memory address decoder 135 into which 2-byte address data is input, the address circuit 136 electrically connected to the IO address decoder 134 and the memory address decoder 135, the address circuit 136, the operation selection circuit 132, and the operation selection circuit 132. It includes a synthesis circuit 137 electrically connected to the target selection circuit 133. The specific configurations of the operation selection circuit 132, the target selection circuit 133, the IO address decoder 134, the memory address decoder 135, the address circuit 136, and the synthesis circuit 137 are the same as those in the first embodiment.

In the switch circuit 132a provided in the operation selection circuit 132, the initialization signal is input when the supply of the operation power to the CPU 101 is started, so that the signal that triggers the output of the operation selection signal is from the RD terminal. It is set to be a WR signal among the RD signal and the WR signal from the WR terminal. Therefore, when the WR signal is output from the CPU core 102, the operation selection signal is output from the operation selection circuit 132.

The target selection circuit 133 outputs the target selection signal regardless of whether the IRQ signal or the MCHECK signal is output from the CPU core 102. The IO address decoder 134 outputs an IO address signal when the 1-byte address data corresponding to the IO address decoder 134 is output from the CPU core 102. The memory address decoder 135 outputs a memory address signal when the 2-byte address data corresponding to the memory address decoder 135 is output from the CPU core 102. The address circuit 136 outputs a composite address signal when either the IO address signal or the memory address signal is output. The synthesis circuit 137 outputs a chip select signal from the chip select terminal CS0 to the output latch circuit 121a when all of the composite address signal, the operation selection signal, and the target selection signal are output. As a result, the data set in the data terminals D0 to D7 of the CPU core 102 is latched to the output latch circuit 121a, and the data is latched to each area of the output port 62b corresponding to the output latch circuit 121a. The data is output. Further, this output data is latched in the input latch circuit 122a through the data path L1 and the branch path L4.

The input circuit 141 is electrically connected to the operation selection circuit 142 electrically connected to the RD terminal and the WR terminal, and the IRQ terminal and the MRQ terminal, as in the electrical configuration shown in FIG. 14 in the first embodiment. When the target selection circuit 143 connected to the CPU core 102, the IO address decoder 144 to which 1 byte of address data is input when the out instruction is executed, and the load instruction are executed in the CPU core 102. A memory address decoder 145 into which 2-byte address data is input, an address circuit 146 electrically connected to an IO address decoder 144 and a memory address decoder 145, an address circuit 146, an operation selection circuit 142, and an operation selection circuit 142. It includes a synthesis circuit 147 electrically connected to the target selection circuit 143. The specific configurations of the operation selection circuit 142, the target selection circuit 143, the IO address decoder 144, the memory address decoder 145, the address circuit 146, and the synthesis circuit 147 are the same as those in the first embodiment.

Although it is shown in FIG. 19 that the CPU core 102 is provided with two address terminals A0 to A15, two RD terminals, two WR terminals, two IRQ terminals, and two MRQ terminals, in reality, the CPU core 102 is provided. Only one of these terminals is provided, and by branching the signal path extending from each terminal, the signal from each terminal is supplied to each of the output circuit 131 and the input circuit 141. There is.

In the switch circuit 142a provided in the operation selection circuit 142, the initialization signal is input when the supply of the operation power to the CPU 101 is started, so that the signal that triggers the output of the operation selection signal is from the RD terminal. It is set to be an RD signal among the RD signal and the WR signal from the WR terminal. Therefore, when the RD signal is output from the CPU core 102, the operation selection signal is output from the operation selection circuit 142.

The target selection circuit 143 outputs the target selection signal regardless of whether the IRQ signal or the MCHECK signal is output from the CPU core 102. The IO address decoder 144 outputs an IO address signal when the 1-byte address data corresponding to the IO address decoder 144 is output from the CPU core 102. The memory address decoder 145 outputs a memory address signal when the 2-byte address data corresponding to the memory address decoder 145 is output from the CPU core 102. The address circuit 146 outputs a composite address signal when either the IO address signal or the memory address signal is output. The synthesis circuit 147 outputs a chip select signal from the chip select terminal CS1 to the input latch circuit 122a when all of the composite address signal, the operation selection signal, and the target selection signal are output. As a result, the data latched by the input latch circuit 122a is supplied to the data bus DB, and the supplied data is acquired in the CPU core 102. This acquired data is the data previously output to the corresponding area of the output port 62b using the output latch circuit 121a.

Here, the 1-byte address data that triggers the output of the IO address signal from the IO address decoder 144 of the input circuit 141 triggers the output of the IO address signal from the IO address decoder 134 of the output circuit 131. It is the same as the 1-byte address data. Further, the 2-byte address data that triggers the output of the memory address signal from the memory address decoder 145 of the input circuit 141 triggers the output of the memory address signal from the memory address decoder 135 of the output circuit 1312. It is the same as the byte address data. As a result, the address data for outputting the chip select signal from the output circuit 131 to the output latch circuit 121a and the address data for outputting the chip select signal from the input circuit 141 to the input latch circuit 122a are the same. It is possible to use the data of. Therefore, it is possible to process the data that has already been output to the output port 62b in the CPU core 102 and output the processed data to the output port 62b by designating one address data.

Further, even if the configuration is such that the chip select signal is output to the output latch circuit 121a and the chip select signal is output to the input latch circuit 122a by designating one address data, the chip to the output latch circuit 121a is output. The output of the select signal is performed when the WR signal is output from the CPU core 102, and the output of the chip select signal to the input latch circuit 122a is performed when the RD signal is output from the CPU core 102. Therefore, it is possible to make the output timing of the data using the output latch circuit 121a different from the input timing of the data using the input latch circuit 122a.

Next, when the processing performed by processing the data already output to the output port 62b in the CPU core 102 and outputting the processed data to the output port 62b is used for display control in the special figure display unit 37a. Will be explained.

FIG. 20A is a front view of the special figure display unit 37a. The special figure display unit 37a is provided with eight light emitting units 151 to 158. Each light emitting unit 151 to 158 has an individual light source composed of LEDs, and by controlling the on / off of these individual light sources, it is possible to light only one arbitrary light emitting unit 151 to 158. , Any combination of light emitting units 151 to 158 can be turned on. Since all of the above individual light sources irradiate light of the same color, the same color is displayed in each of the light emitting units 151 to 158, but the present invention is not limited to this. The light emitting units 151 to 158 may be configured to display different colors. Of the light emitting units 151 to 158, the seven first to seventh light emitting units 151 to 158 are all linear display segments, and the first to seventh light emitting units 151 to so as to be a so-called 7-segment display. 158 are arranged. Further, the remaining one eighth light emitting unit 158 is a circular light emitting unit, and is provided at a position adjacent to the first to seventh light emitting units 151 to 158.

FIG. 20B is an explanatory diagram for explaining an output area 159 in which data defining the contents of data output to the first to eighth light emitting units 151 to 158 is set in the output port 62b.

The output area 159 has a 1-byte data structure, and each bit corresponds to the 1st to 8th light emitting units 151 to 158 on a one-to-one basis. Specifically, in the output area 159, the first bit 159a corresponding to the first light emitting unit 151, the second bit 159b corresponding to the second light emitting unit 152, and the third bit 159c corresponding to the third light emitting unit 153 The fourth bit 159d corresponding to the fourth light emitting unit 154, the fifth bit 159e corresponding to the fifth light emitting unit 155, the sixth bit 159f corresponding to the sixth light emitting unit 156, and the seventh light emitting unit 157. A corresponding 7th bit 159g and an 8th bit 159h corresponding to the 8th light emitting unit 158 are provided. The main control board 61 is provided with a drive circuit for outputting a drive signal to the first to eighth light emitting units 151 to 158 based on the data set in the output area 159. In the drive circuit, the light emitting units 151 to 158 corresponding to the bits 159a to 159h in which the data of "1" corresponding to the light emission compatible data among the first to eighth bits 159a to 159h are set to emit light are turned off. Light emission control is executed for the first to eighth light emitting units 151 to 158 so that the light emitting units 151 to 158 corresponding to the bits 159a to 159h in which the data of "0" corresponding to the corresponding data is set are turned off. ..

FIG. 21 is an explanatory diagram for explaining the relationship between the contents set in the output area 159 and the light emitting modes of the first to eighth light emitting units 151 to 158. 21 (a1) to 21 (a8) are explanatory views for explaining the contents of the data set in the output area 159, and FIGS. 21 (b1) to 21 (b8) are first to eighth. It is explanatory drawing for demonstrating the light emission mode of the light emitting part 151 to 158.

When "1" is set only in the first bit 159a of the output area 159 as shown in FIG. 21 (a1), the first to eighth light emitting units 151 to 158 are set as shown in FIG. 21 (b1). Of these, only the first light emitting unit 151 is turned on and the rest are turned off. From this state, as shown in FIGS. 21 (a2) to 21 (a8), the bits 159a to 159h in which "1" is set are the first bit 159a → the second bit 159b → the third bit 159c → the fourth. By shifting in the order of bit 159d → fifth bit 159e → sixth bit 159f → seventh bit 159g → eighth bit 159h, the light emitting state is set as shown in FIGS. 21 (b2) to 21 (b8). The light emitting units 151 to 158 are the first light emitting unit 151 → the second light emitting unit 152 → the third light emitting unit 153 → the fourth light emitting unit 154 → the fifth light emitting unit 155 → the sixth light emitting unit 156 → the seventh light emitting unit 157 → the eighth. It changes in the order of the light emitting unit 158. As a result, it is possible to change the display content of the special figure display unit 37a only by changing the bit for setting "1" in the output area 159.

Next, the control process of the special figure display unit executed by the MPU 62 of the main control device 60 will be described with reference to the flowchart of FIG. The control process of the special figure display unit is executed in the display control process (step S215) in the timer interrupt process (FIG. 7).

When the variation start condition of the special figure display unit 37a is satisfied even when the variation display of the special figure display unit 37a is not satisfied (step S501: NO, step S502: YES), the drive for the variation start which is a 3-byte instruction. The instruction is read from the ROM 63 (step S503). Then, the first address code set in the first byte of the read instruction is set for the eight upper address terminals A0 to A7 in the CPU core 102, and the second of the read instructions is set. By setting the second address code set in the bytes of the CPU core 102 for the eight lower address terminals A8 to A15 of the CPU core 102, the output of the 2-byte address data is set (step S504). As a result, 2-byte common address data is output from the address terminals A0 to A15.

After that, the output of the MRQ signal is started from the MRQ terminal of the CPU core 102 (step S505), and the output of the WR signal is started from the WR terminal of the CPU core 102 (step S506). After that, the drive data at the start of fluctuation is read from the area of ROM 63 corresponding to the next value with respect to the value of the program counter corresponding to the instruction read in step S503, and the data to be output this time is set to the data bus DB. And set (step S507). For the drive data at the start of fluctuation, "1" is set only in the first bit 159a of the first to eighth bits 159a to 159h of the output area 159, and "0" is set in the remaining bits 159a to 159h. It is the drive data for doing so. By executing the process of step S507, the drive data at the start of fluctuation is latched in the output latch circuit 121a, and the data corresponding to the drive data at the start of fluctuation is the first to eighth bits 159a of the output area 159. It is set to ~ 159h. As a result, the variable display of the pattern is started on the special figure display unit 37a. Further, the data output from the output latch circuit 121a to the output area 159 is latched by the input latch circuit 122a.

When the variation display of the special figure display unit 37a is in progress (step S501: YES), when it is not the end timing of the current variation display (step S508: NO), and when it is the update timing of the display content (step S509). : YES) Read the update drive instruction, which is a 3-byte instruction, from the ROM 63 (step S510). Then, the first address code set in the first byte of the read instruction is set for the eight upper address terminals A0 to A7 in the CPU core 102, and the second of the read instructions is set. By setting the second address code set in the bytes of the CPU core 102 for the eight lower address terminals A8 to A15 of the CPU core 102, the output of the 2-byte address data is set (step S511). As a result, 2-byte common address data is output from the address terminals A0 to A15.

After that, the output of the MRQ signal is started from the MRQ terminal of the CPU core 102 (step S512), and the output of the RD signal is started from the RD terminal of the CPU core 102 (step S513). As a result, the drive data latched by the input latch circuit 122a is provided to the data bus DB, and the drive data is read out to the CPU core 102. This drive data is the drive data currently set in the output area 159.

After that, the rotation processing of the drive data is executed according to the instruction read in step S510 (step S514). Specifically, the rotation process is executed so that each bit of the drive data acquired from the input latch circuit 122a orbits in a predetermined direction. As a result, as shown in FIGS. 21 (a1) to 21 (a8), the bit in which "1" is set in the drive data is shifted so as to orbit in a predetermined direction.

After that, according to the instruction read in step S510, the output setting of the common address data is performed in the same manner as in step S511 (step S515). Then, the output of the MRQ signal is started from the MRQ terminal of the CPU core 102 (step S516), the output of the WR signal is started from the WR terminal of the CPU core 102 (step S517), and the rotation process is further executed in step S514. The drive data after this is set in the data bus DB as the data to be output this time (step S518). As a result, the current drive data is latched in the output latch circuit 121a, and the data corresponding to the drive data is set in the first to eighth bits 159a to 159h of the output area 159. As a result, the display content on the special figure display unit 37a is changed. Further, the data output from the output latch circuit 121a to the output port 62b is latched by the input latch circuit 122a.

The processing contents of steps S510 to S518 are executed each time the display contents are updated before the end timing of the variable display. The update drive instruction data read in this case is always the same instruction. This makes it possible to execute the display control of the special figure display unit 37a while suppressing the number of types of instructions stored in the ROM 63 in advance.

When it is the end timing of the variable display (step S508: YES), the variable display end process is executed (step S519). As a result, the drive data corresponding to the hit / fail judgment result and the distribution judgment result of this game round is set in the output area 159, and the special figure is displayed so as to be the display content corresponding to these hit / miss judgment result and the distribution judgment result. The display of unit 37a is controlled.

According to the present embodiment described in detail above, in addition to the effects in the first embodiment, the following excellent effects are exhibited.

Input latch circuits 122a to 122c are provided in a one-to-one correspondence with output latch circuits 121a to 121c for outputting data to the output port 62b, and output ports are provided from these output latch circuits 121a to 121c. The data output to 62b is configured to be latched by the input latch circuits 122a to 122c corresponding to the output latch circuits 121a to 121c of the output source. Then, the data latched in the input latch circuits 122a to 122c is output as a chip select signal from the chip select terminals CS1, CS3, CS5 provided in a one-to-one correspondence with the input latch circuits 122a to 122c. By doing so, the data is supplied to the data bus DB and input to the data terminals D10 to D17 of the CPU 101. As a result, when data is output to the output port 62b, the data to be output is read out and processed by the CPU core 102 without executing a process for separately storing the data to be output in the register of the CPU core 102 or the RAM 64. The processed data can be output to the output port 62b.

The input latch circuits 122a to 122c supply the acquired output data to the data bus DB. This makes it possible to supply output data to the CPU core 102 by using the existing transmission path configuration.

By outputting the chip select signal from the chip select terminals CS1, CS3, CS5, the data latched by the input latch circuits 122a to 122c is supplied to the data bus DB and input to the data terminals D10 to D17 of the CPU 101. With the configuration, it is possible to acquire data from the input latch circuits 122a to 122c at a preferable timing in the control of the CPU 101.

The data paths L1 to L3 that electrically connect the output latch circuits 121a to 121c and the output ports 62b are branched in the middle, and the branch paths L4 to L6 correspond to the input latch circuits 122a to 122c. It is electrically connected. This makes it possible to reacquire the output data in the CPU core 102 without incorporating the input latch circuits 122a to 122c in the CPU 101.

The 1-byte address data that triggers the output of the IO address signal from the IO address decoder 144 of the input circuit 141 is the 1-byte address data that triggers the output of the IO address signal from the IO address decoder 134 of the output circuit 131. It is the same as the address data. Further, the 2-byte address data that triggers the output of the memory address signal from the memory address decoder 145 of the input circuit 141 triggers the output of the memory address signal from the memory address decoder 135 of the output circuit 1312. It is the same as the byte address data. As a result, the address data for outputting the chip select signal from the output circuit 131 to the output latch circuit 121a and the address data for outputting the chip select signal from the input circuit 141 to the input latch circuit 122a are the same. It is possible to use the data of. Therefore, it is possible to process the data that has already been output to the output port 62b in the CPU core 102 and output the processed data to the output port 62b by designating one address data.

Even if the configuration is such that the chip select signal is output to the output latch circuit 121a and the chip select signal is output to the input latch circuit 122a by designating one address data, the chip select signal to the output latch circuit 121a is output. Is output when the WR signal is output from the CPU core 102, and the chip select signal is output to the input latch circuit 122a when the RD signal is output from the CPU core 102. Therefore, it is possible to make the output timing of the data using the output latch circuit 121a different from the input timing of the data using the input latch circuit 122a.

<Third embodiment>
In this embodiment, the output latch circuit 162 and the input latch circuit 163 used when processing the data already output to the output port 62b in the CPU core 102 and outputting the processed data to the output port 62b are provided. It differs from the second embodiment in that it is not provided outside the CPU 101 but is built in the CPU 101. The different configurations will be described below. The description of the same configuration as that of the second embodiment is basically omitted.

FIG. 23 is a block diagram showing an electrical configuration of the CPU 101.

The CPU 101 includes an output circuit 171 for simultaneously outputting a chip select signal to each of an external output latch circuit 161 provided outside the CPU 101 and an internal output latch circuit 162 provided inside the CPU 101. Only the internal input latch circuit 163 provided inside the CPU 101 is provided with an input circuit 181 for outputting a chip select signal.

The output circuit 171 is electrically connected to the operation selection circuit 172 electrically connected to the RD terminal and the WR terminal, and the IRQ terminal and the MRQ terminal, as in the electrical configuration shown in FIG. 14 in the first embodiment. When the target selection circuit 173 connected to the CPU core 102, the IO address decoder 174 in which 1 byte of address data is input when the out instruction is executed, and the load instruction are executed in the CPU core 102. A memory address decoder 175 to which 2-byte address data is input, an address circuit 176 electrically connected to an IO address decoder 174 and a memory address decoder 175, an address circuit 176, an operation selection circuit 172, and an operation selection circuit 172. It includes a synthesis circuit 177 that is electrically connected to the target selection circuit 173. The specific configurations of the operation selection circuit 172, the target selection circuit 173, the IO address decoder 174, the memory address decoder 175, the address circuit 176, and the synthesis circuit 177 are the same as those in the first embodiment.

In the switch circuit 172a provided in the operation selection circuit 172, the initialization signal is input when the supply of the operation power to the CPU 101 is started, so that the signal that triggers the output of the operation selection signal is from the RD terminal. It is set to be a WR signal among the RD signal and the WR signal from the WR terminal. Therefore, when the WR signal is output from the CPU core 102, the operation selection signal is output from the operation selection circuit 172.

The target selection circuit 173 outputs the target selection signal regardless of whether the IRQ signal or the MCHECK signal is output from the CPU core 102. The IO address decoder 174 outputs an IO address signal when the 1-byte address data corresponding to the IO address decoder 174 is output from the CPU core 102. The memory address decoder 175 outputs a memory address signal when the 2-byte address data corresponding to the memory address decoder 175 is output from the CPU core 102. The address circuit 176 outputs a composite address signal when either the IO address signal or the memory address signal is output. The synthesis circuit 177 outputs a chip select signal from the chip select terminal CS0 to the external output latch circuit 161 when all of the composite address signal, the operation selection signal, and the target selection signal are output. As a result, the data set in the data terminals D0 to D7 of the CPU core 102 is latched by the external output latch circuit 161 and the latch is made to each area of the output port 62b corresponding to the external output latch circuit 161. The data is output.

Further, the signal path L7 that electrically connects the output terminal of the synthesis logic circuit 177a provided in the synthesis circuit 177 and the chip select terminal CS0 is branched at an intermediate position thereof, and the branch path L8 is an internal output. It is electrically connected to the latch circuit 162. As a result, when the chip select signal is output from the chip select terminal CS0 to the external output latch circuit 161, the chip select signal is also output to the internal output latch circuit 162. Then, the internal output latch circuit 162 is the same as the data set in the data terminals D0 to D7 of the CPU core 102, that is, the data latched in the external output latch circuit 161 by inputting the chip select signal. Latch the data.

The internal output latch circuit 162 is electrically connected to the internal input latch circuit 163 through the data path L9. Therefore, the data latched in the internal output latch circuit 162 is supplied to the internal input latch circuit 163 through the data path L9.

The input circuit 181 is electrically connected to the operation selection circuit 182, which is electrically connected to the RD terminal and the WR terminal, and the IRQ terminal and the MRQ terminal, as in the electrical configuration shown in FIG. 14 in the first embodiment. When the target selection circuit 183 connected to the CPU core 102, the IO address decoder 184 in which 1 byte of address data is input when the out instruction is executed, and the load instruction are executed in the CPU core 102. A memory address decoder 185 to which 2-byte address data is input, an address circuit 186 electrically connected to an IO address decoder 184 and a memory address decoder 185, an address circuit 186, an operation selection circuit 182, and an operation selection circuit 182. It includes a target selection circuit 183 and an electrically connected synthesis circuit 187. The specific configurations of the operation selection circuit 182, the target selection circuit 183, the IO address decoder 184, the memory address decoder 185, the address circuit 186, and the synthesis circuit 187 are the same as those in the first embodiment.

Although it is shown in FIG. 23 that the CPU core 102 is provided with two address terminals A0 to A15, two RD terminals, two WR terminals, two IRQ terminals, and two MRQ terminals, in reality, the CPU core 102 is provided. Only one of these terminals is provided, and by branching the signal path extending from each terminal, the signal from each terminal is supplied to each of the output circuit 171 and the input circuit 181. There is.

In the switch circuit 182a provided in the operation selection circuit 182, the initialization signal is input when the supply of the operation power to the CPU 101 is started, so that the signal that triggers the output of the operation selection signal is from the RD terminal. It is set to be the RD signal among the RD signal and the WR signal from the WR terminal. Therefore, when the RD signal is output from the CPU core 102, the operation selection signal is output from the operation selection circuit 182.

The target selection circuit 183 outputs the target selection signal regardless of whether the IRQ signal or the MCHECK signal is output from the CPU core 102. The IO address decoder 184 outputs an IO address signal when the 1-byte address data corresponding to the IO address decoder 184 is output from the CPU core 102. The memory address decoder 185 outputs a memory address signal when the 2-byte address data corresponding to the memory address decoder 185 is output from the CPU core 102. The address circuit 186 outputs a composite address signal when either the IO address signal or the memory address signal is output. When all of the composite address signal, the operation selection signal, and the target selection signal are output, the synthesis circuit 187 electrically connects the output terminal 187a of the synthesis circuit 187 and the internal input latch circuit 163 to the CPU 101. A chip select signal is output to the internal input latch circuit 163 through the signal path L10 provided inside. As a result, the data latched by the internal input latch circuit 163 is supplied to the data bus DB, and the supplied data is acquired in the CPU core 102. This acquired data is the data previously output to the corresponding area of the output port 62b using the external output latch circuit 161.

Here, the 1-byte address data that triggers the output of the IO address signal from the IO address decoder 184 of the input circuit 181 serves as an opportunity to output the IO address signal from the IO address decoder 174 of the output circuit 171. It is the same as the 1-byte address data. Further, the 2-byte address data that triggers the output of the memory address signal from the memory address decoder 185 of the input circuit 181 triggers the output of the memory address signal from the memory address decoder 175 of the output circuit 1712. It is the same as the byte address data. As a result, the address data for outputting the chip select signal from the output circuit 171 to the external output latch circuit 161 and the internal output latch circuit 162, and the chip select signal from the input circuit 181 to the internal input latch circuit 163 are transmitted. It is possible to make the same data as the address data for output. Therefore, it is possible to process the data that has already been output to the output port 62b in the CPU core 102 and output the processed data to the output port 62b by designating one address data.

Further, even in a configuration in which the chip select signal is output to the respective output latch circuits 161, 162 and the chip select signal is output to the internal input latch circuit 163 by designating one address data, each output latch is obtained. The output of the chip select signal to the circuits 161, 162 is performed when the WR signal is output from the CPU core 102, and the output of the chip select signal to the internal input latch circuit 163 is the output of the RD signal from the CPU core 102. It is done when it is done. Therefore, it is possible to make the output timing of the data using the respective output latch circuits 161, 162 different from the data input timing using the internal input latch circuit 163.

According to the present embodiment described in detail above, in addition to the effects in the second embodiment, the following excellent effects are exhibited.

An internal input latch circuit 163 for supplying output data to the CPU core 102 again is built in the CPU 101. As a result, it is not necessary to provide the CPU 101 with a terminal for outputting a chip select signal for supplying data from the internal input latch circuit 163 to the data bus DB. Therefore, it is possible to supply the output data to the CPU core 102 again while suppressing the increase in the number of terminals of the CPU 101.

<Common configuration in each embodiment>
The configuration for accessing the ROM 63 or the RAM 64 in each embodiment will be described. FIG. 24 is a block diagram showing an electrical configuration for outputting a chip select signal to the corresponding input latch circuit when reading data from the RAM 64. When reading an instruction or data from the ROM 63, the electrical configuration for outputting the chip select signal to the corresponding input latch circuit is the same as the electrical configuration shown in FIG. 24. Further, when writing data to the RAM 64, the electrical configuration for outputting the chip select signal to the corresponding output latch circuit is such that the signal that triggers the output of the operation selection signal from the operation selection circuit 191 is an RD signal. Other than that, it is the same as the electrical configuration shown in FIG. 24, although it differs in that it is a WR signal.

The circuit for outputting the chip select signal that triggers the reading of the data from the RAM 64 is the operation selection circuit 191 electrically connected to the RD terminal and the WR terminal, and the target electrically connected to the IRQ terminal and the MRQ terminal. Two bytes of address data are input when the load instruction is executed in the selection circuit 192, the initialization circuit 193 for outputting the initialization signal to the operation selection circuit 191 and the target selection circuit 192, and the CPU core 102. The memory address decoder 194, the operation selection circuit 191 and the target selection circuit 192, and the synthesis circuit 195 electrically connected to the memory address decoder 194 are provided.

In the switch circuit 191a provided in the operation selection circuit 191, an initialization signal is input when the supply of the operation power to the CPU 101 is started, so that the signal that triggers the output of the operation selection signal is from the RD terminal. It is set to be the RD signal among the RD signal and the WR signal from the WR terminal. Therefore, when the RD signal is output from the CPU core 102, the operation selection signal is output from the operation selection circuit 191.

In the switch circuit 192a provided in the target selection circuit 192, the initialization signal is input when the supply of the operating power to the CPU 101 is started, so that the signal that triggers the output of the target selection signal is from the IREC terminal. It is set to be the MRQ signal among the IRQ signal and the MRQ signal from the MRQ terminal. Therefore, when the MRQ signal is output from the CPU core 102, the target selection signal is output from the target selection circuit 192.

The memory address decoder 194 is a memory when the 2-byte address data corresponding to the memory address decoder 194, in other words, the 2-byte address data corresponding to the data read from the RAM 64 is output from the CPU core 102. Output the address signal. The synthesis circuit 195 outputs a chip select signal from the chip select terminal CS20 to the input latch circuit when all of the memory address signal, the operation selection signal, and the target selection signal are output. As a result, the data written in the area corresponding to the current address designation in the RAM 64 is supplied to the data bus DB, and the data is supplied to the CPU core 102 through the data terminals D0 to D7.

<Other embodiments>
It should be noted that the description is not limited to the above-described embodiment, and various modifications and improvements can be made without departing from the spirit of the present invention. For example, it may be changed as follows. Incidentally, the following configuration of another embodiment may be applied individually or in combination to the configuration of the above embodiment.

(1) In the first embodiment, the IO address decoder 114 and the memory address decoder 115 are separately provided in the circuit corresponding to one chip select terminal CS0, but the memory is used. Similar to the address decoder 115, the configuration may be such that one address decoder provided with an input terminal corresponding to the address terminals A0 to A15 on a one-to-one basis is provided. In this case, when the predetermined 1-byte address data is output from the eight address terminals A0 to A7 on the upper side, the address decoder is output from the eight address terminals A8 to A15 on the lower side. Regardless of the content of the existing address data, the address signal (corresponding to the composite address signal in the first embodiment) is output to the synthesis circuit 117. Even in this configuration, the output of the RD signal from the CPU core 102, the output of either the IRQ signal or the MCHECK signal from the CPU core 102, and the output of the predetermined 2-byte address data from the CPU core 102 are performed. In this case, it is possible to output the chip select signal from the chip select terminal CS0. Further, in the case of the configuration, the configuration can be simplified as compared with the first embodiment in that only one address decoder is required. The configuration may be applied as a circuit configuration for outputting a chip select signal to the output latch circuit, or may be applied to the second embodiment or the third embodiment.

(2) In the configuration of (1) above, when accessing the IO space 105, predetermined 1-byte address data is output from the eight address terminals A0 to A7 on the upper side and the eight address data on the lower side. The control content of the CPU core 102 is set so that all "0" or all "1" data is output from the address terminals A8 to A15, and is set in the load instruction when accessing the memory space 106. The 2-byte address data may be output from the address terminals A0 to A15. In this case, even if a predetermined 1-byte address data is output from the 8 address terminals A0 to A7 on the upper side, 1 byte is output from the 8 address terminals A8 to A15 on the lower side. If the address data of is specific data, the chip select signal is not output from the chip select terminal CS0. As a result, even if the 1-byte address data on the upper side is predetermined data, if the 1-byte address data on the lower side is specific data, the chip from the chip select terminal different from the chip select terminal CS0 It can be used as an address that triggers the output of the select signal. The configuration may be applied as a circuit configuration for outputting a chip select signal to the output latch circuit, or may be applied to the second embodiment or the third embodiment.

(3) In the first embodiment, the IO address decoder 114 and the memory address decoder 115 are separately provided in the circuit corresponding to one chip select terminal CS0, but for IO. Similar to the address decoder 114, the configuration may be such that one address decoder provided with an input terminal corresponding to the address terminals A0 to A7 on a one-to-one basis is provided. In this case, when the address data of a predetermined 1 byte is input from the eight address terminals A0 to A7 on the upper side of the address decoder, the address signal (the first embodiment described above) is sent to the synthesis circuit 117. It is configured to output (corresponding to the combined address signal in the form). Even in this configuration, the output of the RD signal from the CPU core 102, the output of either the IRQ signal or the MCHECK signal from the CPU core 102, and the output of the predetermined 2-byte address data from the CPU core 102 are performed. In this case, it is possible to output the chip select signal from the chip select terminal CS0. Further, in the case of the configuration, the configuration can be simplified as compared with the first embodiment in that only one address decoder is required. The configuration may be applied as a circuit configuration for outputting a chip select signal to the output latch circuit, or may be applied to the second embodiment or the third embodiment.

(4) In the first embodiment, the target selection circuit 113 is not provided, and the composite address signal is output from the address circuit 116 and the operation selection signal is output from the operation selection circuit 111. The chip select signal may be output from the circuit 117. In this case, the chip select signal can be output even in a situation where both the IRQ signal and the MREF signal are not output from the CPU core 102, but the chip select signal is output from the CPU core 102 in order to be output. It is necessary that either the RD signal or the WR signal is output and the predetermined address data is output. The configuration may be applied as a circuit configuration for outputting a chip select signal to the output latch circuit, or may be applied to the second embodiment or the third embodiment.

(5) In each of the above embodiments, chip select is used for a circuit for outputting a chip select signal to an input latch circuit for inputting data from the input port 62a and an output latch circuit for collecting data to the output port 62b. All of the circuits for outputting the signal are not limited to the configuration in which the chip select signal is output regardless of whether the IRQ signal or the MCHECK signal is output from the CPU core 102, and the circuit for outputting the signal is not limited to the configuration. A part of them may be configured to output the chip select signal when the IRQ signal is output from the CPU core 102, but not to output the chip select signal when the MCHECK signal is output. In this case, the target selection circuit of the part of the circuit is configured to output the target selection signal only when the IRQ signal is output. Further, the part of the circuit is provided with the IO address decoder, but is not provided with the memory address decoder and the address circuit. In this configuration, the synthesis circuit mounted on a part of the circuits inputs the IO address signal from the IO address decoder, the operation selection signal from the operation selection circuit, and the target selection signal from the target selection circuit. In this case, the chip select signal will be output.

(6) In the third embodiment, the internal output latch circuit 162 may not be provided. In this case, the data transmission path from the external output latch circuit 161 to the output port 62b is branched, and the branch path is electrically connected to the internal input latch circuit 163 to output from the external output latch circuit 161. The data set in the port 62b can be latched in the internal input latch circuit 163.

(7) In the third embodiment, the internal input latch circuit 163 may not be provided, and instead, the function of the internal input latch circuit 163 may be carried by the register of the RAM 64 or the CPU 101. In this case, it is possible to simplify the configuration as compared with the third embodiment in that it is not necessary to provide the internal input latch circuit 163.

(8) Instead of the configuration in which the input port 62a of the MPU 62 is provided with a number of connection terminals larger than one byte, a configuration in which connection terminals for one byte may be provided may be used. In this configuration, a plurality of input latch circuits are provided on the main control board 61, and the MPU 62 is provided with a number of chip select terminals corresponding to those input latch circuits on a one-to-one basis, so that the chip select signal can be output. Data may be input to the input port 62a from the input latch circuit, and the data input to the input port 62a may be supplied to the CPU 101.

Further, instead of the configuration in which the output port 62b of the MPU 62 is provided with a number of connection terminals larger than one byte, a configuration in which connection terminals for one byte may be provided may be used. In this configuration, a plurality of output latch circuits are provided on the main control board 61, and the MPU 62 is provided with a number of chip select terminals corresponding to those output latch circuits on a one-to-one basis, so that the chip select signal can be output. Data may be output from the output port 62b to the output latch circuit.

(9) Display control based on the command transmitted from the main control device 60 instead of the configuration in which the display control device 90 is controlled by the voice emission control device 80 based on the command transmitted from the main control device 60. The device 90 may be configured to control the voice emission control device 80. Further, instead of the configuration in which the voice emission control device 80 and the display control device 90 are separately provided, a configuration in which both control devices are provided as one control device may be used, and the function of one of the two control devices may be provided. May be integrated in the main control device 60, and both functions of both control devices may be integrated in the main control device 60. Further, the configuration of the command transmitted from the main control device 60 to the voice emission control device 80 and the configuration of the command transmitted from the voice emission control device 80 to the display control device 90 are also arbitrary.

(10) Other types of pachinko machines different from the above embodiments, for example, a pachinko machine in which an electric accessory is opened a predetermined number of times when a game ball enters a specific area of a special device, or a game ball in a specific area of a special device. The present invention can also be applied to a pachinko machine, which is a big hit when a right is entered, a pachinko machine equipped with other accessories, an arrange ball machine, a game machine such as a sparrow ball, and the like.

In addition, a non-bullet type gaming machine, for example, a plurality of reels having a plurality of types of symbols attached in the circumferential direction is provided, the reels are started to rotate by inserting medals and operating the start lever, and the stop switch is operated. Or, after the reel has stopped after a predetermined time has elapsed, if a specific symbol or a combination of specific symbols is established on the effective line that can be seen from the display window, a privilege such as paying out a medal is given to the player. The present invention can also be applied to slot machines.

In addition, the game machine main body supported by the outer frame so as to be openable and closable is equipped with a storage unit and a take-in device, and the start lever is operated after a predetermined number of game balls stored in the storage unit are taken in by the take-in device. The present invention can also be applied to a gaming machine that starts rotation of a reel by using a gaming ball as a gaming medium to play a game similar to a slot machine.

<About the invention group extracted from each of the above embodiments>
Hereinafter, the characteristics of the invention group extracted from each of the above-described embodiments will be described while showing the effects and the like as necessary. In the following, for the sake of easy understanding, the corresponding configurations in each of the above embodiments are appropriately shown in parentheses or the like, but the present invention is not limited to the specific configurations shown in the parentheses or the like.

<Characteristic A group>
Features A1. A storage means (ROM63) that stores instructions in advance,
A control execution means (CPU core 102) that executes the instruction read from the storage means, and
In a gaming machine equipped with
The control execution means is
A first signal output means (MRQ terminal) for outputting a signal corresponding to the first command (MRQ signal) when the first command is executed, and
A second signal output means (IREQ terminal) for outputting a signal corresponding to the second instruction (IREQ signal) when executing a second instruction having a different amount of information from the first instruction.
Equipped with
The game machine
A specific output means (first) that outputs a specific signal (chip select signal) regardless of whether the signal corresponding to the first command is output or the signal corresponding to the second command is output. In the embodiment, the synthesis circuit 117, in the second embodiment, the synthesis circuit 137, and in the third embodiment, the synthesis circuit 177).
When the specific signal is output, at least one of the input and output of the information is an operating means (in the first embodiment, the input latch circuit 103 or the output latch circuit 104, the first). In the second embodiment, the output latch circuit 121a, and in the third embodiment, the external output latch circuit 161).
A gaming machine characterized by being equipped with.

According to the feature A1, the first instruction corresponding signal is output from the first signal output means when the first instruction is executed, and the second instruction corresponding signal is output from the second signal output means when the second instruction is executed. Therefore, it is possible to prevent a predetermined operation from being executed in a situation where neither the first instruction nor the second instruction is executed, and the case where the first instruction is executed and the first. It is possible to distinguish the operation target from the case where two instructions are executed.

In this case, the specific signal output to bring the operating means into a specific operating state is output regardless of which of the first command corresponding signal and the second command corresponding signal is output from the control execution means. To. This makes it possible to bring the operating means into a specific operating state regardless of whether the first instruction or the second instruction is executed. Therefore, it is possible to widen the range of instruction types when the operating means is set to a specific operating state.

The "first signal output means" includes a "first signal output unit" or a "first signal output terminal", and the "second signal output means" includes a "second signal output unit" or a "second signal output unit". "Signal output terminal" can be mentioned.

Feature A2. Predetermined output means for outputting a predetermined signal when the first command corresponding signal or the second command corresponding signal is output (target selection circuit 113 in the first embodiment, target selection circuit 133 in the second embodiment). , In the third embodiment, the target selection circuit 173) is provided.
The gaming machine according to feature A1, wherein the specific output means outputs the specific signal when the predetermined signal is output.

According to the feature A2, in the configuration in which the specific signal is output from the specific output means on the condition that the predetermined signal is output from the predetermined output means, the predetermined output means is the first command corresponding signal or the second command. Since the configuration is such that a predetermined signal is output when the corresponding signal is output, it is possible to achieve the above-mentioned excellent effect while diverting the configuration other than the predetermined output means as it is.

Feature A3. The predetermined output means has an input means electrically connected to the first signal output means and an input means electrically connected to the second signal output means, and has the first command corresponding signal and the second signal. The gaming machine according to feature A2, comprising a logic circuit (target selection logic circuit 113a) that outputs the predetermined signal when any of the command corresponding signals is input.

According to the feature A3, when the signal corresponding to the first command or the signal corresponding to the second command is output, the predetermined output means naturally outputs the predetermined signal, so that the signal corresponding to the first command is output. It is not necessary to switch the state of the predetermined output means depending on whether the signal corresponding to the second instruction is output. Therefore, it is possible to achieve the excellent effects as described above while simplifying the configuration of the predetermined output means.

Feature A4. The gaming machine according to any one of features A1 to A3, wherein the first command is a load command and the second command is either an in command or an out command.

According to the feature A4, when the operating means is controlled so that at least one of the input and the output of the information is in a specific operating state, the load instruction as well as the in instruction and the out instruction is executed. Is possible.

Feature A5. The control execution means is
Designated information output means (address terminals A0 to A15) for outputting designated information that specifies the operation target, and
When the operating means is brought into the specific operating state by executing the first instruction, the first designated information is output from the designated information output means, and the operating means is caused by executing the second instruction. A function to execute the processes of the designated information output means (step S305, step S402, step S408, step S415, and step S419 in the CPU core 102) that output the second designated information from the designated information output means in a specific operating state. )When,
Equipped with
The specific output means is characterized in that the specific signal is output regardless of whether the first designated information is output or the second designated information is output. The gaming machine according to any one of.

According to the feature A5, in a configuration in which both the first instruction and the second instruction can be executed when the operating means is set to a specific operating state, the first designated information is output when the first instruction is executed. At the same time, when the second instruction is executed, the second designation information is output. As a result, it becomes possible to output the designated information in the mode corresponding to each of the case of executing the first instruction and the case of executing the second instruction. Further, even if the configuration is such that the first designated information is output when the first command is executed and the second designated information is output when the second command is executed, the first designated information is output. Since the specific signal is output from the specific output means regardless of whether the information is output or the second designated information is output, regardless of whether the first instruction or the second instruction is executed. It is possible to put the operating means into a specific operating state.

The "designated information output means" includes a "designated information output unit" or a "designated information output terminal".

Feature A6. The gaming machine according to feature A5, wherein the first designated information and the second designated information have different amounts of information.

According to the feature A6, when the first instruction is executed, the designated information is output with the amount of information corresponding to the first instruction, and when the second instruction is executed, the information corresponding to the second instruction is executed. The specified information is output by the amount. In this case, the configuration of the above feature A5 is provided, and the specific signal is output from the specific output means regardless of whether the first designated information is output or the second designated information is output. , The operating means can be brought into a specific operating state regardless of whether the first instruction or the second instruction is executed.

Feature A7. Designation corresponding means for outputting the designated correspondence signal when the first designated information or the second designated information is output (in the first embodiment, the IO address decoder 114, the memory address decoder 115, and the address circuit 116). In the second embodiment, the IO address decoder 134, the memory address decoder 135 and the address circuit 136 are provided, and in the third embodiment, the IO address decoder 174, the memory address decoder 175 and the address circuit 176) are provided.
The gaming machine according to feature A5 or A6, wherein the specific output means outputs the specific signal when the designated corresponding signal is output.

According to the feature A7, the designated corresponding means outputs the designated corresponding signal when the first designated information or the second designated information is output, and at least one that the designated corresponding means outputs the designated corresponding signal. Since the configuration is such that a specific signal is output from the specific output means as a condition, it is not necessary for the specific output means to execute an operation corresponding to each of the first designated information and the second designated information. This makes it possible to achieve the excellent effects as described above while simplifying the configuration of the specific output means.

Feature A8. The designated correspondence means
Means for outputting the first corresponding signal when the first designated information is output (memory address decoder 115 in the first embodiment, memory address decoder 135 in the second embodiment, third embodiment). Then, the memory address decoder 175) and
Means for outputting the second corresponding signal when the second designated information is output (IO address decoder 114 in the first embodiment, IO address decoder 134 in the second embodiment, third embodiment). Then, the IO address decoder 174) and
Means for outputting the designated correspondence signal when the first correspondence signal or the second correspondence signal is output (address circuit 116 in the first embodiment, address circuit 136 in the second embodiment, first In the embodiment of 3, the address circuit 176) and
The gaming machine according to the feature A7, which is characterized by having.

According to the feature A8, a means for outputting the first corresponding signal corresponding to the case where the first designated information is output, and a second corresponding signal corresponding to the case where the second designated information is output. By providing the means for outputting the signal separately, it is possible to output the signal corresponding to each of the first designated information and the second designated information with a relatively simple configuration. Further, since the designated corresponding signal is output when the first corresponding signal or the second corresponding signal is output, it is possible to suppress the types of signals output to the specific output means.

It should be noted that one or more of the features A1 to A8, the features B1 to B6, and the features C1 to C6 may be applied to the configurations of the features A1 to A8. This makes it possible to produce a synergistic effect due to the combined configuration.

<Characteristic B group>
Feature B1. A control execution means (CPU core 102) for setting predetermined information for the output means (output port 62b), and
Operation executing means (drive unit 32b for special electric power, drive unit 34b for general electric power, special figure display unit 37a, special figure hold display unit 37b, general) for executing an operation corresponding to the predetermined information set in the output means. Figure display unit 38a, general figure reservation display unit 38b, etc.)
A supply means (in the second embodiment, an input latch) that acquires the predetermined information set in the output means from a transmission path through which the predetermined information is transmitted and supplies the acquired predetermined information to the control execution means. The circuits 122a to 122c, in the third embodiment, the internal output latch circuit 162 and the internal input latch circuit 163),
A gaming machine characterized by being equipped with.

According to the feature B1, predetermined information set in the output means is supplied to the control execution means via the transmission path. This makes it possible for the control execution means to read and use the predetermined information again without separately storing or re-reading the predetermined information set in the output means.

Feature B2. The game according to feature B1, wherein the supply means supplies the predetermined information to the control execution means when an input acquisition signal is input to the supply means based on the control of the control execution means. Machine.

According to the feature B2, it is possible to supply predetermined information from the supply means to the control execution means at a preferable timing in the control execution means.

Feature B3. A first transmission path (data bus DB) that enables transmission of information to the control execution means and transmission of information from the control execution means, and
Output setting means for setting the predetermined information acquired from the first transmission path to the output means (output latch circuits 121a to 121c in the second embodiment, external output latch circuit 161 in the third embodiment). When,
Equipped with
The supply means is electrically connected to a target path which is one of the first transmission path and the second transmission path (data paths L1 to L3) for information from the output setting means to the output means. The gaming machine according to feature B1 or B2, characterized in that the predetermined information acquired from the target route is supplied to the first transmission path in order to supply the predetermined information to the control execution means.

According to the feature B3, it is possible to supply the predetermined information to the control execution means by using the transmission path for setting the predetermined information in the output means.

Feature B4. When the output acquisition signal is input, the output setting means sets the predetermined information acquired from the first transmission path in the output means.
When the input acquisition signal is input, the supply means supplies the predetermined information to the first transmission path in order to supply the predetermined information to the control execution means.
When the predetermined designated information (address data) is output from the control execution means, the first output corresponding means (in the second embodiment, the synthesis circuit 137,) which outputs the output acquisition signal to the output setting means. In the third embodiment, the synthesis circuit 177) and
A second output corresponding means (in the second embodiment, a synthesis circuit 147, a third embodiment) that outputs the input acquisition signal to the supply means when the predetermined designated information is output from the control execution means. Then, the synthesis circuit 187) and
The gaming machine according to the feature B3, which is characterized by having.

According to the feature B4, the output setting means sets predetermined information for the output means when the output acquisition signal is input, and the supply means sets the predetermined information when the input acquisition signal is input. Since the information is supplied to the control execution means, it is possible to make the setting timing of the predetermined information to the output means and the supply timing of the predetermined information to the control execution means preferable. In this case, the predetermined designation information output from the control execution means for causing the output setting means to output the output acquisition signal, and the predetermined designation information output from the control execution means for causing the supply means to output the input acquisition signal. The specified information is the same. This makes it possible to supply the predetermined information to the control execution means by using the predetermined designated information used for setting the predetermined information in the output means.

Feature B5. The control execution means is
A first corresponding means (WR terminal) for outputting a first signal when the predetermined information is set by the output setting means, and
A second corresponding means (RD terminal) for outputting a second signal when the predetermined information is supplied by the supply means, and
Equipped with
When the first signal is output, the first output corresponding means outputs the output acquisition signal to the output setting means.
The gaming machine according to feature B4, wherein the second output corresponding means outputs the input acquisition signal to the supply means when the second signal is output.

According to the feature B5, the output acquisition signal is output when the first signal is output from the control execution means, while the input acquisition signal is output when the second signal is output from the control execution means. Will be done. As a result, the predetermined designation information output from the control execution means for causing the output setting means to output the output acquisition signal, and the predetermined designation output from the control execution means for causing the supply means to output the input acquisition signal. Even if the information is the same, it is possible to make the timing at which the predetermined information is set by the output setting means different from the timing at which the predetermined information is supplied by the supply means.

The "first corresponding means" includes a "first corresponding part" or a "first corresponding terminal", and the "second corresponding means" includes a "second corresponding part" or a "second corresponding terminal". Will be.

Feature B6. The control execution means is
A generation means (a function of executing the process of step S514 in the CPU core 102) for generating different information by executing a predetermined process on the predetermined information supplied by the supply means, and
A means for causing the different information generated by the generation means to be set for the output means (a function of executing the process of step S518 in the CPU core 102) and
The gaming machine according to any one of features B1 to B5.

According to the feature B6, the control execution means can generate different information by processing the predetermined information already set in the output means, and can set the different information in the output means.

It should be noted that any one or more of the features A1 to A8, the features B1 to B6, and the features C1 to C6 may be applied to the configurations of the features B1 to B6. This makes it possible to produce a synergistic effect due to the combined configuration.

<Characteristic C group>
Features C1. A control means (CPU101) that inputs and outputs information using a predetermined transmission path (data bus DB), and
When the selection signal (chip select signal) is output from the selection signal means (chip select terminal CS0) provided in the control means, the predetermined information acquired from the predetermined transmission path is output to the output means (output port 62b). Output setting means (external output latch circuit 161) to be set to
Operation executing means (drive unit 32b for special electric power, drive unit 34b for general electric power, special figure display unit 37a, special figure hold display unit 37b, general) for executing an operation corresponding to the predetermined information set in the output means. Figure display unit 38a, general figure reservation display unit 38b, etc.)
In a gaming machine equipped with
The control means is
A control execution means (CPU core 102) having an information output means capable of outputting the predetermined information to the output means, and a control execution means (CPU core 102).
A supply means (internal output latch circuit 162 and internal input latch circuit 163) that acquires the predetermined information output from the information output means and supplies the acquired predetermined information to the control execution means.
A gaming machine characterized by being equipped with.

According to the feature C1, predetermined information set in the output means is supplied to the control execution means. This makes it possible for the control execution means to read and use the predetermined information again without separately storing or re-reading the predetermined information set in the output means. Further, since the supply means is built in the control means, it is not necessary to prepare the means for operating the supply means in the control means. Therefore, it is possible to read and use the predetermined information again in the control execution means while suppressing the increase in the number of terminals of the control means.

The "selection signal means" includes a "selection unit" or a "selection terminal".

Feature C2. The game according to feature C1, wherein the supply means supplies the predetermined information to the control execution means when an input acquisition signal is input to the supply means based on the control of the control execution means. Machine.

According to the feature C2, it is possible to supply predetermined information from the supply means to the control execution means at a preferable timing in the control execution means.

Feature C3. The predetermined transmission path enables the transmission of information to the control execution means and the transmission of information from the control execution means.
The gaming machine according to feature C1 or C2, wherein the supply means supplies the predetermined information acquired from the predetermined transmission path to the predetermined transmission path in order to supply the predetermined information to the control execution means.

According to the feature C3, the predetermined information can be supplied to the control execution means by using the predetermined transmission path for setting the predetermined information in the output means.

Feature C4. When the output acquisition signal is input, the output setting means sets the predetermined information acquired from the predetermined transmission path in the output means.
When the input acquisition signal is input, the supply means supplies the predetermined information to the predetermined transmission path in order to supply the predetermined information to the control execution means.
A first output corresponding means (synthesis circuit 177) that outputs the output acquisition signal to the output setting means when predetermined designated information (address data) is output from the control execution means.
A second output corresponding means (synthesis circuit 187) that outputs the input acquisition signal to the supply means when the predetermined designated information is output from the control execution means.
The gaming machine according to the feature C3, which is characterized by having.

According to the feature C4, the output setting means sets predetermined information to the output means when the output acquisition signal is input, and the supply means controls the control execution means when the input acquisition signal is input. Since the predetermined information is supplied to, it is possible to make the setting timing of the predetermined information to the output means and the supply timing of the predetermined information to the control execution means preferable. In this case, the predetermined designation information output from the control execution means for causing the output setting means to output the output acquisition signal, and the predetermined designation information output from the control execution means for causing the supply means to output the input acquisition signal. The specified information is the same. This makes it possible to supply the predetermined information to the control execution means by using the predetermined designated information used for setting the predetermined information in the output means.

Feature C5. The control execution means is
A first corresponding means (WR terminal) for outputting a first signal when the predetermined information is set by the output setting means, and
A second corresponding means (RD terminal) for outputting a second signal when the predetermined information is supplied by the supply means, and
Equipped with
When the first signal is output, the first output corresponding means outputs the output acquisition signal to the output setting means.
The gaming machine according to feature C4, wherein the second output corresponding means outputs the input acquisition signal to the supply means when the second signal is output.

According to the feature C5, the output acquisition signal is output when the first signal is output from the control execution means, while the input acquisition signal is output when the second signal is output from the control execution means. Will be done. As a result, the predetermined designation information output from the control execution means for causing the output setting means to output the output acquisition signal, and the predetermined designation output from the control execution means for causing the supply means to output the input acquisition signal. Even if the information is the same, it is possible to make the timing at which the predetermined information is set by the output setting means different from the timing at which the predetermined information is supplied by the supply means.

The "first corresponding means" includes a "first corresponding part" or a "first corresponding terminal", and the "second corresponding means" includes a "second corresponding part" or a "second corresponding terminal". Will be.

Feature C6. The control execution means is
A generation means (a function of executing the process of step S514 in the CPU core 102) for generating different information by executing a predetermined process on the predetermined information supplied by the supply means, and
A means for causing the different information generated by the generation means to be set for the output means (a function of executing the process of step S518 in the CPU core 102) and
The gaming machine according to any one of features C1 to C5.

According to the feature C6, the control execution means can generate different information by processing the predetermined information already set in the output means, and can set the different information in the output means.

It should be noted that any one or more of the features A1 to A8, the features B1 to B6, and the features C1 to C6 may be applied to the configurations of the features C1 to C6. This makes it possible to produce a synergistic effect due to the combined configuration.

According to the inventions relating to the feature A group, the feature B group, and the feature C group, the following problems can be solved.

Pachinko gaming machines, slot machines, and the like are known as a type of gaming machine. These gaming machines include a control element such as a CPU, a read-only storage element such as a ROM, and a read / write storage element such as a RAM. The control element executes the process according to the program read from the read-only storage element while writing the information to the read / write storage element and reading the information from the storage element. When executing this process, information is input from a sensor or the like to the control element, and information is output from the control element to the electric actuator, the light emitting element, or the like. It is also known that a control element, a read-only storage element, a read / write storage element, and the like are integrated into a single chip.

Here, in a gaming machine such as the above example, there is a demand for a configuration capable of suitably performing control, and there is still room for improvement in this respect.

The following shows the basic configuration of a gaming machine to which each of the above features can be applied or is applied to each feature.

Pachinko gaming machine: An operating means operated by a player, a game ball launching means for launching a game ball based on the operation of the operating means, a ball passage for guiding the launched game ball to a predetermined game area, and a game. A gaming machine that includes each gaming component arranged in an area and grants a privilege to a player when a gaming ball passes through a predetermined passing portion of each gaming component.

Rotating machine such as a slot machine: Equipped with a picture display device that variably displays a plurality of pictures, the variable display of the plurality of pictures is started due to the operation of the start operation means, and is caused by the operation of the stop operation means. A gaming machine in which the variable display of the plurality of symbols is stopped after a lapse of a predetermined time, and a privilege is given to the player according to the symbols after the stop.

10 ... pachinko machine, 32b ... drive unit for special electric power, 34b ... drive unit for general electric power, 37a ... special figure display unit, 37b ... special figure hold display unit, 38a ... normal figure display unit, 38b ... normal figure hold display Unit, 62b ... Output port, 63 ... ROM, 102 ... CPU core, 103 ... Input latch circuit, 104 ... Output latch circuit, 113 ... Target selection circuit, 113a ... Target selection logic circuit, 114 ... IO address decoder , 115 ... memory address decoder, 116 ... address circuit, 117 ... synthesis circuit, 121a ... output latch circuit, 122a-122c ... input latch circuit, 133 ... target selection circuit, 134 ... IO address decoder, 135 ... Memory address decoder, 136 ... address circuit, 137 ... synthesis circuit, 147 ... synthesis circuit, 161 ... external output latch circuit, 162 ... internal output latch circuit, 163 ... internal input latch circuit, 173 ... target selection circuit 174 ... IO address decoder, 175 ... memory address decoder, 176 ... address circuit, 177 ... synthesis circuit, 187 ... synthesis circuit, A0 to A15 ... address terminal, CS0 ... chip select terminal, DB ... data bus, L1 ~ L3 ... Data route.

Claims (1)

A storage means for storing commands in advance,
A control execution means for executing the instruction read from the storage means, and a control execution means.
In a gaming machine equipped with
The control execution means is
A first signal output means for outputting a signal corresponding to the first instruction when the first instruction is executed, and
A second signal output means for outputting a signal corresponding to the second instruction when the second instruction having a different amount of information from the first instruction is executed.
Equipped with
This gaming machine is
A specific output means for outputting a specific signal regardless of whether the signal corresponding to the first command is output or the signal corresponding to the second command is output.
An operating means that, when the specific signal is output, is in a specific operating state at least one of the input and output of information.
Equipped with
A gaming machine characterized in that a plurality of the operating means are provided, and a plurality of the specific output means are provided corresponding to the plurality of the operating means .

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