JP2019115817A - Game machine - Google Patents

Abstract

To provide a game machine capable of suitably performing control.SOLUTION: A CPU core built into an MPU 62 can execute a load command as well as an in command and an out command when inputting data from an input port 62a and outputting data to an output port 62b. The CPU core outputs an IREQ signal in execution of the in command or the out command, and outputs an MREQ signal in execution of the load command, but a circuit for outputting a chip select signal to an input latch circuit or an output latch circuit outputs a chip select signal even in a situation in that either the IREQ signal or the MREQ signal is being outputted. Data outputted toward the output port 62b via a data bus from the CPU core are configured to be supplied to the CPU core.SELECTED DRAWING: Figure 4

Description

  The present invention relates to a gaming machine.

  Pachinko gaming machines and slot machines are known as a type of gaming machine. These gaming machines include a control element such as a CPU, a read only memory element such as a ROM, and a read / write memory element such as a RAM. The control element executes processing according to a program read from the read-only storage element while writing information to the read / write storage element and reading information from the storage element. In executing this process, information from a sensor or the like is input to the control element, and information from the control element is output to an electric actuator, a light emitting element, or the like (see, for example, Patent Document 1). It is also known that a control element, a read-only storage element, and a read-write storage element are integrated into one chip.

JP, 2009-261415, A

  Here, in the gaming machine as illustrated above etc., there is a demand for a configuration capable of suitably performing control, and there is still room for improvement in this respect.

  The present invention has been made in view of the above-described circumstances and the like, and it is an object of the present invention to provide a gaming machine capable of suitably performing control.

In order to solve the above problems, the invention according to claim 1 comprises control execution means for setting predetermined information to the output means;
Operation execution means for executing an operation corresponding to the predetermined information set in the output means;
Supply means for acquiring the predetermined information set in the output means from a transmission path through which the predetermined information is transmitted, and supplying the acquired predetermined information to the control execution means;
It is characterized by having.

  According to the present invention, control can be suitably performed.

It is a perspective view showing a pachinko machine in a 1st embodiment. It is a perspective view which disassembles and shows the main structure of a pachinko machine. It is a front view which shows the structure of a game board. It is a block diagram which shows the electric constitution of a pachinko machine. It is explanatory drawing for demonstrating the content of the various counters used for the etc. lottery. It is a flowchart which shows the main processing performed by MPU of a main control apparatus. It is a flowchart which shows the timer interruption process performed by MPU of a main control apparatus. It is a block diagram for demonstrating the electric constitution of CPU provided in MPU. (A) It is a block diagram of the latch circuit for input, (b) It is a block diagram of the latch circuit for output. It is explanatory drawing for demonstrating the area where instruction | indication is memorize | stored in ROM. (A) is an explanatory diagram for explaining in-instructions and out-instructions that are 2-byte instructions, and (b) is an explanatory diagram for explaining load instructions that are 3-byte instructions. It is a block diagram for demonstrating IO space and memory space. It is an explanatory view for explaining a memory space. FIG. 6 is a block diagram showing an electrical configuration for outputting a chip select signal from a chip select terminal corresponding to an input latch circuit for inputting data from an input port. (A)-(h) It is a time chart which shows a mode that a chip | tip select signal is output from a chip | tip select terminal. It is a flowchart which shows the instruction execution process performed by CPU core. It is a flowchart which shows the process for 3-byte instructions performed by CPU core. It is explanatory drawing for demonstrating the electric constitution of CPU in 2nd Embodiment. FIG. 6 is a block diagram showing an output circuit for outputting a chip select signal to an output latch circuit in a CPU, and an input circuit for outputting a chip select signal to an input latch circuit in a CPU. (A) It is a front view of a special figure display part, (b) It is explanatory drawing for demonstrating an output area. (A1) to (a8) is an explanatory diagram for explaining the contents of data set in the output area, and (b1) to (b8) an explanation for describing the light emission mode of the first to eighth light emitting units FIG. It is a flowchart which shows the control processing of the special figure display part performed by MPU of a main control apparatus. It is a block diagram which shows the electric constitution of CPU in 3rd Embodiment. FIG. 6 is a block diagram showing an electrical configuration for outputting a chip select signal to a corresponding input latch circuit when reading data from a RAM.

First Embodiment
Hereinafter, a first embodiment of a pachinko gaming machine (hereinafter referred to as "pachinko machine"), which is a type of gaming machine, will be described in detail based on the drawings. FIG. 1 is a perspective view of a pachinko machine 10, and FIG. 2 is an exploded perspective view showing the main configuration of the pachinko machine 10. As shown in FIG. In addition, in FIG. 2, the structure in the game area of the pachinko machine 10 is abbreviate | omitted for convenience.

  As shown in FIG. 1, the pachinko machine 10 has an outer frame 11 forming an outer shell of the pachinko machine 10 and a gaming machine main body 12 rotatably attached to the outer frame 11 in the forward direction. . The outer frame 11 is configured by connecting wooden plate members to four sides, and has a rectangular frame shape. The pachinko machine 10 is installed in the game hall by fixing the outer frame 11 to the island facility. In the pachinko machine 10, the outer frame 11 is not an essential component, and the outer frame 11 may be provided on an island facility of the game hall.

  As shown in FIG. 2, the gaming machine main body 12 includes an inner frame 13, a front door frame 14 disposed in front of the inner frame 13, and a back pack unit 15 disposed behind the inner frame 13. ing. The inner frame 13 of the gaming machine main body 12 is rotatably supported relative to the outer frame 11. In detail, the inner frame 13 is pivotable forward with the left side as the pivoting base end and the right side as the pivoting tip side in front view.

  A front door frame 14 is rotatably supported by the inner frame 13 and can be pivoted forward with the left side as a pivoting base end and the right side as a pivoting tip side in a front view. In addition, the back pack unit 15 is rotatably supported by the inner frame 13 and can be rotated backward with the left side as the rotation base end side and the right side as the rotation tip end side in a front view.

  In addition, the gaming machine main body 12 is provided with a locking device at its rotating tip, and has a function to lock the gaming machine main body 12 against the outer frame 11 so as not to be opened, and The door frame 14 has a function of locking the inner frame 13 so as not to be opened. Each of these locked states is released by performing an unlocking operation on the cylinder lock 17 provided exposed on the front surface of the pachinko machine 10 using an unlocking key.

  Next, the configuration of the front side of the gaming machine body 12 will be described.

  The inner frame 13 mainly includes a resin base 21 whose outer shape is substantially the same as the outer frame 11. A substantially elliptical window hole 23 is formed in the central portion of the resin base 21. A game board 24 is removably attached to the resin base 21. The game board 24 is made of plywood, and the game area PA formed on the front of the game board 24 is exposed to the front side of the inner frame 13 through the window hole 23 of the resin base 21.

  Here, the configuration of the game board 24 will be described based on FIG. FIG. 3 is a front view of the game board 24. As shown in FIG.

  The inner rail portion 25 and the outer rail portion 26 are attached to the game board 24 so as to partition a part of the outer edge of the game area PA, and the inner rail portion 25 and the outer rail portion 26 guide means Guide rails are configured as. The game balls fired from the game ball launch mechanism 27 (see FIG. 2) attached below the window holes 23 in the resin base 21 are guided to the top of the game area PA by the guide rails.

  Incidentally, the game ball firing mechanism 27 includes a firing rail 27a extending toward the guide rail, a ball feeding device 27b for supplying game balls stored in an upper tray 55a described later onto the firing rail 27a, and a firing rail 27a. And a solenoid 27c, which is an electric actuator that causes the game ball supplied to the control unit to shoot toward the guide rail. By rotating the firing operation device (or operation handle) 28 provided on the front door frame 14, the solenoid 27c is driven and controlled, and the gaming ball is fired.

  The game board 24 is formed with a plurality of large and small openings penetrating in the front-rear direction. Each opening is provided with a general winning opening 31, a special electric winning device 32, a first operation opening 33, a second operation opening 34, a through gate 35, a variable display unit 36, a special drawing unit 37, a drawing unit 38, etc. ing.

  Even if the ball enters the through gate 35, the payout of the game ball is not executed. On the other hand, when entering the general winning opening 31, the special power winning device 32, the first operation opening 33 and the second operation opening 34, a predetermined number of game balls are paid out. Specifically, with respect to the number of winning balls, when entering the first operation port 33 occurs or when entering the second operation port 34, three winning balls are paid out. When the entry to the general winning opening 31 occurs, the payout of 10 winning balls is executed, and when the entry to the special electric winning device 32 occurs, the payout of 15 winning balls is To be executed.

  The number of winning balls is arbitrary. For example, the second operating port 34 may have a smaller number of winning balls than the first operating port 33, and the second operating port 34 may be a first operating port. The number of balls may be greater than 33.

  In addition, an out port 24a is provided at the lowermost portion of the game board 24, and game balls which did not enter the various winning ports etc. are discharged from the game area PA through the out port 24a. Further, on the game board 24, a large number of nails 24b are implanted to appropriately disperse and adjust the falling direction of the game balls, and various members such as a windmill are disposed.

  Here, entering the ball means that the gaming ball passes through the predetermined opening, and not only the aspect of being ejected from the gaming area PA after passing through the opening, but also from the gaming area PA after passing through the opening Also included is an aspect of continuing the flow of the game area PA without being discharged. However, in the following description, in order to distinguish the game ball from entering the out port 24 a clearly, the general winning port 31, the special power winning device 32, the first operating port 33, the second operating port 34 and the through gate 35 The entry of the game ball to the is also expressed as a winning.

  The first operating port 33 and the second operating port 34 are unitized as an operating port device and installed on the game board 24. The first operation port 33 and the second operation port 34 are both open upward. Further, both operation ports 33 and 34 are aligned in the vertical direction so that the first operation port 33 is on the upper side. The second operating port 34 is provided with a general-purpose utility product 34 a as a guide piece consisting of a pair of left and right movable pieces. In the closed state of the commercial power item 34a, the gaming ball can not win in the second operation port 34, and when the common electric symbol 34a is in the open state, it is possible to win the second operating port 34.

  A through gate 35 is provided upstream of the second operation opening 34 in the flow direction of the gaming ball. The through gate 35 has a through hole (not shown) penetrating in the vertical direction, and the gaming ball that has won the through gate 35 flows down the gaming area PA after winning. Thereby, it is possible for the game ball that has won the through gate 35 to win the second operation port 34.

  Based on the winning on the through gate 35, the utility power supply 34a of the second operation port 34 is switched from the closed state to the open state. Specifically, the internal lottery is performed triggered by the winning on the through gate 35, and a common drawing display of the drawing unit 38 provided in the lower right corner which is an area where the gaming ball does not pass in the gaming area PA The variation display of the pattern is performed in the section 38a. Then, when the result of the internal lottery is the electronic combination open winning, the result of the stop corresponding to the result is displayed, and the variable display of the common view display unit 38a is ended, the state shifts to the general electric power transmission open state. In the general-purpose open state, the general-purpose utility item 34a is open in a predetermined manner.

  In addition, although the common view display part 38a is comprised by the segment display which a some segment light emission part is arranged in a predetermined | prescribed aspect, it is not limited to this, A liquid crystal display device, an organic electroluminescence display , Or a display device such as a CRT or dot matrix display. In addition, as a pattern that is variably displayed in the common view display unit 38a, a configuration in which plural types of characters are variably displayed, a configuration in which plural types of symbols are variably displayed, a configuration in which plural types of characters are variably displayed A configuration in which a plurality of colors are switched and displayed may be considered.

  In the common drawing unit 38, a common drawing suspension display unit 38b is provided at a position adjacent to the common drawing display unit 38a. The number of game balls winning through the through gate 35 is held at a maximum of four, and the number of the held balls is displayed by lighting of the common drawing hold display unit 38b.

  A lottery is triggered by winning of the first operation port 33 or the second operation port 34 as a trigger. Then, the lottery result is clearly indicated through display effects in the special display unit 37 and the symbol display device 41 of the variable display unit 36.

  In detail, the special drawing unit 37 is provided with a special drawing display unit 37 a. The display area of the special view display unit 37 a is narrower than the display surface 41 a of the symbol display device 41. In the special view display unit 37a, the winning of the first operation opening 33 or the winning of the second operation opening 34 is used as a trigger and a lottery is performed, thereby performing variable display of symbols or predetermined display. Then, the result corresponding to the lottery result is displayed. In addition, although the special view display part 37a is comprised by the segment display in which several segment light emission parts are arranged in a predetermined | prescribed aspect, it is not limited to this, A liquid crystal display device, an organic electroluminescence display , Or a display device such as a CRT or dot matrix display. Moreover, as a pattern displayed on the special view display unit 37a, a configuration in which a plurality of types of characters are displayed, a configuration in which a plurality of types of symbols are displayed, a configuration in which a plurality of types of characters are displayed, or a plurality of colors May be displayed.

  In the special drawing unit 37, a special drawing reservation display unit 37b is provided at a position adjacent to the special drawing display unit 37a. The number of game balls played in the first operation opening 33 or the second operation opening 34 is held up to a maximum of four, and the number of holdings is displayed by turning on the special view holding display unit 37b.

  In detail, the symbol display device 41 is configured as a liquid crystal display device having a liquid crystal display, and the display content is controlled by a display control device described later. The symbol display device 41 is not limited to a liquid crystal display device, and may be another display device having a display screen such as a plasma display device, an organic EL display device or a CRT, and is a dot matrix display. May be

  In the symbol display device 41, when the special pattern display or the predetermined display is performed on the special view display unit 37a based on the winning on the first operation opening 33 or the winning on the second operation opening 34, the symbol is displayed accordingly. Variable display or predetermined display is performed. For example, on the display surface 41a of the symbol display device 41, three symbol rows of the upper row, middle row and lower row are set as a plurality of display areas, and the main characters with numbers "1" to "9" attached in each symbol row The symbols are scrolled in an ascending or descending order. In this scroll display, scroll display in all symbol rows is first started, and scroll display is switched from standby display to standby display in the order of upper symbol row → lower symbol row → middle symbol row, and finally predetermined in each symbol row It is ended in the state where the symbol is displayed still. Then, for example, in the game round where the game result is a big hit result, the symbols of the predetermined combination are stopped and displayed on the effective line preset on the display surface 41 a of the symbol display device 41.

  In the symbol display device 41, not only display effects triggered by winning in the first operation port 33 or the second operation port 34, but also display effects in the open / close execution mode to be shifted after winning are won. It will be. In addition, based on winning in any of the operation openings 33, 34, the display is started on the special view display unit 37a and the symbol display device 41, and a predetermined result is displayed and one game cycle is completed. It corresponds to the number of times. In addition, the aspect of the variation display of the symbols in the symbol display device 41 is not limited to the above and is arbitrary, the number of symbol rows, the direction of the variation display of symbols in the symbol row, the number of symbols in each symbol row, etc. Can be changed as appropriate. Further, the pattern variably displayed by the symbol display device 41 is not limited to the above-described symbol, and for example, only numbers may be variably displayed as the pattern.

  When the jackpot is won in the winning lottery based on the winning of the first operation opening 33 or the winning of the second operation opening 34, transition to the open / close execution mode in which winning to the special power prize device 32 is possible. The special power winning device 32 has a large winning opening (not shown) leading to the back side of the game board 24 and an open / close door 32a for opening and closing the large winning opening. The open / close door 32a is disposed in either the closed state or the open state. Specifically, the open / close door 32a is normally in a closed state in which the game ball can not be won, and is switched to an open state in which the game ball can be won if the shift to the open / close execution mode is won in the internal lottery. It has become. By the way, the open / close execution mode is a mode in which transition is made when a hit result is obtained. In the closed state, although it is not impossible to win, it may be in a state in which the winning is less likely to occur than in the open state.

  As shown in FIG. 2, a front door frame 14 is provided so as to cover the entire front side of the inner frame 13 formed by attaching the gaming board 24 of the above configuration to the resin base 21. As shown in FIG. 1, the front door frame 14 is formed with a window portion 51 that enables the player to view substantially the entire game area PA from the front. The window portion 51 has a substantially elliptical shape, and the window panel 52 is fitted therein. The window panel 52 is formed to be colorless and transparent by glass, but is not limited to this and may be formed to be colorless and transparent by a synthetic resin, and the game area PA may be made through the window panel 52 from the front of the pachinko machine 10 If it is visible, it may be colored and transparent.

  The display light emitting unit 53 is provided above the window unit 51. In addition, a pair of left and right speaker units 54 to which sound effects and the like according to the game state are output are provided. Further, below the window 51, an upper bulging portion 55 and a lower bulging portion 56 bulging toward the front side are vertically juxtaposed. An upper plate 55a opened upward is provided inside the upper bulging portion 55, and a lower plate 56a opening similarly upward is provided inside the lower bulging portion 56. The upper tray 55a has a function for temporarily storing the game balls paid out from the later described payout device and guiding the game balls to the game ball launch mechanism 27 side while aligning them in a line. Further, the lower tray 56a has a function of storing the game balls which become surplus in the upper tray 55a.

  Next, the configuration of the back side of the gaming machine body 12 will be described.

  As shown in FIG. 2, on the back of the inner frame 13 (specifically, the game board 24), a main control device 60 which controls the main control of the game is mounted. The main controller 60 has a main control board housed in a board box. The substrate box may be provided with a trace means for leaving a trace of the opening or a trace structure for leaving a trace of the opening. As the trace means, a plurality of case bodies constituting the substrate box can not be separably joined, and the structure of the joining portion which requires destruction of a predetermined portion at the time of the separation, and peeling by the adhesive layer remaining at the adhesion target at peeling A configuration is conceivable in which a seal seal that leaves a trace of what has been done is applied across the boundaries between multiple case bodies. Moreover, as a trace structure, the structure which apply | coats an adhesive agent with respect to the boundary between several case bodies which comprise a board | substrate box can be considered.

  A back pack unit 15 is installed so as to cover the back side of the inner frame 13 including the main control device 60. The back pack unit 15 includes a back pack 72 formed of a synthetic resin having transparency, and to the back pack 72, a dispensing mechanism portion 73 and a control device assembly unit 74 are attached.

  The payout mechanism section 73 includes a tank 75 to which the gaming balls supplied from the island facility of the game hall are successively replenished, and a payout device 76 for paying out the gaming balls stored in the tank 75. The game balls paid out from the payout device 76 are discharged to the upper tray 55a or the lower tray 56a through the payout passage provided on the downstream side of the payout device 76. In addition, for example, a main pack power of, for example, 24 AC, is supplied to the dispensing mechanism portion 73, and a back pack substrate having a power switch for performing an ON operation and an OFF operation of the power is mounted.

  The control device assembly unit 74 generates and outputs a predetermined amount of power required by various control devices and the like as a payout control device 77 having a function of controlling the payout device 76 and is accompanied by the operation of the discharge operation device 28 by the player. A power supply and launch control device 78 is provided to control the launch of the game balls. The payout control device 77 and the power supply / discharge control device 78 are disposed so as to be stacked back and forth so that the payout control device 77 is located behind the pachinko machine 10.

<Electric Configuration of Pachinko Machine 10>
FIG. 4 is a block diagram showing the electrical configuration of the pachinko machine 10.

  The main control device 60 comprises a main control board 61 which controls the main control of the game, and a power failure monitoring board 65 which monitors the power supply. The MPU 62 is mounted on the main control board 61. The MPU 62 is a ROM 63 storing various control programs to be executed by the MPU 62 and fixed value data, and a memory for temporarily storing various data etc. when the control program stored in the ROM 63 is executed. A RAM 64, an interrupt circuit, a timer circuit, a data input / output circuit, various counter circuits as a random number generator, etc. are incorporated. The fact that the ROM 63 and the RAM 64 are integrated into one chip with respect to the MPU 62 is not an essential configuration, and each may be configured as an individual chip. The same applies to the MPUs of control devices other than the main control device 60.

  The MPU 62 is provided with an input port 62a and an output port 62b. The input port 62a is provided with 24 connection terminals, and the output port 62b is provided with 40 connection terminals. A power failure monitoring board 65 and a payout control device 77 provided in the main control device 60 are connected to an input port 62 a of the MPU 62. A power and emission control device 78 having a function of supplying operating power is connected to the power failure monitoring board 65, and power is supplied to the MPU 62 through the power failure monitoring board 65.

  In addition, various sensors such as various winning detection sensors 66a to 66e are connected to the input port 62a of the MPU 62. The various winning detection sensors 66a to 66e are provided in a one-to-one correspondence with the winning correspondence entry portion such as the general winning opening 31, the special power winning device 32, the first operation opening 33, the second operation opening 34 and the through gate 35. A detection sensor is included, and the MPU 62 makes a winning determination on each ball entry unit. Further, in the MPU 62, various types of lottery are executed based on the winning on the first operation port 33, and, in addition, various types of lottery are executed based on the winning on the second operation port 34.

  To the output port 62b of the MPU 62, the power failure monitoring board 65, the payout control device 77, and the sound emission control device 80 are connected. A payout ball command is output to the payout control device 77, for example, based on the result of the winning determination on the winning portion entry portion. The voice light emission control device 80 outputs various commands such as a variation command, a type command, and an opening command. Details of these various commands will be described later. The MPU 62 transmits a command to the sound emission control apparatus 80 by parallel communication.

  In addition, the drive portion 32b for special power to operate the open / close door 32a of the special power prize device 32 to the output port 62b of the MPU 62, and the drive for general power to operate the general purpose battery 34a of the second operation opening 34 34b, a special drawing unit 37 and a drawing unit 38 are connected. Incidentally, the special drawing unit 37 is provided with a special drawing display unit 37 a and a special drawing reservation display unit 37 b, all of which are connected to the output side of the MPU 62. Similarly, the common drawing unit 38 is provided with a common drawing display unit 38 a and a common drawing reservation display unit 38 b, all of which are connected to the output side of the MPU 62. The main control substrate 61 is provided with various driver circuits, and the MPU 62 executes drive control of various driving units and various display units through the driver circuits.

  That is, in the open / close execution mode, the MPU 62 executes drive control of the drive unit 32b for special power so that the special power prize device 32 is opened and closed. In addition, when the open state of the common utility player 34a is won, the MPU 62 executes drive control of the common drive unit 34b so that the common utility product 34a is opened and closed. In addition, at each gaming session, the MPU 62 executes display control of the special view display unit 37a. Further, when the lottery result as to whether or not the common use role product 34a is to be opened is specified, the display control of the common view display unit 38a is executed in the MPU 62. In addition, when winning is generated in the first operation port 33 or the second operation port 34, or when the variable display is started in the special view display unit 37a, the display control of the special view suspension display unit 37b is executed in the MPU 62 When the winning on the through gate 35 occurs or when the variable display is started in the common drawing display unit 38a, the display control of the common drawing reservation display unit 38b is executed in the MPU 62.

  The power failure monitoring board 65 relays the main control board 61 and the power supply and emission control device 78, and monitors the voltage of the DC stable 24 volts which is the maximum voltage output from the power supply and emission control device 78. The payout control device 77 performs the payout control of the winning balls and the rental balls by the payout device 76 based on the winning ball command received from the main control device 60.

  The power supply and launch control device 78 is connected to, for example, a commercial power supply (external power supply) in a game hall or the like. Then, based on the external power supplied from the commercial power supply, the main control board 61, the payout control device 77, etc. generate necessary operation power for each, and supply the generated operation power. Incidentally, the power supply / discharge control device 78 is provided with a power supply unit for powering off such as a backup capacitor, and even if the power of the pachinko machine 10 is in the OFF state, the powering unit for powering off mainly The RAM 64 of the control device 60 is supplied with storage power. Further, the power source and launch control device 78 is responsible for the launch control of the game ball launch mechanism 27, and the game ball launch mechanism 27 is driven when predetermined launch conditions are satisfied.

  The sound emission control device 80 controls the display light emitting unit 53 and the speaker unit 54 provided on the front door frame 14 based on various commands received from the main control device 60 and controls the display control device 90. It is. The display control device 90 executes display control of the symbol display device 41 based on the command received from the sound emission control device 80.

<Electrical configuration for performing various lottery with MPU 62 of main controller 60>
Next, an electrical configuration for performing various lottery in the MPU 62 of the main control device 60 will be described with reference to FIG.

  The MPU 62 uses a variety of counter information during the game to set winning display lottery, setting of display of the special view display unit 37a, setting of symbol display of the symbol display device 41, setting of display of the common view display unit 38a, etc. Specifically, as shown in FIG. 5, when the random number counter C1 used for lottery of occurrence of hit, the big hit type counter C2 used when determining the big hit type, and the symbol display device 41 deviates out The reach random number counter C3 used for the reach occurrence lottery, the random number initial value counter CINI used for setting the initial value of the per random number counter C1, and the variation type for determining the display duration in the special view display unit 37a and the symbol display device 41 The counter CS is used. Furthermore, a common control utility release counter C4 used in the lottery for determining whether the common control utility 34a of the second operation port 34 is to be put into the common use release state is used. The counters C1 to C3, CINI, CS, and C4 are provided in various counter areas 64b of the RAM 64.

  Each of the counters C1 to C3, CINI, CS, and C4 is a loop counter in which 1 is added to the previous value each time it is updated, and after reaching the maximum value, it returns to "0". Each counter is updated at short intervals. The information corresponding to the per random number counter C1, the big hit type counter C2 and the reach random number counter C3 is provided in the RAM 64 as acquisition information storage means when a winning on the first operation port 33 or the second operation port 34 occurs. It is stored in the pending storage area 64a.

  The holding storage area 64a includes a holding area RE and an execution area AE. The reserve area RE includes a first reserve area RE1, a second reserve area RE2, a third reserve area RE3 and a fourth reserve area RE4, and the winning history to the first operation port 33 or the second operation port 34 In addition, the combination of each numerical information of the per-random number counter C1, the jackpot type counter C2 and the reach random number counter C3 is stored as one of the holding areas RE1 to RE4 as holding information.

  In this case, if winnings to the first operation port 33 or the second operation port 34 occur consecutively in a plurality of times in the first holding area RE1 to the fourth holding area RE4, the first holding area RE1 → second Each numerical value information is stored in chronological order in the order of reserved area RE2, third reserved area RE3, and fourth reserved area RE4. By providing four reserve areas RE1 to RE4 as described above, the game ball's winning history of the first operation opening 33 or the second operation opening 34 is reserved and stored up to four at maximum. .

  The number that can be reserved and stored is not limited to four and is arbitrary, and may be other plural such as two, three, five or more, or may be singular.

  The execution area AE is an area for moving each numerical information stored in the first holding area RE1 of the holding area RE when the variable display of the special view display unit 37a is started, and the start of one game cycle is started On the occasion of the above, on the basis of various numerical value information stored in the execution area AE, a judgment of success or failure is performed.

  The respective counters will be described in detail.

  First, the general purpose power product release counter C4 will be described. For example, the commercial power release counter C4 is sequentially incremented by 1 within the range of 0 to 250, and returns to “0” after reaching the maximum value. The routine charge release counter C4 is periodically updated, and is stored in the general-purpose hold area 64c of the RAM 64 at the timing when the game ball wins the through gate 35. Then, at a predetermined timing, a lottery is performed to determine whether or not the general-purpose utility 34a is controlled to an open state by the value of the stored general-purpose utility open counter C4.

  In the pachinko machine 10, a plurality of types of support modes are set such that the modes of support by the power control unit 34a differ from one another. In detail, in the support mode, when compared with the situation where the firing of the game ball is continued in the same manner with respect to the game area PA, the commercial electric utility 34a of the second operation opening 34 per unit time The high frequency support mode and the low frequency support mode are set such that the frequency of the open state is relatively high and low.

  In the high-frequency support mode and the low-frequency support mode, the probability of winning the common power open status in the common power open lottery using the common power utility open counter C4 is the same (for example, both are 4/5) In the high-frequency support mode, the number of times the general-purpose product 34a becomes open when the general-purpose open state is won is set to a larger number than in the low-frequency support mode, and one open time is set longer It is done. In this case, when the general electric power release state is won in the high frequency support mode and the open state of the general power utility item 34a occurs a plurality of times, it is from the end of one open state to the start of the next open state. The closing time is set to be shorter than one opening time. Furthermore, in the high frequency support mode, the securing time minimumly secured in performing the next public power release lottery after the first public power release lottery is performed rather than the low frequency support mode One display continuation time in the display unit 38a is set to be short.

  As described above, in the high frequency support mode, the probability of winning in the second operation port 34 is higher than in the low frequency support mode. In other words, in the low frequency support mode, the probability of winning in the first operation port 33 is higher than that of the second operation port 34, but in the high frequency support mode, the second operation is higher than the first operation port 33. There is a high probability that a winning on the mouth 34 will occur. And, when the winning a prize to the 2nd operation opening 34 occurs, because the payout of the game sphere of specified number is executed, in the high frequency support mode, the game while the player does not decrease the ball very much It can be carried out.

  Note that the configuration for increasing the frequency at which the common power release state occurs per unit time in the high-frequency support mode rather than the low-frequency support mode is not limited to the above-described one. It is good also as composition which makes high the probability of being in a state where the general public is released. In addition, a securement time (for example, based on winning on the through gate 35) is performed in the generalization display portion 38a, which is secured when the next general public open lottery is performed after one public open public lottery is performed. In the configuration in which multiple types of variable display time) are prepared, the high frequency support mode is set so that the short securing time is easier to be selected or the average securing time is shorter than the low frequency support mode. It is also good. Furthermore, the number of opening times is increased, the opening time is extended, and the securing time secured in performing the next public power release lottery after the one public power opening lottery is performed, the securing time to be related, The advantage of the high frequency support mode over the low frequency support mode may be enhanced by applying any one condition or any combination of conditions among the shortening of the average time of and the increase of the winning probability.

  Next, the per-random number counter C1 will be described. The per-random number counter C1 is configured to be sequentially incremented by one, for example, within the range of 0 to 599, and return to “0” after reaching the maximum value. In particular, when the per random number counter C1 makes one revolution, the value of the random number initial value counter CINI at that time is read as the initial value of the per random number counter C1. The random number initial value counter CINI is a loop counter similar to the per random number counter C1 (value = 0 to 599). The random number counter C1 is periodically updated, and is stored in the hold storage area 64a of the RAM 64 at the timing when the gaming ball wins the first operation port 33 or the second operation port 34.

  The value of the random number for winning the jackpot is stored in the ROM 63 as a success or failure table. As the pass / fail table, a pass / fail table for the low probability mode and a pass / fail table for the high probability mode are set. That is, in the pachinko machine 10, the low probability mode and the high probability mode are set as the lottery mode in the hit / fall lottery means.

  Under the gaming state where the low probability mode hit / fail table is referred to at the time of the lottery, the number of random numbers to be a big hit is two. On the other hand, under the gaming state where the high-probability mode hit / fail table is referred to at the time of the lottery, the number of random numbers to be a big hit is twenty. If the winning probability in the high probability mode is higher than that in the low probability mode, the number of random numbers to be won is arbitrary.

  The jackpot type counter C2 is configured to be sequentially incremented by one within the range of 0 to 29 and to return to “0” after reaching the maximum value. The jackpot type counter C2 is periodically updated, and is stored in the hold storage area 64a at a timing when the gaming ball has won the first operation port 33 or the second operation port 34.

  In the pachinko machine 10, a plurality of jackpot results are set. These plural jackpot results are (1) the mode of opening and closing control of the special power winning device 32 in the opening and closing execution mode, (2) the lottery mode in the lottery means after completion of the opening and closing execution mode, and (3) the third after opening and closing execution mode A plurality of jackpot results are set by making a difference in the three conditions of the support mode in the common use utility 34 a of the 2 operation port 34.

  As an aspect of the open / close control of the special power winning device 32 in the open / close execution mode, the frequency of occurrence of winnings on the special power winning device 32 in the period from the start to the end of the open / close execution mode is relatively high. A frequency winning mode and a low frequency winning mode are set. Specifically, in any of the high-frequency winning mode and the low-frequency winning mode, a predetermined number of round games are executed with an upper limit.

  Here, the round game is continued until either a predetermined upper limit continuation time elapses or a predetermined upper limit number of gaming balls wins the special power prize device 32 is satisfied. It is a game to play. Further, the number of round games in the opening / closing execution mode triggered by the jackpot result is the same as the fixed round number regardless of the type of jackpot result triggered by the transition. Specifically, the upper limit number of round games is set to 15 rounds regardless of which jackpot result.

  Further, in the pachinko machine 10, a plurality of types of one-time opening mode of the special electric winning device 32 is set by making the opening continuation time from the opening of the special electric winning device 32 to the closing different. Specifically, a long-time mode in which the opening continuation time is set to 29 sec, which is a long time, and a short-time mode in which the opening continuation time is set to 0.06 sec, which is a short time shorter than the long time, are set. It is done.

  In the pachinko machine 10, in a situation where the launch operation device 28 is operated by the player, the game ball emission mechanism 27 is drive-controlled so that one game ball is emitted toward the game area in 0.6 sec. Ru. In addition, the upper limit number of end conditions of the round game is set to nine. Then, in the long time mode among the open modes, the open continuation time of a time longer than the product of the firing cycle of the game balls and one round game is set. On the other hand, in the short time mode, the opening duration time of the time shorter than the product of the game ball firing cycle and one round game, more specifically, the time shorter than the game ball firing cycle is set. Therefore, when one opening is performed in the long time mode, it is expected that the special power winning device 32 will receive winnings for the upper limit number in one round game, and the short time mode 1 When the opening is performed, it is expected that no prize will be generated on the special power winning device 32, or even if there is a prize, it will be about one.

  In the high frequency winning mode, the special power winning device 32 is opened once by the long time mode in each round game. On the other hand, in the low frequency winning mode, the special power winning device 32 is opened once in a short time mode in each round game.

  In addition, the number of opening and closing times of special power winning device 32 in high frequency winning mode and low frequency winning mode, the number of round games, opening continuation time for one opening, and the upper limit number in one round game, the high frequency winning mode If the frequency of occurrence of winnings to the special power winning device 32 in the period from when the opening / closing execution mode is started to the end is higher than in the low frequency winning mode, it is not limited to the above value and is arbitrary It is.

  The distribution destination of the game result for the jackpot type counter C2 is stored in the ROM 63 as a distribution table. Then, as the distribution destination, the low probability jackpot result, the low winning high probability jackpot result, and the most advantageous jackpot result are set.

  The low probability jackpot result is a jackpot result in which the opening / closing execution mode becomes the high frequency winning mode, and after the opening / closing execution mode ends, the pass / fail lottery mode becomes the low probability mode and the support mode becomes the high frequency support mode. However, in the high-frequency support mode, the transition to the low-frequency support mode is made when the number of games has reached the end reference frequency (specifically, 100 times) after the transition.

  In the low winning high probability big hit result, the opening and closing execution mode becomes the low frequency winning mode, and after the opening and closing execution mode ends, the success or failure lottery mode becomes the high probability mode and the support mode becomes the high frequency support mode. is there. The high probability mode and the high frequency support mode continue until the lottery result in the success or failure lottery is a big hit, and the mode is switched to the open / close execution mode.

  The most advantageous jackpot result is a jackpot result in which the opening / closing execution mode becomes the high frequency winning mode, and after the opening / closing execution mode ends, the pass / fail lottery mode becomes the high probability mode and the support mode becomes the high frequency support mode. The high probability mode and the high frequency support mode continue until the lottery result in the success or failure lottery is a big hit, and the mode is switched to the open / close execution mode.

  Note that the normal gaming state is not the opening / closing execution mode, but the winning lottery mode is the low probability mode and the support mode is the low frequency support mode, in relation to the above gaming states. Further, as a game result, a configuration may be made in which the low winning high probability big hit result is not set.

  In the sorting table, among the values of the big hit type counter C2 of "0 to 29", "0 to 9" corresponds to the low probability big hit result, and "10 to 14" corresponds to the low winning high certain jackpot result “15-29” corresponds to the most advantageous jackpot result.

  Next, the reach random number counter C3 will be described. For example, the reach random number counter C3 is sequentially incremented by one within the range of 0 to 238, and returns to “0” after reaching the maximum value. Here, in the present pachinko machine 10, an expected effect is set as a type of display effect in the symbol display device 41. An expected effect includes the symbol display device 41 capable of performing variable display of symbols, and in the gaming machine that results in a predetermined jackpot, the symbol display device 41 in the gaming machine in which the final stop result is the corresponding result. Before the stop result is derived and displayed after the variable display of the symbol in is started, it means the display state for making the player think that it is a variable display state in which the above-mentioned correspondence with correspondence result is likely to be obtained. In addition, specifically, about the provision corresponding | compatible result, the combination of the symbol in which the same number was attached | subjected on one effective line is stopped-displayed.

  In the expectation effect, two types of reach display and advance notice display for expecting the occurrence of reach display and the occurrence of the response to an assignment in a stage before the reach display and the like are set.

  In the reach display, a combination of reach symbols consisting of the same symbol is displayed by stopping and displaying the symbols for a part of the plurality of symbol rows displayed on the display surface 41a of the symbol display device 41. In the state, the display state in which the variable display of the symbols is performed in the remaining symbol rows is included. Also, while displaying combinations of reach symbols as described above, while performing variable display of symbols in the remaining symbol rows, and performing reach effects by displaying a predetermined character or the like as a moving image on the background screen, or Also, there is a method of performing reach effect by displaying a predetermined character or the like as a moving image over substantially the entire display surface 41 a after reducing or displaying a combination of reach symbols in reduced size or non-display.

  In the advance notice display, after the variable display of the symbols is started on the display surface 41a of the symbol display device 41, the symbols are variably displayed in all the symbol rows, or a part of the symbol rows are plural. In a situation where symbols are variably displayed in the symbol row, a mode is included in which a character is displayed separately from the symbols on the symbol row. In addition, the background screen is a predetermined mode different from the previous modes, and the pattern on the symbol array is the predetermined mode different from the previous modes. Such advance notice may occur at any of the game times when the reach display is performed and when the reach display is not performed, but the case where the reach display is performed is higher than the case where the reach display is not performed. It is set to occur with probability.

  The reach display is executed regardless of the value of the reach random number counter C3 in the game times in which the combination of the same symbols is finally stopped and displayed. Moreover, in the game time corresponding to the big hit result in which the combination of the same symbol is not stopped and displayed, it is not performed irrespective of the value of the reach random number counter C3. Further, the game times corresponding to the disconnection result are executed when the reach random number counter C3 acquired at a predetermined timing with reference to the reach table stored in the ROM 63 corresponds to the occurrence of the reach display.

  On the other hand, the main control unit 60 does not determine whether to display the advance notice, but the sound emission control unit 80 determines. In this case, in the voice light emission control device 80, the game display corresponding to any of the big hit results is more likely to generate a notice display than the game play corresponding to the out result, and the notice display having a low appearance rate A lottery process for displaying a notice is performed so as to satisfy at least one of the conditions that are likely to occur. By the way, this lottery result is reflected when the effect for the game round is executed by the symbol display device 41.

  Next, the variation type counter CS will be described. For example, the fluctuation type counter CS is sequentially incremented by one within the range of 0 to 198, and returns to “0” after reaching the maximum value. The fluctuation type counter CS is used when the MPU 62 determines the display continuation time in the special view display unit 37 a and the display continuation time of the symbol in the symbol display device 41. The fluctuation type counter CS is updated once each time a normal process to be described later is executed once, and is repeatedly updated even within the remaining time in the normal process. Then, the buffer value of the fluctuation type counter CS is acquired at the time of the start of the fluctuation display in the special view display unit 37a and the time of the fluctuation pattern determination at the time of the fluctuation start of the symbol by the symbol display device 41.

<About Processing Configuration of Main Controller 60>
Next, each process executed to advance the game in the MPU 62 of the main control device 60 will be described. The processes of the MPU 62 are roughly classified into a main process activated upon power-on and a timer interrupt process activated periodically (with a cycle of 4 msec in the present embodiment).

<Main processing>
First, the main processing will be described with reference to the flowchart of FIG.

  In step S101, power on wait processing is performed. In the power-on wait process, for example, the process waits until the predetermined time for wait (specifically, 1 sec) elapses after the main process is started, without progressing to the next process. The operation start and initialization of the symbol display device 41 are completed in the execution period of the power on wait process. In the following step S102, access to the RAM 64 is permitted, and in step S103, the internal function register of the MPU 62 is set.

  Thereafter, in step S104, it is determined whether or not the RAM erase switch provided in the power / emission control device 78 is manually operated, and in the subsequent step S105, "1" is set in the power failure flag of the RAM 64 or not. Determine if In step S106, a checksum calculation process is performed to calculate a checksum. In the subsequent step S107, it is determined whether the checksum matches the checksum stored at the time of power shutdown, that is, the validity of stored data. judge.

  In the pachinko machine 10, when initializing the RAM data at the time of power on, for example, at the start of business operation of the game hall, the power is turned on while pressing the RAM erase switch. Therefore, if the RAM erase switch is pressed, the process proceeds to step S108. In addition, when the occurrence information of the power-off is not set, or when the abnormality of the data stored and held is confirmed by the checksum, the process similarly shifts to the process of step S108. In step S108, the RAM 64 is cleared. Thereafter, the process proceeds to step S109.

  On the other hand, when the RAM erase switch is not pressed, the process in step S108 is not performed under the condition that the power failure flag is set to “1” and the checksum is normal. Go to In step S109, power on setting processing is performed. In the power-on setting process, a predetermined area of the RAM 64 such as initialization of the power failure flag is set to an initial value, and a command corresponding to the current gaming state is transmitted to the voice emission control device 80 to recognize the current gaming state. Do.

  Thereafter, the process proceeds to the remaining process of step S110 to step S113. That is, although the MPU 62 is configured to periodically execute the timer interrupt process, a remaining time is generated between one timer interrupt process and the next timer interrupt process. Although this remaining time fluctuates in accordance with the processing completion time of each timer interrupt process, the remaining process of step S110 to step S113 is repeatedly executed using such irregular time. In this regard, it can be said that the remaining process of the step S110 to the step S113 is a non-periodic process which is executed irregularly.

  In the remaining process, first, in step S110, in order to inhibit the generation of the timer interrupt process, the interrupt disable setting is performed. In the following step S111, the random number initial value updating process for updating the random number initial value counter CINI is executed, and in step S112, the variation counter updating process for updating the variation type counter CS is executed. In these update processes, the present numerical value information is read out from the corresponding counter of the RAM 64, and the process of adding one to the read out numerical value information is executed, and then the process of overwriting the read source counter is executed. In this case, when the counter value reaches the maximum value, it is cleared to "0". After that, in step S113, interrupt permission setting is performed to switch from the state where the generation of the timer interrupt processing is prohibited to the state where it is permitted. If the process of step S113 is performed, it will return to step S110 and will repeat the process of step S110-step S113.

<Timer interrupt processing>
Next, timer interrupt processing will be described with reference to the flowchart of FIG. The timer interrupt process is executed periodically (for example, 4 msec cycle).

  First, in step S201, a power failure information storage process is executed. In the power failure information storage process, it is monitored whether or not a power failure signal corresponding to the occurrence of the power interruption is received from the power interruption monitoring board 65, and when the occurrence of the power interruption is specified, the power failure time process is executed.

  In the subsequent step S202, a lottery random number update process is executed. In the random number updating process for drawing, the update of the per random number counter C1, the big hit type counter C2, the reach random number counter C3, and the general purpose battery release counter C4 is executed. Specifically, the present numerical value information was sequentially read out from the per random number counter C1, the big hit type counter C2, the reach random number counter C3 and the general electric utility release counter C4, and the process of adding one each of the read numerical information was executed. Later, the process of overwriting the read source counter is executed. In this case, when the counter value reaches the maximum value, it is cleared to "0".

  Thereafter, in step S203, the random number initial value updating process is performed as in step S111, and in step S204, the variation counter updating process is performed as in step S112.

  In the subsequent step S205, a fraud detection process is performed to monitor whether or not a predetermined event set as a fraud monitoring target has occurred. In the fraud detection process, occurrence of multiple types of events is monitored, and it is confirmed that a predetermined event has occurred, thereby setting “1” to the game stop flag provided in the RAM 64.

  In the subsequent step S206, it is determined whether or not the progress of the game is stopped by determining whether or not "1" is set to the game stop flag. If a negative determination is made in step S206, processing in step S207 and subsequent steps is executed.

  In step S207, port output processing is performed. In the port output process, when output information is set in the previous timer interrupt process, the process corresponding to the output information is performed to the various drive units 32b and 34b through the output port 62b of the MPU 62. Run. For example, when the information to switch the special power winning device 32 to the open state is set, the output of the drive signal to the drive unit 32b for the special power is started, and the information to switch to the closed state is set. Stops the output of the drive signal. In addition, when the information to switch the common use utility 34 a in the second operation port 34 to the open state is set, the output of the drive signal to the drive unit 34 b for general use should be started to switch to the closed state. When the information is set, the output of the drive signal is stopped.

  In the following step S208, a reading process is performed. In the reading process, reading of signals other than the power failure signal and the winning signal is executed through the input port 62a of the MPU 62, and the read information is stored for future processing.

  In the subsequent step S209, a winning detection process is executed. In the winning detection process, the signals received from the winning detection sensors 66a to 66e are read through the input port 62a of the MPU 62, and the general winning opening 31, the special electric winning device 32, the first operation opening 33, and the second operation opening A process is executed to specify the presence or absence of winning on 34 and the through gate 35.

  In the subsequent step S210, a timer update process is performed to collectively update numerical information of a plurality of types of timer counters provided in the RAM 64. In this case, the timer counter is stored in which the stored numerical information is subtracted and updated, but both the update of the subtraction type timer counter and the update of the addition type timer counter are collectively performed. It is good also as composition.

  In the following step S211, a launch control process is performed to control the launch of the gaming ball. In the situation where the launch operation to the launch operation device 28 is continued, as described above, one gaming ball is launched in 0.6 sec which is a predetermined launch cycle.

  In the following step S212, as input state monitoring processing, confirmation of disconnection of each of the winning detection sensors 66a to 66e and confirmation of opening of the gaming machine main body 12 and the front door frame 14 based on the information read in the reading processing of step S208. Do.

  In the following step S213, special figure special power control processing for executing execution control of the game times and execution control of the open / close execution mode is executed. In the special figure special power control process, in the case where the first operation port 33 or the second operation port 34 has a prize, the number of the suspension information stored in the suspension storage area 64a is less than the upper limit number, A process of storing each numerical value information of the per random number counter C1, the big hit type counter C2 and the reach random number counter C3 at the time point as the hold information in time series in the hold storage area 64a is executed. Further, in the special view special power control process, on the condition that the game is not running or in the opening / closing execution mode and the holding information is stored, it is determined whether the holding information corresponds to a big hit or not. If it corresponds to processing and jackpot winning, distribution determination processing is executed to determine which jackpot result the hold information corresponds to. Further, in the special view special power control process, in addition to the success / failure determination process and the distribution determination process, when the hold information does not correspond to the jackpot win, it is determined whether the hold information corresponds to the reach occurrence. While performing the reach determination process to determine, the process which selects the continuation time of a game time using the numerical information of the fluctuation | variation type | mold counter CS in that time is performed. And while transmitting the command for change including the information on the duration according to the result of each of those processing and the type command including the information on the game result to the voice emission control device 80, the pattern in the special view display portion 37a Start variable display. As a result, one game cycle is started, and the special game display unit 37a and the symbol display device 41 start producing effects for the game cycle.

  Also, in the special view special power control process, it is determined whether or not it is the end timing of the game turn during execution of one game turn, and in the state where the display corresponding to the game result is performed in the end timing. , Execute processing to end the game times. In this case, a final stop command indicating that the game play should be ended is transmitted to the sound emission control device 80. Further, in the special view special power control process, when the result of the game play is a result corresponding to the transition to the open / close execution mode, a process for starting the open / close execution mode is executed. At the time of this start, an opening command indicating that the open / close execution mode is started is transmitted to the sound emission control apparatus 80. Further, in the special view special power control process, a process for starting each round game and a process for ending each round game are executed. At the time of each processing, an open command indicating that a round game is to be started is transmitted to the sound emission control device 80, and a close command indicating that the round game is to be ended is transmitted to the sound emission control device 80. Further, in the special figure special power control process, when ending the open / close execution mode, an ending command indicating that is transmitted to the voice emission control device 80 and for setting the lottery mode or support mode after the open / close execution mode. Execute the process

  After the special figure special power control process of step S213 is executed in the timer interrupt process, the general view general power control process is executed in step S214. When the winning gate on the through gate 35 has been awarded, the routine control routine executes processing for acquiring the hold information on the general view side, and the hold information on the general view side is stored. Then, the release determination is performed on the hold information, and the release determination is used as a trigger to execute processing for producing effects for the common drawing. Also, based on the result of the open determination, processing is performed to open and close the general purpose utility product 34 a of the second operation port 34.

  In the following step S215, based on the processing results of the immediately preceding step S213 and step S214, setting of output information for reflecting the increase / decrease number of the hold information concerning the special view display unit 37a on the special view hold display unit 37b is performed. The output information is set to reflect the increase / decrease number of the suspension information related to the common drawing display unit 38a on the common drawing reservation display unit 38b. Further, in step S215, based on the processing results of the previous step S213 and step S214, setting of output information for updating the display content of the special view display unit 37a is performed, and the display content of the common view display unit 38a is set. Set the output information for updating. The setting of the output information in step S215 is performed through the output port 62b of the MPU 62.

  In the subsequent step S216, the contents of the command and signal received from the payout control device 77 are confirmed, and a payout state reception process for performing a process corresponding to the confirmation result is executed. In step S217, a payout output process for setting a winning ball command as an output target is executed. In the subsequent step S218, an external information setting process is performed to control the start and end of the output of the external signal according to the processing results of various processes executed in the timer interrupt process this time. Thereafter, this timer interrupt processing is ended.

<Electrical Configuration for Reading Data in MPU 62>
Next, an electrical configuration for reading an instruction and data and writing data in the MPU 62 will be described. FIG. 8 is a block diagram for explaining the electrical configuration of the CPU 101 provided in the MPU 62. As shown in FIG.

  The MPU 62 incorporates the CPU 101. The CPU core 102 incorporated in the CPU 101 reads various instructions from the ROM 83 incorporated in the MPU 62, and executes arithmetic processing, analysis processing of input data, and output processing of data according to a program corresponding to the instructions. Specifically, the CPU core 102 reads an instruction from the area of the address corresponding to the value of the program counter which is built in the CPU core 102 and updated as the processing of the CPU core 102 proceeds, and the processing corresponding to the instruction To execute various processes according to the program.

  The CPU core 102 includes a Vcc terminal, a GND terminal, an INT terminal, an NMI terminal, data terminals D0 to D7, address terminals A0 to A15, an RD terminal, a WR terminal, an IREQ terminal, an MREQ terminal, and the like. The data terminals D0 to D7, the address terminals A0 to A15, the RD terminal, the WR terminal, the IREQ terminal, and the MREQ terminal will be described in detail below. The description of the Vcc terminal, the GND terminal, the INT terminal and the NMI terminal is omitted. The Vcc terminal, the GND terminal, the INT terminal, and the NMI terminal are also provided in the CPU 101, but the description thereof is also omitted.

  Data terminals D0 to D7 read an instruction in CPU core 102, read data referred to in executing processing in CPU core 102 according to a program corresponding to the instruction, and CPU core 102 according to a program corresponding to the instruction. Is a terminal for writing data derived as a result of the processing in A plurality of data terminals D0 to D7 are provided, and are electrically connected to data terminals D10 to D17 provided in the CPU 101. Specifically, eight data terminals D0 to D7 of CPU core 102 are provided, and eight data terminals D10 to D17 of CPU 101 are also made to correspond to data terminals D0 to D7 of CPU core 102 on a one-to-one basis. It is provided. Data terminals D0 to D7 of CPU core 102 are electrically connected to data terminals D10 to D17 of CPU 101 through data bus DB built in CPU 101, and data terminals D10 to D17 of CPU 101 are provided in MPU 62. It is electrically connected to the data bus DB. With such a configuration, the CPU core 102 can read 8-bit (i.e., 1 byte) data collectively through the data bus DB, and also transmit 8-bit (i.e., 1 byte) data to the data bus DB. Can be written together.

  Address terminals A0 to A15 are used to read an instruction from ROM 63 in CPU core 102 and to specify an address of an area in which the instruction or data exists when reading data from ROM 63 or RAM 64 in CPU core 102. It is a terminal. The address terminals A0 to A15 are terminals for designating an address of an area to which the data is to be written when the CPU core 102 writes the data to the ROM 63 or the RAM 64. A plurality of address terminals A0 to A15 are provided, and are electrically connected to address terminals A20 to A35 provided in the CPU 101. Specifically, 16 address terminals A0 to A15 of CPU core 102 are provided, and 16 address terminals A20 to A35 of CPU 101 are also made to correspond to address terminals A0 to A15 of CPU core 102 on a one-to-one basis. It is provided. The address terminals A0 to A15 of the CPU core 102 are electrically connected to the address terminals A20 to A35 of the CPU 101 through an address bus AB built in the CPU 101, and the address terminals A20 to A35 of the CPU 101 are provided inside the MPU 62. It is electrically connected to the address bus AB. With this configuration, the CPU core 102 can specify an address to the ROM 63 and the RAM 64.

  The address terminals A0 to A15 are used not only when addressing the ROM 63 and the RAM 64 but also when outputting chip select signals from chip select terminals CS0 to CS12 provided in the CPU 101. Here, the chip select terminals CS0 to CS12 designate an input latch circuit 103 (see FIG. 9A) to be operated when reading an instruction in the CPU core 102 and reading data in the CPU core 102. When writing data in the CPU core 102, it is a terminal for specifying the output latch circuit 104 (see FIG. 9B) to be operated.

  A plurality of input latch circuits 103 are built in the MPU 62. The plurality of input latch circuits 103 include an input latch circuit for specifying the ROM 63 as a read target when reading an instruction and data, an input latch circuit for specifying the RAM 64 as a read target when data is read, An input latch circuit is provided to designate an area in which the input data is stored when reading data input to the input port 62a of the MPU 62 as an object to be read. The input latch circuit for specifying the area where the input data is stored as the reading target when reading the data input to the input port 62a of the MPU 62 makes the area to be specified as the reading target different in the input port 62a. A plurality of these are provided.

  A plurality of output latch circuits 104 are incorporated in the MPU 62. The plurality of output latch circuits 104 include an output latch circuit for specifying the RAM 64 as a write target when writing data, and an area for storing the output data when outputting data to the output port 62b of the MPU 62 as a write target An output latch circuit for designating as is provided. An output latch circuit for designating an area for storing the output data as a write target when outputting data to the output port 62b of the MPU 62 is provided in a plurality with different areas designated for the read target in the output port 62b. There is.

  A plurality of chip select terminals CS0 to CS12 are provided, and the chip select terminals CS0 to CS12 are electrically connected to select signal lines provided inside the MPU 62, respectively. Specifically, thirteen chip select terminals CS0 to CS12 are provided, and thirteen select signal lines are provided in one-to-one correspondence with the chip select terminals CS0 to CS12. A plurality of chip select terminals CS0 to CS4, which are a part of the chip select terminals CS0 to CS12, are for outputting the CS0 signal to CS4 signal as a chip select signal to the input latch circuit 103, and the remaining plural chips The select terminals CS5 to CS12 are for outputting the CS5 signal to the CS12 signal as a chip select signal to the output latch circuit 104.

  The input latch circuit 103 will be described by taking, as an example, one used in the CPU 101 when predetermined data is input from the input port 62 a of the MPU 62. FIG. 9A is a block diagram of the input latch circuit 103. As shown in FIG. 9A, the input latch circuit 103 uses the input terminals Q0 to Q7 for receiving data from the input port 62a and the data stored in the input latch circuit 103 through the input terminals Q0 to Q7 as data. Data terminals D20 to D27 for supplying data to the bus DB, a CK terminal to which a CS0 signal output from a chip select terminal CS0 of the CPU 101 is input, and the like are provided. The input latch circuit 103 receives the signal CS0 from the chip select terminal CS0 of the CPU 101 to the CK terminal, whereby the data stored in the input latch circuit 103 through the input terminals Q0 to Q7 is converted to the data terminal D20 to The data is supplied to the data bus DB through D27. The input latch circuit 103 is provided with a Vcc terminal, a GND terminal, a CLR terminal and the like in addition to these terminals.

  The output latch circuit 104 will be described by taking, as an example, one used in the CPU 101 when predetermined data is output to the output port 62 b of the MPU 62. FIG. 9 (b) is a block diagram of the output latch circuit 104. As shown in FIG. 9B, the output latch circuit 104 outputs the data stored in the output latch circuit 104 through data terminals D30 to D37 and data terminals D30 to D37 for receiving data from the data bus DB. The output terminal Q10 to Q17 for supplying to the port 62b, the CK terminal to which the CS5 signal output from the chip select terminal CS5 of the CPU 101 is input, and the like are provided. When the CS5 signal is input from the chip select terminal CS5 of the CPU 101 to the CK terminal, the output latch circuit 104 places the data provided to the data bus DB through the data terminals D30 to D37 into the output latch circuit 104. After capturing, the captured data is output from the output terminals Q10 to Q17 to the output port 62b. The output latch circuit 104 has a Vcc terminal, a GND terminal, a CLR terminal, and the like in addition to these terminals.

  While the chip select terminals CS0 to CS12 of the CPU 101 have the above functions, the address data output from the address terminals A0 to A15 (see FIG. 8) of the CPU core 102 is a chip select for outputting a chip select signal. It is used to select terminals CS0 to CS12. Further, when selecting the chip select terminals CS0 to CS12 for outputting a chip select signal, signals output from the RD terminal, the WR terminal, the IREQ terminal and the MREQ terminal of the CPU core 102 are used.

  The RD terminal is a terminal for outputting an RD signal which specifies that the CPU core 102 reads an instruction or reads data. The WR terminal is a terminal for outputting a WR signal which specifies that the CPU core 102 writes data. The IREQ terminal designates an IREQ signal designating that the CPU core 102 is to execute an in instruction for inputting data from the input port 62a or an out instruction for outputting data to the output port 62b. It is a terminal for outputting. The MREQ terminal specifies that the CPU core 102 is to execute a load instruction for reading an instruction or data from the ROM 63, writing data to the RAM 64, reading data from the RAM 64, or the like. It is a terminal for outputting.

  Next, various instructions executed in the CPU core 102 will be described. FIG. 10 is an explanatory diagram for explaining an area in which an instruction is stored in the ROM 63. As shown in FIG.

  In the ROM 63, a 1-byte instruction, a 2-byte instruction and a 3-byte instruction are stored in advance as instructions. Among these instructions, the in-instruction and out-instruction described above correspond to a 2-byte instruction, and the load instruction corresponds to a 3-byte instruction. Incidentally, 2-byte instructions include instructions other than in-instructions and out-instructions, and 3-byte instructions include instructions other than load instructions. Further, the number of bytes of the instruction is not limited to these, and a 4-byte instruction may be stored in advance in addition to or instead of the instruction of the number of bytes.

  FIG. 11A is an explanatory diagram for explaining in-instructions and out-instructions which are 2-byte instructions. The in instruction and the out instruction include the address code shown in FIG. 11 (a1) and the IO identification code shown in FIG. 11 (a2). The address code has a 1-byte data structure and is set to the first byte in the in-instruction and out-instruction. Depending on the contents set in the address code, the type of input latch circuit 103 to be operated when outputting data from the input port 62a and the type of operation when outputting data to the output port 62b The type of output latch circuit 104 is identified. In this case, since the address code has a 1-byte data configuration, it is possible to specify 256 addresses as an address for specifying the type of latch circuit 103 or 104 to be operated. However, in the pachinko machine 10, as described above, the number of chip select terminals CS0 to CS12 of the CPU 101 is thirteen, so the number of types of addresses actually designated is thirteen or less.

  The IO identification code has a 1-byte data configuration, and the content set in the IO identification code identifies whether the type of the 2-byte instruction is an in instruction or an out instruction. Incidentally, if it is an out instruction, the value next to the value of the program counter corresponding to the out instruction corresponds to a 1 byte instruction, and 1 byte of output data to be output to the output port 62b for that 1 byte instruction Is set.

  FIG. 11B is an explanatory diagram for explaining a load instruction which is a 3-byte instruction. The load instruction includes the first address code shown in FIG. 11 (b1), the second address code shown in FIG. 11 (b2), and the execution code shown in FIG. 11 (b3). The first address code and the second address code both have 1-byte data configuration, the first address code is set to the first byte in the load instruction, and the second address code is the second in the load instruction. Is set to byte. The type of area to be read when reading instructions and data according to the contents set in the first address code and the second address code, and the type of area to be written when writing data Is identified.

  The execution code has a 1-byte data configuration, and the type of the instruction to be executed is specified by the contents set in the execution code. As an instruction to be executed, a transfer instruction, an arithmetic operation instruction, a logical operation instruction, a bit operation instruction, a rotate instruction, a shift instruction, and the like are set. In the case of a transfer instruction, processing of reading data of an address designated by the first address code and the second address code to the CPU core 102, or predetermined data at the address designated by the first address code and the second address code The process of transferring Further, in the case of an arithmetic operation instruction, processing of adding predetermined data to data and processing of subtracting data are executed. Further, in the case of a logical operation instruction, processing for performing a predetermined logical operation on data is executed. Further, in the case of a bit manipulation instruction, processing of switching a predetermined bit of data between "0" and "1" is executed. Also, in the case of a rotate instruction, processing is performed to shift bits included in data so as to circulate in a predetermined direction. Further, in the case of the shift instruction, processing for shifting in a predetermined direction is performed without circulating bits included in the data.

  Next, the IO space 105 and the memory space 106, which are virtual spaces accessed by the CPU core 102, will be described. FIG. 12 is a block diagram for explaining the IO space 105 and the memory space 106.

  The IO space 105 is a virtual space accessed by the CPU core 102 when the CPU core 102 executes an in instruction or an out instruction. The situation where the CPU core 102 is accessing the IO space 105 is, in fact, chip select from the corresponding chip select terminal of the CPU 101 to the corresponding input latch circuit 103 in order to input data from the input port 62a. A signal is being output, or a chip select signal is output from the corresponding chip select terminal of the CPU 101 to the corresponding output latch circuit 104 in order to output data to the output port 62b.

  The address code is 1 byte as described above in the in instruction and out instruction to access the IO space 105. Therefore, the number of addresses that can be designated as the IO space 105 in the CPU core 102 is 256 corresponding to 1 byte. Corresponding to this, when accessing the IO space 105, among the 16 address terminals A0 to A15 of the CPU core 102, only a plurality of eight address terminals A0 to A7 which are a part and plural are used. Address is specified. That is, when the IO space 105 is accessed, the same number of address terminals A0 to A7 as the number of bits of the address code set in the in instruction and out instruction are used. This makes it possible to use the contents of the address code set in the in command and out command as they are as data to be set in the address terminals A0 to A7. The address data set in the first byte in the in instruction and out instruction are eight consecutive address terminals A0 of the address terminals A0 to A15 of the CPU core 102 from the zeroth address terminal A0 toward the lower side. Corresponds to ~ A7.

  The memory space 106 is a virtual memory that the CPU core 102 accesses when the CPU core 102 reads an instruction from the area of the ROM 63 at an address corresponding to the value of the program counter and when the CPU core 102 executes a load instruction. It is a space. The situation where the CPU core 102 is accessing the memory space 106 is, in fact, to read an instruction or data from the ROM 63 or read data from the RAM 64 to the corresponding chip select terminals CS0 to CS4 of the CPU 101. The situation where the chip select signal is output to the corresponding input latch circuit 103 corresponds to the above, and the output latch circuit corresponding to the corresponding chip select terminals CS5 to CS12 of the CPU 101 to write data to the RAM 64. The situation where the chip select signal is output to 104 corresponds.

  In the load instruction to access the memory space 106, as described above, the address code is 2 bytes in total of the first address code and the second address code. Therefore, the number of addresses that can be designated as the memory space 106 in the CPU core 102 is 65,536 corresponding to 2 bytes. Corresponding to this, when the memory space 106 is accessed, addressing is performed using all of the 16 address terminals A0 to A15 of the CPU core 102. That is, when accessing the memory space 106, the same number of address terminals A0 to A15 as the total number of bits of the first address code and the second address code set in the load instruction are used. As a result, the contents of the first address code and the second address code set in the load instruction can be used as they are as data to be set in the address terminals A0 to A15.

  The first address data set in the first byte in the load instruction is eight consecutive address terminals A0 to A15 among the address terminals A0 to A15 of the CPU core 102 from the zeroth address terminal A0. It corresponds to A7. Further, the second address data set in the second byte in the load instruction is eight consecutive address terminals of the address terminals A0 to A15 of the CPU core 102 from the eighth address terminal A8 toward the lower side. It corresponds to A8 to A15.

  Here, as described above, in the in command and out command, the address data is set in the first byte, and the data corresponding to the address terminals A0 to A7 is set in the address data as the address code. . That is, data corresponding to the address terminals A0 to A7 is set in the first byte in any of the in instruction, the out instruction, and the load instruction. As a result, data set in the first byte may be set in the address terminals A0 to A7 regardless of whether it is an in instruction, an out instruction, or a load instruction. It becomes possible to achieve simplification of the processing configuration by enabling the processing configuration to be common.

  Next, the contents that the CPU core 102 can execute the load instruction will be described also when inputting data from the input port 62a and when outputting data to the output port 62b.

  As described above, the in-instruction and out-instruction consist of 2 bytes of the address code and the IO identification code, and the address code sets an address for specifying the type of the latch circuit 103 or 104 to be operated. The IO identification code is set with data indicating which of the in instruction and the out instruction corresponds to. In the case of this configuration, the execution code can not be set as in the load instruction in the in instruction and the out instruction. Furthermore, since the total number of bits of 2-byte instructions is smaller than that of 3-byte instructions, naturally, the usable number of 2-byte instructions is also limited.

  On the other hand, the load instruction can be executed in the CPU core 102 also when data is input from the input port 62a and when data is output to the output port 62b. This makes it possible to use the execution code even when these data are input / output. For example, when data is input from the input port 62a, a load instruction is executed to read data in a state after changing the arrangement of a plurality of bits, or data set in a plurality of bits It is possible to read data of the state after respectively inverting. Further, for example, when data is output to output port 62b, by executing a load instruction, the data output to output port 62b is held as it is on CPU core 102 side, and the data is divided into bits in a predetermined order. It is possible to output data of the state after changing the arrangement to the output port 62b.

  However, in the case of the load instruction, as described above, the first address code is set in the first byte and the second address code is set in the second byte, and the CPU core 102 executes the load instruction. Even when it accesses the ROM 63 or the RAM 64 and the input port 62a or the output port 62b, addressing is performed using all 16 address terminals A0 to A15. The memory space 106 is being accessed. When handling of the load instruction in the CPU core 102 is made different depending on whether the ROM 63 or the RAM 64 is accessed or the input port 62 a or the output port 62 b is accessed, data for identifying an access target is an address code. Is required to be set separately, and in this case, the load instruction can not be set as a 3-byte instruction. Also, with the above configuration, when accessing the input port 62a or the output port 62b in the CPU core 102, the load instruction is executed when executing the in instruction or out instruction (that is, when accessing the IO space 105). In the case where the memory space 106 is accessed (ie, the memory space 106 is accessed), different addressing will be performed.

  As described above, when the load instruction is executed in the CPU core 102, different addresses need to be set for accessing the ROM 63 or the RAM 64 and accessing the input port 62a or the output port 62b. Therefore, as shown in the explanatory diagram of the memory space 106 of FIG. 13, the memory space 106 includes not only the ROM space 106a corresponding to the ROM 63 and the RAM space 106b corresponding to the RAM 64 but also inputs corresponding to the input port 62a. An output port space 106 d corresponding to the port space 106 c and the output port 62 b is present. The addresses set in the ROM space 106a, the RAM space 106b, the input port space 106c, and the output port space 106d are different from each other.

  The number of areas requiring addressing is the largest in ROM 63, the next largest in RAM 64, the next largest in output latch circuits 104 corresponding to output port 62b, the smallest in number of input latch circuits 103 corresponding to input port 62a. . Therefore, the number of types of addresses set in the ROM space 106 a is the largest, the number of types of addresses set in the RAM space 106 b is the second largest, and the type of addresses set in the output port space 106 d is the next The number of types of addresses set in the input port space 106c is the smallest.

  Next, whether or not the CPU core 102 executes an in instruction or an out instruction and whether it executes a load instruction, data input from the input port 62a or data output to the output port 62b The configuration for carrying out will be described. FIG. 14 is a block diagram showing an electrical configuration for outputting a chip select signal from the chip select terminal CS0 corresponding to the input latch circuit 103 for inputting data from the input port 62a. An electrical configuration for outputting a chip select signal from another chip select terminal corresponding to input latch circuit 103 for inputting data from input port 62a, and an output for outputting data to output port 62b The electrical configuration for outputting a chip select signal from a chip select terminal corresponding to latch circuit 104 is the same as the electrical configuration shown in FIG.

  The RD terminal and the WR terminal of the CPU core 102 are both electrically connected to the operation selection circuit 111 built in the CPU 101. Specifically, the operation selection circuit 111 is provided with an input terminal corresponding to the RD terminal, and a signal path is formed by electrically connecting the RD terminal and the input terminal. Further, the operation selection circuit 111 is provided with an input terminal corresponding to the WR terminal, and a signal path is formed by electrically connecting the WR terminal and the input terminal.

  The operation selection circuit 111 selects one of the RD signal output from the RD terminal and the WR signal output from the WR terminal as a signal serving as an output trigger of the operation selection signal from the operation selection terminal 111a. Is the circuit of The operation selection circuit 111 is configured such that an initialization signal is input when supply of operation power from the initialization circuit 112 incorporated in the CPU 101 to the CPU 101 is started, and an initialization signal is input. Thus, as a signal serving as an output trigger of the operation selection signal, the signal on the side determined at the design stage of the pachinko machine 10 is selected among the RD signal and the WR signal. Specifically, switch circuit 111b is provided in operation selection circuit 111, and when the initialization signal is input from initialization circuit 112, a state in which the RD terminal and operation selection terminal 111a are electrically connected, and WR Among the states in which the terminal and the operation selection terminal 111a are conducted, the state of the side determined in the design stage of the pachinko machine 10 is set. Since the RD signal is a LOW level signal, when the switch circuit 111b conducts the RD terminal and the operation selection terminal 111a in a conductive state, the RD signal is not output (that is, the HI level signal is output from the RD terminal) If the operation selection terminal 111a of the operation selection circuit 111 outputs the HI level signal as a non-operation selection signal, and if the RD signal is output, the operation selection terminal 111a of the operation selection circuit 111 operates. A LOW level signal is output as a selection signal. Similarly, since the WR signal is a LOW level signal, when the switch circuit 111b is in a state of bringing the WR terminal and the operation selection terminal 111a into conduction, the WR signal is not output (ie, the HI level signal is output from the WR terminal). If it is output, the operation selection terminal 111a of the operation selection circuit 111 outputs the HI level signal as a non-operation selection signal, and if the WR signal is output, the operation selection terminal 111a of the operation selection circuit 111 A low level signal is output as an operation selection signal from.

  FIG. 14 shows a chip select terminal CS0 for outputting a chip select signal to the input latch circuit 103. Therefore, the operation selection circuit 111 brings the RD terminal and the operation selection terminal 111a into conduction. As a result, when the RD signal is output from the RD terminal of the CPU core 102, the operation selection circuit 111 outputs an operation selection signal from the operation selection terminal 111a.

  In the case of the operation selection circuit 111 corresponding to the chip select terminals CS5 to CS12 for outputting a chip select signal to the output latch circuit 104, the initialization signal is input from the initialization circuit 112, whereby the WR terminal is obtained. When the WR signal is output from the WR terminal of the CPU core 102, the operation selection signal is output from the operation selection terminal 111a of the operation selection circuit 111. Although details will be described later, it is a necessary condition for the chip select signal to be output from the chip select terminal CS0 that the operation select signal be output from the operation select circuit 111.

  The IREQ terminal and the MREQ terminal of the CPU core 102 are both electrically connected to the object selection circuit 113 built in the CPU 101. Specifically, the object selection circuit 113 is provided with an input terminal corresponding to the IREQ terminal, and a signal path is formed to electrically connect the IREQ terminal and the input terminal. Further, the object selection circuit 113 is provided with an input terminal corresponding to the MREQ terminal, and a signal path is formed by electrically connecting the MREQ terminal and the input terminal.

  The object selection circuit 113 is provided with an object selection logic circuit 113 a. Each of the signal output from the IREQ terminal and the signal output from the MREQ terminal is input to the NOR circuit in the object selection logic circuit 113a through each NOT circuit in the object selection logic circuit 113a. Since the IREQ signal is the LOW level signal and the MREQ signal is the LOW level signal, the LOW level signal is output from the target selection logic circuit 113a in a situation where either the IREQ signal or the MREQ signal is output. Ru. Then, in a situation where a LOW level signal is output from the object selection logic circuit 113a, a LOW level signal is output from the object selection terminal 113b of the object selection circuit 113 as an object selection signal. That is, the target selection signal is output from the target selection circuit 113 regardless of whether the IREQ signal is output from the IREQ terminal or the MREQ signal is output from the MREQ terminal. As a result, the CPU core 102 accesses the input port 62a or the output port 62b not only when executing the in instruction or the out instruction but also when there is a case where the load instruction is executed. Even in this case, the target selection signal can be output from the target selection circuit 113. Although the details will be described later, it is a necessary condition for the chip select signal to be output from the chip select terminal CS0 that the target selection signal be output from the target selection circuit 113. In the situation where the IREQ signal is not output and the MREQ signal is not output either, the object selection circuit 113 outputs the HI level signal as the non-object selection signal.

  Of the address terminals A0 to A15 of the CPU core 102, eight consecutive address terminals A0 to A7 directed from the 0th address terminal A0 downward are electrically connected to the IO address decoder 114. Specifically, the IO address decoder 114 is provided with eight input terminals in a one-to-one correspondence with eight address terminals A0 to A7, and corresponding address terminals A0 to A7 and input terminals are provided. Are electrically connected to form a signal path. Further, all sixteen address terminals A0 to A15 are electrically connected to the memory address decoder 115. Specifically, the memory address decoder 115 is provided with 16 input terminals in a one-to-one correspondence with the 16 address terminals A0 to A15, and the corresponding address terminals A0 to A15 and the input terminals are provided. Are electrically connected to form a signal path. The signal path from the address terminals A0 to A7 to each input terminal of the IO address decoder 114 is an intermediate position of the signal path electrically connecting the address terminals A0 to A7 and each input terminal of the memory address decoder 115. It is provided branched from.

  The IO address decoder 114 outputs an LOW level signal as an IO address signal from the IO address output terminal 114a when the 1-byte address data corresponding to the chip select terminal CS0 is output from the CPU core 102. It is formed. Even when the CPU core 102 outputs a chip select signal from a chip select terminal CS1 to CS12 different from the chip select terminal CS0, it outputs address data from the address terminals A0 to A7. The IO address decoder 114 provided correspondingly is not to output the IO address signal from the IO address output terminal 114a even if the address data different from the address data corresponding to the circuit provided in itself is input. That is, the HI level signal is output as the non-IO address signal from the IO address output terminal 114a.

  The memory address decoder 115 outputs an LOW level signal as a memory address signal from the memory address output terminal 115a when the 2-byte address data corresponding to the chip select terminal CS0 is output from the CPU core 102. It is formed. Even when the CPU core 102 outputs a chip select signal from chip select terminals CS1 to CS12 different from the chip select terminal CS0, the address data is output from the address terminals A0 to A15. The memory address decoder 115 provided correspondingly is not to output a memory address signal from the memory address output terminal 115a even if address data different from the address data corresponding to the circuit provided in itself is inputted. That is, the HI address signal is output as a non-memory address signal from the memory address output terminal 115a.

  Although the details will be described later, it is a necessary condition for the chip select signal to be output from the chip select terminal CS0 that the corresponding address signal is output from the IO address decoder 114 or the memory address decoder 115.

  Here, the first of the 1-byte address data that is an output trigger of the IO address signal from the IO address decoder 114 and the 2-byte address data that is an output trigger of the memory address signal from the memory address decoder 115 The 1-byte address data set in the bytes is the same data. For example, while the 1-byte address data serving as an output trigger of the IO address signal from the IO address decoder 114 is set to “A5” in hexadecimal, the output of the memory address signal from the memory address decoder 115 The address data of the first byte of the two bytes of address data to be triggered is set to "A5" in hexadecimal and the address data of the second byte is set to "00" in hexadecimal.

  In the electric circuit for outputting the chip select signal to the input latch circuit 103 for inputting data from the input port 62a and the output latch circuit 104 for outputting data to the output port 62b, as described above, IREQ Even when either the signal or the MREQ signal is output, the target selection signal is output from the target selection circuit 113. Then, when the 1-byte address data output from the upper address terminals A0 to A7 corresponds to the output of the address signal from the IO address decoder 114, the lower address terminals A8 to A15. The IO address signal is output from the IO address decoder 114 regardless of which one-byte address data is output. In this case, the 2-byte address data in which the address data of the upper address terminals A0 to A7 corresponds to the IO address decoder 114 is a chip select different from the chip select terminal corresponding to the IO address decoder 114. It can not be used as address data corresponding to the IO address decoder and the memory address decoder in the electric circuit of the terminal. Under such circumstances, one byte of address data set in the first byte of the two bytes of address data for outputting the memory address signal from the memory address decoder 115 is transferred from the IO address decoder 114 to the IO. By matching the address data of 1 byte for outputting the address signal, it is possible to suppress the number of types of address data which can not be used as an electric circuit of another chip select terminal.

  The IO address output terminal 114 a of the IO address decoder 114 and the memory address output terminal 115 a of the memory address decoder 115 are both electrically connected to the address circuit 116 built in the CPU 101. Specifically, the address circuit 116 is provided with an input terminal corresponding to the IO address output terminal 114a, and a signal path is established by electrically connecting the IO address output terminal 114a and the input terminal. It is formed. Further, the address circuit 116 is provided with an input terminal corresponding to the memory address output terminal 115a, and a signal path is formed by electrically connecting the memory address output terminal 115a and the input terminal. There is.

  The address circuit 116 is provided with an address logic circuit 116 a. Each of the signal output from the IO address output terminal 114a and the signal output from the memory address output terminal 115a are input to the NOR circuit in the address logic circuit 116a through each NOT circuit in the address logic circuit 116a. ing. Since the IO address signal is a LOW level signal and the memory address signal is a LOW level signal, the LOW logic level signal is output from the address logic circuit 116a in a situation where at least one of the address signals is output. Then, in the situation where the LOW level signal is output from the address logic circuit 116a, the LOW level signal is output from the address output terminal 116b of the address circuit 116 as a combined address signal. That is, the combined address signal is output from the address circuit 116 regardless of whether the IO address signal is output from the IO address output terminal 114a or the memory address signal is output from the memory address output terminal 115a. . Although the details will be described later, the output of the combined address signal from the address circuit 116 is a necessary condition for the chip select signal to be output from the chip select terminal CS0. The address circuit 116 outputs the HI level signal as a non-combined address signal in a situation where the IO address signal is not output and the memory address signal is not output.

  The address output terminal 116b of the address circuit 116, the operation selection terminal 111a of the operation selection circuit 111, and the object selection terminal 113b of the object selection circuit 113 are all electrically connected to the synthesis circuit 117 built in the CPU 101. . Specifically, the combining circuit 117 is provided with an input terminal corresponding to the address output terminal 116b, and a signal path is formed by electrically connecting the address output terminal 116b and the input terminal. There is. Further, the synthesizing circuit 117 is provided with an input terminal corresponding to the operation selection terminal 111a, and a signal path is formed so as to electrically connect the operation selection terminal 111a and the input terminal. Further, the combining circuit 117 is provided with an input terminal corresponding to the target selection terminal 113b, and a signal path is formed by electrically connecting the target selection terminal 113b and the input terminal.

  The synthesis circuit 117 is provided with a synthesis logic circuit 117 a. The signal output from the address output terminal 116b, the signal output from the operation selection terminal 111a, and the signal output from the target selection terminal 113b are NAND circuits in the synthesis logic circuit 117a through respective NOT circuits in the synthesis logic circuit 117a. It is designed to be input to the circuit. Since all of the combined address signal, the operation selection signal, and the target selection signal are LOW level, the synthesis circuit 117 outputs the LOW level when all of the combined address signal, operation selection signal, and target selection signal are output. A signal is output. Then, in the situation where the LOW level signal is output from the combining logic circuit 117a, the LOW level signal is output as the chip select signal from the chip select terminal CS0. That is, when the combined address signal is output from the address circuit 116, the operation selection signal is output from the operation selection circuit 111, and the target selection signal is output from the target selection circuit 113, the chip select terminal CS0 outputs a chip select signal. A signal is output. By outputting the chip select signal from the chip select terminal CS0, the data latched in the input latch circuit 103 corresponding to the chip select terminal CS0 is supplied to the data bus DB.

  Note that the synthesis circuit 117 outputs an HI level signal as a non-chip select signal in a situation where any one of the synthetic address signal, the operation selection signal, and the target selection signal is not output. In this case, the data latched in the input latch circuit 103 corresponding to the chip select terminal CS0 is not supplied to the data bus DB.

  Next, how the chip select signal is output from the chip select terminal CS0 will be described with reference to the time chart of FIG. FIG. 15 (a) shows a period in which 1 byte of address data is outputted from the CPU core 102, and FIG. 15 (b) shows a period in which 2 bytes of address data are outputted from the CPU core 102. Shows a period during which the combined address signal is output from the address circuit 116, FIG. 15 (d) shows a period during which the operation selection signal is output from the operation selection circuit 111, and FIG. FIG. 15 (f) shows a period in which the MREQ signal is output from the CPU core 102, and FIG. 15 (g) shows a period in which the target selection signal is output from the target selection circuit 113. FIG. 15H shows a period in which a chip select signal is output from the chip select terminal CS0.

  First, the case where the chip select signal is output from the chip select terminal CS0 when the CPU core 102 executes the in command will be described.

  At timing t1, the output of 1-byte address data is started from the CPU core 102 as shown in FIG. 15A, and the output of the IREQ signal is started from the CPU core 102 as shown in FIG. Be done. The output of the RD signal from the CPU core 102 is started at the timing of t1. The address data output at the timing of t1 is the address data corresponding to the IO address decoder 114.

  When the output of 1-byte address data is started at the timing of t1, the output of the IO address signal from the IO address decoder 114 is started. Then, when the output of the IO address signal is started, the output of the combined address signal from the address circuit 116 is started as shown in FIG. 15C at the timing of t2.

  Further, when the output of the RD signal is started at the timing of t1, the output of the operation selection signal from the operation selecting circuit 111 is started at the timing of t2 as shown in FIG. Further, when the output of the IREQ signal is started at the timing of t1, the output of the target selection signal from the target selection circuit 113 is started as shown in FIG. 15 (g) at the timing of t2.

  As all outputs of the combined address signal, the operation selection signal, and the target selection signal are started at the timing of t2, the output of the chip select signal from the chip select terminal CS0 as shown in FIG. 15 (h) at the timing of t3. Is started. As a result, the data latched in the input latch circuit 103 corresponding to the chip select terminal CS0 is supplied to the data bus DB.

  Thereafter, at timing t4, the output of 1-byte address data from the CPU core 102 is stopped as shown in FIG. 15A, and the IREQ signal from the CPU core 102 as shown in FIG. Output is stopped. The output of the RD signal from the CPU core 102 is also stopped at the timing of t4. Thus, at timing t5, the output of the combined address signal is stopped as shown in FIG. 15 (c), and the output of the operation selection signal is stopped as shown in FIG. 15 (d). As shown, the output of the target selection signal is stopped. Then, when the output of these signals is stopped, the output of the chip select signal from the chip select terminal CS0 is stopped at the timing of t6 as shown in FIG. 15 (h). By stopping the output of the chip select signal, the supply of the data latched in the input latch circuit 103 corresponding to the chip select terminal CS0 to the data bus DB is stopped.

  The flow of the above operation is the same as in the case where an out instruction is executed in the CPU core 102 when data is output to the output port 62 b by using the output latch circuit 104.

  Next, the case where the chip select signal is output from the chip select terminal CS0 when the load instruction is executed in the CPU core 102 will be described.

  At time t7, output of 2-byte address data is started from the CPU core 102 as shown in FIG. 15 (b), and output of an MREQ signal is started from the CPU core 102 as shown in FIG. 15 (f). Be done. The output of the RD signal from the CPU core 102 is started at the timing of t7. The address data output at the timing of t7 is the address data corresponding to the memory address decoder 115.

  When the output of the 2-byte address data is started at the timing of t7, the output of the memory address signal from the memory address decoder 115 is started. Then, when the output of the memory address signal is started, the output of the combined address signal from the address circuit 116 is started at the timing of t8 as shown in FIG.

  Further, when the output of the RD signal is started at the timing of t7, the output of the operation selection signal from the operation selection circuit 111 is started at the timing of t8 as shown in FIG. Further, when the output of the MREQ signal is started at the timing of t7, the output of the target selection signal from the target selection circuit 113 is started at the timing of t8 as shown in FIG.

  As all outputs of the combined address signal, the operation selection signal, and the target selection signal are started at the timing of t8, the output of the chip select signal from the chip select terminal CS0 as shown in FIG. 15 (h) at the timing of t9. Is started. As a result, the data latched in the input latch circuit 103 corresponding to the chip select terminal CS0 is supplied to the data bus DB.

  Thereafter, at timing t10, the output of 2-byte address data from the CPU core 102 is stopped as shown in FIG. 15B, and the MREQ signal from the CPU core 102 as shown in FIG. 15F. Output is stopped. The output of the RD signal from the CPU core 102 is also stopped at the timing of t10. Thus, at timing t11, the output of the combined address signal is stopped as shown in FIG. 15 (c), and the output of the operation selection signal is stopped as shown in FIG. 15 (d). As shown, the output of the target selection signal is stopped. Then, when the output of these signals is stopped, the output of the chip select signal from the chip select terminal CS0 is stopped at the timing of t12 as shown in FIG. 15 (h). By stopping the output of the chip select signal, the supply of the data latched in the input latch circuit 103 corresponding to the chip select terminal CS0 to the data bus DB is stopped.

  As described above, the object selection circuit 113 is provided with an OR circuit of negative logic using the signal output from the IREQ terminal of the CPU core 102 and the signal output from the MREQ terminal of the CPU core 102 as input signals. Thus, the target selection signal is output from the target selection circuit 113 regardless of whether the CPU core 102 is outputting either the IREQ signal or the MREQ signal. In this case, when data is input from input port 62a using input latch circuit 103 corresponding to chip select terminal CS0, CPU core 102 executes either an in instruction or a load instruction. Even in the situation where either the IREQ signal or the MREQ signal is output from the CPU core 102, the target selection signal can be output from the target selection circuit 113 without switching the state of the target selection circuit 113. It becomes. This makes it possible to output the chip select signal from the chip select terminal CS0 regardless of whether the in instruction or the load instruction is executed while simplifying the processing configuration.

  In the electric circuit corresponding to the chip select terminal CS0, an IO address decoder 114 corresponding to 1-byte address data and a memory address decoder 115 corresponding to 2-byte address data are provided. When 1-byte address data is output from 102, an IO address signal is output from IO address decoder 114, and when 2-byte address data is output from CPU core 102, memory is output from memory address decoder 115. An address signal is output. When at least one of the IO address signal and the memory address signal is output, a combined address signal is output from the address circuit 116. In this case, when data is input from input port 62a using input latch circuit 103 corresponding to chip select terminal CS0, CPU core 102 executes either an in instruction or a load instruction. Even if the CPU core 102 outputs either 1-byte address data or 2-byte address data, the address circuit 116 does not switch the state of the circuit for outputting the address signal. Can output the combined address signal. This makes it possible to output the chip select signal from the chip select terminal CS0 regardless of whether the in instruction or the load instruction is executed while simplifying the processing configuration.

  Next, the contents of the instruction execution process repeatedly executed in a short cycle by the CPU core 102 will be described with reference to the flowchart of FIG. By the processing of FIG. 16 being executed by CPU core 102, as a result, the main processing (FIG. 6) and timer interrupt processing (FIG. 7) already described are executed by MPU 62 of main control device 60. .

  First, an instruction is read out from the area of the ROM 63 corresponding to the address designated by the current value of the program counter (step S301). If the read instruction is a 2-byte instruction (step S302: YES), it is determined whether the IO identification code is set in the instruction (step S303). If the IO identification code is not set (step S303: NO), this means that the current instruction is neither an in instruction nor an out instruction, so processing corresponding to the current instruction in the other processing of step S304 Run.

  If the IO identification code is set to the current instruction (step S303: YES), it means that the current instruction is an in instruction or an out instruction, so the process proceeds to step S305. In step S305, the address code set in the first byte of the instruction read this time is set for the upper eight address terminals A0 to A7 to perform output setting of 1-byte address data. . Thus, 1-byte address data is output from the address terminals A0 to A7. In this case, the output states of the remaining eight address terminals A8 to A15 are maintained at the previous output states. In step S306, output of the IREQ signal is started from the IREQ terminal of the CPU core 102.

  Thereafter, when the IO identification code in the current instruction corresponds to the input of data from the input port 62a (step S307: YES), the output of the RD signal is started from the RD terminal of the CPU core 102 (step S308). On the other hand, when the IO identification code in the current instruction corresponds to the output of data from the output port 62b (step S307: NO), the output of the WR signal is started from the WR terminal of the CPU core 102 (step S309). Thereafter, 1 byte of output data is read out from the area of ROM 63 corresponding to the address designated by the next value of the program counter referred to in step S301, and the output data is set to data bus DB (step S310). ).

  If the current instruction is not a 2-byte instruction (step S302: NO), it is determined whether the current instruction is a 3-byte instruction (step S311). If it is not a 3-byte instruction, it means that the current instruction is a 1-byte instruction or an instruction of 4 bytes or more, so the processing corresponding to the current instruction is executed in the other processing of step S304. If it is a 3-byte instruction (step S311: YES), 3-byte instruction processing is executed (step S312).

  FIG. 17 is a flowchart showing 3-byte instruction processing.

  If the current 3-byte instruction is an input instruction to the input port 62a (step S401: YES), the first address code set in the first byte of the instruction read this time is set to the upper eight address terminals A0. By setting the second address code set to the second byte of the instruction read this time to the lower eight address terminals A8 to A15 while setting up to A7, the 2-byte Make address data output settings. Thus, 2-byte address data is output from the address terminals A0 to A15.

  Thereafter, the output of the MREQ signal is started from the MREQ terminal of the CPU core 102 (step S403), and the output of the RD signal from the RD terminal of the CPU core 102 is started (step S404). Thereafter, if the current input instruction includes a logical operation instruction (step S405: YES), the logical operation processing specified in the current instruction is executed on the data input this time from the input port 62a. (Step S406). For example, when it is designated as an instruction to execute AND processing of the data stored and held in the register of the MPU 62 and the data inputted this time from the input port 62a, the AND processing is executed.

  If the current 3-byte instruction is an output instruction to the output port 62b (step S407: YES), output setting of 2-byte address data is performed (step S408) as in step S402. Thus, 2-byte address data is output from the address terminals A0 to A15.

  Thereafter, the output of the MREQ signal is started from the MREQ terminal of the CPU core 102 (step S409), and the output of the WR signal from the WR terminal of the CPU core 102 is started (step S410). After that, if the current output instruction includes a shift instruction (step S411: YES), processing is performed to shift the bit of the data to be output to the output port 62b this time in a predetermined direction (step S412). ). Thereafter, data to be output this time is set in the data bus DB (step S413).

  If the current 3-byte instruction is a read instruction (step S414: YES), output setting of 2-byte address data is performed as in step S402 (step S415). Thus, 2-byte address data is output from the address terminals A0 to A15. Thereafter, the output of the MREQ signal is started from the MREQ terminal of the CPU core 102 (step S416), and the output of the RD signal from the RD terminal of the CPU core 102 is started (step S417). Thereby, data is read from the area corresponding to the present address data in the ROM 63 or the RAM 64.

  If the current 3-byte instruction is a write instruction (step S418: YES), output setting of 2-byte address data is performed as in step S402 (step S419). Thus, 2-byte address data is output from the address terminals A0 to A15. Thereafter, the output of the MREQ signal is started from the MREQ terminal of the CPU core 102 (step S420), and the output of the WR signal from the WR terminal of the CPU core 102 is started (step S421). Thereafter, data to be output this time is set in the data bus DB (step S422).

  If the current 3-byte instruction is not a write instruction (step S418: NO), the other processing is executed (step S423). In the other processing, for example, a calculation operation instruction or a bit manipulation instruction is executed.

  According to the embodiment described above, the following excellent effects can be obtained.

  The CPU core 102 outputs an MREQ signal from the MREQ terminal when executing a load instruction, and outputs an IREQ signal from the IREQ terminal when executing an in instruction or an out instruction. This makes it possible to prevent data reading, data writing and data input / output from being performed when none of the load instruction, in instruction and out instruction is executed, and the load instruction It is possible to distinguish the operation target between the case where the command is being executed and the case where the in command or the out command is being executed. In this case, the combining circuit 117 for outputting the chip select signal to the input latch circuit 103 corresponding to the input port 62a can output either the MREQ signal or the IREQ signal from the CPU core 102. A chip select signal is output. The same applies to a configuration for outputting a chip select signal to the output latch circuit 104 corresponding to the output port 62b. Thereby, not only when an in instruction or an out instruction is executed but also when data is executed under a load instruction, data is received from input port 62a or data is set to output port 62b. It becomes possible. Therefore, it is possible to widen the range of types of instructions to be executed when receiving data from the input port 62a or setting data to the output port 62b.

  In a configuration in which the chip select signal is output from the synthesis circuit 117 under the condition that the target selection signal is output from the target selection circuit 113, the target selection circuit 113 outputs the IREQ signal or the MREQ signal. Since the configuration is such that the target selection signal is output, it is possible to achieve the above-described excellent effects while using the configuration other than the target selection circuit 113 as it is.

  The object selection circuit 113 is provided with a negative logic OR circuit in which the signal output from the IREQ terminal of the CPU core 102 and the signal output from the MREQ terminal of the CPU core 102 are input signals, respectively. The target selection signal is output from the target selection circuit 113 regardless of whether the core 102 is outputting either the IREQ signal or the MREQ signal. In this case, when data is input from input port 62a using input latch circuit 103 corresponding to chip select terminal CS0, CPU core 102 executes either an in instruction or a load instruction. Even in the situation where either the IREQ signal or the MREQ signal is output from the CPU core 102, the target selection signal can be output from the target selection circuit 113 without switching the state of the target selection circuit 113. It becomes. This makes it possible to output the chip select signal from the chip select terminal CS0 regardless of whether the in instruction or the load instruction is executed while simplifying the processing configuration.

  When an in instruction or an out instruction is executed, 1 byte of address data is output from the CPU core 102, and when a load instruction is executed, 2 bytes of address data are output from the CPU core 102. This makes it possible to output the address data in a manner corresponding to the case of executing the in-instruction or the out-instruction and the case of executing the load instruction. In addition, 1 byte of address data is output when executing an in instruction or an out instruction as described above, and 1 byte of address data is output when executing a load instruction. The chip select signal is output from the combining circuit 117 regardless of whether the address data of the address data is output or the address data of 2 bytes is output. Thereby, not only when an in instruction or an out instruction is executed but also when data is executed under a load instruction, data is received from input port 62a or data is set to output port 62b. It becomes possible.

  In the electric circuit corresponding to the chip select terminal CS0, an IO address decoder 114 corresponding to 1-byte address data and a memory address decoder 115 corresponding to 2-byte address data are provided. When 1-byte address data is output, the IO address signal is output from the IO address decoder 114. When 2-byte address data is output from the CPU core 102, the memory address signal is output from the memory address decoder 115. Is output. When at least one of the IO address signal and the memory address signal is output, a combined address signal is output from the address circuit 116. In this case, when data is input from input port 62a using input latch circuit 103 corresponding to chip select terminal CS0, CPU core 102 executes either an in instruction or a load instruction. Even if the CPU core 102 outputs either 1-byte address data or 2-byte address data, the address circuit 116 does not switch the state of the circuit for outputting the address signal. Can output the combined address signal. This makes it possible to output the chip select signal from the chip select terminal CS0 regardless of whether the in instruction or the load instruction is executed while simplifying the processing configuration.

Second Embodiment
The present embodiment is an electrical method that enables processing of data that has already been output and output of the data after processing without executing processing for separately storing output data in the CPU core 102. It differs from the first embodiment in that it is configured. The different configurations will be described below. The description of the same configuration as that of the first embodiment is basically omitted.

  FIG. 18 is an explanatory diagram for explaining an electrical configuration of the CPU 101 in the present embodiment.

  The CPU 101 is provided with chip select terminals CS0 to CS12 as in the first embodiment. However, in this embodiment, the chip select terminal CS0, the chip select terminal CS2, the chip select terminal CS4, and the chip select terminal CS6 are for outputting chip select signals to the output latch circuits 121a to 121d. The other chip select terminals CS1, CS3, CS5, CS7 to CS12 are for outputting chip select signals to the input latch circuits 122a to 122i.

  Chip select terminals CS0, CS2, CS4, CS6 corresponding to output latch circuits 121a-121d form signal paths with corresponding output latch circuits 121a-121d, and input latch circuits 122a-122i. The corresponding chip select terminals CS1, CS3, CS5, CS7 to CS12 form a signal path with the corresponding input latch circuits 122a to 122i. Each of output latch circuits 121a to 121d has a signal path formed between data terminals D10 to D17 of CPU 101 and data bus DB electrically connected, and data buses D10 to D17 are connected to data bus. It is possible to latch the data supplied to DB in output latch circuits 121a to 121d. Each input latch circuit 122a to 122i has a signal path formed with the data bus DB, and temporarily stores and holds data supplied from the output source of the corresponding data. Data can be supplied to the data bus DB as needed.

  A plurality (specifically, three) of chip select terminals CS0, CS2, CS4 which are a part of chip select terminals CS0, CS2, CS4, CS6 corresponding to output latch circuits 121a-121d are connected to output port 62b. The other chip select terminal CS6 outputs a chip select signal to the output latch circuit 121d for outputting data to the RAM 64. It is for outputting a select signal. In this case, input latch circuits 122a-122c are provided in a one-to-one correspondence with output latch circuits 121a-121c for outputting data to output port 62b, and output latch circuits 121a-121c are provided. The data output from 121c to the output port 62b is configured to be latched in the input latch circuits 122a to 122c corresponding to the output latch circuits 121a to 121c. More specifically, data paths L1 to L3 electrically connecting output latch circuits 121a to 121c and output port 62b are branched in the middle, and an input latch circuit corresponding to branch paths L4 to L6. It is electrically connected with 122a-122c. The data latched in the input latch circuits 122a to 122c is output as chip select signals from chip select terminals CS1, CS3, and CS5 provided in one-to-one correspondence with the input latch circuits 122a to 122c. As a result, the data is supplied to the data bus DB and is input to the data terminals D10 to D17 of the CPU 101. Thus, when data is output to the output port 62b, the CPU core 102 reads and processes the data to be output without executing processing for separately storing the data in the register or the RAM 64 of the CPU core 102. It becomes possible to output the processed data to the output port 62b.

  Next, a configuration for processing data that has already been output to the output port 62b in the CPU core 102 and outputting the processed data to the output port 62b will be described in detail. FIG. 19 is a block diagram showing an output circuit 131 for outputting a chip select signal to the output latch circuit 121 a in the CPU 101, and an input circuit 141 for outputting a chip select signal to the input latch circuit 122 a in the CPU 101. It is. An electrical configuration for outputting a chip select signal to a combination of the other output latch circuits 121b and 121c for circulating output data to the output port 62b and the input latch circuits 122b and 122c is shown in FIG. It is identical to the electrical configuration shown.

  Similarly to the electrical configuration shown in FIG. 14 in the first embodiment, the output circuit 131 is electrically connected to the operation selection circuit 132 electrically connected to the RD terminal and the WR terminal, the IREQ terminal and the MREQ terminal. When the CPU core 102 executes a load instruction, the object selection circuit 133 connected to the I / O address decoder 134 to which 1 byte address data is input when the CPU core 102 executes an out instruction, and when the CPU core 102 executes a load instruction A memory address decoder 135 to which 2-byte address data is input, an address circuit 136 electrically connected to the IO address decoder 134 and the memory address decoder 135, an address circuit 136, an operation selection circuit 132, and And a synthesis circuit 137 electrically connected to the object selection circuit 133. That. The specific configurations of the operation selection circuit 132, the object selection circuit 133, the IO address decoder 134, the memory address decoder 135, the address circuit 136, and the combining circuit 137 are the same as those in the first embodiment.

  The switch circuit 132a provided in the operation selection circuit 132 receives the initialization signal when the supply of the operation power to the CPU 101 is started, whereby the signal serving as the output selection of the operation selection signal is from the RD terminal. Among the WR signal from the RD signal and the WR terminal, the WR signal is set. Therefore, when the WR signal is output from the CPU core 102, the operation selection signal is output from the operation selection circuit 132.

  The target selection circuit 133 outputs a target selection signal regardless of whether the CPU core 102 is outputting either the IREQ signal or the MREQ signal. The IO address decoder 134 outputs an IO address signal when the 1-byte address data corresponding to the IO address decoder 134 is output from the CPU core 102. The memory address decoder 135 outputs a memory address signal when 2-byte address data corresponding to the memory address decoder 135 is output from the CPU core 102. The address circuit 136 outputs a combined address signal when either the IO address signal or the memory address signal is output. The synthesis circuit 137 outputs a chip select signal to the output latch circuit 121a from the chip select terminal CS0 when all of the synthesized address signal, the operation selection signal, and the target selection signal are output. As a result, the data set in the data terminals D0 to D7 of the CPU core 102 is latched by the output latch circuit 121a, and is latched for each area of the output port 62b corresponding to the output latch circuit 121a. Data is output. The output data is latched by the input latch circuit 122a through the data path L1 and the branch path L4.

  Similar to the electrical configuration shown in FIG. 14 in the first embodiment, the input circuit 141 is electrically connected to the operation selection circuit 142 electrically connected to the RD terminal and the WR terminal, the IREQ terminal and the MREQ terminal. When the CPU core 102 executes a load instruction, the object selection circuit 143 connected to the I / O address decoder 144 to which 1 byte of address data is input when the CPU core 102 executes an out instruction, and when the CPU core 102 executes a load instruction. A memory address decoder 145 to which 2-byte address data is input, an address circuit 146 electrically connected to the IO address decoder 144 and the memory address decoder 145, an address circuit 146, an operation selection circuit 142, and And a synthesis circuit 147 electrically connected to the object selection circuit 143. That. The specific configurations of the operation selection circuit 142, the object selection circuit 143, the IO address decoder 144, the memory address decoder 145, the address circuit 146, and the combining circuit 147 are the same as those in the first embodiment.

  Although FIG. 19 shows that each of the address terminals A0 to A15, the RD terminal, the WR terminal, the IREQ terminal, and the MREQ terminal is provided in the CPU core 102, in actuality, Only one each of these terminals is provided, and by branching the signal path extending from each terminal, the signal from each terminal is supplied to each of the output circuit 131 and the input circuit 141. There is.

  The switch circuit 142a provided in the operation selection circuit 142 receives the initialization signal when the supply of the operation power to the CPU 101 is started, whereby the signal serving as the output selection of the operation selection signal is from the RD terminal. The RD signal and the WR signal from the WR terminal are set to be the RD signal. Therefore, when the RD signal is output from the CPU core 102, the operation selection signal is output from the operation selection circuit 142.

  The object selection circuit 143 outputs an object selection signal regardless of whether the CPU core 102 is outputting either the IREQ signal or the MREQ signal. The IO address decoder 144 outputs an IO address signal when the 1-byte address data corresponding to the IO address decoder 144 is output from the CPU core 102. The memory address decoder 145 outputs a memory address signal when 2-byte address data corresponding to the memory address decoder 145 is output from the CPU core 102. The address circuit 146 outputs a combined address signal when either the IO address signal or the memory address signal is output. The synthesis circuit 147 outputs a chip select signal from the chip select terminal CS1 to the input latch circuit 122a when all of the synthesized address signal, the operation selection signal, and the target selection signal are output. Thereby, the data latched in the input latch circuit 122 a is supplied to the data bus DB, and the supplied data is acquired by the CPU core 102. The acquired data is data previously output to the area corresponding to the output port 62b using the output latch circuit 121a.

  Here, the 1-byte address data that triggers the output of the IO address signal from the IO address decoder 144 of the input circuit 141 triggers the output of the IO address signal from the IO address decoder 134 of the output circuit 131. It is the same as 1-byte address data. The 2-byte address data that triggers the output of the memory address signal from the memory address decoder 145 of the input circuit 141 becomes the trigger that the memory address signal of the output circuit 131 is output. It is identical to the byte address data. Thus, the address data for outputting the chip select signal from the output circuit 131 to the output latch circuit 121a and the address data for outputting the chip select signal from the input circuit 141 to the input latch circuit 122a are the same. It is possible to use Therefore, it becomes possible to process data that has been output to the output port 62b in the CPU core 102 and output the processed data to the output port 62b by specifying one address data.

  Further, even if the chip select signal is output to the output latch circuit 121a and the chip select signal is output to the input latch circuit 122a by designation of one address data, the chip to the output latch circuit 121a is The output of the select signal is performed when the WR signal is output from the CPU core 102, and the output of the chip select signal to the input latch circuit 122a is performed when the RD signal is output from the CPU core 102. Therefore, it is possible to make the output timing of data using the output latch circuit 121a different from the input timing of data using the input latch circuit 122a.

  Next, processing is performed by processing data already output to the output port 62 b in the CPU core 102 and outputting the processed data to the output port 62 b for display control in the special view display unit 37 a Will be explained.

  FIG. 20 (a) is a front view of the special view display unit 37a. In the special view display unit 37a, eight light emitting units 151 to 158 are provided. Each of the light emitting units 151 to 158 has an individual light source formed of an LED, and it is possible to turn on only one arbitrary light emitting unit 151 to 158 by performing on / off control of the individual light sources. The light emitting units 151 to 158 in any combination can be lighted. The individual light sources all emit light of the same color, so the same color is displayed in each of the light emitting parts 151 to 158, but the invention is not limited thereto. Different colors may be displayed in each of the light emitting units 151 to 158. Of the light emitting units 151 to 158, the seven first to seventh light emitting units 151 to 158 are all linear display segments, and the first to seventh light emitting units 151 to 151 are so-called seven-segment displays. 158 is arranged. The remaining one eighth light emitting unit 158 is a circular light emitting unit, and is provided at a position adjacent to the first to seventh light emitting units 151 to 158.

  FIG. 20B is an explanatory diagram for describing an output area 159 in which data for setting contents of data output to the first to eighth light emitting units 151 to 158 is set in the output port 62b.

  The output area 159 has a 1-byte data configuration, and each bit corresponds to the first to eighth light emitting units 151 to 158 on a one-to-one basis. Specifically, in the output area 159, a first bit 159a corresponding to the first light emitting unit 151, a second bit 159b corresponding to the second light emitting unit 152, and a third bit 159c corresponding to the third light emitting unit 153. , The fourth bit 159 d corresponding to the fourth light emitting unit 154, the fifth bit 159 e corresponding to the fifth light emitting unit 155, the sixth bit 159 f corresponding to the sixth light emitting unit 156, and the seventh light emitting unit 157. A corresponding seventh bit 159g and an eighth bit 159h corresponding to the eighth light emitting portion 158 are provided. The main control board 61 is provided with a drive circuit for outputting a drive signal to the first to eighth light emitting units 151 to 158 based on the data set in the output area 159. In the drive circuit, of the first to eighth bits 159a to 159h, the light emitting portions 151 to 158 corresponding to the bits 159a to 159h to which the data “1” corresponding to the light emission correspondence data is set are turned on. The light emission control for the first to eighth light emitting units 151 to 158 is performed so that the light emitting units 151 to 158 corresponding to the bits 159a to 159h in which data "0" corresponding to the corresponding data is set are turned off. .

  FIG. 21 is an explanatory diagram for explaining the relationship between the contents set in the output area 159 and the light emission modes of the first to eighth light emitting units 151 to 158. In FIG. 21 (a1) to 21 (a8) are explanatory diagrams for explaining the contents of data set in the output area 159, and FIGS. 21 (b1) to 21 (b8) are the first to eighth It is explanatory drawing for demonstrating the light emission aspect of the light emission parts 151-158.

  When "1" is set only in the first bit 159a of the output area 159 as shown in FIG. 21 (a1), the first to eighth light emitting portions 151 to 158 as shown in FIG. 21 (b1). Among them, only the first light emitting unit 151 is turned on and the rest is turned off. From this state, as shown in FIGS. 21 (a2) to 21 (a8), the bits 159a to 159h in which "1" is set are the first bit 159a → the second bit 159b → the third bit 159c → the fourth By shifting in the order of bit 159 d → fifth bit 159 e → sixth bit 159 f → seventh bit 159 g → eighth bit 159 h, as shown in FIG. 21 (b 2) to FIG. 21 (b 8), light emission occurs. The light emitting units 151 to 158 are first light emitting unit 151 → second light emitting unit 152 → third light emitting unit 153 → fourth light emitting unit 154 → fifth light emitting unit 155 → sixth light emitting unit 156 → seventh light emitting unit 157 → eighth It changes in order of the light emission part 158. FIG. As a result, it is possible to change the display content of the special view display unit 37a only by changing the bit that sets “1” in the output area 159.

  Next, the control processing of the special view display unit executed by the MPU 62 of the main control device 60 will be described with reference to the flowchart of FIG. The control process of the special view display unit is executed in the display control process (step S215) in the timer interrupt process (FIG. 7).

  If the variable display of the special view display unit 37a is not being performed, and the change start condition of the special view display unit 37a is satisfied (step S501: NO, step S502: YES), the drive for changing start which is a 3-byte instruction An instruction is read from the ROM 63 (step S503). Then, the first address code set in the first byte of the read instruction is set to the upper eight address terminals A0 to A7 in the CPU core 102, and the second read instruction is set. By setting the second address code set in the lower byte in the lower eight address terminals A8 to A15 in the CPU core 102, the output setting of the 2-byte address data is performed (step S504). Thereby, 2-byte common address data is output from the address terminals A0 to A15.

  Thereafter, the output of the MREQ signal is started from the MREQ terminal of the CPU core 102 (step S505), and the output of the WR signal from the WR terminal of the CPU core 102 is started (step S506). Thereafter, with respect to the value of the program counter corresponding to the instruction read in step S503, the drive data at the start of fluctuation is read out from the area of the ROM 63 corresponding to the next value, and this data is output to the data bus DB. Setting (step S507). In the drive data at the start of fluctuation, "1" is set to only the first bit 159a among the first to eighth bits 159a to 159h of the output area 159, and "0" is set to the remaining bits 159a to 159h. It is drive data for making it. By execution of the process of step S507, the drive data at the start of the change is latched in the output latch circuit 121a, and the data corresponding to the drive data at the start of the change is the first to eighth bits 159a of the output area 159. It is set to -159 h. Thereby, the variable display of the pattern is started in the special view display unit 37a. The data output from output latch circuit 121a to output area 159 is latched in input latch circuit 122a.

  If the variable display of the special view display unit 37a is being performed (step S501: YES), it is not the end timing of the current variable display (step S508: NO), and the display timing is updated (step S509). (YES), a drive instruction for updating, which is a 3-byte instruction, is read from the ROM 63 (step S510). Then, the first address code set in the first byte of the read instruction is set to the upper eight address terminals A0 to A7 in the CPU core 102, and the second read instruction is set. By setting the second address code set in the lower byte in the lower eight address terminals A8 to A15 in the CPU core 102, the output setting of the 2-byte address data is performed (step S511). Thereby, 2-byte common address data is output from the address terminals A0 to A15.

  Thereafter, the output of the MREQ signal is started from the MREQ terminal of the CPU core 102 (step S512), and the output of the RD signal from the RD terminal of the CPU core 102 is started (step S513). Thereby, the drive data latched in the input latch circuit 122 a is provided to the data bus DB, and the drive data is read out to the CPU core 102. The drive data is drive data currently set in the output area 159.

  Thereafter, rotation processing of drive data is executed in accordance with the instruction read out in step S510 (step S514). Specifically, rotation processing is performed such that each bit of the drive data acquired from the input latch circuit 122 a circulates in a predetermined direction. As a result, as shown in FIGS. 21 (a1) to 21 (a8), the bits for which “1” is set in the drive data are shifted so as to circulate in a predetermined direction.

  Thereafter, in accordance with the instruction read out in step S510, output setting of common address data is performed as in step S511 (step S515). Then, the output of the MREQ signal is started from the MREQ terminal of the CPU core 102 (step S516), and the output of the WR signal is started from the WR terminal of the CPU core 102 (step S517), and the rotation processing is executed in step S514. The drive data after this is set in the data bus DB as data to be output this time (step S518). As a result, the current drive data is latched in the output latch circuit 121a, and data corresponding to the drive data is set in the first to eighth bits 159a to 159h of the output area 159. Thereby, the display content in the special view display unit 37a is changed. The data output from the output latch circuit 121a to the output port 62b is latched by the input latch circuit 122a.

  The processing contents of step S510 to step S518 are executed each time the display content update timing is reached before the end timing of the variable display. The update drive instruction data read out in this case is always the same instruction. This makes it possible to execute display control of the special view display unit 37a while suppressing the number of types of instructions stored in advance in the ROM 63.

  If it is the end timing of the variable display (step S508: YES), the variable display end process is executed (step S519). As a result, the drive data corresponding to the success / failure determination result and the distribution determination result of the current game round is set in the output area 159, and the special map display is made to be the display content corresponding to the success / failure determination result and the distribution determination result. The display control of the unit 37a is performed.

  According to the present embodiment described above, in addition to the effects of the first embodiment, the following excellent effects can be obtained.

  Input latch circuits 122a-122c are provided in a one-to-one correspondence with output latch circuits 121a-121c for outputting data to output port 62b, and output latch circuits 121a-121c are connected to output ports. The data output to 62b is configured to be latched in input latch circuits 122a to 122c corresponding to output output latch circuits 121a to 121c. The data latched in the input latch circuits 122a to 122c is output as chip select signals from chip select terminals CS1, CS3, and CS5 provided in one-to-one correspondence with the input latch circuits 122a to 122c. As a result, the data is supplied to the data bus DB and is input to the data terminals D10 to D17 of the CPU 101. Thus, when data is output to the output port 62b, the CPU core 102 reads and processes the data to be output without executing processing for separately storing the data in the register or the RAM 64 of the CPU core 102. It becomes possible to output the processed data to the output port 62b.

  The input latch circuits 122a to 122c supply the acquired output data to the data bus DB. This makes it possible to supply output data to the CPU core 102 using the configuration of the existing transmission path.

  As chip select signals are output from chip select terminals CS1, CS3 and CS5, data latched in input latch circuits 122a to 122c is supplied to data bus DB and input to data terminals D10 to D17 of CPU 101. With this configuration, it is possible to acquire data from the input latch circuits 122a to 122c at a preferable timing in control by the CPU 101.

  The data paths L1 to L3 electrically connecting the output latch circuits 121a to 121c and the output port 62b are branched on the way, and the input latch circuits 122a to 122c corresponding to the branch paths L4 to L6, respectively. It is electrically connected. This makes it possible to reacquire output data in the CPU core 102 without incorporating the input latch circuits 122 a to 122 c in the CPU 101.

  One byte of address data that triggers an IO address signal to be output from the IO address decoder 144 of the input circuit 141 is one byte of an address data that triggers an IO address signal to be output from the IO address decoder 134 of the output circuit 131. It is the same as the address data. The 2-byte address data that triggers the output of the memory address signal from the memory address decoder 145 of the input circuit 141 becomes the trigger that the memory address signal of the output circuit 131 is output. It is identical to the byte address data. Thus, the address data for outputting the chip select signal from the output circuit 131 to the output latch circuit 121a and the address data for outputting the chip select signal from the input circuit 141 to the input latch circuit 122a are the same. It is possible to use Therefore, it becomes possible to process data that has been output to the output port 62b in the CPU core 102 and output the processed data to the output port 62b by specifying one address data.

  Even when the chip select signal is output to the output latch circuit 121a and the chip select signal is output to the input latch circuit 122a by designation of one address data, the chip select signal to the output latch circuit 121a Is outputted when the WR signal is outputted from the CPU core 102, and the chip select signal is outputted to the input latch circuit 122a when the RD signal is outputted from the CPU core 102. Therefore, it is possible to make the output timing of data using the output latch circuit 121a different from the input timing of data using the input latch circuit 122a.

Third Embodiment
In this embodiment, the output latch circuit 162 and the input latch circuit 163 used when processing data already output to the output port 62 b in the CPU core 102 and outputting the processed data to the output port 62 b The second embodiment differs from the second embodiment in that it is not provided outside the CPU 101 but is built in the CPU 101. The different configurations will be described below. The description of the same configuration as that of the second embodiment is basically omitted.

  FIG. 23 is a block diagram showing an electrical configuration of the CPU 101. As shown in FIG.

  The CPU 101 includes an external output latch circuit 161 provided outside the CPU 101 and an output circuit 171 for simultaneously outputting a chip select signal to each of the internal output latch circuits 162 provided inside the CPU 101, An input circuit 181 for outputting a chip select signal is provided only to the internal input latch circuit 163 provided inside the CPU 101.

  Similarly to the electrical configuration shown in FIG. 14 in the first embodiment, the output circuit 171 is electrically connected to the operation selection circuit 172 electrically connected to the RD terminal and the WR terminal, the IREQ terminal and the MREQ terminal. When the CPU core 102 executes a load instruction, the object selection circuit 173 connected to the I / O address decoder 174 to which 1-byte address data is input when the CPU core 102 executes an out instruction, and when the CPU core 102 executes a load instruction. A memory address decoder 175 to which 2-byte address data is input, an address circuit 176 electrically connected to the IO address decoder 174 and the memory address decoder 175, an address circuit 176, an operation selection circuit 172, and And a synthesis circuit 177 electrically connected to the object selection circuit 173. That. The specific configurations of the operation selection circuit 172, the object selection circuit 173, the IO address decoder 174, the memory address decoder 175, the address circuit 176 and the synthesis circuit 177 are the same as those in the first embodiment.

  The switch circuit 172a provided in the operation selection circuit 172 receives the initialization signal when the supply of the operation power to the CPU 101 is started, whereby the signal serving as the output selection of the operation selection signal is from the RD terminal. Among the WR signal from the RD signal and the WR terminal, the WR signal is set. Therefore, when the WR signal is output from the CPU core 102, the operation selection signal is output from the operation selection circuit 172.

  The target selection circuit 173 outputs a target selection signal regardless of whether the CPU core 102 is outputting either the IREQ signal or the MREQ signal. The IO address decoder 174 outputs an IO address signal when the 1-byte address data corresponding to the IO address decoder 174 is output from the CPU core 102. The memory address decoder 175 outputs a memory address signal when 2-byte address data corresponding to the memory address decoder 175 is output from the CPU core 102. The address circuit 176 outputs a combined address signal when either the IO address signal or the memory address signal is output. The synthesis circuit 177 outputs a chip select signal to the external output latch circuit 161 from the chip select terminal CS0 when all of the synthesized address signal, the operation selection signal, and the target selection signal are output. As a result, the data set in the data terminals D0 to D7 of the CPU core 102 is latched by the external output latch circuit 161, and the latch is performed for each area of the output port 62b corresponding to the external output latch circuit 161. The output data is output.

  The signal path L7 electrically connecting the output terminal of the synthesis logic circuit 177a provided in the synthesis circuit 177 and the chip select terminal CS0 branches at an intermediate position, and the branch path L8 is an internal output. It is electrically connected to the latch circuit 162. Thus, when the chip select signal is output from the chip select terminal CS0 to the external output latch circuit 161, the chip select signal is also output to the internal output latch circuit 162. The internal output latch circuit 162 receives the chip select signal, whereby the same data as the data set in the data terminals D0 to D7 of the CPU core 102, that is, the data latched in the external output latch circuit 161 is obtained. Latch the data.

  The internal output latch circuit 162 is electrically connected to the internal input latch circuit 163 through the data path L9. Therefore, the data latched in the internal output latch circuit 162 is supplied to the internal input latch circuit 163 through the data path L9.

  Similar to the electrical configuration shown in FIG. 14 in the first embodiment, the input circuit 181 is electrically connected to the operation selection circuit 182 electrically connected to the RD terminal and the WR terminal, the IREQ terminal and the MREQ terminal. When the CPU core 102 executes a load instruction, the object selection circuit 183 connected to the I / O address decoder 184 to which 1 byte of address data is input when the CPU core 102 executes an out instruction, and when the CPU core 102 executes a load instruction. A memory address decoder 185 to which 2-byte address data is input, an address circuit 186 electrically connected to the IO address decoder 184 and the memory address decoder 185, an address circuit 186, an operation selection circuit 182, and And a synthesis circuit 187 electrically connected to the object selection circuit 183. That. The specific configurations of the operation selection circuit 182, the object selection circuit 183, the IO address decoder 184, the memory address decoder 185, the address circuit 186, and the combining circuit 187 are the same as those in the first embodiment.

  In FIG. 23, the CPU core 102 is illustrated as having two address terminals A0 to A15, two RD terminals, two RD terminals, two IREQ terminals, and two MREQ terminals. Only one each of these terminals is provided, and by branching the signal path extending from each terminal, the signal from each terminal is supplied to each of the output circuit 171 and the input circuit 181. There is.

  The switch circuit 182a provided in the operation selection circuit 182 receives the initialization signal when the supply of the operation power to the CPU 101 is started, whereby the signal serving as the output selection of the operation selection signal is from the RD terminal. The RD signal and the WR signal from the WR terminal are set to be the RD signal. Therefore, when the RD signal is output from the CPU core 102, the operation selection signal is output from the operation selection circuit 182.

  The object selection circuit 183 outputs an object selection signal regardless of whether the CPU core 102 is outputting either the IREQ signal or the MREQ signal. The IO address decoder 184 outputs an IO address signal when 1-byte address data corresponding to the IO address decoder 184 is output from the CPU core 102. The memory address decoder 185 outputs a memory address signal when 2-byte address data corresponding to the memory address decoder 185 is output from the CPU core 102. The address circuit 186 outputs a combined address signal when either the IO address signal or the memory address signal is output. The synthesis circuit 187 electrically connects the output terminal 187a of the synthesis circuit 187 with the internal input latch circuit 163 when all of the synthesis address signal, the operation selection signal, and the target selection signal are output. The chip select signal is output to the internal input latch circuit 163 through the signal path L10 provided therein. Thereby, the data latched in the internal input latch circuit 163 is supplied to the data bus DB, and the supplied data is acquired in the CPU core 102. The acquired data is data previously output to the area corresponding to the output port 62b using the external output latch circuit 161.

  Here, the 1-byte address data that triggers the output of the IO address signal from the IO address decoder 184 of the input circuit 181 triggers the output of the IO address signal from the IO address decoder 174 of the output circuit 171. It is the same as 1-byte address data. Also, 2-byte address data that triggers the output of a memory address signal from the memory address decoder 185 of the input circuit 181 becomes a trigger that the memory address signal of the output circuit 171 is output. It is identical to the byte address data. Thus, the address data for outputting the chip select signal from the output circuit 171 to the external output latch circuit 161 and the internal output latch circuit 162, and the chip select signal from the input circuit 181 to the internal input latch circuit 163. Address data to be output can be made the same data. Therefore, it becomes possible to process data that has been output to the output port 62b in the CPU core 102 and output the processed data to the output port 62b by specifying one address data.

  Further, each output latch is configured to output the chip select signal to each output latch circuit 161 and 162 and output the chip select signal to the internal input latch circuit 163 according to the designation of one address data. The chip select signal is output to the circuits 161 and 162 when the WR signal is output from the CPU core 102, and the output of the chip select signal to the internal input latch circuit 163 is the RD signal from the CPU core 102. It takes place if it is done. Therefore, it is possible to make the output timing of data using the output latch circuits 161 and 162 different from the input timing of data using the internal input latch circuit 163.

  According to the present embodiment described above, in addition to the effects of the second embodiment, the following excellent effects can be obtained.

  An internal input latch circuit 163 for resupplying output data to the CPU core 102 is incorporated in the CPU 101. As a result, there is no need to provide the CPU 101 with a terminal for outputting a chip select signal for supplying data from the internal input latch circuit 163 to the data bus DB. Therefore, output data can be supplied again to the CPU core 102 while suppressing an increase in the number of terminals of the CPU 101.

<Common Configuration in Each Embodiment>
The configuration for accessing the ROM 63 or the RAM 64 in each embodiment will be described. FIG. 24 is a block diagram showing an electrical configuration for outputting a chip select signal to a corresponding input latch circuit when reading data from RAM 64. Referring to FIG. The electrical configuration for outputting a chip select signal to the corresponding input latch circuit when reading out a command or data from the ROM 63 is the same as the electrical configuration shown in FIG. In addition, when writing data in the RAM 64, the electrical configuration for outputting the chip select signal to the corresponding output latch circuit is the RD signal when the operation select signal is output from the operation select circuit 191. However, the other points are the same as the electrical configuration shown in FIG. 24 except that they are WR signals.

  A circuit for outputting a chip select signal that triggers reading of data from the RAM 64 is an operation selection circuit 191 electrically connected to the RD terminal and the WR terminal, and an object electrically connected to the IREQ terminal and the MREQ terminal. When the load instruction is executed in CPU core 102, 2-byte address data is input when selection circuit 192, initialization circuit 193 for outputting an initialization signal to operation selection circuit 191 and target selection circuit 192, and the like. And a combination circuit 195 electrically connected to the operation selection circuit 191, the target selection circuit 192, and the memory address decoder 194.

  The switch circuit 191a provided in the operation selection circuit 191 receives the initialization signal when the supply of the operation power to the CPU 101 is started, and the signal serving as the output selection of the operation selection signal is from the RD terminal. The RD signal and the WR signal from the WR terminal are set to be the RD signal. Therefore, when the RD signal is output from the CPU core 102, the operation selection signal is output from the operation selection circuit 191.

  The switch circuit 192a provided in the target selection circuit 192 receives the initialization signal when the supply of the operation power to the CPU 101 is started, and thus the signal serving as the output trigger of the target selection signal is from the IREQ terminal. Of the MREQ signal from the IREQ signal and the MREQ terminal, the MREQ signal is set. Therefore, when the MREQ signal is output from the CPU core 102, the target selection signal is output from the target selection circuit 192.

  The memory address decoder 194 is a memory when the CPU core 102 outputs 2-byte address data corresponding to the memory address decoder 194, in other words, 2-byte address data corresponding to data read from the RAM 64. Output address signal. The synthesis circuit 195 outputs a chip select signal from the chip select terminal CS20 to the input latch circuit when all of the memory address signal, the operation selection signal, and the target selection signal are output. Thereby, the data written in the area corresponding to the present address specification in the RAM 64 is supplied to the data bus DB, and the data is supplied to the CPU core 102 through the data terminals D0 to D7.

Other Embodiments
In addition, it is not limited to the description content of embodiment mentioned above, A various deformation | transformation improvement is possible within the range which does not deviate from the meaning of this invention. For example, it may be changed as follows. Incidentally, the configurations of the following different embodiments may be applied individually to the configuration of the above embodiment, or may be applied in combination.

  (1) In the first embodiment, the IO address decoder 114 and the memory address decoder 115 are separately provided in the circuit corresponding to one chip select terminal CS0. Similar to the address decoder 115, one address decoder may be provided in which input terminals corresponding to the address terminals A0 to A15 are provided one to one. In this case, when a predetermined 1-byte address data is output from the upper eight address terminals A0 to A7, the address decoder outputs the address decoder from the lower eight address terminals A8 to A15. An address signal (corresponding to the combined address signal in the first embodiment) is output to the combining circuit 117 regardless of the content of the existing address data. Even in this configuration, the output of the RD signal from the CPU core 102, the output of one of the IREQ signal and the MREQ signal from the CPU core 102, and the output of predetermined two bytes of address data from the CPU core 102 In this case, the chip select signal can be output from the chip select terminal CS0. Further, in the case of the configuration, the configuration can be simplified as compared with the first embodiment in that only one address decoder is required. The configuration may be applied as a circuit configuration for outputting a chip select signal to the output latch circuit, and may be applied to the second embodiment or the third embodiment.

  (2) In the configuration of (1) above, when accessing the IO space 105, predetermined 1 byte of address data is output from the upper 8 address terminals A0 to A7 and the lower 8 side address data are output. The control content of CPU core 102 is set so that all “0” or all “1” data is output from address terminals A8 to A15, and when accessing memory space 106, it is set in a load instruction. Alternatively, two bytes of address data may be output from the address terminals A0 to A15. In this case, even if a predetermined 1-byte address data is output from the upper 8 address terminals A0 to A7, 1 byte is output from the lower 8 address terminals A8 to A15. When the address data of is a specific data, the chip select signal is not output from the chip select terminal CS0. Thereby, even if the upper 1 byte of address data is predetermined data, if the lower 1 byte of address data is specific data, the chip from the chip select terminal different from the chip select terminal CS0 It becomes possible to use as an address which becomes an output opportunity of a select signal. The configuration may be applied as a circuit configuration for outputting a chip select signal to the output latch circuit, and may be applied to the second embodiment or the third embodiment.

  (3) In the first embodiment, the IO address decoder 114 and the memory address decoder 115 are separately provided in the circuit corresponding to one chip select terminal CS0. Similar to the address decoder 114, one address decoder may be provided with input terminals corresponding to the address terminals A0 to A7 on a one-to-one basis. In this case, when a predetermined 1-byte address data is input from the upper eight address terminals A0 to A7, the address decoder outputs the address signal to the synthesizing circuit 117 (the first embodiment described above). Output corresponding to the combined address signal in the embodiment). Even in this configuration, the output of the RD signal from the CPU core 102, the output of one of the IREQ signal and the MREQ signal from the CPU core 102, and the output of predetermined two bytes of address data from the CPU core 102 In this case, the chip select signal can be output from the chip select terminal CS0. Further, in the case of the configuration, the configuration can be simplified as compared with the first embodiment in that only one address decoder is required. The configuration may be applied as a circuit configuration for outputting a chip select signal to the output latch circuit, and may be applied to the second embodiment or the third embodiment.

  (4) In the first embodiment, when the object selection circuit 113 is omitted, and the combined address signal is output from the address circuit 116 and the operation selection signal is output from the operation selection circuit 111, the combination is performed. A chip select signal may be output from the circuit 117. In this case, the chip select signal can be output even when both the IREQ signal and the MREQ signal are not output from the CPU core 102. However, the CPU core 102 can output the chip select signal. It is necessary that either the RD signal or the WR signal is output and predetermined address data is output. The configuration may be applied as a circuit configuration for outputting a chip select signal to the output latch circuit, and may be applied to the second embodiment or the third embodiment.

  (5) In the above embodiments, a chip select circuit is provided for outputting a chip select signal to an input latch circuit for inputting data from an input port 62a, and an output latch circuit for outputting data to an output port 62b. All of the circuits for outputting signals are not limited to the configuration for outputting a chip select signal even when either the IREQ signal or the MREQ signal is output from the CPU core 102, and those circuits Among them, a chip select signal may be output when an IREQ signal is output from the CPU core 102, but a chip select signal may not be output when an MREQ signal is output. In this case, the target selection circuit of the part of the circuits outputs the target selection signal only when the IREQ signal is output. In addition, while part of the circuits includes the IO address decoder, the memory address decoder and the address circuit are not provided. In the configuration, the synthesis circuit mounted in a part of the circuits inputs the IO address signal from the IO address decoder, the operation selection signal from the operation selection circuit, and the target selection signal from the target selection circuit. In this case, a chip select signal will be output.

  (6) In the third embodiment, the internal output latch circuit 162 may not be provided. In this case, the data transmission path from the external output latch circuit 161 to the output port 62b is branched, and the branch path is electrically connected to the internal input latch circuit 163, whereby the output from the external output latch circuit 161 is performed. It becomes possible for the data set to the port 62b to be latched in the internal input latch circuit 163.

  (7) In the third embodiment, the internal input latch circuit 163 may be omitted, and instead, the function of the internal input latch circuit 163 may be performed by the RAM 64 or the register of the CPU 101. In this case, the configuration can be simplified as compared with the third embodiment in that the internal input latch circuit 163 need not be provided.

  (8) Instead of the configuration in which the input port 62a of the MPU 62 is provided with connection terminals in a number greater than one byte, a configuration may be employed in which connection terminals for one byte are provided. In this configuration, the main control board 61 is provided with a plurality of input latch circuits, and a number of chip select terminals corresponding to the input latch circuits are provided one by one in the MPU 62 to be an output target of chip select signals. Data may be input from the input latch circuit to the input port 62a, and the data input to the input port 62a may be supplied to the CPU 101.

  Further, instead of the configuration in which the output port 62b of the MPU 62 is provided with connection terminals having a number greater than one byte, a configuration may be employed in which connection terminals for one byte are provided. In this configuration, the main control board 61 is provided with a plurality of output latch circuits, and a number of chip select terminals corresponding to the output latch circuits in a one-to-one manner are provided in the MPU 62 to be output targets of chip select signals. Alternatively, data may be output from the output port 62b to an output latch circuit.

  (9) Instead of the configuration in which the display control device 90 is controlled by the voice emission control device 80 based on the command transmitted from the main control device 60, display control based on the command transmitted from the main control device 60 The device 90 may control the sound emission control device 80. Further, instead of the configuration in which the sound emission control device 80 and the display control device 90 are separately provided, both control devices may be provided as one control device, and one function of the both control devices may be provided. May be integrated into the main control unit 60, and both functions of both control units may be integrated into the main control unit 60. Further, the configuration of the command transmitted from the main control device 60 to the sound emission control device 80 and the configuration of the command transmitted from the sound emission control device 80 to the display control device 90 are also arbitrary.

  (10) Other types of pachinko machines and the like different from the above embodiments, for example, pachinko machines in which a motorized role opens a predetermined number of times when gaming balls enter a specific area of a special device The present invention can be applied to a pachinko machine that becomes a jackpot when a right enters and becomes a jackpot, a pachinko machine equipped with other features, an arrange ball machine, a game machine such as a ball ball, and the like.

  A non-ball-ball type game machine, for example, a plurality of reels having a plurality of kinds of symbols attached in the circumferential direction, starts the rotation of the reels by inserting medals and operating the start lever, and the stop switch is operated. If a specific symbol or a combination of specific symbols is established on an effective line visible from the display window after the reel is stopped by the passage of a predetermined time, a bonus such as payout of medals is given to the player The present invention can also be applied to slot machines.

  In addition, the gaming machine main body supported in an openable and closable manner by the outer frame is provided with the storage section and the loading device, and the start lever is operated after the predetermined number of gaming balls stored in the storage section are loaded by the loading device. The present invention can also be applied to a gaming machine that starts rotation of a reel and performs a game similar to a slot machine by using gaming balls as gaming media.

<About the invention group extracted from each of the above embodiments>
Hereinafter, the features of the invention group extracted from the above-described embodiments will be described while showing effects and the like as necessary. In the following, for ease of understanding, the corresponding configurations in the above-described embodiments are appropriately shown in parentheses, but the present invention is not limited to the specific configurations shown in parentheses.

<Feature A group>
Features A1. Storage means (ROM 63) for storing instructions in advance;
Control execution means (CPU core 102) for executing the instruction read from the storage means;
In a gaming machine provided with
The control execution means is
First signal output means (MREQ terminal) for outputting a first instruction corresponding signal (MREQ signal) when executing the first instruction;
Second signal output means (IREQ terminal) for outputting a second instruction corresponding signal (IREQ signal) when executing a second instruction having a different amount of information from the first instruction;
Equipped with
The game machine is
A specific output unit (a first output unit) that outputs a specific signal (chip select signal) regardless of at least the first command corresponding signal being output and the second command corresponding signal being output. In the embodiment, the synthesis circuit 117; in the second embodiment, the synthesis circuit 137; and in the third embodiment, the synthesis circuit 177);
Operating means (in the first embodiment, the input latch circuit 103 or the output latch circuit 104, the first embodiment) in which the specific operation state is at least one of input and output of information when the specific signal is output In the second embodiment, the output latch circuit 121a, and in the third embodiment, the external output latch circuit 161);
A game machine characterized by comprising:

  According to the feature A1, when the first command is executed, the first signal output unit outputs the first command corresponding signal, and when the second command is executed, the second signal output unit outputs the second command corresponding signal. Therefore, it is possible to prevent the predetermined operation from being executed in the situation where neither the first instruction nor the second instruction is executed, and the first instruction is executed and It becomes possible to distinguish the operation target from the case where two instructions are executed.

  In this case, the specific signal output to bring the operating means into the specific operating state is also output when any of the first command corresponding signal and the second command corresponding signal is output from the control execution means. Ru. This makes it possible to bring the operating means into a specific operating state regardless of whether the first instruction or the second instruction is executed. Therefore, it is possible to widen the range of types of instructions in the case of setting the operating means to a specific operating state.

  The “first signal output unit” may be a “first signal output unit” or a “first signal output terminal”, and the “second signal output unit” may be a “second signal output unit” or a “second signal output unit”. "Signal output terminal" can be mentioned.

Feature A2. A predetermined output means (a target selection circuit 113 in the first embodiment, a target selection circuit 133 in the second embodiment) for outputting a predetermined signal when the first command corresponding signal or the second command corresponding signal is output. , And in the third embodiment, an object selection circuit 173),
The gaming machine according to feature A1, wherein the specific output unit outputs the specific signal when the predetermined signal is output.

  According to the feature A2, in the configuration in which the specific signal is output from the specific output device under the condition that the predetermined signal is output from the predetermined output device, the predetermined output device is the first command corresponding signal or the second command Since the predetermined signal is output when the corresponding signal is output, it is possible to obtain the above-described excellent effect while using the configuration other than the predetermined output means as it is.

  Feature A3. The predetermined output means includes an input means electrically connected to the first signal output means, and an input means electrically connected to the second signal output means. A game machine according to feature A2, comprising a logic circuit (object selection logic circuit 113a) for outputting the predetermined signal when any one of command corresponding signals is input.

  According to the feature A3, when the first command corresponding signal or the second command corresponding signal is output, the predetermined output unit is configured to output the predetermined signal by itself. It is not necessary to switch the state of the predetermined output means when the second instruction corresponding signal is output. Therefore, it is possible to achieve the excellent effects as described above while simplifying the configuration of the predetermined output means.

  Feature A4. The gaming machine according to any one of features A1 to A3, wherein the first instruction is a load instruction and the second instruction is either an in instruction or an out instruction.

  According to the feature A4, when controlling the operating means to be in a specific operating state which is at least one of input and output of information, not only either the in instruction or the out instruction but also the load instruction is executed. Is possible.

Feature A5. The control execution means is
Designated information output means (address terminals A0 to A15) for outputting designation information to designate an operation target;
When the operation means is brought into the specific operation state by executing the first instruction, the first designation information is outputted from the designation information output means, and the operation means is outputted by executing the second instruction. Designated information output means for outputting the second designated information from the designated information output means when in a specific operation state (function to execute processing of step S305, step S402, step S408, step S415 and step S419 in the CPU core 102) )When,
Equipped with
The features A1 to A4 are characterized in that the specific output unit outputs the specific signal regardless of whether the first specification information is output or the second specification information is output. The gaming machine according to any one of the above.

  According to the feature A5, in the configuration in which both the first instruction and the second instruction are executable when the operation means is in the specific operation state, the first specification information is output when the first instruction is executed. When the second instruction is executed, the second specification information is output. This makes it possible to output the designation information in a mode corresponding to each of the case of executing the first instruction and the case of executing the second instruction. Further, even if the first designation information is output when the first instruction is executed and the second designation information is output when the second instruction is executed, the first designation information is output. Since the specific signal is output from the specific output means in either of the case where the second instruction information is output or the second instruction information is output, either of the first instruction and the second instruction is executed, It is possible to bring the operating means into a specific operating state.

  In addition, as a "designation information output means", a "designation information output part" or a "designation information output terminal" is mentioned.

  Feature A6. The gaming machine according to feature A5, wherein the first designation information and the second designation information have different amounts of information.

  According to the feature A6, when the first instruction is executed, the designation information is output with the amount of information corresponding to the first instruction, and when the second instruction is executed, the information corresponding to the second instruction Output of specified information is performed by quantity. In this case, the specific output unit is provided with the configuration of the feature A5, and the specific output unit outputs the specific signal regardless of whether the first specified information is output or the second specified information is output. The operating means can be brought into a specific operating state regardless of whether the first instruction or the second instruction is executed.

Feature A7. Designated correspondence means (in the first embodiment, the IO address decoder 114, the memory address decoder 115, and the address circuit 116 that outputs the designated correspondence signal when the first designated information or the second designated information is output. In the second embodiment, an IO address decoder 134, a memory address decoder 135 and an address circuit 136, and in the third embodiment, an IO address decoder 174, a memory address decoder 175 and an address circuit 176),
The gaming machine according to feature A5 or A6, wherein the specific output unit outputs the specific signal when the designated correspondence signal is output.

  According to the feature A7, the designated corresponding means outputs the designated corresponding signal when the first designated information or the second designated information is outputted, and at least one of the designated corresponding means being outputted from the designated corresponding means. Since the specific output unit outputs the specific signal as the condition, there is no need to execute the operation corresponding to each of the first specified information and the second specified information in the specific output means. As a result, it is possible to achieve the excellent effects as described above while simplifying the configuration of the specific output unit.

Feature A8. The designated correspondence means is
A means for outputting a first corresponding signal when the first designation information is output (in the first embodiment, the address decoder for memory 115, in the second embodiment, the address decoder for memory 135, the third embodiment) In the memory address decoder 175),
A unit for outputting a second corresponding signal when the second designation information is output (in the first embodiment, the IO address decoder 114, in the second embodiment, the IO address decoder 134, the third embodiment) Here, the IO address decoder 174),
A unit for outputting the designated corresponding signal when the first corresponding signal or the second corresponding signal is output (in the first embodiment, the address circuit 116; in the second embodiment, the address circuit 136, Address circuit 176) in the third embodiment;
The gaming machine according to feature A7, comprising:

  According to the feature A8, the means for outputting the first corresponding signal in response to the output of the first designation information, and the second corresponding signal in response to the output of the second designation information. By separately providing means for outputting the signals, it is possible to perform the output of the signal corresponding to each of the first designation information and the second designation information with a relatively simple configuration. Further, since the designated corresponding signal is output when the first corresponding signal or the second corresponding signal is output, it is possible to suppress the type of the signal output to the specific output unit.

  Note that any one or more of the features A1 to A8, the features B1 to B6, and the features C1 to C6 may be applied to the features A1 to A8. This makes it possible to produce a synergistic effect by the combined configuration.

<Feature B group>
Feature B1. Control execution means (CPU core 102) for setting predetermined information to the output means (output port 62b);
Operation executing means (the drive unit 32b for special power, the drive unit 34b for general power, the special view display unit 37a, the special view hold display unit 37b, the general purpose drive execution means for executing the operation corresponding to the predetermined information set in the output means Diagram display unit 38a, common view suspension display unit 38b, etc.),
Supply means for acquiring the predetermined information set in the output means from the transmission path through which the predetermined information is transmitted, and supplying the acquired predetermined information to the control execution means (in the second embodiment, an input latch Circuits 122a to 122c, and in the third embodiment, an internal output latch circuit 162 and an internal input latch circuit 163);
A game machine characterized by comprising:

  According to the feature B1, the predetermined information set in the output means is supplied to the control execution means via the transmission path. By this, even if the predetermined information set in the output means is not separately stored or read out again, the predetermined information can be read out again in the control execution means and used.

  Feature B2. The game according to the feature B1, wherein the supply means supplies the predetermined information to the control execution means when an input acquisition signal is input to the supply means based on control of the control execution means. Machine.

  According to the feature B2, it becomes possible to supply predetermined information from the supply means to the control execution means at a preferable timing in the control execution means.

Feature B3. A first transmission path (data bus DB) that enables transmission of information to the control execution means and transmission of information from the control execution means;
Output setting means for setting the predetermined information acquired from the first transmission path in the output means (output latch circuits 121a to 121c in the second embodiment, external output latch circuit 161 in the third embodiment) When,
Equipped with
The supply means is electrically connected to a target path which is any one of the first transmission path and a second transmission path (data paths L1 to L3) of information from the setting means for output to the output means. A game machine according to feature B1 or B2, characterized in that the predetermined information acquired from the target path is supplied to the first transmission path to be supplied to the control execution means.

  According to the feature B3, it is possible to supply the predetermined information to the control execution means using the transmission path for setting the predetermined information in the output means.

Feature B4. The output setting unit sets the predetermined information acquired from the first transmission path in the output unit when the output acquisition signal is input.
The supply means supplies the predetermined information to the first transmission path so as to supply the control execution means when the input acquisition signal is input.
First output handling means (a combining circuit 137 in the second embodiment) for outputting the output acquisition signal to the output setting means when predetermined designation information (address data) is output from the control execution means In the third embodiment, a synthesis circuit 177),
Second output handling means (the combining circuit 147 in the second embodiment, the third embodiment) for outputting the acquisition signal for input to the supply means when the predetermined designation information is output from the control execution means And the synthesis circuit 187),
The gaming machine according to feature B3, comprising:

  According to the feature B4, the setting means for output sets predetermined information to the output means when the acquisition signal for output is inputted, and the supply means outputs the predetermined information when the acquisition signal for input is inputted In order to supply the control execution means, it is possible to make the setting timing of the predetermined information to the output means and the supply timing of the predetermined information to the control execution means preferable. In this case, the predetermined designation information output from the control execution unit to cause the output setting unit to output the output acquisition signal, and the predetermined output from the control execution unit to cause the supply unit to output the input acquisition signal The specification information is the same. Accordingly, it becomes possible to supply the predetermined information to the control execution means by using predetermined designation information used to set the predetermined information in the output means.

Feature B5. The control execution means is
First corresponding means (WR terminal) for outputting a first signal when setting the predetermined information by the output setting means;
Second corresponding means (RD terminal) for outputting a second signal when the supply means is to supply the predetermined information;
Equipped with
The first output corresponding means outputs the output acquisition signal to the output setting means when the first signal is outputted.
The game machine according to feature B4, wherein the second output corresponding means outputs the acquisition signal for input to the supply means when the second signal is outputted.

  According to the feature B5, while the acquisition signal for output is outputted when the first signal is outputted from the control execution means, the acquisition signal for input is outputted when the second signal is outputted from the control execution means Be done. Thus, the predetermined designation information output from the control execution unit to cause the output setting unit to output the output acquisition signal and the predetermined designation output from the control execution unit to cause the supply unit to output the input acquisition signal Even when the information has the same configuration, it is possible to differentiate the timing at which the setting of the predetermined information is performed by the setting means for output and the timing at which the supply of the predetermined information is performed by the supplying means.

  In addition, as the "first corresponding means", "the first corresponding portion" or "the first corresponding terminal" may be mentioned, and as the "second corresponding means", the "second corresponding portion" or the "second corresponding terminal" may be mentioned. Be

Feature B6. The control execution means is
Generation means (function of executing the process of step S514 in the CPU core 102) for generating different information by executing a predetermined process on the predetermined information supplied by the supply means;
A unit for causing the different information generated by the generation unit to be set for the output unit (a function of executing the processing of step S518 in the CPU core 102);
The gaming machine according to any one of features B1 to B5, comprising:

  According to the feature B6, the control execution means can generate different information by processing the predetermined information already set in the output means, and can set the different information in the output means.

  Note that any one or more of the features A1 to A8, the features B1 to B6, and the features C1 to C6 may be applied to the features B1 to B6. This makes it possible to produce a synergistic effect by the combined configuration.

<Feature C group>
Feature C1. Control means (CPU 101) for inputting and outputting information using a predetermined transmission path (data bus DB);
When the selection signal (chip select signal) is output from the selection signal means (chip select terminal CS0) provided in the control means, the predetermined information acquired from the predetermined transmission path is output means (output port 62b) Setting means for output (external output latch circuit 161) set to
Operation executing means (the drive unit 32b for special power, the drive unit 34b for general power, the special view display unit 37a, the special view hold display unit 37b, the general purpose drive execution means for executing the operation corresponding to the predetermined information set in the output means Diagram display unit 38a, common view suspension display unit 38b, etc.),
In a gaming machine provided with
The control means
A control execution unit (CPU core 102) having an information output unit capable of outputting the predetermined information to the output unit;
Supply means (internal output latch circuit 162 and internal input latch circuit 163) for acquiring the predetermined information output from the information output means and supplying the acquired predetermined information to the control execution means;
A game machine characterized by comprising:

  According to the feature C1, the predetermined information set in the output means is supplied to the control execution means. By this, even if the predetermined information set in the output means is not separately stored or read out again, the predetermined information can be read out again in the control execution means and used. In addition, since the supply means is built in the control means, there is no need to provide means for operating the supply means in the control means. Therefore, it becomes possible to read out and use predetermined information again in the control execution means while suppressing an increase in the number of terminals of the control means.

  In addition, a "selection part" or a "selection terminal" is mentioned as a "means for selection signal."

  Feature C2. The game according to the feature C1, wherein the supply means supplies the predetermined information to the control execution means when the input acquisition signal is input to the supply means based on the control of the control execution means. Machine.

  According to the feature C2, it is possible to supply predetermined information from the supply means to the control execution means at a preferable timing in the control execution means.

Feature C3. The predetermined transmission path enables transmission of information to the control execution means and transmission of information from the control execution means.
The gaming machine according to feature C1 or C2, wherein the supply means supplies the predetermined information obtained from the predetermined transmission path to the predetermined transmission path so as to supply the control execution means.

  According to the feature C3, it is possible to supply the predetermined information to the control execution means by using the predetermined transmission path for setting the predetermined information in the output means.

Feature C4. The output setting means sets the predetermined information acquired from the predetermined transmission path in the output means when the output acquisition signal is input.
The supply means supplies the predetermined information to the predetermined transmission path so as to supply the control execution means when the input acquisition signal is input.
First output corresponding means (combining circuit 177) for outputting the output acquisition signal to the output setting means when predetermined designation information (address data) is output from the control execution means;
Second output corresponding means (combining circuit 187) for outputting the input acquisition signal to the supply means when the predetermined designation information is outputted from the control execution means;
The gaming machine according to feature C3, comprising:

  According to the feature C4, the setting means for output sets predetermined information to the output means when the acquisition signal for output is inputted, and the supply means performs the control execution means when the acquisition signal for input is inputted In order to supply the predetermined information to the control unit, it is possible to make the setting timing of the predetermined information to the output unit and the supply timing of the predetermined information to the control execution unit preferable. In this case, the predetermined designation information output from the control execution unit to cause the output setting unit to output the output acquisition signal, and the predetermined output from the control execution unit to cause the supply unit to output the input acquisition signal The specification information is the same. Accordingly, it becomes possible to supply the predetermined information to the control execution means by using predetermined designation information used to set the predetermined information in the output means.

Feature C5. The control execution means is
First corresponding means (WR terminal) for outputting a first signal when setting the predetermined information by the output setting means;
Second corresponding means (RD terminal) for outputting a second signal when the supply means is to supply the predetermined information;
Equipped with
The first output corresponding means outputs the output acquisition signal to the output setting means when the first signal is outputted.
The game machine according to Feature C4, wherein the second output corresponding means outputs the acquisition signal for input to the supply means when the second signal is outputted.

  According to the feature C5, while the acquisition signal for output is outputted when the first signal is outputted from the control execution means, the acquisition signal for input is outputted when the second signal is outputted from the control execution means Be done. Thus, the predetermined designation information output from the control execution unit to cause the output setting unit to output the output acquisition signal and the predetermined designation output from the control execution unit to cause the supply unit to output the input acquisition signal Even when the information has the same configuration, it is possible to differentiate the timing at which the setting of the predetermined information is performed by the setting means for output and the timing at which the supply of the predetermined information is performed by the supplying means.

  In addition, as the "first corresponding means", "the first corresponding portion" or "the first corresponding terminal" may be mentioned, and as the "second corresponding means", the "second corresponding portion" or the "second corresponding terminal" may be mentioned. Be

Feature C6. The control execution means is
Generation means (function of executing the process of step S514 in the CPU core 102) for generating different information by executing a predetermined process on the predetermined information supplied by the supply means;
A unit for causing the different information generated by the generation unit to be set for the output unit (a function of executing the processing of step S518 in the CPU core 102);
The gaming machine according to any one of the features C1 to C5, comprising:

  According to the feature C6, the control execution means can generate different information by processing the predetermined information already set in the output means, and can set the different information in the output means.

  Note that any one or more of the features A1 to A8, the features B1 to B6, and the features C1 to C6 may be applied to the features C1 to C6. This makes it possible to produce a synergistic effect by the combined configuration.

  According to the invention relating to the feature group A, the feature group B, and the feature group C, the following problems can be solved.

  Pachinko gaming machines and slot machines are known as a type of gaming machine. These gaming machines include a control element such as a CPU, a read only memory element such as a ROM, and a read / write memory element such as a RAM. The control element executes processing according to a program read from the read-only storage element while writing information to the read / write storage element and reading information from the storage element. When executing this process, information from a sensor or the like is input to the control element, and information from the control element is output to an electric actuator, a light emitting element, or the like. It is also known that a control element, a read-only storage element, and a read-write storage element are integrated into one chip.

  Here, in the gaming machine as illustrated above etc., there is a demand for a configuration capable of suitably performing control, and there is still room for improvement in this respect.

  The basic configuration of the gaming machine to which each of the above features can be applied or applied to each of the features is described below.

  Pachinko gaming machine: operation means operated by a player, game ball firing means for firing game balls based on the operation of the operation means, a ball passage for guiding the fired game balls to a predetermined game area, and a game A gaming machine comprising: each gaming component arranged in an area, and providing a bonus to a player when a gaming ball passes through a predetermined passing portion of the gaming components.

  Throttle type gaming machines such as slot machines: A pattern display device for variably displaying a plurality of patterns, variable display of the plurality of patterns is started due to the operation of the start operation means, and the cause is due to the operation of the stop operation means And / or a variable display of the plurality of symbols is stopped when a predetermined time elapses, and a game machine which provides a bonus to the player according to the symbols after the stop.

  10: Pachinko machine, 32b: drive unit for special electric power, 34b: drive unit for common use, 37a: special view display unit, 37b: special view reservation display unit, 38a: common view display unit, 38b: common view reservation display Section 62b: output port 63: ROM 102: CPU core 103: input latch circuit 104: output latch circuit 113: target selection circuit 113a: target selection logic circuit 114: IO address decoder , 115: memory address decoder, 116: address circuit, 117: combination circuit, 121a: output latch circuit, 122a to 122c, input latch circuit, 133: target selection circuit, 134: IO address decoder, 135: Address decoder for memory, 136: circuit for address, 137: combining circuit, 147: combining circuit, 161: latch circuit for external output, 1 2 ... internal output latch circuit, 163 ... internal input latch circuit, 173 ... target selection circuit, 174 ... IO address decoder, 175 ... memory address decoder, 176 ... address circuit, 177 ... synthesis circuit, 187 ... synthesis Circuit, A0 to A15: Address terminal, CS0: Chip select terminal, DB: Data bus, L1 to L3: Data path.

Claims (1)

Control execution means for setting predetermined information to the output means;
Operation execution means for executing an operation corresponding to the predetermined information set in the output means;
Supply means for acquiring the predetermined information set in the output means from a transmission path through which the predetermined information is transmitted, and supplying the acquired predetermined information to the control execution means;
A game machine characterized by comprising:

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