JP6985377B2 - 連続するメモリアドレスにおけるデータ記憶 - Google Patents

連続するメモリアドレスにおけるデータ記憶 Download PDF

Info

Publication number
JP6985377B2
JP6985377B2 JP2019515353A JP2019515353A JP6985377B2 JP 6985377 B2 JP6985377 B2 JP 6985377B2 JP 2019515353 A JP2019515353 A JP 2019515353A JP 2019515353 A JP2019515353 A JP 2019515353A JP 6985377 B2 JP6985377 B2 JP 6985377B2
Authority
JP
Japan
Prior art keywords
data
valid
memory
offset
vector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2019515353A
Other languages
English (en)
Japanese (ja)
Other versions
JP2019530091A5 (enExample
JP2019530091A (ja
Inventor
エリック・マフリン
デイヴィッド・ホイル
Original Assignee
クアルコム,インコーポレイテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by クアルコム,インコーポレイテッド filed Critical クアルコム,インコーポレイテッド
Publication of JP2019530091A publication Critical patent/JP2019530091A/ja
Publication of JP2019530091A5 publication Critical patent/JP2019530091A5/ja
Application granted granted Critical
Publication of JP6985377B2 publication Critical patent/JP6985377B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/3004Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043LOAD or STORE instructions; Clear instruction
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/30007Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30021Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/30007Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/30007Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3887Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple data lanes [SIMD]
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • H03M7/60General implementation details not specific to a particular type of compression
    • H03M7/6011Encoder aspects
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • H03M7/60General implementation details not specific to a particular type of compression
    • H03M7/6017Methods or arrangements to increase the throughput
    • H03M7/6023Parallelization

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Complex Calculations (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Communication Control (AREA)
JP2019515353A 2016-09-22 2017-07-27 連続するメモリアドレスにおけるデータ記憶 Active JP6985377B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/273,366 2016-09-22
US15/273,366 US10162752B2 (en) 2016-09-22 2016-09-22 Data storage at contiguous memory addresses
PCT/US2017/044227 WO2018057115A1 (en) 2016-09-22 2017-07-27 Data storage at contiguous memory addresses

Publications (3)

Publication Number Publication Date
JP2019530091A JP2019530091A (ja) 2019-10-17
JP2019530091A5 JP2019530091A5 (enExample) 2020-08-20
JP6985377B2 true JP6985377B2 (ja) 2021-12-22

Family

ID=59558510

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2019515353A Active JP6985377B2 (ja) 2016-09-22 2017-07-27 連続するメモリアドレスにおけるデータ記憶

Country Status (8)

Country Link
US (1) US10162752B2 (enExample)
EP (1) EP3516774B1 (enExample)
JP (1) JP6985377B2 (enExample)
KR (1) KR102561619B1 (enExample)
CN (1) CN109690956B (enExample)
CA (1) CA3033960A1 (enExample)
ES (1) ES2967320T3 (enExample)
WO (1) WO2018057115A1 (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111158757B (zh) * 2019-12-31 2021-11-30 中昊芯英(杭州)科技有限公司 并行存取装置和方法以及芯片
US11281554B2 (en) * 2020-03-17 2022-03-22 Samsung Electronics Co., Ltd. System and method for in-memory computation

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0731669B2 (ja) * 1986-04-04 1995-04-10 株式会社日立製作所 ベクトル・プロセツサ
JP2000022707A (ja) 1998-07-03 2000-01-21 Fujitsu Ltd データ伝送方法、およびデータ伝送システム
EP1267580A3 (en) 2001-05-28 2009-06-03 Panasonic Corporation Data transfer device
US7889765B2 (en) 2005-11-30 2011-02-15 Time Warner Cable Inc. Apparatus and methods for utilizing variable rate program streams in a network
WO2008127458A2 (en) 2006-12-06 2008-10-23 Fusion Multisystems, Inc. (Dba Fusion-Io) Apparatus, system, and method for a shared, front-end, distributed raid
JP5262177B2 (ja) * 2008-02-22 2013-08-14 富士通株式会社 ベクトル積の並列処理方法
US9280342B2 (en) * 2011-07-20 2016-03-08 Oracle International Corporation Vector operations for compressing selected vector elements
US9792117B2 (en) * 2011-12-08 2017-10-17 Oracle International Corporation Loading values from a value vector into subregisters of a single instruction multiple data register
US9697174B2 (en) * 2011-12-08 2017-07-04 Oracle International Corporation Efficient hardware instructions for processing bit vectors for single instruction multiple data processors
US9274937B2 (en) 2011-12-22 2016-03-01 Longitude Enterprise Flash S.A.R.L. Systems, methods, and interfaces for vector input/output operations
CN107729018A (zh) * 2012-09-28 2018-02-23 英特尔公司 循环向量化方法和设备
US9268571B2 (en) * 2012-10-18 2016-02-23 Qualcomm Incorporated Selective coupling of an address line to an element bank of a vector register file
US9606961B2 (en) * 2012-10-30 2017-03-28 Intel Corporation Instruction and logic to provide vector compress and rotate functionality
US11113054B2 (en) * 2013-09-10 2021-09-07 Oracle International Corporation Efficient hardware instructions for single instruction multiple data processors: fast fixed-length value compression
US10133570B2 (en) * 2014-09-19 2018-11-20 Intel Corporation Processors, methods, systems, and instructions to select and consolidate active data elements in a register under mask into a least significant portion of result, and to indicate a number of data elements consolidated
US9697176B2 (en) * 2014-11-14 2017-07-04 Advanced Micro Devices, Inc. Efficient sparse matrix-vector multiplication on parallel processors

Also Published As

Publication number Publication date
CN109690956A (zh) 2019-04-26
ES2967320T3 (es) 2024-04-29
EP3516774B1 (en) 2023-11-29
US10162752B2 (en) 2018-12-25
WO2018057115A1 (en) 2018-03-29
KR20190056365A (ko) 2019-05-24
KR102561619B1 (ko) 2023-07-28
EP3516774A1 (en) 2019-07-31
US20180081803A1 (en) 2018-03-22
CN109690956B (zh) 2024-02-13
CA3033960A1 (en) 2018-03-29
BR112019005612A2 (pt) 2019-10-08
JP2019530091A (ja) 2019-10-17

Similar Documents

Publication Publication Date Title
JP6243000B2 (ja) マルチモードベクトル処理を提供するためのプログラム可能データ経路構成を有するベクトル処理エンジン、ならびに関連ベクトルプロセッサ、システム、および方法
US9639369B2 (en) Split register file for operands of different sizes
CN104969215B (zh) 具有用于提供蝶形向量处理电路的可编程数据路径的向量处理引擎以及相关的向量处理器、系统和方法
EP3033670B1 (en) Vector accumulation method and apparatus
TWI644208B (zh) 藉由對硬體資源之限制實現的向後相容性
JP6345231B2 (ja) 外部からプログラム可能なメモリ管理ユニット
US11372804B2 (en) System and method of loading and replication of sub-vector values
KR101697548B1 (ko) Fifo 로드 명령
JP2016511470A (ja) スカラーレジスタデータ値に基づいたベクトルレジスタアドレス指定および関数
US20160004636A1 (en) Electronic device with cache memory and method of operating the same
JP6258525B2 (ja) 再構成可能フェッチパイプライン
JP6985377B2 (ja) 連続するメモリアドレスにおけるデータ記憶
US10706316B2 (en) System and method of feature descriptor processing
JP6737869B2 (ja) スライディングウィンドウ演算
US20150161401A1 (en) Processor having a variable pipeline, and system-on-chip
JP6687803B2 (ja) 区分線形近似のためのシステムおよび方法
BR112019005612B1 (pt) Armazenamento de dados em endereços de memória contíguos
JP2002182905A (ja) ディジタル信号処理プロセッサ

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20200708

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20200708

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20210630

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20210719

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20211019

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20211101

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20211125

R150 Certificate of patent or registration of utility model

Ref document number: 6985377

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250