ES2967320T3 - Almacenamiento de datos en direcciones de memoria contiguas - Google Patents

Almacenamiento de datos en direcciones de memoria contiguas Download PDF

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Publication number
ES2967320T3
ES2967320T3 ES17749310T ES17749310T ES2967320T3 ES 2967320 T3 ES2967320 T3 ES 2967320T3 ES 17749310 T ES17749310 T ES 17749310T ES 17749310 T ES17749310 T ES 17749310T ES 2967320 T3 ES2967320 T3 ES 2967320T3
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ES
Spain
Prior art keywords
data
memory
valid
vector
offset
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
ES17749310T
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English (en)
Spanish (es)
Inventor
Eric Mahurin
David Hoyle
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Application granted granted Critical
Publication of ES2967320T3 publication Critical patent/ES2967320T3/es
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30021—Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3887—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple data lanes [SIMD]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • H03M7/60—General implementation details not specific to a particular type of compression
    • H03M7/6011—Encoder aspects
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • H03M7/60—General implementation details not specific to a particular type of compression
    • H03M7/6017—Methods or arrangements to increase the throughput
    • H03M7/6023—Parallelization

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Complex Calculations (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Communication Control (AREA)
ES17749310T 2016-09-22 2017-07-27 Almacenamiento de datos en direcciones de memoria contiguas Active ES2967320T3 (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/273,366 US10162752B2 (en) 2016-09-22 2016-09-22 Data storage at contiguous memory addresses
PCT/US2017/044227 WO2018057115A1 (en) 2016-09-22 2017-07-27 Data storage at contiguous memory addresses

Publications (1)

Publication Number Publication Date
ES2967320T3 true ES2967320T3 (es) 2024-04-29

Family

ID=59558510

Family Applications (1)

Application Number Title Priority Date Filing Date
ES17749310T Active ES2967320T3 (es) 2016-09-22 2017-07-27 Almacenamiento de datos en direcciones de memoria contiguas

Country Status (8)

Country Link
US (1) US10162752B2 (enExample)
EP (1) EP3516774B1 (enExample)
JP (1) JP6985377B2 (enExample)
KR (1) KR102561619B1 (enExample)
CN (1) CN109690956B (enExample)
CA (1) CA3033960A1 (enExample)
ES (1) ES2967320T3 (enExample)
WO (1) WO2018057115A1 (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111158757B (zh) * 2019-12-31 2021-11-30 中昊芯英(杭州)科技有限公司 并行存取装置和方法以及芯片
US11281554B2 (en) * 2020-03-17 2022-03-22 Samsung Electronics Co., Ltd. System and method for in-memory computation

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0731669B2 (ja) * 1986-04-04 1995-04-10 株式会社日立製作所 ベクトル・プロセツサ
JP2000022707A (ja) 1998-07-03 2000-01-21 Fujitsu Ltd データ伝送方法、およびデータ伝送システム
EP1267580A3 (en) 2001-05-28 2009-06-03 Panasonic Corporation Data transfer device
US7889765B2 (en) 2005-11-30 2011-02-15 Time Warner Cable Inc. Apparatus and methods for utilizing variable rate program streams in a network
WO2008127458A2 (en) 2006-12-06 2008-10-23 Fusion Multisystems, Inc. (Dba Fusion-Io) Apparatus, system, and method for a shared, front-end, distributed raid
JP5262177B2 (ja) * 2008-02-22 2013-08-14 富士通株式会社 ベクトル積の並列処理方法
US9280342B2 (en) * 2011-07-20 2016-03-08 Oracle International Corporation Vector operations for compressing selected vector elements
US9792117B2 (en) * 2011-12-08 2017-10-17 Oracle International Corporation Loading values from a value vector into subregisters of a single instruction multiple data register
US9697174B2 (en) * 2011-12-08 2017-07-04 Oracle International Corporation Efficient hardware instructions for processing bit vectors for single instruction multiple data processors
US9274937B2 (en) 2011-12-22 2016-03-01 Longitude Enterprise Flash S.A.R.L. Systems, methods, and interfaces for vector input/output operations
CN107729018A (zh) * 2012-09-28 2018-02-23 英特尔公司 循环向量化方法和设备
US9268571B2 (en) * 2012-10-18 2016-02-23 Qualcomm Incorporated Selective coupling of an address line to an element bank of a vector register file
US9606961B2 (en) * 2012-10-30 2017-03-28 Intel Corporation Instruction and logic to provide vector compress and rotate functionality
US11113054B2 (en) * 2013-09-10 2021-09-07 Oracle International Corporation Efficient hardware instructions for single instruction multiple data processors: fast fixed-length value compression
US10133570B2 (en) * 2014-09-19 2018-11-20 Intel Corporation Processors, methods, systems, and instructions to select and consolidate active data elements in a register under mask into a least significant portion of result, and to indicate a number of data elements consolidated
US9697176B2 (en) * 2014-11-14 2017-07-04 Advanced Micro Devices, Inc. Efficient sparse matrix-vector multiplication on parallel processors

Also Published As

Publication number Publication date
CN109690956A (zh) 2019-04-26
EP3516774B1 (en) 2023-11-29
US10162752B2 (en) 2018-12-25
WO2018057115A1 (en) 2018-03-29
KR20190056365A (ko) 2019-05-24
KR102561619B1 (ko) 2023-07-28
EP3516774A1 (en) 2019-07-31
US20180081803A1 (en) 2018-03-22
CN109690956B (zh) 2024-02-13
CA3033960A1 (en) 2018-03-29
BR112019005612A2 (pt) 2019-10-08
JP2019530091A (ja) 2019-10-17
JP6985377B2 (ja) 2021-12-22

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