JP6981289B2 - Compound semiconductor devices, their manufacturing methods, and receivers - Google Patents

Description

The present invention relates to a compound semiconductor device, a method for manufacturing the same, and a receiver using the compound semiconductor device.

A Schottky diode or a backward diode is used as a detection element of a receiving device that receives and detects high-frequency radio waves such as millimeter waves and terahertz waves.

Further, these diodes can also be used as a power conversion element of a power conversion device that receives such high-frequency radio waves and converts them into electric power.

Of these diodes, the backward diode is a diode that utilizes the electron band-to-band tunnel phenomenon.

This backward diode has higher detection sensitivity and power conversion efficiency than a Schottky diode when used in a receiving device or a power conversion device, and is therefore suitable for receiving weak radio waves.

In the backward diode, a mesa type having a trapezoidal cross section is adopted as a pn junction structure in which a p-type semiconductor and an n-type semiconductor are joined.

On the other hand, in order to further improve the detection sensitivity and the power conversion efficiency of the diode, it is effective to reduce the area of the pn junction and reduce the junction capacitance.

However, since the mesa-type pn junction is formed by patterning, there is a limit to the reduction of the area of the pn junction due to the patterning performance, and accordingly, there is a limit to the improvement of the detection sensitivity and the power conversion efficiency of the diode. There is.

As a method of reducing the area of the pn junction, a method of forming a pn junction with nanowires by continuously growing linear p-type semiconductors and n-type semiconductors upward from a substrate can be considered.

According to this method, the area of the pn junction can be reduced to the nano-level size.

Japanese Unexamined Patent Publication No. 2010-251689 Japanese Patent Publication No. 2013-508966

However, nanowires with a pn junction have room for improvement in terms of suppressing leakage current.

According to one aspect, an object thereof is to suppress a leakage current of a nanowire having a pn junction in a compound semiconductor device, a method for manufacturing the same, and a receiver.

According to one aspect of the technique disclosed below, the substrate and the linear compound semiconductor extending upward from the substrate, the lower part of the first conduction type and the second conduction extending above the lower part. possess a linear semiconductor that includes a mold top, and a protective layer of i-type compound semiconductor crystal covering a side surface of the linear semiconductor, the first conductivity type is n-type, the second conductivity The type is p-type, and the lower end of the conduction band of the protective layer is higher than the lower end of the lower conduction band, and the upper end of the valence band of the protective layer is lower than the upper end of the upper valence band. Equipment is provided.

According to the technique disclosed below, since the side surface of the linear semiconductor is covered with the protective layer of the i-type compound semiconductor crystal, the side surface of the linear semiconductor is not oxidized and a conductive oxide is formed on this side surface. Can be suppressed.

As a result, on the side surface of the linear semiconductor, it is possible to prevent the lower part of the first conductive type and the upper part of the second conductive type from being electrically connected by the conductive oxide. This makes it possible to suppress the leakage current flowing on the side surface of the linear semiconductor when a voltage is applied to the linear semiconductor.

FIG. 1 is a cross-sectional view of the compound semiconductor device used in the study. 2 (a) is a perspective view illustrating the structure of a mesa-type pn junction, and FIG. 2 (b) is a cross-sectional view taken along the line I-I of FIG. 2 (a). FIG. 3 (a) is a perspective view illustrating the structure of a nanowire type pn junction, and FIG. 3 (b) is a cross-sectional view taken along the line II-II of FIG. 3 (a). FIG. 4 is a cross-sectional view (No. 1) of the compound semiconductor device according to the first embodiment during manufacturing. FIG. 5 is a cross-sectional view (No. 2) of the compound semiconductor device according to the first embodiment during manufacturing. FIG. 6 is a cross-sectional view (No. 3) of the compound semiconductor device according to the first embodiment during manufacturing. FIG. 7 is a cross-sectional view (No. 4) of the compound semiconductor device according to the first embodiment during manufacturing. FIG. 8 is a cross-sectional view (No. 5) of the compound semiconductor device according to the first embodiment during manufacturing. FIG. 9 is a cross-sectional view (No. 6) of the compound semiconductor device according to the first embodiment during manufacturing. FIG. 10 is a cross-sectional view (No. 7) of the compound semiconductor device according to the first embodiment during manufacturing. FIG. 11 is a cross-sectional view (No. 1) of the compound semiconductor device according to the first embodiment during manufacturing. FIG. 12 is a cross-sectional view (No. 8) of the compound semiconductor device according to the first embodiment during manufacturing. FIG. 13 is a cross-sectional view (No. 9) of the compound semiconductor device according to the first embodiment during manufacturing. FIG. 14 is a cross-sectional view (No. 10) of the compound semiconductor device according to the first embodiment during manufacturing. FIG. 15 is a cross-sectional view (No. 11) of the compound semiconductor device according to the first embodiment during manufacturing. FIG. 16 is a cross-sectional view (No. 12) of the compound semiconductor device according to the first embodiment during manufacturing. FIG. 17 is a cross-sectional view (No. 13) of the compound semiconductor device according to the first embodiment during manufacturing. FIG. 18 is a cross-sectional view (No. 14) of the compound semiconductor device according to the first embodiment during manufacturing. FIG. 19 is a cross-sectional view (No. 15) of the compound semiconductor device according to the first embodiment during manufacturing. FIG. 20 is a cross-sectional view (No. 16) of the compound semiconductor device according to the first embodiment during manufacturing. FIG. 21 is a cross-sectional view (No. 17) of the compound semiconductor device according to the first embodiment during manufacturing. FIG. 22 is a cross-sectional view (No. 18) of the compound semiconductor device according to the first embodiment during manufacturing. FIG. 23 is a cross-sectional view (No. 19) of the compound semiconductor device according to the first embodiment during manufacturing. FIG. 24 (a) is a cross-sectional view of a portion of the structure obtained in the step of FIG. 8 on line III-III, and FIG. 24 (b) is a cross-sectional view of the portion of the structure obtained in the same manner on line IV-IV. .. 25 (a) to 25 (c) are diagrams showing the energy band of nanowires in the compound semiconductor device according to the first embodiment. FIG. 26 is a graph showing the current-voltage characteristics of the nanowires of the first embodiment. FIG. 27 (a) is a diagram showing the energy bands of the n-type lower portion and the protective layer of the nanowire of the first embodiment, and FIG. 27 (b) is a diagram showing the energy bands of the p-type upper portion and the protective layer. .. FIG. 28 is a cross-sectional view (No. 1) of the compound semiconductor device according to the second embodiment during manufacturing. FIG. 29 is a cross-sectional view (No. 2) of the compound semiconductor device according to the second embodiment during manufacturing. FIG. 30 is a cross-sectional view (No. 3) of the compound semiconductor device according to the second embodiment during manufacturing. FIG. 31 is a cross-sectional view (No. 4) of the compound semiconductor device according to the second embodiment during manufacturing. FIG. 32 is a cross-sectional view (No. 5) of the compound semiconductor device according to the second embodiment during manufacturing. 33 (a) is a cross-sectional view of a portion of the structure obtained in the process of FIG. 30 on the V-V line, and FIG. 33 (b) is a cross-sectional view of the portion of the structure obtained in the same V-VI line. .. FIG. 34 is a cross-sectional view (No. 1) of the compound semiconductor device according to the third embodiment during manufacturing. FIG. 35 is a cross-sectional view (No. 2) of the compound semiconductor device according to the third embodiment during manufacturing. FIG. 36 is a cross-sectional view (No. 3) of the compound semiconductor device according to the third embodiment during manufacturing. FIG. 37 is a cross-sectional view (No. 4) of the compound semiconductor device according to the third embodiment during manufacturing. FIG. 38 is a cross-sectional view (No. 5) of the compound semiconductor device according to the third embodiment during manufacturing. 39 (a) is a cross-sectional view of a portion of the structure obtained in the process of FIG. 36 on line VII-VII, and FIG. 39 (b) is a cross-sectional view of the portion of the structure obtained in the same line VIII-VIII. .. FIG. 40 is a circuit diagram of the energy conversion device according to the fourth embodiment. FIG. 41 is a cross-sectional view showing an example of the structure of a compound semiconductor device including nanowires operating as an esaki diode. FIG. 42 is a diagram showing an energy band of nanowires when the Esaki diode is heterojunction. FIG. 43 is a cross-sectional view showing another example of the structure of a compound semiconductor device including nanowires operating as an esaki diode. FIG. 44 is a diagram showing an energy band of nanowires when the Esaki diode is homozygous. FIG. 45 is a cross-sectional view showing an example of the structure of a compound semiconductor device including nanowires that operate as a normal diode. FIG. 46 is a diagram showing an energy band of nanowires when a normal diode is heterojunction. FIG. 47 is a cross-sectional view showing another example of the structure of a compound semiconductor device including nanowires that operate as a normal diode. FIG. 48 is a diagram showing the energy band of nanowires when a normal diode is homozygous.

Prior to the description of the present embodiment, the matters examined by the inventor of the present application will be described.

FIG. 1 is a cross-sectional view of the compound semiconductor device used in the study.

The compound semiconductor device 1 is a backward diode adopting the above-mentioned nanowire type bulk, and a contact layer 3 and a mask layer 4 are formed in this order on a semi-insulating GaAs substrate 2.

Of these, the contact layer 3 is a high-concentration n-type GaAs layer in which impurities are heavily doped in the semiconductor.

_{Further, the mask layer 4 is a SiO 2} layer provided with an opening 4a in which a part of the contact layer 3 is exposed, and serves as a mask when the nanowires described later are selectively formed on the contact layer 3.

Nanowires 5 extend upward from the contact layer 3 in the opening 4a. The nanowire 5 has an n-type lower portion 6 of an n-type semiconductor and a p-type upper portion 7 of a p-type semiconductor, and forms a pn junction in which the n-type lower portion 6 and the p-type upper portion 7 are joined.

In this example, the n-type lower part 6 forms an n-type InAs linear body doped with n-type impurities, and the p-type upper part 7 is a high-concentration p-type GaAsSb linear body doped with p-type impurities. Form the body.

The side surface 5a of the nanowire 5 is covered with a moisture-preventing insulating layer 8 that prevents the ingress of moisture from the outside. _{In this example, the Al 2} O ₃ layer is formed as the moisture-proof insulating layer 8.

Further, a metal cathode electrode 9 is formed on the contact layer 3. The cathode electrode 9 is in ohmic contact with the contact layer 3 by heat treatment.

A resin film such as BCB (benzocyclobutene) is formed as a coating insulating film 10 on the entire upper surface of the GaAs substrate 2 including the cathode electrode 9, and the nanowires 5 are embedded in the coating insulating film 10.

A metal anode electrode 11 is formed on the covering insulating film 10 and the nanowires 5. The anode electrode 11 is in ohmic contact with the p-type upper portion 7 by heat treatment.

Further, a contact hole 10a is formed in the covering insulating film 10, and a lead-out wiring 12 is formed in the contact hole 10a and on the covering insulating film 10. The extraction electrode 12 is connected to the cathode electrode 9.

In such a compound semiconductor device 1, when a voltage in the opposite direction is applied to the nanowire 5, electrons in the valence band of the p-type upper part 7 are transported to the conduction band of the n-type lower part 6 by interband tunneling, and a current is generated. Flows.

On the other hand, when a forward voltage is applied to the nanowire 5, electrons in the conduction band of the n-type lower part 6 cannot move to the valence band of the p-type upper part 7 due to the potential barrier, and the electrons in the valence band of the p-type upper part 7 cannot move. The holes cannot move to the conduction band of the n-type lower part 6, and no current flows.

According to such a compound semiconductor device 1, since the side surface 5a of the nanowire 5 is covered with the moisture-preventing insulating layer 8, deterioration of the pn junction due to moisture can be suppressed, and long-term use is possible.

However, in such a compound semiconductor device 1, a leakage current flowing through the side surface 5a of the nanowire 5 may be generated. The reason is considered as follows.

In contained in the n-type lower portion 6 of the nanowire 5 and Sb contained in the p-type upper portion 7 exhibit conductivity even when oxidized to form an oxide.

On the other hand, the moisture-proof insulating layer 8 covering the side surface 5a of the nanowire 5 is formed by an ALD (Atomic Layer Deposition) method capable of forming a thin layer having a nanolevel thickness on the nanowire 5 having a nanolevel width. Will be done.

Moreover, as the ALD method, an ALD method that does not use plasma may be adopted in order to suppress damage to the nanowire 5.

_{When forming an Al 3} O ₂ layer as a moisture-proof insulating layer 8 by the ALD method that does not use this plasma, an organic metal gas containing Al is used as a raw material gas and water vapor (H ₂ O) is used as an oxidizing agent. Raise the substrate temperature to a high temperature.

Therefore, when the moisture-preventing insulating layer 8 is formed, a conductive oxide of In is formed on the side surface 6a of the n-type lower portion 6 of the side surface 5a of the nanowire 5, and the side surface of the p-type upper portion 7 is formed. A conductive oxide of Sb is formed on 7a.

As a result, the n-type lower portion 6 and the p-type upper portion 7 are electrically connected by these conductive oxides.

As a result, when a forward voltage is applied to the nanowire 5, a leak current flows on the side surface 5a of the nanowire 5 even though no current flows inside the nanowire 5.

When this leakage current is generated, a part of the current flowing when a voltage in the reverse direction is applied to the nanowire 5 is canceled by the leakage current, so that the detection sensitivity and the power conversion efficiency of the diode are lowered. Become.

In particular, the nanowire type pn junction is more affected by the leak current flowing on the side surface than the mesa type pn junction because of its fineness. The reason is as follows.

2 (a) is a perspective view showing the structure of a mesa-type pn junction, and FIG. 2 (b) is a cross-sectional view taken along the line I-I of FIG. 2 (a). Further, FIG. 3 (a) is a perspective view showing the structure of a nanowire type pn junction, and FIG. 3 (b) is a cross-sectional view taken along the line II-II of FIG. 3 (a).

As shown in FIG. 2A, the mesa-type pn junction is a junction between the n-type lower portion 16 and the p-type upper portion 17, and the width dm of the pn junction surface 15b is about 1 μm to 10 μm.

On the other hand, as shown in FIG. 3A, the nanowire type pn junction is a junction of the above-mentioned n-type lower portion 6 and p-type upper portion 7, and the width dw of the pn junction surface 5b is 100 nm (= 0.1 μm). ) It is as follows.

As described above, the width dw of the nanowire type pn junction is about 1/10 to 1/100 of the width dm of the mesa type bulk, which is narrower than that of the mesa type pn junction.

By the way, the magnitude of the current flowing inside the pn junction is determined by the area of the cross section cut by the plane parallel to the substrate plane, assuming that the current density is constant.

On the other hand, the magnitude of the leak current flowing on the side surface of the pn junction is determined by the length around the side surface, assuming that the magnitude of the leak current per unit length is constant.

Here, assuming that the shape of the cross section cut by the plane parallel to the substrate surface of the pn junction is circular, as shown in FIG. 2 (b), in the mesa type pn junction, the cross-sectional area of the pn junction surface 15b. Sm length Lm of the surrounding πdm ^2/4, and the addition pn junction surface 15b becomes Paidm.

On the other hand, as shown in FIG. 3 (b), the nanowire-type pn junction, the cross-sectional area Sw of the pn junction plane 5b the length Lw of the surrounding πdw ^2/4, and the addition pn junction surface 5b becomes Paidw.

Then, when the ratio of the peripheral length L to the cross-sectional area S of the pn junction is L / S, the Lw / Sw (= 4 / dw) of the nanowire type pn junction is the Lm / of the mesa type pn junction. It is about 10 to 100 times that of Sm (= 4 / dm).

From this, it is said that the ratio of the leakage current flowing on the side surface to the current flowing inside the nanowire type pn junction is about 10 to 100 times larger than that of the mesa type pn junction, and the influence of the leakage current flowing on the side surface is considerably large. I can say.

As the moisture-preventing insulating layer 8, it is conceivable to form _{a SiO 2} layer having the same moisture-preventing function _{as the Al 3} O ₂ layer instead of the Al ₃ O _{2 layer.}

_{However, when the SiO 2} layer is formed by the ALD method that does not use plasma, _{ozone (O 3} ) is used as an oxidizing agent and the substrate temperature becomes high. Therefore, even in this case, a conductive oxide is formed on the side surface 5a of the nanowire 5.

In view of such findings, in the present embodiment, the generation of leakage current flowing on the side surface of the nanowire type pn junction is suppressed as follows.

(First Embodiment)
The compound semiconductor device according to the present embodiment will be described while following the manufacturing method thereof.

4 to 23 are cross-sectional views of the compound semiconductor device according to the present embodiment during manufacturing.

In the present embodiment, a compound semiconductor device including a backward diode having a nanowire type pn junction is manufactured as follows.

First, as shown in FIG. 4A, a semi-insulating GaAs substrate is prepared as the substrate 20. The plane orientation of the surface of the GaAs substrate is the (111) B plane in which only As of group V atoms are lined up on the surface.

The substrate 20 to be prepared is not particularly limited. For example, a compound semiconductor substrate such as an InP substrate or a GaSb substrate, or a Si substrate may be used.

Further, the substrate 20 may be a conductive substrate. However, considering the use of high-frequency radio waves in the compound semiconductor device, the substrate 20 is preferably a semi-insulating substrate in which carriers are hard to come out.

Then, a GaAs layer is formed on the substrate 20 as the contact layer 21 by the MOVPE (Metal Organic Vapor Phase Epitaxy) method to a thickness of 200 nm.

The growth gas for forming the GaAs layer is not particularly limited. For example, using the triethyl gallium _{((C 2 H 5) 3} Ga) as a material gas of Ga, may be used arsine (AsH ₃₎ as a source gas of As.

Further, by adding a silane-based gas such as silane or disilane to the above-mentioned growth gas for GaAs, Si is doped in the GaAs layer as an n-type impurity. Further, by adjusting the flow rate of the silane-based gas, the doping amount of Si in the GaAs layer is set to about ^{5 × 10 18} cm- ^{2 in the present embodiment.}

_{Next, as shown in FIG. 4B, a SiO 2} layer is formed on the entire upper surface of the substrate 20 as a mask layer 22 by a CVD (Chemical Vapor Deposition) method to a thickness of about 50 nm.

Next, as shown in FIG. 5A, an electron beam resist is applied onto the mask layer 22, exposed to the electron beam, and then developed to provide a circular opening 23a in a plan view. The resist layer 23 of 1 is formed.

Subsequently, as shown in FIG. 5B, a circular opening having a width of about 100 nm is exposed by dry etching the mask layer 22 through the opening 23a of the first resist layer 23. 22a is formed on the mask layer 22.

The etching gas used in the dry etching is not particularly limited, but for example, _{a gas containing fluorine such as CF 4} can be used as the etching gas.

Next, as shown in FIG. 6A, the Au layer 24 has a thickness of about 30 nm on the first resist layer 23 and on the contact layer 21 in the opening 22a of the mask layer 22 by a thin-film deposition method. Formed by.

Subsequently, as shown in FIG. 6B, the first resist layer 23 is removed with an organic solvent to leave the Au layer 24 formed in the opening 22a on the contact layer 21 as the catalyst 24a. Such a patterning method for the Au layer 24 is also called a lift-off method.

Next, the process shown in FIG. 7 will be described.

First, the catalyst 24a is liquefied by placing the substrate 20 in a chamber (not shown) and raising the substrate temperature to about 400 ° C.

Then, by supplying a growth gas for InAs into the chamber, the contact layer 21 is used as a seed crystal, and the liquefied catalyst 24a is used as a solvent in the VLS (Vapor Liquid Solid) method in the opening 22a of the mask layer 22. InAs crystals are grown upward from the contact layer 21.

At this time, since a GaAs substrate having a surface orientation of (111) B surface is used as the substrate 20 as described above, the contact layer 21 inherits the surface orientation of the substrate 20 and As from the surface of the contact layer 21. Crystals of InAs containing are more likely to grow upwards.

The growth gas for InAs is not particularly limited. For example, using triethyl indium _{((C 2 H 5) 3} In) as a source gas for In, may be used arsine (AsH ₃₎ as a source gas of As.

Further, by adding a silane-based gas such as silane or disilane to the above-mentioned growth gas for InAs, Si is doped into InAs as an n-type impurity. In this embodiment, InAs is doped with Si at a concentration of about ^{1 × 10 17} cm ^-3.

The substrate temperature at which InAs is grown is not particularly limited, but is set to, for example, 500 ° C.

In this way, a linear body of n-type InAs is formed on the contact layer 21 as the n-type lower portion 26 of the nanowire 25. The size of the linear body of InAs is, for example, 80 nm in width, which is smaller than the opening 22a of the mask layer 22, and 0.5 to 1 μm in length.

Subsequently, by stopping the supply of the growth gas for InAs and supplying the growth gas for GaAsSb into the chamber, the above-mentioned liquefied catalyst 24a is used as a solvent in the VLS method from the n-type lower portion 26. Grow GaAsSb crystals upwards.

The growth gas for the GaAsSb is not particularly limited. For example, the above-mentioned triethyl gallium ((C ₂ H ₅ ) ₃ Ga) is used as the raw material gas for Ga, arsine (AsH ₃ ) is used as the raw material gas for As, and trimethylantimony ((CH _{3)) is used as the raw material gas for Sb.} ) ₃ Sb) can be used.

Further, by adding an organometallic gas containing zinc such as diethylzinc and dimethylzinc to the above-mentioned growth gas for GaAsSb, Zn is doped in GaAsSb as a p-type impurity. Further, by adjusting the flow rate of the organometallic gas, the doping amount of Zn in GaAsSb is set to about ^{1 × 10 18} cm ^{-3 in the present embodiment.}

The substrate temperature at which GaAsSb is grown is not particularly limited, but is, for example, 500 ° C., which is the same as InAs.

In this way, a high-concentration p-type GaAsSb striatum is formed on the n-type lower part 26 as the p-type upper part 27. The size of the GaAsSb striatum is, for example, 80 nm, which is the same as that of the InAs striatum, and 0.5 to 1 μm in length.

As described above, a pn junction is formed in which the n-type lower portion 26 and the p-type upper portion 27 are joined to the nanowire 25.

After that, the supply of the growth gas for GaAsSb is stopped.

Next, the process shown in FIG. 8 will be described.

First, the above chamber is still used to reduce the substrate temperature from 500 ° C to 400 ° C.

Then, the same growth gas for GaAs as the contact layer 21 is supplied into the chamber. However, unlike the contact layer 21, no gas for doping impurities is added to the growth gas for GaAs.

As a result, i-type GaAs crystals are grown from the side surface 25a of the nanowire 25 in the direction parallel to the substrate surface to form the i-type GaAs layer as the protective layer 28.

The protective layer 28 is formed to have a thickness equal to or less than the critical film thickness immediately before the lattice unmatched dislocations, for example, a thickness of 5 nm. The thickness range of the protective layer 28 is about 10 nm from one atomic layer (0.2 nm) as a guide, and if the critical film thickness is exceeded, the crystal is broken and causes a leak current.

Therefore, in this step, even if the lattice constant of the protective layer 28 deviates from each of the lattice constants of the n-type lower portion 26 and the p-type upper portion 27, the protective layer 28 is placed on the side surface 26a of the n-type lower portion 26 and the p-type upper portion 27. Can be grown on each of the sides 27a of the.

FIG. 24 is a cross-sectional view taken along a plane parallel to the substrate surface of the structure obtained in this step. FIG. 24 (a) shows the structure of the part in line III-III of FIG. 8, and FIG. 24 (b) shows the structure of the part in line IV-IV of FIG.

By performing the step of FIG. 8, the side surface 26a of the n-shaped lower portion 26 is covered with the protective layer 28 as shown in FIG. 24 (a). Further, as shown in FIG. 24 (b), the side surface 27a of the p-shaped upper portion 27 is also covered with the protective layer 28.

In this way, the entire side surface 25a of the nanowire 25 is covered with the protective layer 28.

Then, the substrate 20 is taken out from the above chamber.

Next, the process shown in FIG. 9 will be described.

As shown in FIG. 9, on the surface of the catalyst 24a, the entire surface of the protective layer 28, and the mask layer 22, an Al ₃ O ₂ layer of several nm is formed as a moisture-preventing insulating layer 29 by the ALD method without using plasma. Form to thickness.

The _{growth gas for forming the Al 3} O ₂ layer is not particularly limited. _{For example, trimethylaluminum ((CH 3} ) ₃ Al) can be used as the raw material gas for Al, and _{water vapor (H 2} O) can be used as the oxidizing agent.

Further, by using the ALD method that does not use plasma in this way, it is possible to avoid damaging the nanowire 25 due to plasma.

Instead of the Al ₃ O _{2 layer, a SiO 2} layer or a SiN layer may be formed as the moisture-preventing insulating layer 29 by the ALD method. However, _{even when forming a SiO 2} layer or a SiN layer, it is preferable to use the ALD method that does not use plasma in order to avoid damage caused by plasma.

Next, as shown in FIG. 10, a photoresist is applied to the entire upper surface of the substrate 20 and exposed and developed to form a second resist layer 30 having an opening 30a.

Subsequently, as shown in FIG. 11, by dry etching the moisture-preventing insulating layer 29 and the mask layer 22 while using the second resist layer 30 as a mask, the contact layer 21 is attached to each of the layers 29 and 22. It forms openings 29b and 22b that are partially exposed.

The etching gas used in the dry etching is not particularly limited, but for example, _{a gas containing fluorine such as CF 4} can be used as the etching gas.

Next, as shown in FIG. 12, a metal laminated film 31 is formed on the second resist layer 30 and on the contact layer 21 in the openings 29b and 22b by a thin-film deposition method.

The metal laminated film 31 is, for example, a laminated film in which an AuGe layer having a thickness of about 30 nm and an Au layer having a thickness of about 300 nm are laminated in order from the bottom.

Subsequently, as shown in FIG. 13, by removing the second resist layer 30 with an organic solvent, the metal laminated film 31 formed in the openings 29b and 22b is left on the contact layer 21 as the cathode electrode 31a. ..

Further, by heat-treating the cathode electrode 31a, the cathode electrode 31a is brought into ohmic contact with the contact layer 21.

Next, as shown in FIG. 14, BCB is applied as a resin material to the entire upper surface of the substrate 20, and the resin is heated and heat-cured to completely embed the resin film as the covering insulating film 32. Form to a certain thickness.

The material of the covering insulating film 32 is not particularly limited. For example, polyimide or SOG (Spin on Glass) may be used instead of BCB.

However, considering the use of high-frequency radio waves in the compound semiconductor device, the material of the coated insulating film 32 is preferably a material having a low dielectric constant that shortens the signal delay time.

Subsequently, as shown in FIG. 15, the moisture-preventing insulating film 29 is exposed by etching back the upper surface 32b of the coated insulating film 32.

The etching gas used in the etching back is not particularly limited, but for example, a mixed gas of a gas containing fluorine such as _{CF 4} capable of etching _{Al 2} O _{3 and an O 2} gas is used as the etching gas.

Thereby, in this step, a part of the upper side of the moisture-preventing insulating layer 29 is also removed.

In this way, the catalyst 24a and the upper surface 28b of the protective layer 28 are exposed on the upper surface 32b of the coated insulating film 32.

On the other hand, the side surface 28a of the protective layer 28 remains covered with the moisture-preventing insulating layer 29.

Next, as shown in FIG. 16, a photoresist is applied to the entire upper surface of the substrate 20, and by exposing and developing the photoresist, a third resist layer 33 having an opening 33a containing nanowires 25 is formed inside the photoresist layer 33. Form.

Subsequently, as shown in FIG. 17, a metal laminated film 34 is formed on the third resist layer 33 and in the opening 33a thereof by a thin-film deposition method.

The metal laminated film 34 is, for example, a laminated film in which an AuZn layer having a thickness of about 30 nm and an Au layer having a thickness of about 300 nm are laminated in this order from the bottom, and covers the catalyst 24a.

Next, as shown in FIG. 18, by removing the third resist layer 33 with an organic solvent, the metal laminated film 34 formed in the opening 33a of the third resist layer 33 is used as the anode electrode 34a for coating insulation. Leave on the membrane 32.

Further, by heat-treating the anode electrode 34, the catalyst 24a on the nanowire 25 is alloyed with the anode electrode 34a and integrated, and the anode electrode 34a is brought into ohmic contact with the p-type upper portion 27 of the nanowire 25.

Next, as shown in FIG. 19, a photoresist is applied to the entire upper surface of the substrate 20 and exposed and developed to form a fourth resist layer 35 having an opening 35a above the cathode electrode 31a. do.

Subsequently, as shown in FIG. 20, the contact hole 32a in which a part of the cathode electrode 31a is exposed is provided in the coating insulating film 32 by dry etching the covering insulating film 32 while using the fourth resist layer 35 as a mask. Form.

The etching gas used in the dry etching is not particularly limited, but for example, the same etching gas as the etching gas used in the above-mentioned etch back may be used.

After that, the fourth resist layer 35 is removed.

Next, a barrier metal film (not shown) is formed on the covering insulating film 32 and on the inner wall of the contact hole 32a. Subsequently, as shown in FIG. 21, a photoresist layer 36 is provided with an opening 36a including a contact hole 32a inside by applying a photoresist on the entire upper surface of the substrate 20 and exposing and developing the photoresist. To form.

Subsequently, as shown in FIG. 22, an Au film 37 in which the inner wall of the opening 36a of the fifth resist layer 36 and the contact hole 32a are embedded is formed by an electrolytic plating method using a barrier metal film as a seed layer.

Next, as shown in FIG. 23, the Au film 37 formed in the opening 36a of the fifth resist layer 36 by removing the fifth resist layer 36 with an organic solvent is used as a drawing electrode 37a as a covering insulating film. Leave on top of 32. Then, an extra seed layer (not shown) is removed.

As described above, the basic structure of the compound semiconductor device 40 according to the present embodiment is completed.

25 (a) to 25 (c) are diagrams showing the energy band of the nanowire 25 in the compound semiconductor device 40.

Note that FIG. 25 (a) shows an energy band in an equilibrium state, FIG. 25 (b) shows an energy band when a voltage in the opposite direction is applied to the nanowire 25, and FIG. 25 (c) shows the nanowire 25. The energy band when a forward voltage is applied to.

In the present embodiment, the concentration of the n-type impurity of InAs, which is the lower part of the n-type 26, is adjusted in the step of FIG. 7, and the concentration of the p-type impurity of GaAsSb, which is the upper part of the p-type 27, is adjusted.

As a result, as shown in FIG. 25 (a), in the n-type lower part 26, the lower end E _{C of the} conduction band almost coincides with the Fermi level E _F in the equilibrium state, and the high-concentration p-type upper part. At 27, the upper end E _V of the valence band is higher than the Fermi level E _F.

Then, as shown in FIG. 25 (b), when a voltage in the opposite direction is applied to the nanowire 25, the portion A in which the energy band is bent at the interface between the n-type lower portion 26 and the p-type upper portion 27 becomes thin.

Therefore, the electrons in the valence band of the p-type upper 27 are transported to the conduction band of the n-type lower 26 by interband tunneling, and a current flows.

On the other hand, as shown in FIG. 25 (c), when a forward voltage is applied to the nanowire 25, the electrons in the conduction band of the n-type lower 26 cannot move to the valence band of the p-type upper 27 due to the potential barrier PB. Also, the holes in the valence band of the p-type upper 27 cannot move to the conduction band of the n-type lower 26, and no current flows.

FIG. 26 is a graph showing the current-voltage characteristics of the nanowire 25.

In this way, the nanowire 25 of the present embodiment operates as a backward diode as shown in FIG. 26.

FIG. 27 (a) is a diagram showing the energy bands of the n-type lower portion 26 and the protective layer 28 of the nanowire 25, and FIG. 27 (b) is a diagram showing the energy bands of the p-type upper portion 27 and the protective layer 28. ..

According to the present embodiment, the InAs which becomes the n-type lower part 26 is doped with the n-type impurity in the step of FIG. 7, the p-type impurity is doped into the GaAsSb which becomes the p-type upper part 27, and the nanowire is further doped in the step of FIG. The entire side surface 25a of the 25 is covered with the protective layer 28 of the i-type semiconductor.

In this way, as shown in FIG. 27 (a), the lower end E _{C of the conduction band of the protective layer 28 is made higher than the lower end E C} of the conduction band of the n-type lower 26, and as shown in FIG. 27 (b). _{The upper end E V} of the valence band of the protective layer 28 is lower than _{the upper end E V} of the valence band of the p-type upper 27.

As a result, when a forward voltage is applied to the nanowire 25, the electrons in the conduction band of the n-type lower 26 can move to the valence band of the p-type upper 27 without overcoming the potential barrier PB of the protective layer 28. It disappears. Further, the holes in the valence band of the p-type upper part 27 do not get over the potential barrier PB due to the protective layer 28 and cannot move to the conduction band of the n-type lower part 26.

Therefore, it is possible to suppress the leakage current flowing inside the nanowire 25 that occurs when a forward voltage is applied to the nanowire 25.

Further, according to the present embodiment, as described above, the entire side surface 25a of the nanowire 25 is covered with the protective layer 28, so that even if an oxidizing agent such as water vapor is used in the step of FIG. 9, the oxidizing agent can be used. Moisture and oxygen can be prevented from entering the side surface 25a of the nanowire 25.

As a result, the side surface 26a of the n-type lower part 26 and the side surface 27a of the p-type upper part 27 are not oxidized, and conductive oxides such as In oxide and Sb oxide are formed on these side surfaces 26a and 27a. Can be suppressed.

Moreover, since the protective layer 28 is made of i-type GaAs, the protective layer 28 itself does not become a conductive oxide even if it is oxidized by the oxidizing agent.

As a result, on the side surface 25a of the nanowire 25, it is possible to prevent the n-type lower portion 26 and the p-type upper portion 27 from being electrically connected by the conductive oxide.

Therefore, it is possible to suppress the leakage current flowing through the side surface 25a of the nanowire 25, which is generated when a forward voltage is applied to the nanowire 25.

In particular, since the nanowire 25 is greatly affected by the leak current flowing through the side surface 25a due to its fineness, it is effective to suppress the generation of this leak current.

Further, according to the present embodiment, since the nanowires 25 and the protective layer 28 are continuously formed in the same chamber, the substrate 20 is in the atmosphere between the formation of the nanowires 25 and the formation of the protective layer 28. Not exposed to.

This makes it possible to further suppress the formation of conductive oxides on the side surface 25a of the nanowire 25.

In this way, in the present embodiment, the leakage current flowing through the side surface 25a of the nanowire 25 can be suppressed, so that the original electrical conduction characteristics of the nanowire 25 that the diode detection sensitivity and the power conversion efficiency are excellent are maintained. be able to.

(Second Embodiment)
In the first embodiment, the protective layer 28 is formed on both the side surface 26a of the n-type lower portion 26 and the side surface 27a of the p-type lower portion 27, but in the present embodiment, the protective layer is formed on only one of these side surfaces. do.

28 to 32 are cross-sectional views of the compound semiconductor device according to the present embodiment during manufacturing. In FIGS. 28 to 32, the same elements as those in the first embodiment are designated by the same reference numerals as those in the first embodiment, and the description thereof will be omitted below.

First, by performing the steps of FIGS. 4 to 6 of the first embodiment, as shown in FIG. 28, a catalyst 24a for forming nanowires was formed on the contact layer 21 in the opening 22a of the mask layer 22. Get the structure.

Next, the process shown in FIG. 29 will be described.

First, the catalyst 24a is liquefied by placing the substrate 20 in a chamber (not shown) and raising the substrate temperature to about 400 ° C.

Then, by supplying a growth gas for InAs into the chamber, the contact layer 21 is used as a seed crystal, and the InAs crystal is grown upward from the contact layer 21 by the VLS method using the liquefied catalyst 24a as a solvent. Let me.

As the growth gas for InAs, for example, triethylindium can be used as the raw material gas for In and arsine can be used as the raw material gas for As as in the first embodiment. Further, the InAs is doped with Si as an n-type impurity at a concentration of about ^{1 × 10 17} cm ^-3.

Further, the substrate temperature at which InAs is grown is also set to, for example, 500 ° C. as in the first embodiment.

On the other hand, among the above-mentioned growth gases for InAs, the flow rate of the raw material gas of In of the group III atom is the same as that of the first embodiment, and the flow rate of the raw material gas of As of the group V atom is smaller than that of the first embodiment. By doing so, the flow rate ratio between the raw material gas of In and the raw material gas of As is changed.

As a result, the InAs of the first embodiment has a sphalerite-type crystal structure, whereas the InAs of the present embodiment has a wurtzite-type crystal structure.

In this way, a linear body of n-type InAs is formed on the contact layer 21 as the n-type lower portion 46 of the nanowire 45. The size of the linear body of this InAs is the same as that of the first embodiment, for example, the width is 80 nm and the length is 0.5 to 1 μm.

On the other hand, unlike the first embodiment, the side surface of the linear body of InAs has a wurtzite-type crystal structure, so that the unevenness is reduced and the side surface is relatively flat.

Subsequently, by stopping the supply of the growth gas for InAs and supplying the growth gas for GaAsSb into the chamber, the above-mentioned liquefied catalyst 24a is used as a solvent in the VLS method from the n-type lower portion 46 to the GaAsSb. Grow the crystals upwards.

As for the growth gas for GaAsSb, for example, triethylgallium is used as the raw material gas for Ga, arsine (AsH ₃ ) is used as the raw material gas for As, and trimethylantimony is used as the raw material gas for Sb. Can be. Further, the GaAsSb is doped with Zn as a p-type impurity at a concentration of about ^{1 × 10 18} cm ^-3.

Further, the substrate temperature at which GaAsSb is grown is also set to, for example, 500 ° C. as in the first embodiment.

Furthermore, the flow rate ratio of the Ga raw material gas of the Group III atom and the raw material gas of Sb of the V group atom in the above-mentioned growth gas for GaAsSb is also the same as in the first embodiment. As a result, the GaAsSb of the present embodiment has a sphalerite-type crystal structure as in the first embodiment.

In this way, a high-concentration p-type GaAsSb striatum is formed on the n-type lower portion 46 as the p-type upper portion 47. The size of the linear body of the GaAsSb is the same as that of the first embodiment, for example, the width is 80 nm and the length is 0.5 to 1 μm.

Further, the side surface of the linear body of the GaAsSb has a large number of irregularities by forming a sphalerite-type crystal structure as in the first embodiment.

As described above, a pn junction is formed in which the n-type lower portion 46 and the p-type upper portion 47 are joined to the nanowire 45.

After that, the supply of the growth gas for GaAsSb is stopped.

Next, the process shown in FIG. 30 will be described.

The above chamber will continue to be used, the substrate temperature will be lowered from 500 ° C to 400 ° C, and the same growth gas for i-type GaAs as in the first embodiment will be supplied into this chamber.

As a result, among the side surfaces 45a of the nanowire 45, i-type GaAs crystals are grown from the side surface 47a of the p-type upper portion 47 of the sphalerite-type crystal structure having many irregularities in the direction parallel to the substrate surface, and the protective layer 28 is formed. Form an i-type GaAs layer.

The protective layer 28 is formed to have a thickness equal to or less than the critical film thickness, for example, a thickness of 5 nm.

Therefore, in this step, even if the lattice constant of the protective layer 28 deviates from the lattice constant of the p-type upper portion 47, the protective layer 28 can be grown on the side surface 47a of the p-type upper portion 47.

On the other hand, on the side surface 46a of the n-type lower portion 46 of the wurtzite-type crystal structure having few irregularities, the i-type GaAs crystal is difficult to grow in the direction parallel to the substrate surface. Therefore, i-type GaAs crystals hardly grow from the side surface 46a of the n-type lower portion 46.

FIG. 33 is a cross-sectional view taken along a plane parallel to the substrate surface of the structure obtained in this step. 33 (a) shows the structure of the portion on the VV line of FIG. 30, and FIG. 33 (b) shows the structure of the portion on the VI-VI line of FIG. 30.

By performing the step of FIG. 30, the side surface 47a of the p-shaped upper portion 47 is covered with the protective layer 28 as shown in FIG. 33 (b). On the other hand, as shown in FIG. 33A, the side surface 46a of the n-type lower portion 46 is exposed without being covered with the protective layer 28.

In this way, only the side surface 47a of the p-shaped upper portion 47 of the side surface 45a of the nanowire 45 is covered with the protective layer 28.

Then, the substrate 20 is taken out from the above chamber.

Next, the process shown in FIG. 31 will be described.

As shown in FIG. 31, moisture prevention insulation is performed on the surface of the catalyst 24a, the entire surface of the protective layer 28 including the side surface 28a, the side surface 46a of the n-type lower portion 46, and the mask layer 22 by the ALD method without using plasma. As the layer 29, an Al ₃ O ₂ layer is formed to a thickness of several nm.

As _{the growth gas for forming the Al 3} O ₂ layer, for example, trimethylaluminum can be used as the raw material gas for Al, and water vapor can be used as the oxidizing agent, as in the first embodiment.

Instead of the Al ₃ O _{2 layer, a SiO 2} layer or a SiN layer may be formed as the moisture-preventing insulating layer 29 by the ALD method that does not use plasma.

After that, by performing the steps of FIGS. 10 to 23 described in the first embodiment, as shown in FIG. 32, the basic structure of the compound semiconductor device 50 according to the present embodiment is completed.

According to the present embodiment described above, since the side surface 47a of the p-type upper portion 47 of the side surface 45a of the nanowire 45 is covered with the protective layer 28, it is assumed that an oxidizing agent such as water vapor is used in the step of FIG. 31. Also, it is possible to prevent the moisture and oxygen of the oxidizing agent from entering the side surface 47a of the p-type upper portion 47.

As a result, the side surface 47a of the p-type upper portion 47 is not oxidized, and it is possible to suppress the formation of a conductive oxide such as the oxide of Sb on the side surface 47a.

On the other hand, since the side surface 46a of the n-type lower portion 46 is not covered with the protective layer 28, the side surface 46a of the n-type lower portion 46 is oxidized by the oxidizing agent, and the side surface 46a is conductive like an oxide of In. Oxides can form.

However, since the conductive oxide is not formed on the side surface 47a of the p-type upper portion 47, the n-type lower portion 46 and the p-type upper portion 47 are electrically connected by the conductive oxide on the side surface 45a of the nanowire 45. Can be suppressed.

Therefore, it is possible to suppress the leakage current flowing through the side surface 45a of the nanowire 45, which is generated when a forward voltage is applied to the nanowire 45.

Further, according to the present embodiment, since the nanowires 45 and the protective layer 28 are continuously formed in the same chamber, the substrate is exposed to the atmosphere between the formation of the nanowires 45 and the formation of the protective layer 28. Not exposed.

As a result, it is possible to further suppress the formation of the conductive oxide on the side surface 45a of the nanowire 45.

In this way, also in this embodiment, it is possible to maintain the original electrical conduction characteristics of the nanowire 45, which is that the detection sensitivity and the power conversion efficiency of the diode are excellent as in the first embodiment.

In this embodiment, the case where only the side surface 47a of the p-type upper portion 47 of the side surface 45a of the nanowire 45 is covered with the protective layer 28 has been described as an example, but only the side surface 46a of the n-type lower portion 46 is covered with the protective layer 28. You may cover it.

When only the side surface 46a of the n-type lower portion 46 is covered with the protective layer 28, the flow rate of the In raw gas of the Group III atom and the raw material gas of As of the V group atom in the growth gas for InAs in the step of FIG. The ratio is the same as in the first embodiment, and InAs, which is the n-type lower portion 46, has a sphalerite-type crystal structure.

On the other hand, among the growth gases for GaAsSb, the flow rate of the raw material gas of Ga of the group III atom is the same as that of the first embodiment, and the flow rate of the raw material gas of Sb of the group V atom is smaller than that of the first embodiment. Change the flow rate ratio between the raw material gas of Ga and the raw material gas of As and Sb.

In this way, the GaAsSb that becomes the p-type upper portion 47 is formed into a wurtzite-type crystal structure.

As a result, in the process of FIG. 30, i-type GaAs crystals grow from the side surface 46a of the n-type lower portion 46 of the sphalerite-type crystal structure having many irregularities in the direction parallel to the substrate surface, while wurtzite has few irregularities. The i-type GaAs crystal hardly grows from the side surface 47a of the p-type upper portion 47 of the ore-type crystal structure.

In this way, only the side surface 46a of the n-shaped lower portion 46 of the side surface 45a of the nanowire 45 is covered with the protective layer 28.

The method of changing the crystal structure from the sphalerite type to the wurtzite type is to use the raw material gas of the group III atom and the raw material gas of the group V atom in either the growth gas for InAs or the growth gas for GaAsSb described above. It is not limited to changing the flow rate ratio of.

For example, by increasing the total flow rate of the raw material gas of the group III atom and the raw material gas of the group V atom without changing the flow rate ratio of these raw material gases, the growth rate of either InAs or GaAsSb should be increased. You may do it.

Even in this way, the crystal structure of either InAs or GaAsSb can be changed from the sphalerite type to the wurtzite type.

(Third Embodiment)
In this embodiment, a protective layer is formed on the side surface of the nanowire by a method different from that of the first embodiment and the second embodiment.

34 to 38 are cross-sectional views of the compound semiconductor device according to the present embodiment during manufacturing. In FIGS. 34 to 38, the same elements as those in the first embodiment are designated by the same reference numerals as those in the first embodiment, and the description thereof will be omitted below.

First, by performing the steps of FIGS. 4 to 6 of the first embodiment, as shown in FIG. 34, a catalyst 24a for forming nanowires was formed on the contact layer 21 in the opening 22a of the mask layer 22. Get the structure.

Next, the process shown in FIG. 35 will be described.

First, the catalyst 24a is liquefied by placing the substrate 20 in a chamber (not shown) and raising the substrate temperature to about 400 ° C.

Then, by supplying a growth gas for InAs into the chamber, the contact layer 21 is used as a seed crystal, and the InAs crystal is grown upward from the contact layer 21 by the VLS method using the liquefied catalyst 24a as a solvent. Let me.

As the growth gas for InAs, for example, triethylindium can be used as the raw material gas for In and arsine can be used as the raw material gas for As as in the first embodiment. Further, the InAs is doped with Si as an n-type impurity at a concentration of about ^{1 × 10 17} cm ^-3.

Further, the substrate temperature when growing InAs is, for example, 500 ° C. as in the first embodiment.

On the other hand, among the above-mentioned growth gases for InAs, the flow rate of the raw material gas of In of the group III atom is the same as that of the first embodiment, and the flow rate of the raw material gas of As of the group V atom is smaller than that of the first embodiment. By doing so, the flow rate ratio between the raw material gas of In and the raw material gas of As is changed.

As a result, the InAs of the present embodiment has a wurtzite-type crystal structure unlike the first embodiment.

In this way, a linear body of n-type InAs is formed on the contact layer 21 as the n-type lower portion 46 of the nanowire 45. The size of the linear body of this InAs is the same as that of the first embodiment, for example, the width is 80 nm and the length is 0.5 to 1 μm.

Subsequently, by stopping the supply of the growth gas for InAs and supplying the growth gas for GaAsSb into the chamber, the above-mentioned liquefied catalyst 24a is used as a solvent in the VLS method from the n-type lower portion 46 to the GaAsSb. Grow the crystals upwards.

As for the growth gas for GaAsSb, for example, triethylgallium is used as the raw material gas for Ga, arsine (AsH ₃ ) is used as the raw material gas for As, and trimethylantimony is used as the raw material gas for Sb. Can be. Further, the GaAsSb is doped with Zn as a p-type impurity at a concentration of about ^{1 × 10 18} cm ^-3.

Further, the substrate temperature at which GaAsSb is grown is also set to, for example, 500 ° C. as in the first embodiment.

Furthermore, the flow rate ratio of the Ga raw material gas of the Group III atom and the raw material gas of Sb of the V group atom in the above-mentioned growth gas for GaAsSb is also the same as in the first embodiment.

As a result, the GaAsSb of the present embodiment has a sphalerite-type crystal structure as in the first embodiment.

In this way, a high-concentration p-type GaAsSb striatum is formed on the n-type lower portion 46 as the p-type upper portion 47. The size of the linear body of the GaAsSb is the same as that of the first embodiment, for example, the width is 80 nm and the length is 0.5 to 1 μm.

As described above, a pn junction is formed in which the n-type lower portion 46 and the p-type upper portion 47 are joined to the nanowire 45.

Next, the process shown in FIG. 36 will be described.

The above chamber will continue to be used, and the supply of the Sb raw material gas among the growth gases for GaAsSb and the organometallic gas for doping Zn will be stopped, and the substrate temperature will be lowered from 500 ° C. to 400 ° C.

As a result, among the side surfaces 45a of the nanowire 45, i-type GaAs crystals are grown from the side surface 47a of the p-type upper portion 47 of the sphalerite-type crystal structure having many irregularities in the direction parallel to the substrate surface, and the protective layer 58 is formed. Form an i-type GaAs layer.

The protective layer 58 is formed to have a thickness equivalent to several atomic layers.

As a result, in this step, even if the lattice constant of the protective layer 58 deviates from the lattice constant of the p-type upper portion 47, it is sufficiently thinner than the critical film thickness, so that the protective layer 58 is grown on the side surface 47a of the p-type upper portion 47. be able to.

FIG. 39 is a cross-sectional view taken along a plane parallel to the substrate plane of the structure obtained in this step. 39 (a) shows the structure of the portion of line VII-VII of FIG. 36, and FIG. 39 (b) shows the structure of the portion of line VIII-VIII of FIG.

By performing the step of FIG. 36, the side surface 47a of the p-shaped upper portion 47 is covered with the protective layer 58 as shown in FIG. 39 (b). On the other hand, as shown in FIG. 39 (a), the side surface 46a of the n-type lower portion 46 is exposed without being covered with the protective layer 58.

In this way, only the side surface 47a of the p-shaped upper portion 47 of the side surface 45a of the nanowire 45 is covered with the protective layer 58.

Then, the substrate 20 is taken out from the above chamber.

Next, the process shown in FIG. 37 will be described.

As shown in FIG. 37, moisture prevention insulation is performed by the ALD method without using plasma on the surface of the catalyst 24a, the entire surface of the protective layer 58 including the side surface 58a, the side surface 46a of the n-type lower portion 46, and the mask layer 22. As the layer 29, an Al ₃ O ₂ layer is formed to a thickness of several nm.

As _{the growth gas for forming the Al 3} O ₂ layer, for example, trimethylaluminum can be used as the raw material gas for Al, and water vapor can be used as the oxidizing agent, as in the first embodiment.

Instead of the Al ₃ O _{2 layer, a SiO 2} layer or a SiN layer may be formed as the moisture-preventing insulating layer 29 by the ALD method that does not use plasma.

After that, by performing the steps of FIGS. 10 to 23 described in the first embodiment, as shown in FIG. 38, the basic structure of the compound semiconductor device 60 according to the present embodiment is completed.

According to the present embodiment described above, since the side surface 47a of the p-type upper portion 47 of the side surface 45a of the nanowire 45 is covered with the protective layer 58, it is assumed that an oxidizing agent such as water vapor is used in the step of FIG. 37. Also, it is possible to prevent the moisture and oxygen of the oxidizing agent from entering the side surface 47a of the p-type upper portion 47.

As a result, the side surface 47a of the p-type upper portion 47 is not oxidized, and it is possible to suppress the formation of a conductive oxide such as an oxide of Sb on the side surface 47a.

Moreover, since the protective layer 58 is made of i-type GaAs, the protective layer 58 itself does not become a conductive oxide even if it is oxidized by the oxidizing agent.

On the other hand, the side surface 46a of the n-shaped lower portion 46 is not covered with the protective layer 58.

However, since the conductive oxide is not formed on the side surface 47a of the p-type upper portion 47, the n-type lower portion 46 and the p-type upper portion 47 are electrically connected by the conductive oxide on the side surface 45a of the nanowire 45. Can be suppressed.

Therefore, it is possible to suppress the leakage current flowing through the side surface 45a of the nanowire 45, which is generated when a forward voltage is applied to the nanowire 45.

Further, according to the present embodiment, since the nanowires 45 and the protective layer 58 are continuously formed in the same chamber, the substrate 20 is in the atmosphere between the formation of the nanowires 45 and the formation of the protective layer 58. Not exposed to.

As a result, it is possible to further suppress the formation of the conductive oxide on the side surface 45a of the nanowire 45.

As described above, also in this embodiment, it is possible to maintain the original electrical conduction characteristics of the nanowire 45, which is that the detection sensitivity and the power conversion efficiency of the diode are excellent as in the first embodiment.

By the way, in the above-described embodiment, the protective layer 58 is formed of an i-type semiconductor containing As like i-type GaAs.

When the p-type upper portion 45 is formed of p-type GaAsSb, the raw material gas of Sb among the growth gases for GaAsSb and the organic for doping Zn are formed in the step of FIG. 36 for forming the protective layer 58. The supply of metal gas is stopped.

On the other hand, for example, when the upper part of the p-type is formed of the p-type GaSb described later, in the step of FIG. 36 for forming the protective layer 58, the raw material gas of Sb among the growth gases for GaSb and Zn are doped. The supply of organometallic gas for this purpose may be stopped and arsine (AsH ₃ ) may be supplied as a raw material gas for As.

Further, in the above-described embodiment, the case where only the side surface 47a of the p-type upper portion 47 of the side surface 45a of the nanowire 45 is covered with the ultrathin protective layer 58 has been described as an example, but the side surface 46a of the n-type lower portion 46 has been described. Only may be covered with an ultrathin protective layer 58.

When only the side surface 46a of the n-type lower portion 46 is covered with the ultrathin protective layer 58, the InAs of the n-type lower portion 46 is formed into a sphalerite-type crystal structure and the GaAsSb of the p-type upper portion 47 is formed in the step of FIG. It may have a wurtzite-type crystal structure.

Furthermore, as in the first embodiment, both the side surface 26a of the n-type lower part 26 and the side surface 27a of the p-type upper part 27, that is, the entire side surface 25a of the nanowire 25 may be covered with the ultrathin protective layer 58. ..

When the entire side surface 25a of the nanowire 25 is covered with an ultrathin protective layer 58, if both InAs at the lower part of the n-type and GaAsSb at the upper part of the p-type are formed into a sphalerite-type crystal structure in the step of FIG. good.

In the first to third embodiments described above, the n-type lower parts 26 and 46 of the nanowires 25 and 45 operating as backward diodes are formed of n-type InAs, and the p-type upper parts 27 and 47 are formed of p-type GaAsSb. The case of doing this was explained as an example.

However, the materials of the n-type lower part 26, 46 and the p-type upper part 27, 47 are not limited to this.

For example, the n-type lower portion may be formed of n-type InGaAs as an n-type III-V group compound semiconductor containing In. Further, the upper part of p-type may be formed of p-type GaSb or p-type AlGaSb as a p-type III-V compound semiconductor containing Sb.

Further, the case where the concentration of impurities in the p-type upper parts 27 and 47 among the n-type lower parts 26 and 46 and the p-type upper parts 27 and 47 of the nanowires 25 and 45 is made high is described as an example. The concentration of impurities in the lower portions 26 and 46 may be increased.

Further, in the first embodiment and the second embodiment, the case where the protective layers 28 and 58 are formed of i-type GaAs crystals has been described as an example, but even if they are oxidized in the same manner as i-type GaAs crystals, they are electrically conductive. The protective layer may be formed of i-type GaN, GaP, InP, or InGaP crystals that do not become a substance.

(Fourth Embodiment)
In this embodiment, a power conversion device using the compound semiconductor device manufactured in the first to third embodiments will be described.

FIG. 40 is a circuit diagram of the power conversion device.

As shown in FIG. 40, the power conversion device 70 includes an antenna 71, a matching circuit 72, a power conversion element 73 which is one of the compound semiconductor devices manufactured in the first to third embodiments, and a booster circuit 74. And a capacitor 75.

Of these, the matching circuit 72 matches the impedance of a high-frequency radio wave RF such as a microwave received by the antenna 71.

The power conversion element 73 includes nanowires 25 and 45 that operate as the backward diode described above.

In the nanowires 25 and 45, the n-type lower portions 26 and 46 are connected to the matching circuit 72 via the contact layer 21, the cathode electrode 31a, and the lead-out wiring 37a. On the other hand, the p-type upper parts 27 and 47 are grounded via the anode electrode 34a.

In this way, the power conversion element 73 inputs the impedance-matched radio wave in the matching circuit 72, and converts it into a DC voltage by the nanowires 25 and 45.

The booster circuit 74 boosts the voltage converted by the power conversion element 73. Then, the charge of the boosted voltage is temporarily stored in the capacitor 75 as electric power.

Then, the power conversion device 70 supplies the power stored in this way to an external device 77, for example, a temperature sensor or a humidity sensor having a communication function that can be connected to the Internet.

According to the present embodiment described above, since the power conversion element 73 includes nanowires 25 and 45 having excellent power conversion efficiency, the radio waves are efficiently converted into electric power even if there is only weak radio waves in the surrounding environment. can do.

Therefore, it is possible to provide the power conversion device 70 capable of driving the above-mentioned device 77 even in an environment without a power transmission facility.

In this embodiment, the case where the power conversion device 70 is provided with one power conversion element 73 has been described as an example, but a plurality of power conversion elements 73 may be provided. As a result, the power converter 70 can store a larger amount of electric power.

In a power conversion device including a plurality of power conversion elements 73, a plurality of nanowires 25 and 45 are formed on one substrate 20, and the side surfaces 25a and 45a of the plurality of nanowires 25 and 45 are protected layers 28 and 58. You can cover it with.

Further, in the present embodiment, the case where the compound semiconductor devices 40, 50, and 60 manufactured in the first to third embodiments are applied to the power conversion element 73 of the power conversion device 70 has been described as an example. The compound semiconductor devices 40, 50, and 60 of the above may be applied to the detection element of the receiving device.

According to the receiving device applied in this way, since the detection element includes nanowires 25 and 45 having excellent detection sensitivity, sufficient detection characteristics can be obtained even for weak radio waves.

(Other embodiments)
In the first to third embodiments described above, the compound semiconductor devices 40, 50, 60 provided with the nanowires 25, 45 operating as the backward diode have been described as an example, but the diode operating with the nanowires 25, 45 has been described. The type of is not limited to this.

In this embodiment, variations of the compound semiconductor device will be described.

<Esaki diode>
The Esaki diode of this example is a tunnel diode like the backward diode, but unlike the backward diode, both the n-type lower part and the p-type upper part are heavily doped with impurities.

FIG. 41 is a cross-sectional view showing an example of the structure of a compound semiconductor device including nanowires that operate as the esaki diode. In FIG. 41, the same elements as those in the first embodiment are designated by the same reference numerals as those in the first embodiment, and the description thereof will be omitted below.

As shown in FIG. 41, in the compound semiconductor device 85 of this example, the nanowire 81 operating as an esaki diode has an n-type lower portion 82 of a high-concentration n-type semiconductor and a p-type upper portion 83 of a high-concentration p-type semiconductor.

The material of the n-type lower part 82 is n-type InGaAs, and the material of the p-type upper part 83 is p-type GaAsSb. As described above, the Esaki diode of this example is a heterojunction.

FIG. 42 is a diagram showing an energy band of nanowires when the Esaki diode is heterojunction.

As shown in FIG. 42, in the equilibrium state, the lower end E _{C of the} conduction band is lower than the Fermi level E _{F in the n-type lower part 82, and the upper end E V of the} valence band is in the p-type upper part 83. It is higher than the Fermi level E _F.

As shown in FIG. 41, also in the compound semiconductor device 85 of this example, the entire side surface 81a of the nanowire 81 is covered with the protective layer 28 of the i-type GaAs crystal as in the first embodiment.

As a result, on the side surface 81a of the nanowire 81, it is possible to suppress the electrical connection between the n-type lower portion 82 and the p-type upper portion 83 by conductive oxides such as In oxide and Sb oxide. can.

Therefore, it is possible to suppress the leakage current flowing through the side surface 81a of the nanowire 81, which is generated when a voltage is applied to the nanowire 81.

The Esaki diode is not limited to the heterojunction.

FIG. 43 is a cross-sectional view showing another example of the structure of a compound semiconductor device including nanowires operating as an esaki diode. In FIG. 43, the same elements as those in the first embodiment are designated by the same reference numerals as those in the first embodiment, and the description thereof will be omitted below.

As shown in FIG. 43, in the compound semiconductor device 90 of this example, the nanowire 86 operating as an esaki diode has the same as the nanowire 85 described above, that is, the n-type lower portion 87 of the high-concentration n-type semiconductor and the p of the high-concentration p-type semiconductor. It has a mold upper 88.

On the other hand, unlike the nanowire 85, the material of the n-type lower portion 87 is n-type InGaAs, and the material of the p-type upper portion 88 is p-type InGaAs. As described above, the Esaki diode of this example is homozygous.

FIG. 44 is a diagram showing an energy band of nanowires when the Esaki diode is homozygous.

As shown in FIG. 44, in the equilibrium state, the lower end E _{C of the} conduction band is lower than the Fermi level E _{F in the n-type lower 87, and the upper end E V of the} valence band is in the p-type upper 88. It is higher than the Fermi level E _F.

As shown in FIG. 43, also in the compound semiconductor device 90 of this example, the entire side surface 86a of the nanowire 86 is covered with the protective layer 28 of the i-type GaAs crystal as in the first embodiment.

As a result, on the side surface 86a of the nanowire 86, it is possible to prevent the n-type lower portion 87 and the p-type upper portion 88 from being electrically connected by a conductive oxide such as an oxide of In.

Therefore, it is possible to suppress the leakage current flowing through the side surface 86a of the nanowire 86, which is generated when a voltage is applied to the nanowire 86.

<Normal diode>
The normal diode in this example means a diode that is not a tunnel diode.

Unlike the backward diode and the Esaki diode, the ordinary diode is doped with impurities at a low concentration in both the n-type lower part and the p-type upper part.

FIG. 45 is a cross-sectional view showing an example of the structure of a compound semiconductor device including nanowires that operate as a normal diode. In FIG. 45, the same elements as those in the first embodiment are designated by the same reference numerals as those in the first embodiment, and the description thereof will be omitted below.

As shown in FIG. 45, in the compound semiconductor device 95 of this example, the nanowire 91 operating as a normal diode has an n-type lower portion 92 of an n-type semiconductor and a p-type upper portion 93 of a p-type semiconductor.

The material of the n-type lower part 92 is n-type InGaAs, and the material of the p-type upper part 93 is p-type GaAsSb. As described above, the diode of this example is a heterojunction.

FIG. 46 is a diagram showing an energy band of nanowires when a normal diode is heterojunction.

As shown in FIG. 46, in the equilibrium state, the lower end E _{C of the} conduction band is higher than the Fermi level E _{F in the n-type lower part 92, and the upper end E V of the} valence band is higher in the p-type upper 93. It is lower than the Fermi level E _F.

As shown in FIG. 45, also in the compound semiconductor device 95 of this example, the entire side surface 91a of the nanowire 91 is covered with the protective layer 28 of the i-type GaAs crystal as in the first embodiment.

As a result, on the side surface 91a of the nanowire 91, it is possible to suppress the electrical connection between the n-type lower portion 92 and the p-type upper portion 93 by conductive oxides such as In oxide and Sb oxide. can.

Therefore, it is possible to suppress the side leakage current flowing through the side surface 91a of the nanowire 91, which is generated when a voltage is applied to the nanowire 91.

The ordinary diode is not limited to the heterojunction.

FIG. 47 is a cross-sectional view showing another example of the structure of a compound semiconductor device including nanowires that operate as a normal diode. In FIG. 47, the same elements as those in the first embodiment are designated by the same reference numerals as those in the first embodiment, and the description thereof will be omitted below.

As shown in FIG. 47, in the compound semiconductor device 100 of this example, the nanowire 96 operating as a normal diode is the n-type lower portion 97 of the n-type semiconductor and the p-type upper portion 98 of the p-type semiconductor, similarly to the nanowire 95 described above. Has.

On the other hand, unlike the nanowire 95, the material of the n-type lower part 97 is n-type InGaAs, and the material of the p-type upper part 98 is p-type InGaAs. As described above, the diode of this example is homozygous.

FIG. 48 is a diagram showing the energy band of nanowires when the diode is homozygous.

As shown in FIG. 48, in the equilibrium state, the lower end E _{C of the} conduction band is higher than the Fermi level E _{F in the n-type lower 97, and the upper end E V of the} valence band is higher in the p-type upper 98. It is lower than the Fermi level E _F.

As shown in FIG. 47, also in the compound semiconductor device 100 of this example, the entire side surface 96a of the nanowire 96 is covered with the protective layer 28 of the i-type GaAs crystal as in the first embodiment.

As a result, on the side surface 96a of the nanowire 96, it is possible to prevent the n-type lower portion 97 and the p-type upper portion 98 from being electrically connected by a conductive oxide such as an oxide of In.

Therefore, it is possible to suppress the side leakage current flowing through the side surface 96a of the nanowire 96, which is generated when a voltage is applied to the nanowire 96.

In the present embodiment described above, the case where InGaAs or GaAsSb is used as the material of the n-type lower part 82, 87, 92, 97 and the p-type upper part 83, 88, 93, 98 has been described as an example. GaAs, InP, GaN, or Si may be used as the material of.

The following additional notes will be further disclosed with respect to each of the above-described embodiments.

(Appendix 1) Board and
A linear compound semiconductor extending upward from the substrate, the linear semiconductor having a lower portion of a first conductive type and an upper portion of a second conductive type extending above the lower portion.
A compound semiconductor device comprising an i-type compound semiconductor crystal protective layer that covers the side surfaces of the linear semiconductor.

(Appendix 2) The first conductive type is n type, and the second conductive type is p type.
Note 1 is characterized in that the lower end of the conduction band of the protective layer is higher than the lower end of the lower conduction band, and the upper end of the valence band of the protective layer is lower than the upper end of the upper valence band. Compound semiconductor device.

(Supplementary Note 3) The compound semiconductor apparatus according to Supplementary note 1 or Supplementary note 2, wherein the protective layer covers both the lower portion and the upper portion of the linear semiconductor.

(Supplementary Note 4) The compound semiconductor apparatus according to Supplementary note 1 or Supplementary note 2, wherein the protective layer covers one of the lower portion and the upper portion of the linear semiconductor.

(Supplementary Note 5) The compound semiconductor device according to any one of Supplementary note 1 to Supplementary note 4, wherein the protective layer is composed of any one of GaN, GaP, GaAs, InP, and InGaP.

(Appendix 6) A plurality of the linear semiconductors extend upward from the substrate.
The compound semiconductor device according to any one of Supplementary note 1 to Supplementary note 5, wherein each side surface of the plurality of linear semiconductors is covered with the protective layer.

(Supplementary Note 7) The compound semiconductor device according to any one of Supplementary note 1 to Supplementary note 6, further comprising a moisture-preventing insulating layer that covers the surface of the protective layer and prevents moisture from entering the protective layer. ..

(Appendix 8) A receiver that receives radio waves and
It has a conversion unit that converts radio waves received by the reception unit into voltage.
The conversion unit
With the board
A linear compound semiconductor extending upward from the substrate, having a lower portion of a first conductive mold into which radio waves are input and an upper portion of a second conductive mold extending above the lower portion. With semiconductors
A receiver characterized by having a protective layer of an i-type compound semiconductor crystal covering the side surface of the linear semiconductor.

(Appendix 9) A step of forming a lower portion of the linear semiconductor on the substrate by linearly growing the first conductive type compound semiconductor from the substrate.
A step of forming an upper portion of the linear semiconductor on the lower portion by linearly growing a second conductive type compound semiconductor from the lower portion.
A method for manufacturing a compound semiconductor device, which comprises a step of growing a protective layer of an i-type compound semiconductor crystal on a side surface of the linear semiconductor.

(Appendix 10) The method for manufacturing a compound semiconductor device according to Appendix 9, wherein in the step of growing the protective layer, the protective layer is grown on both the lower portion and the upper portion of the linear semiconductor.

(Appendix 11) The method for manufacturing a compound semiconductor device according to Appendix 9, wherein in the step of growing the protective layer, the protective layer is grown on one of the lower portion and the upper portion of the linear semiconductor. ..

(Supplementary Note 12) The method for manufacturing a compound semiconductor device according to any one of Supplementary note 9 to Supplementary note 11, wherein in the step of growing the protective layer, the protective layer is made to have a film thickness equal to or less than the critical film thickness. ..

(Supplementary Note 13) The method for manufacturing a compound semiconductor device according to any one of Supplementary note 9 to Supplementary note 12, wherein the protective layer is composed of any one of GaN, GaP, GaAs, InP, and InGaP. ..

(Supplementary note 14) The steps of forming the lower portion of the linear semiconductor, forming the upper portion, and growing the protective layer are performed without exposing the substrate to the atmosphere. The method for manufacturing a compound semiconductor device according to any one of Supplementary note 13.

(Appendix 15) After the step of growing the protective layer,
The compound semiconductor device according to any one of Supplementary note 9 to Supplementary note 14, wherein a step of forming a moisture-preventing insulating layer for preventing the ingress of moisture into the protective layer is provided on the surface of the protective layer. Production method.

(Appendix 16) The method for manufacturing a compound semiconductor device according to Appendix 15, wherein the step of forming the moisture-preventing insulating layer is performed by an ALD (Atomic Layer Deposition) method that does not use plasma.

1,40,50,60,85,90,95,100 ... compound semiconductor device, 2,20 ... substrate, 3,21 ... contact layer, 4,22 ... mask layer, 5,25,45,81,86, 91, 96 ... Nanowires, 5a, 25a, 45a, 81a, 86a, 91a, 96a ... Side surfaces of nanowires, 6,26,46,82,87,92,97 ... n-type lower part, 6a, 26a, 46a, 82a, 87a, 92a, 97a ... n-type lower side surface, 7,27,47,83,88,93,98 ... p-type lower part, 7a, 27a, 47a, 83a, 88a, 93a, 98a ... p-type lower side surface, 28, 58 ... protective layer, 28a, 58a ... side surface of protective layer, 8, 29 ... moisture-preventing insulating layer, 9, 31a ... cathode electrode, 10, 32 ... coated insulating film, 11, 34a ... anode electrode, 70 ... power Conversion device, 71 ... antenna, 73 ... power conversion element.

Claims (12)

With the board
A linear compound semiconductor extending upward from the substrate, the linear semiconductor having a lower portion of a first conductive type and an upper portion of a second conductive type extending above the lower portion.
A protective layer of an i-type compound semiconductor crystal covering the side surface of the linear semiconductor,
Have,
The first conductive type is n-type, and the second conductive type is p-type.
The lower end of the conduction band of the protective layer is higher than the conduction band bottom of the lower, lower it to that of compound wherein the upper end of the upper end of the valence band of the protective layer is the valence band of the upper Semiconductor device. The compound semiconductor device according to claim 1, wherein the protective layer covers both the lower portion and the upper portion of the linear semiconductor. The compound semiconductor device according to claim 1, wherein the protective layer covers one of the lower portion and the upper portion of the linear semiconductor. With the board
A linear compound semiconductor extending upward from the substrate, the linear semiconductor having a lower portion of a first conductive type and an upper portion of a second conductive type extending above the lower portion.
A protective layer of an i-type compound semiconductor crystal covering the side surface of the linear semiconductor,
Have,
The protective layer, characterized in that in said linear semiconductor covering one of the lower and the upper of compound semiconductor devices. The compound semiconductor device according to any one of claims 1 to 4, wherein the protective layer is composed of any one of GaN, GaP, GaAs, InP, and InGaP. With the board
A linear compound semiconductor extending upward from the substrate, the linear semiconductor having a lower portion of a first conductive type and an upper portion of a second conductive type extending above the lower portion.
A protective layer of an i-type compound semiconductor crystal covering the side surface of the linear semiconductor,
Have,
The protective layer is a compound semiconductor device comprising any one of GaN, GaP, GaAs, InP, and InGaP. The compound semiconductor device according to any one of claims 1 to 6, further comprising a moisture-preventing insulating layer that covers the surface of the protective layer and prevents moisture from entering the protective layer. With the board
A linear compound semiconductor extending upward from the substrate, the linear semiconductor having a lower portion of a first conductive type and an upper portion of a second conductive type extending above the lower portion.
A protective layer of an i-type compound semiconductor crystal covering the side surface of the linear semiconductor,
A moisture-preventing insulating layer that covers the surface of the protective layer and prevents moisture from entering the protective layer .
It shall be the characterization compound semiconductor device that has a. The receiver that receives radio waves and
It has a conversion unit that converts radio waves received by the reception unit into voltage.
The conversion unit
With the board
A linear compound semiconductor extending upward from the substrate, having a lower portion of a first conductive mold into which radio waves are input and an upper portion of a second conductive mold extending above the lower portion. With semiconductors
A receiver characterized by having a protective layer of an i-type compound semiconductor crystal covering the side surface of the linear semiconductor. A step of forming a lower portion of the linear semiconductor on the substrate by linearly growing the first conductive type compound semiconductor from the substrate.
A step of forming an upper portion of the linear semiconductor on the lower portion by linearly growing the second conductive type compound semiconductor from the lower portion.
A method for manufacturing a compound semiconductor device, which comprises a step of growing a protective layer of an i-type compound semiconductor crystal on a side surface of the linear semiconductor. The method for manufacturing a compound semiconductor device according to claim 10 , wherein the protective layer is made of any one of GaN, GaP, GaAs, InP, and InGaP. Claim 10 or claim 11 is characterized in that the step of forming the lower portion of the linear semiconductor, the step of forming the upper portion, and the step of growing the protective layer are performed without exposing the substrate to the atmosphere. The method for manufacturing a compound semiconductor device according to the above.

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