JP6961297B2 - チップの製造方法 - Google Patents

チップの製造方法 Download PDF

Info

Publication number
JP6961297B2
JP6961297B2 JP2017142910A JP2017142910A JP6961297B2 JP 6961297 B2 JP6961297 B2 JP 6961297B2 JP 2017142910 A JP2017142910 A JP 2017142910A JP 2017142910 A JP2017142910 A JP 2017142910A JP 6961297 B2 JP6961297 B2 JP 6961297B2
Authority
JP
Japan
Prior art keywords
workpiece
holding
chip
work piece
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2017142910A
Other languages
English (en)
Japanese (ja)
Other versions
JP2019024048A5 (enExample
JP2019024048A (ja
Inventor
良彰 淀
金艶 趙
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Disco Corp
Original Assignee
Disco Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Disco Corp filed Critical Disco Corp
Priority to JP2017142910A priority Critical patent/JP6961297B2/ja
Priority to KR1020180081428A priority patent/KR102575795B1/ko
Priority to CN201810795006.0A priority patent/CN109300827B/zh
Priority to TW107125134A priority patent/TWI745606B/zh
Publication of JP2019024048A publication Critical patent/JP2019024048A/ja
Publication of JP2019024048A5 publication Critical patent/JP2019024048A5/ja
Application granted granted Critical
Publication of JP6961297B2 publication Critical patent/JP6961297B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67098Apparatus for thermal treatment
    • H01L21/67115Apparatus for thermal treatment mainly by radiation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/677Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
    • H01L21/67793Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations with orientating and positioning by means of a vibratory bowl or track
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6831Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using electrostatic chucks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Laser Beam Processing (AREA)
  • Dicing (AREA)
  • Perforating, Stamping-Out Or Severing By Means Other Than Cutting (AREA)
  • Processing Of Stones Or Stones Resemblance Materials (AREA)
JP2017142910A 2017-07-24 2017-07-24 チップの製造方法 Active JP6961297B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2017142910A JP6961297B2 (ja) 2017-07-24 2017-07-24 チップの製造方法
KR1020180081428A KR102575795B1 (ko) 2017-07-24 2018-07-13 칩의 제조 방법
CN201810795006.0A CN109300827B (zh) 2017-07-24 2018-07-19 芯片的制造方法
TW107125134A TWI745606B (zh) 2017-07-24 2018-07-20 晶片製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2017142910A JP6961297B2 (ja) 2017-07-24 2017-07-24 チップの製造方法

Publications (3)

Publication Number Publication Date
JP2019024048A JP2019024048A (ja) 2019-02-14
JP2019024048A5 JP2019024048A5 (enExample) 2020-03-05
JP6961297B2 true JP6961297B2 (ja) 2021-11-05

Family

ID=65172593

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2017142910A Active JP6961297B2 (ja) 2017-07-24 2017-07-24 チップの製造方法

Country Status (4)

Country Link
JP (1) JP6961297B2 (enExample)
KR (1) KR102575795B1 (enExample)
CN (1) CN109300827B (enExample)
TW (1) TWI745606B (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11433487B2 (en) * 2019-01-07 2022-09-06 Disco Corporation Method of processing workpiece

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021015823A (ja) * 2019-07-10 2021-02-12 株式会社ディスコ ウェーハの加工方法
JP7262904B2 (ja) * 2019-08-26 2023-04-24 株式会社ディスコ キャリア板の除去方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3408805B2 (ja) 2000-09-13 2003-05-19 浜松ホトニクス株式会社 切断起点領域形成方法及び加工対象物切断方法
JP2005135964A (ja) * 2003-10-28 2005-05-26 Disco Abrasive Syst Ltd ウエーハの分割方法
JP5791866B2 (ja) 2009-03-06 2015-10-07 株式会社ディスコ ワーク分割装置
JP5964580B2 (ja) * 2011-12-26 2016-08-03 株式会社ディスコ ウェーハの加工方法
JP2014199834A (ja) * 2013-03-29 2014-10-23 株式会社ディスコ 保持手段及び加工方法
JP2014236034A (ja) * 2013-05-31 2014-12-15 株式会社ディスコ ウェーハの加工方法
JP6223804B2 (ja) * 2013-12-09 2017-11-01 株式会社ディスコ ウェーハ加工装置
JP6391471B2 (ja) * 2015-01-06 2018-09-19 株式会社ディスコ ウエーハの生成方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11433487B2 (en) * 2019-01-07 2022-09-06 Disco Corporation Method of processing workpiece

Also Published As

Publication number Publication date
CN109300827A (zh) 2019-02-01
TW201909263A (zh) 2019-03-01
CN109300827B (zh) 2024-03-19
KR102575795B1 (ko) 2023-09-06
TWI745606B (zh) 2021-11-11
JP2019024048A (ja) 2019-02-14
KR20190011197A (ko) 2019-02-01

Similar Documents

Publication Publication Date Title
JP6991656B2 (ja) チップの製造方法
JP6961297B2 (ja) チップの製造方法
JP6858455B2 (ja) チップの製造方法
JP7102065B2 (ja) チップの製造方法
JP2019218235A (ja) チップの製造方法
JP6973927B2 (ja) チップの製造方法
JP6976654B2 (ja) チップの製造方法
JP6961301B2 (ja) チップの製造方法
JP6961300B2 (ja) チップの製造方法
JP6961298B2 (ja) チップの製造方法
JP6961299B2 (ja) チップの製造方法
JP6932452B2 (ja) チップの製造方法
JP7051198B2 (ja) チップの製造方法
JP6932451B2 (ja) チップの製造方法
JP6991657B2 (ja) チップの製造方法
JP2019220583A (ja) チップの製造方法
JP2019220584A (ja) チップの製造方法
JP2019220582A (ja) チップの製造方法
JP2019220586A (ja) チップの製造方法
JP2019220585A (ja) チップの製造方法
JP2019022901A (ja) チップの製造方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20200122

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20200515

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20210427

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20210525

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20210720

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20211012

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20211012

R150 Certificate of patent or registration of utility model

Ref document number: 6961297

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250