JP6956115B2 - インテグラルポストパッケージリペア - Google Patents

インテグラルポストパッケージリペア Download PDF

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Publication number
JP6956115B2
JP6956115B2 JP2018561677A JP2018561677A JP6956115B2 JP 6956115 B2 JP6956115 B2 JP 6956115B2 JP 2018561677 A JP2018561677 A JP 2018561677A JP 2018561677 A JP2018561677 A JP 2018561677A JP 6956115 B2 JP6956115 B2 JP 6956115B2
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Prior art keywords
memory
error
data
ecc
channel controller
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Japanese (ja)
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JP2019520639A (ja
JP2019520639A5 (https=
Inventor
エム． ブランドル ケビン
エム． ブランドル ケビン
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/52—Protection of memory contents; Detection of errors in memory contents
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • G06F11/106—Correcting systematically all correctable errors, i.e. scrubbing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G06F3/0619—Improving the reliability of storage systems in relation to data integrity, e.g. data losses, bit errors
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G06F3/064—Management of blocks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair
    • G11C29/4401—Indication or identification of errors, e.g. for repair for self repair
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0411—Online error correction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/76—Masking faults in memories by using spares or by reconfiguring using address translation or modifications

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Quality & Reliability (AREA)
  • Computer Hardware Design (AREA)
  • Computer Security & Cryptography (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Detection And Correction Of Errors (AREA)
  • Memory System (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
JP2018561677A 2016-05-28 2016-09-22 インテグラルポストパッケージリペア Active JP6956115B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/168,045 US10042700B2 (en) 2016-05-28 2016-05-28 Integral post package repair
US15/168,045 2016-05-28
PCT/US2016/053138 WO2017209781A1 (en) 2016-05-28 2016-09-22 Integral post package repair

Publications (3)

Publication Number Publication Date
JP2019520639A JP2019520639A (ja) 2019-07-18
JP2019520639A5 JP2019520639A5 (https=) 2019-11-07
JP6956115B2 true JP6956115B2 (ja) 2021-10-27

Family

ID=60417909

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2018561677A Active JP6956115B2 (ja) 2016-05-28 2016-09-22 インテグラルポストパッケージリペア

Country Status (5)

Country Link
US (1) US10042700B2 (https=)
JP (1) JP6956115B2 (https=)
KR (1) KR102460513B1 (https=)
CN (1) CN109155146A (https=)
WO (1) WO2017209781A1 (https=)

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KR102410022B1 (ko) * 2017-11-24 2022-06-21 에스케이하이닉스 주식회사 에러스크럽방법 및 이를 이용한 반도체모듈
KR102623234B1 (ko) * 2018-08-14 2024-01-11 삼성전자주식회사 스토리지 장치 및 그것의 동작 방법
EP3864500A4 (en) * 2018-10-12 2022-10-12 Supermem, Inc. ERROR CORRECTING MEMORY SYSTEMS
US11494087B2 (en) 2018-10-31 2022-11-08 Advanced Micro Devices, Inc. Tolerating memory stack failures in multi-stack systems
US10770164B1 (en) 2019-05-02 2020-09-08 International Business Machines Corporation Soft post package repair function validation
US11416334B2 (en) * 2019-05-24 2022-08-16 Texas Instmments Incorporated Handling non-correctable errors
KR102669545B1 (ko) * 2019-07-23 2024-05-27 삼성전자주식회사 휘발성 메모리 장치의 리페어 제어 방법 및 이를 수행하는 스토리지 장치
KR102748832B1 (ko) * 2019-08-29 2025-01-02 삼성전자주식회사 반도체 메모리 장치, 이를 포함하는 메모리 시스템 및 이의 리페어 제어 방법
KR102706482B1 (ko) * 2019-08-30 2024-09-12 삼성전자주식회사 휘발성 메모리 장치의 리페어 제어 방법 및 이를 수행하는 스토리지 장치
KR102657760B1 (ko) * 2019-09-23 2024-04-17 에스케이하이닉스 주식회사 메모리 시스템 및 그 메모리 시스템의 동작 방법
US11989106B2 (en) 2019-12-11 2024-05-21 Intel Corporation Inline buffer for in-memory post package repair (PPR)
KR102787324B1 (ko) 2020-01-07 2025-03-27 삼성전자주식회사 반도체 메모리 장치 및 이를 포함하는 메모리 시스템 및 반도체 메모리 장치의 동작 방법
TWI708248B (zh) * 2020-02-11 2020-10-21 華邦電子股份有限公司 記憶體裝置和調整用於記憶體裝置的參數的方法
CN113284533B (zh) * 2020-02-20 2023-10-13 华邦电子股份有限公司 存储器装置和调整用于存储器装置的参数的方法
US11127481B1 (en) * 2020-07-10 2021-09-21 Micron Technology, Inc. Managing execution of scrub operations in a memory sub-system
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Also Published As

Publication number Publication date
WO2017209781A1 (en) 2017-12-07
KR20190003591A (ko) 2019-01-09
JP2019520639A (ja) 2019-07-18
US10042700B2 (en) 2018-08-07
US20170344421A1 (en) 2017-11-30
KR102460513B1 (ko) 2022-10-31
CN109155146A (zh) 2019-01-04

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