JP6949590B2 - Pachinko machine - Google Patents

Description

The present invention relates to a gaming machine capable of playing a game.

As a gaming machine, a slot machine in which a predetermined number of bets is set and a plurality of types of identification information are variably displayed based on a start operation, or a gaming medium such as a gaming ball is launched into a gaming area by a launching device. There is a pachinko gaming machine or the like in which a plurality of types of identification information are variably displayed when a game medium wins a prize in a starting area such as a winning opening provided in the game area.

Further, as a gaming machine of this type, when an abnormal condition such as an error occurs, the gaming machine shifts to a specific state in which the progress of the game is disabled and an abnormality notification is executed (see Patent Document 1).

Japanese Unexamined Patent Publication No. 2016-112109

In the gaming machine described in Patent Document 1, when the abnormality notification is executed, the notification that has been executed until the abnormality notification is executed ends. Therefore, the player or the like could not recognize what the state of the gaming machine was when the abnormal condition was satisfied.

The present invention has been conceived in view of such circumstances, and an object of the present invention is that when a player shifts to a specific state in which the progress of the game becomes impossible, the player changes the state of the gaming machine when the state shifts to the specific state. It is to provide a gaming machine that makes the player recognizable.

It is a gaming machine that can play games,
Advantage setting means that can set the advantage for the player,
The advantage confirmation state control means for controlling the advantage confirmation state for confirming the advantage set by the advantage setting means, and the advantage confirmation state control means.
The first advantageous notification execution control means for controlling the execution of the first advantageous notification for notifying the advantageous state, and
A second advantageous notification execution control means for controlling the execution of the second advantageous notification for notifying the advantageous state, and
An error state control means for controlling an error state in which the game cannot proceed when an abnormality occurs in the game machine, and an error state control means.
An error notification execution control means for controlling the execution of error notification for notifying that the error state is controlled is provided.
The first advantageous notification execution control means continues the execution of the first advantageous notification when the advantage confirmation state control means controls the advantage confirmation state in the advantageous state.
When the error state control means controls the error state in the advantageous state,
The error notification execution control means starts execution of the error notification, and the error notification execution control means starts execution.
The first advantageous notification execution control means continues the execution of the first advantageous notification.
The second advantageous notification execution control means interrupts the execution of the second advantageous notification.
When the error state control means controls the error state in the advantageous state, when a power failure occurs and recovers from the power failure,
The error state control means resumes control of the error state and
The error notification execution control means restarts the execution of the error notification.
The first advantageous notification execution control means restarts the execution of the first advantageous notification.
Further, the gaming machine may have the following configuration.
(1) A gaming machine (for example, a slot machine 1) capable of playing a game.
An advantageous notification executing means (for example, the advantageous section LED19 shown in FIG. 3) for executing advantageous notification for notifying that the vehicle is in an advantageous state (for example, an advantageous section), and
Abnormal state transition means for transitioning to an abnormal state when an abnormality occurs in the gaming machine,
A specific notification executing means (for example, a liquid crystal display 51) for executing a specific notification for notifying that the abnormal state (for example, an error state) is provided.
When the specific state is entered during the execution of the advantageous notification by the advantageous notification executing means, the specific notification executing means executes the specific notification, and the advantageous notification executing means continues the advantageous notification (for example,). , As shown in FIG. 6, when the state shifts to the specific state, the specific state is notified and the light emission of the advantageous section LED that has been emitting light is maintained).

According to such a configuration, even if the player shifts to the specific state during the execution of the advantageous notification, the player can be made to recognize that the specific state and the advantageous state. Therefore, when the game shifts to a specific state in which the progress of the game becomes impossible, the player can be made to recognize the state of the gaming machine at the time of shifting to the specific state.

Further, the state of the gaming machine that can be recognized by the player is, for example, whether or not it is a specific state and whether or not it is an advantageous state.

(2) In the gaming machine of (1) above
The specific state is a state (for example, an error state) that is shifted when an abnormality (for example, an error) occurs in the gaming machine.

According to such a configuration, it is possible to prevent the game from proceeding when an abnormality occurs in the gaming machine.

(3) In the gaming machine of (1) or (2) above
The advantageous notification executing means includes a first advantageous notification executing means (for example, main side advantageous section notification shown in FIG. 7 (E)) and a second advantageous notification executing means (for example, sub-side advantageous shown in FIG. 7 (F)). Including section notification)
When the specific state is entered during the execution of the advantageous notification by the first advantageous notification executing means and the execution of the advantageous notification by the second advantageous notification executing means, the first advantageous notification executing means terminates the advantageous notification. On the other hand, the second advantageous notification executing means continues the advantageous notification (for example, as shown in FIGS. 7 (E) and 7 (F), when the state shifts to the specific state, the main side advantageous section notification is terminated. However, the sub-side advantageous section notification is maintained).

According to such a configuration, even if the player shifts to the specific state during the execution of the advantageous notification, the player can appropriately recognize that the advantageous state and the transition to the specific state have occurred.

(4) In any of the above (1) to (3) gaming machines
The specific notification executing means ends the specific notification when a power failure occurs during the execution of the specific notification, and resumes the finished specific notification when the power failure is restored (for example, in FIG. 6). As shown, during the notification of the specific state, the notification of the specific state is terminated at the timing T2 when the power failure occurs, and the notification of the specific state is restarted at the timing T3 when the power failure is restored).
The specific notification executing means ends the advantageous notification when a power failure occurs during the execution of the advantageous notification, and resumes the finished advantageous notification when the power interruption is restored (for example, in FIG. 6). As shown, during the notification of the specific state, the light emission of the advantageous section LED is terminated at the timing T2 when the power failure occurs, and the light emission of the advantageous section LED is restarted at the timing T3 when the power failure is restored).

According to such a configuration, even if a power failure occurs in a specific state, the player can be made to recognize that the power is in the specific state when the power failure is restored. Further, even if the power failure occurs in the advantageous state, the player can be made to recognize that the power failure is in the advantageous state when the power failure is restored.

(5) In any of the above (1) to (4) gaming machines
Further provided with suggestion means (for example, the input request LED and the start valid LED shown in FIG. 6D) for executing suggestion control suggesting that the operation by the player is effective.
The suggestion means ends the suggestion control when it shifts to the specific state (for example, as shown in FIG. 6D, when it shifts to the specific state, the input request LED and the start effective LED Turn off both).

According to such a configuration, it is possible to prevent the player from misunderstanding that the operation of the player is effective in a specific state.

(A) is a front view of the slot machine 1 according to the present embodiment, and (b) is a diagram showing an example of a main internal configuration of the slot machine 1. It is a figure which shows the 7-segment display. It is a figure which shows the output port, DG and the like. It is a figure which shows the flowchart of the signal switching process. It is a figure which shows the switching of a selection signal. It is a figure which shows the timing chart at the time of transitioning to a specific state. It is a figure which shows the timing chart (modification example) at the time of transitioning to a specific state.

A mode for carrying out the slot machine 1 according to the present invention will be described below based on examples. In the following embodiment, an example of the case where the present invention is applied to the slot machine 1 will be described, but if necessary, a pachinko gaming machine will also be described as an example.

[Configuration of slot machine 1]
FIG. 1A is a front view of the slot machine 1 according to the present embodiment, and FIG. 1B is a diagram showing an example of a main internal configuration of the slot machine 1.

As shown in FIG. 1A, the slot machine 1 is provided with a liquid crystal display 51 on the front door 1b. A perspective window 3 is formed on the decorative panel 1c located below the liquid crystal display 51 on the front door 1b. The player can visually recognize the reels 2L, 2C, and 2R arranged side by side inside the housing 1a through the see-through window 3. On each reel, a plurality of types of symbols, each of which can be identified, are arranged in a predetermined order.

As shown in FIG. 1A, the front door 1b is defined as an example of the operating means according to the game state within the range of credits stored as the game value (number of medals) owned by the player. MAXBET switch 6 operated when setting the specified number of bets, medals stored as credits and medals used for setting the number of bets are settled (medals used for setting the credits and the number of bets) The settlement switch 10 is operated when the game is started, the start switch 7 is operated when the game is started, the stop switches 8L, 8C, 8R are operated when the rotation of the reel is stopped, and the production is used. For this purpose, a production switch 56 and the like are provided.

When playing a game on the slot machine 1, first, a predetermined number of bets (for example, 3) is set by inserting medals into the medal insertion slot 4 or operating the MAXBET switch 6. As a result, the winning line LN becomes valid, the operation to the start switch 7 becomes valid, and the game can be started. If a medal is inserted with the number of bets already set, that amount will be added to the credit.

When the start switch 7 is operated while the game can be started, the reels 2L, 2C, 2R are rotated to display the symbol in a variable manner, and when the stop switches 8L, 8C, 8R are operated, the corresponding reel rotation is performed. By stopping, three symbols are derived and displayed as display results in the upper, middle, and lower stages of the perspective window 3. When the specified number of bets (for example, 3) is set, the winning line LN is activated and the game can be started.

When the combination of winning symbols stops on the winning line LN and a winning occurs, a predetermined number of medals are given to the player according to the winning, and credits are added or the credit reaches the upper limit (50). If this is the case, medals will be paid out from the medal payment exit 9. When the medal is paid out from the medal payout outlet 9, the medal is paid out from the medal payout outlet 9 by driving a hopper motor (not shown) controlled by the main control unit 41.

Here, the "game (also referred to as a unit game)" in the slot machine 1 means, in a narrow sense, from the operation of the start switch 7 to the stop of all reels, but when the game is played, the start switch is used. Since the number of bets set before the operation of 7 is set, medals are paid out and the game state is changed after all reels are stopped, these incidental processes are also included in the "game" in a broad sense.

The front door 1b is provided with a game display unit 13 for notifying information about the game as an example of the notification means. The game display unit 13 is provided with a credit display 11, a payout display 12, 1BETLED14, 2BETLED15, 3BETLED16, an input request LED17, a start effective LED18, an advantageous section LED19, and a replaying LED20.

The credit display 11 displays the number of medals stored as credits. The payout display 12 displays the number of medals to be paid out when a predetermined combination wins a prize. Further, the payout display 12 displays an error code or the like when an error occurs.

The 1BETLED 14 is an LED that starts emitting light when one medal is bet. The 2BETLED 15 is an LED that starts emitting light when two medals are bet. The 3BETLED 16 is an LED that starts emitting light when three medals are bet. Further, the 1BETLED14, the 2BETLED15, and the 3BETLED16 are turned off when the game in which the medal is bet ends. In addition, "light emission" may be referred to as "lighting".

The insertion request LED 17 is an LED that notifies that a medal can be inserted. The on-request LED 17 starts emitting light when the game ends. Further, the on-request LED 17 ends the light emission when the game starts.

The start effective LED 18 is an LED that notifies that the game can be started by operating the start switch 7. The start-enabled LED 18 starts emitting light when the bet number is set. Further, the start effective LED 18 ends the light emission when the game starts.

The advantageous section LED 19 is an LED that emits light when it is in the advantageous section. The advantageous section is a section having a performance related to an instruction function for instructing the player of the operation mode of the stop switches 8L, 8C, 8R. By winning the advantageous section transition lottery executed under predetermined conditions, the advantageous section is transferred to the advantageous section. At the end of the game determined to be transferred to the advantageous section in the advantageous section transition lottery (the game won in the advantageous section transition lottery), the light emission of the advantageous section LED 19 starts. Further, the advantageous section LED 19 is turned off at the end of the last game of the advantageous section.

The replay LED 20 is an LED that emits light during a replay game due to a replay prize. Replay is a winning role that grants a replay by winning a prize. During replay, the LED 20 starts emitting light when the replay wins a prize. Further, the LED 20 during replay turns off when the replay game ends.

Further, since the credit display 11 and the payout display 12 can display double-digit numerical values, they are composed of two 7-segment displays. The two 7-segment displays are a first-digit 7-segment display and a second-digit 7-segment display.

The slot machine 1 of the present embodiment also includes a game information display (see FIG. 3). The game information display displays game information based on the game history. The game information is, for example, a medal payout ratio in a predetermined period. The medal payout ratio is a value obtained by dividing the total number of medals paid out by the total number of medals consumed.

Since the game information display can display 4-digit numerical values, it is composed of four 7-segment displays. The four 7-segment displays are, for example, a 1-digit 7-segment display, a 2-digit 7-segment display, a 3-digit 7-segment display, and a 4-digit 7-segment display. Is.

The game information display uses, for example, a 3-digit 7-segment display and a 4-digit 7-segment display to display the type of game information, and a 1-digit 7-segment display and a 2-digit display. The value of the game information is displayed using the 7-segment display of the digit.

Further, the slot machine 1 of the present embodiment also includes a set value display (see FIG. 3). In the present embodiment, the set value display is provided inside the slot machine 1. However, as a modification, the set value display may be provided outside the slot machine 1.

The set value display displays the set value. The set value is a value that specifies the winning probability in the internal lottery. The set value consists of 6 levels from 1 to 6, with 6 having the highest degree of advantage for the player (higher medal payout rate), and the smaller the value in the order of 5, 4, 3, 2, 1 the lower the degree of advantage. (The medal payout rate will be lower).

In addition, the set value is displayed on the set value display when the setting is controlled to the changed state. When controlled to the setting change state, the set value can be changed by a specific operation such as a clerk of a game store. The setting change state is controlled by turning on the setting key switch (not particularly shown) and then supplying the power of the slot machine 1. Further, when the setting change state is controlled, the setting change state ends when the start switch is operated and the setting key switch is turned off.

In addition, the set value is displayed on the set value display even when the setting is controlled to the confirmation state. When the setting is controlled to the setting confirmation state, the set value is displayed on the set value display, so that the clerk of the game store or the like can confirm the set value. The setting confirmation state is controlled by turning on the setting key switch when the bet number is not set. Further, when the setting confirmation state is controlled, the setting confirmation state is terminated by turning off the setting key switch 37.

Since the set value display can display a single-digit numerical value (1 to 6), it is composed of one 7-segment display.

Further, in the present embodiment, the game information display is installed inside the slot machine 1. Regardless of whether the front door 1a of the slot machine 1 is open or the front door 1a is closed, the 4-digit 7-segment display emits light to cause the game information display to play a game. Display information.

Further, in the present embodiment, when the front door 1a of the credit display 11, the payout display 12, and the game display unit 13 is in the closed state, the segments and LEDs corresponding to the game state emit light. Further, when the front door 1a is opened, the light emitting state of the segment and the LED when the front door 1a is in the closed state is maintained.

As shown in FIG. 1B, inside the slot machine 1, a main control board 40 that controls the progress of the game (which can be said to control the game) and outputs various commands according to the progress of the game, and An effect control board 90 or the like that controls the effect in response to a command is provided. The main control board 40 includes a main control unit 41 that performs processing related to the progress of the game and controls a configuration mounted or connected to the main control board 40. The effect control board 90 includes a sub control unit 91 that receives a command transmitted from the main control board 40 to perform an effect, and controls a configuration mounted or connected to the effect control board 90.

The main control unit 41 includes a RAM 41c used as a work memory, a main CPU 41a that performs a control operation according to a program, and the like, performs processing related to the progress of the game, and directly connects each part of the control circuit mounted on the main control board 40. Control objectively or indirectly.

When the MAXBET switch 6, the start switch 7, the stop switches 8L, 8C, 8R, and the settlement switch 10 are operated, a detection signal for detecting the operation is input to the main control unit 41. The main control unit 41 detects operations on these various switches based on the detection signals from these various switches.

From the main control unit 41, control signals for controlling light emission or display control of various indicators included in the game display unit 13 are output to the game display unit 13. Various indicators included in the game display unit 13 emit light or display predetermined information based on the control signal from the main control unit 41.

The sub-control unit 91 includes a RAM 91c used as a work memory, a sub CPU 91a that performs a control operation according to a program, and the like, and performs various controls for producing the effect, and each unit of the control circuit mounted on the effect control board 90. Directly or indirectly control. The RAM 91c included in the sub control unit 91 has a larger storage capacity than the RAM 41c included in the main control unit 41, and data necessary for processing such as production and notification of predetermined information can be stored accordingly.

When the effect switch 56 is operated, a detection signal for detecting the operation is input to the sub control unit 91. The sub control unit 91 detects the operation on the effect switch 56 based on the detection signal from the effect switch 56.

The sub-control unit 91 outputs control signals for controlling each of the liquid crystal display 51 and the speakers 53 and 54 to the liquid crystal display 51 and the speakers 53 and 54, respectively.

[7-segment display]
Next, FIG. 2 shows a 7-segment display that constitutes each of the credit display 11, the payout display 12, and the game information display. As shown in FIG. 2, the 7-segment display includes seven segments, segments A to G, and a segment DP (decimal point). For example, when displaying "1" on the 7-segment display of 1, segment B and segment C are made to emit light. As a result, "1" can be displayed on the 7-segment display. Further, in the following, one segment constituting the seven segments and one LED such as 1BETLED14 are collectively referred to as a “light emitting unit”.

[Control by main CPU 41a]
The control by the main CPU 41a will be described with reference to FIG. First, the digit will be described. The "digit" is composed of one or more light emitting units. In the following, the digit is also referred to as “DG”. Further, two or more DGs are also referred to as a DG group. In this embodiment, the first DG group includes DG1 to DG6. The second DG group includes DG1 to those included in the first DG group.
DG4 Includes DG1 to DG4 that are different from each other. DG is sometimes called a "group".

In the example of FIG. 3, DG1 of the first DG group is a DG including seven segments (segments A to G) included in the first digit 7-segment display of the credit display 11 and an anode. The DG2 of the first DG group is a DG including seven segments (segments A to G) included in the second-digit 7-segment display of the credit display 11 and an anode. The DG3 of the first DG group is a DG including seven segments (segments A to G) included in the first digit 7-segment display of the payout display 12 and an anode. The DG4 of the first DG group is a DG including seven segments (segments A to G) included in the second-digit 7-segment display of the payout display 12 and an anode.

DG5 of the first DG group is a DG including 7 LEDs and an anode. The seven LEDs are 1BETLED14, 2BETLED15, 3BETLED16, turn-on request LED17, start effective LED18, advantageous section LED19, and replaying LED20, respectively. The DG 6 of the first DG group is a DG including seven segments (segments A to G) included in the 7-segment display of the set value display and an anode.

In FIG. 3, the second-digit 7-segment display (DG2) of the credit display of the first DG group and the second-digit 7-segment display (DG4) of the credit display of the second DG group are shown. For simplification of drawings, segments A to G are collectively described in one block.

The DG1 of the second DG group is a DG including eight segments (segments A to G and a segment DP) included in the first-digit 7-segment display of the game information display and an anode. Similarly, DG2 to DG4 of the second DG group have eight segments (segments A to G and segment DP) including the second to fourth digit 7-segment displays of the game information display, and an anode. DG including.

Next, the main control board 40 will be described. The main control board 40 is equipped with a main CPU 41a and a plurality of output ports. In the example of FIG. 3, the first output port 61, the second output port 62, and the third output port 63 are described as a plurality of output ports, but in reality, other output ports also exist.

The first output port 61, the second output port 62, and the third output port 63 each have eight output terminals D0 to D7. Of the eight output terminals D0 to D7 of the first output port 61, the light emitting signals S0 to S6 are output from each of the seven output terminals D0 to D6. Of the eight output terminals D0 to D7 of the second output port 62, light emitting signals S10 to S17 are output from each of the eight output terminals D0 to D7. In this way, the light emitting signals S0 to S6 and the light emitting signals S10 to S17 are output separately (from another output port). Of the eight output terminals D0 to D7 of the third output port 63, the selection signals DG1 to DG6 are output from each of the six output terminals D0 to D5.

The selection signal DG is a signal for selecting (designating) the DG of the light emitting unit to be light-emitting. The light emitting signals S0 to S6 are signals for designating the light emitting mode of the light emitting unit included in the DG selected by the selection signal DG among the six DGs in the first DG group. The light emitting signals S10 to S17 are signals for designating the light emitting mode of the light emitting unit included in the DG selected by the selection signal DG among the four DGs in the second DG group.

First, the first output port 61 will be described.
The signal line from the output terminal D0 of the first output port 61 is connected to each of the segments A of DG1 to DG4 of the first DG group, the segment A of DG6, and the 1BETLED of DG5 of the first DG group. The light emitting signal S0 is output from the output terminal D0 of the first output port 61 under the control of the main CPU 41a. Therefore, the light emission signal S0 is input to each of the segments A of DG1 to DG4 of the first DG group, the segment A of DG6, and the 1BETLED of DG5 of the first DG group.

The signal line from the output terminal D1 of the first output port 61 is connected to each of the segment B of each of the DG1 to DG4 of the first DG group, the segment B of the DG6, and the 2BETLED of the DG5 of the first DG group. The light emitting signal S1 is output from the output terminal D1 of the first output port 61 under the control of the main CPU 41a. Therefore, the light emitting signal S1 is input to each of the segment B of each of the DG1 to DG4 of the first DG group, the segment B of the DG6, and the 2BETLED of the DG5 of the first DG group.

The signal line from the output terminal D2 of the first output port 61 is connected to each of the segments C of DG1 to DG4 of the first DG group, the segment C of DG6, and the 3BETLED of DG5 of the first DG group. The light emitting signal S2 is output from the output terminal D2 of the first output port 61 under the control of the main CPU 41a. Therefore, the light emission signal S2 is input to each of the segment C of each of the DG1 to DG4 of the first DG group, the segment C of the DG6, and the 3BETLED of the DG5 of the first DG group.

The signal line from the output terminal D3 of the first output port 61 is connected to each of the segments D of DG1 to DG4 of the first DG group, the segment D of DG6, and the replaying LED of DG5 of the first DG group. The light emitting signal S3 is output from the output terminal D3 of the first output port 61 under the control of the main CPU 41a. Therefore, the light emitting signal S3 is input to each of the segment D of each of the DG1 to DG4 of the first DG group, the segment D of the DG6, and the replaying LED of the DG5 of the first DG group.

The signal line from the output terminal D4 of the first output port 61 is connected to each of the segment E of each of the DG1 to DG4 of the first DG group, the segment E of the DG6, and the advantageous section LED of the DG5 of the first DG group. The light emitting signal S4 is output from the output terminal D4 of the first output port 61 under the control of the main CPU 41a. Therefore, the light emitting signal S4 is input to each of the segment E of each of the DG1 to DG4 of the first DG group, the segment E of the DG6, and the advantageous section LED of the DG5 of the first DG group.

The signal line from the output terminal D5 of the first output port 61 is connected to each of the segment F of each of the DG1 to DG4 of the first DG group, the segment F of the DG6, and the start effective LED of the DG5 of the first DG group. The light emitting signal S5 is output from the output terminal D5 of the first output port 61 under the control of the main CPU 41a. Therefore, the light emitting signal S5 is input to each of the segment F of each of the DG1 to DG4 of the first DG group, the segment F of the DG6, and the start effective LED of the DG5 of the first DG group.

The signal line from the output terminal D6 of the first output port 61 is connected to each of the segment G of each of the DG1 to DG4 of the first DG group, the segment G of the DG6, and the input request LED of the DG5 of the first DG group. The light emitting signal S6 is output from the output terminal D6 of the first output port 61 under the control of the main CPU 41a. Therefore, the light emitting signal S6 is input to each of the segment G of each of the DG1 to DG4 of the first DG group, the segment G of the DG6, and the input request LED of the DG5 of the first DG group.

Further, the output terminal D7 of the first output port 61 is unused.
Next, the second output port 62 will be described.

The signal line from the output terminal D0 of the second output port 62 is connected to each segment A of DG1 to DG4 of the second DG group. The light emitting signal S10 is output from the output terminal D0 of the second output port 62 under the control of the main CPU 41a. Therefore, the light emission signal S10 is input to each segment A of DG1 to DG4 of the second DG group.

The signal line from the output terminal D1 of the second output port 62 is connected to each segment B of DG1 to DG4 of the second DG group. The light emitting signal S11 is output from the output terminal D1 of the second output port 62 under the control of the main CPU 41a. Therefore, the light emission signal S11 is input to each segment B of DG1 to DG4 of the second DG group.

The signal line from the output terminal D2 of the second output port 62 is connected to each segment C of DG1 to DG4 of the second DG group. The light emitting signal S12 is output from the output terminal D2 of the second output port 62 under the control of the main CPU 41a. Therefore, the light emission signal S12 is input to each segment C of DG1 to DG4 of the second DG group.

The signal line from the output terminal D3 of the second output port 62 is connected to each segment D of DG1 to DG4 of the second DG group. The light emitting signal S13 is output from the output terminal D3 of the second output port 62 under the control of the main CPU 41a. Therefore, the light emission signal S13 is input to each segment D of DG1 to DG4 of the second DG group.

The signal line from the output terminal D4 of the second output port 62 is connected to each segment E of DG1 to DG4 of the second DG group. The light emitting signal S14 is output from the output terminal D4 of the second output port 62 under the control of the main CPU 41a. Therefore, the light emission signal S14 is input to each segment E of DG1 to DG4 of the second DG group.

The signal line from the output terminal D5 of the second output port 62 is connected to each segment F of DG1 to DG4 of the second DG group. The light emitting signal S15 is output from the output terminal D5 of the second output port 62 under the control of the main CPU 41a. Therefore, the light emission signal S15 is input to each segment F of DG1 to DG4 of the second DG group.

The signal line from the output terminal D6 of the second output port 62 is connected to each segment G of DG1 to DG4 of the second DG group. The light emitting signal S16 is output from the output terminal D6 of the second output port 62 under the control of the main CPU 41a. Therefore, the light emission signal S16 is input to each segment G of DG1 to DG4 of the second DG group.

The signal line from the output terminal D7 of the second output port 62 is connected to each segment DP of DG1 to DG4 of the second DG group. The light emitting signal S17 is output from the output terminal D7 of the second output port 62 under the control of the main CPU 41a. Therefore, the light emission signal S17 is input to each segment DP of DG1 to DG4 of the second DG group.

Next, the third output port 63 will be described.
The signal line from the output terminal D0 of the third output port 63 is connected to the anode of DG1 of the first DG group and the anode of DG1 of the second DG group. The selection signal DG1 is output from the output terminal D0 of the third output port 63 under the control of the main CPU 41a. Therefore, the selection signal DG1 is input to the anode of DG1 in the first DG group and the anode of DG1 in the second DG group.

The signal line from the output terminal D1 of the third output port 63 is connected to the anode of DG2 of the first DG group and the anode of DG2 of the second DG group. The selection signal DG2 is output from the output terminal D1 of the third output port 63 under the control of the main CPU 41a. Therefore, the selection signal DG2 is input to the anode of DG2 in the first DG group and the anode of DG2 in the second DG group.

The signal line from the output terminal D2 of the third output port 63 is connected to the anode of the DG3 of the first DG group and the anode of the DG3 of the second DG group. The selection signal DG3 is output from the output terminal D2 of the third output port 63 under the control of the main CPU 41a. Therefore, the selection signal DG3 is input to the anode of DG3 in the first DG group and the anode of DG3 in the second DG group.

The signal line from the output terminal D3 of the third output port 63 is connected to the anode of the DG4 of the first DG group and the anode of the DG4 of the second DG group. The selection signal DG4 is output from the output terminal D3 of the third output port 63 under the control of the main CPU 41a. Therefore, the selection signal DG4 is input to the anode of DG4 in the first DG group and the anode of DG4 in the second DG group.

The signal line from the output terminal D4 of the third output port 63 is connected to the anode of the DG5 of the first DG group. The selection signal DG5 is output from the output terminal D4 of the third output port 63 under the control of the main CPU 41a. Therefore, the selection signal DG5 is input to the anode of the DG5 of the first DG group.

The signal line from the output terminal D5 of the third output port 63 is connected to the anode of the DG6 of the first DG group. The selection signal DG6 is output from the output terminal D5 of the third output port 63 under the control of the main CPU 41a. Therefore, the selection signal DG6 is input to the anode of the DG6 of the first DG group.

Both the output terminal D6 and the output terminal D7 of the third output port 63 are unused. Further, in the present embodiment, as shown in FIG. 3, the selection signals DG1 to the selection signal DG4 are shared between the first DG group and the second DG group. In other words, the selection signal DG1 to the selection signal DG4 are shared by the first DG group and the second DG group. Further, the selection signal DG5 and the selection signal DG6 are used in the first DG group, but are not used in the second DG group.

Further, each of the output terminals D0 to D6 of the first output port 61 corresponds to each of the light emitting units to which the light emitting signals output from the output terminals D0 to D6 are input. Further, each of the output terminals D0 to D7 of the second output port 62 corresponds to each of the light emitting units to which the light emitting signals output from the output terminals D0 to D7 are input.

For example, the output terminal D0 of the first output port 61 is segment A of DG1 of the first DG group, segment A of DG2 of the first DG group, segment A of DG3 of the first DG group, segment A of DG4 of the first DG group, and the first. It corresponds to 1BETLED of DG5 of 1DG group and segment A of DG6 of 1st DG group. Further, the output terminal D0 of the second output port 62 is a segment A of the DG1 of the second DG group, a segment A of the DG2 of the second DG group, a segment A of the DG3 of the second DG group, and a segment A of the DG4 of the second DG group. It corresponds. In FIG. 3, the signal lines from the output terminals D0 to D6 of the first output port 61 and the signal lines from the output terminals D0 to D7 of the second output port 62 are omitted for simplification of the drawings. doing.

Further, unused output terminals (NC: Non-Connect) that are considered to be unused, that is, D7 of the first output port 61 and D6 and D7 of the third output port 63 are ground-connected in this embodiment. ing. No signal line is wired between the unused output terminal and the light emitting unit.

The anode of each DG is an anode common common to the cathodes of the light emitting portions included in the DG. For example, the anode of the DG1 of the first DG group is the anode common common to the canodes of the first digit segments A to G of the credit display 11.

The main CPU 41a executes bit control (8-bit control) for controlling the first output port 61, the second output port 62, and the third output port 63. Regarding the selection signal DG output from the third output port 63, for example, when the selection signal DG1 is output, the bit control of "00000001" is executed, and when the selection signal DG3 is output, "00000100" is executed. Bit control is executed. Further, of the 8-digit bit notation, the 1st digit value corresponds to the control to the output terminal D0 of each output port, and the 8th digit value corresponds to the control to the output terminal D7 of each output port. ..

Further, when the segments A of the DG1 to DG4 and the DG6 of the first DG group are to emit light, the emission signal S0 is output from the output terminal D0 of the first output port 61, so that the bit control of "00000001" is executed. .. Further, when the segments A of the DG1 to DG4 of the second DG group are to emit light, the emission signal S0 is output from the output terminal D0 of the second output port 62, so that the bit control of "00000001" is executed.

When the selection signal DG is output from the third output port 63, the selection signal DG is input to the anode of the corresponding DG. Further, when the light emitting signal S is output from the first output port 61, the light emitting signal S is input to the cathode of the corresponding light emitting portion of the DGs of the first DG group. When the light emitting signal S is input to the cathode of the light emitting unit, the selection signal DG input to the anode flows to the cathode as a current. As the current flows from the anode to the cathode in this way, the light emitting unit to which the light emitting signal S is input emits light.

When the light emitting signal S is output from the second output port 62, the light emitting signal S is input to the cathode of the corresponding light emitting unit in the DG of the second DG group. When the light emitting signal S is input to the cathode of the light emitting unit, the selection signal DG input to the anode flows to the cathode as a current. As the current flows from the anode to the cathode in this way, the light emitting unit to which the light emitting signal S is input emits light.

As described above, the selection signals DG1 to the selection signal DG6 output from the third output port 63 can be said to be signals for selecting (designating) the DG that causes the light emitting unit to emit light. Further, the light emitting signal S0 to the light emitting signal S6 output from the first output port 61 and the light emitting signal S10 to the light emitting signal S17 output from the second output port 62 are light emission included in the DG selected by the selection signal DG. It can be said that it is a signal for designating the light emitting mode of the unit.

Further, in FIG. 3, the signal lines of the respective output terminals and the corresponding light emitting units may be directly connected or indirectly (for example, via a substrate such as a relay substrate). You may try to connect.

Further, as the state of the slot machine 1, there are a normal state, a setting change state, and a setting confirmation state. The normal state refers to a state in which a game is in progress and a state in which a game is waiting (for example, a state in which a demo screen is displayed). In the following, as the DG state, a state in which the light emitting unit can emit light (a state in which light can be emitted) is referred to as a “light emitting state”, and a state in which the light emitting unit cannot emit light is referred to as a “non-light emitting state”.

In the normal state, DG1 to DG5 of the first DG group and DG1 to DG4 of the second DG group are in a light emitting state, and the other DGs are in a non-light emitting state. In the setting change state and the setting confirmation state, DG6 of the first DG group and DG1 to DG4 of the second DG group are in a light emitting state, and the other DGs are in a non-light emitting state. As a modification, the DG1 to DG4 of the second DG group may be in the non-light emitting state in the setting change state and the setting confirmation state. Further, in the setting change state and the setting confirmation state, the DGs 1 to DG5 of the first DG group may be in a light emitting state.

Further, all the DGs 1 to DG5 included in the first DG group are mounted on the display board. The display board is attached to the inside of the slot machine 1 so that each light emitting unit included in the DGs 1 to DG5 is exposed to the outside (see the portion of the game display unit 13 shown in FIG. 1). Further, the DG 6 included in the first DG group is mounted on the relay board. The DG1 to DG4 included in the second DG group are mounted on the main control board 40. In the description of FIG. 3, the DG1 to DG4 of the second DG group and the main control board 40 are described separately, but in reality, the DG1 to DG4 are mounted on the main control board 40.

Further, the storage area of the slot machine 1 includes a game program area in which a game program related to the progress of the game is stored, a game data area in which game data used by the game program is stored, a game RAM area, and a game progress. It includes a non-game program area in which unrelated non-game programs are stored, a non-game data area in which non-game data used by the non-game program is stored, a non-game RAM area, and the like. Further, the game program area, the game data area, and the game RAM area are collectively referred to as a game area, and the non-game program area, the non-game data area, and the non-game RAM area are collectively referred to as a non-game area.

The game program is, for example, bet number setting, BET processing for credit settlement / bet number settlement, internal lottery processing for determining whether or not to allow the occurrence of winning by random number lottery (internal lottery), reel This is a program for executing a reel rotation process related to rotation, a payout process for paying out medals, and the like. The non-gaming program includes, for example, test signal output processing, foreign matter detection processing, door monitoring processing, error processing, and the like. The test signal output process is a process for outputting a test signal generated in connection with the result of the game. The foreign matter detection process is a process for detecting a foreign matter in the medal passage by the insertion slot sensor that detects the medal inserted from the medal insertion slot 4. The door monitoring process is a process for detecting the opening of the front door 1a. The error processing is a process of disabling the game when an error is detected.

The light emitting unit included in the DG of the first DG group is a light emitting unit involved in the progress of the game. Therefore, the process to the first output port 61 (the process of creating the light emission signal of the first DG group), which is the output port corresponding to the first DG group, is the process executed by the game program. Hereinafter, the processing executed by the game program is referred to as "in-capacity processing".

On the other hand, the light emitting unit included in the DG of the second DG group is a light emitting unit that is not involved in the progress of the game. Therefore, the process to the second output port 62 (the process of creating the light emission signal of the second DG group), which is the output port corresponding to the second DG group, is the process executed by the non-game program. Hereinafter, the processing executed by the non-game program is referred to as "out-of-capacity processing".

In this way, since the in-capacity processing and the out-capacity processing can be separated according to the output port, it is compared with the gaming machine in which the in-capacity processing and the out-capacity processing are mixed for one output port. , The processing load can be reduced.

[About signal switching processing]
FIG. 4 is a flowchart of the signal switching process executed by the main CPU 41a.
This signal switching process is executed by an interrupt process executed every predetermined period (0.56 ms in this embodiment).

First, in ST1, the main CPU 41a clears the selection signal DG from the third output port 63. Here, "clearing the signal" means, in the present embodiment, executing the bit control of "00000000000" in which all the output ports outputting the signal are "0". For example, clearing the selection signal DG means executing a bit control of "00000000000" on the third output port 63.

Next, in ST2, the light emission signal of the first output port 61 (that is, the light emission signal of the DG of the first DG group) is cleared. Next, in ST3, bit control for updating and setting the light emission signal of the first output port 61 (that is, the light emission signal of the DG of the first DG group) is executed for the first output port 61. The ST2 and ST3 are executed in the capacity processing.

Next, in ST4, the light emission signal of the second output port 62 (that is, the light emission signal of the DG of the second DG group) is cleared. Next, in ST5, bit control for updating and setting the light emission signal of the second output port 62 (that is, the light emission signal of the DG of the second DG group) is executed for the second output port 62. The ST4 and ST5 are executed by out-of-capacity processing.

Next, in ST6, bit control is executed for the third output port 63 so as to update and set the selection signal DG from the third output port 63. By this bit control, the update-set selection signal is output from the third output port 63.

Further, the output of the updated light emitting signal from the first output port 61 and the updated light emitted signal from the second output port 62 until the next signal switching process (after 0.56 ms has elapsed) are executed. The output and the output of the update-set selection signal from the third output port 63 continue.

Next, the process of FIG. 4 will be described with reference to a specific example. In this specific example, a case where "14" is displayed on the credit display, "08" is displayed on the payout display, and "0723" is displayed on the game information display will be described in the normal state. Here, among these cases, the display of "14" on the credit display and the display of "23" on the first and second digits of the game information display will be described. Actually, in addition to the credit display, the payout display, and the game information display, the state LED (DG5 of the first DG group) also emits light according to the state of the game state. Further, the game information display emits light of the segment DP, while the credit display, the payout display, and the set value display do not emit light of the segment DP.

First, a process for displaying "4" on the first digit of the credit display (DG1 of the first DG group) and displaying "3" on the first digit of the game information display (DG1 of the second DG group). Will be described. As this process, first, by outputting the selection signal DG1 from the third output port 63, the DG1 of the first DG group and the DG1 of the second DG group are selected as the DG that causes the segment (light emitting unit) to emit light. Further, the bit control for outputting the selection signal DG1 from the third output port 63 is "00000001", and the bit control is executed for the third output port 63.

During the period in which the selection signal DG1 is output from the third output port 63, the first output port 61 is processed to display "4" on the DG1 of the first DG group, that is, the segment B, the segment C, and the segment. The process of causing the F and the segment G to emit light is executed.
The process of causing these segments to emit light outputs the light emission signal S1, the light emission signal S2, the light emission signal S6, and the light emission signal S7 from the first output port 61, and prevents the other light emission signals S from being output. That is, the bit control "01100110" is executed for the first output port 61.

Further, during the period in which the selection signal DG1 is output from the third output port 63, the second output port 62 is processed to display "3" on the DG1 of the second DG group, that is, the segment A and the segment B. , Segment C, segment D, segment G, and segment DP are executed. The process of causing these segments to emit light outputs a light emitting signal S10, a light emitting signal S11, a light emitting signal S12, a light emitting signal S13, a light emitting signal S16, and a light emitting signal S17 from the second output port 62, and outputs another light emitting signal S. Do not let it. That is, the bit control "1100111" is executed for the second output port 62.

In this way, in order to display "4" in the first digit of the credit display (DG1 of the first DG group) and to display "3" in the first digit of the game information display (DG1 of the second DG group). As the process of, the bit control of "01100110" is executed for the first output port 61, the bit control of "11000111" is executed for the second output port 62, and the bit control of "00000001" is executed for the third output port 63. do.

When such a state continues for 0.56 ms, the signal switching process shown in FIG. 4 is executed. In ST1, the selection signal DG is cleared. Specifically, the bit control of "00000001" for the third output port 63 is changed to the bit control of "0000000000".

Next, in ST2, the light emission signal of the first output port 61 is cleared. Specifically, the bit control of "01100110" for the first output port 61 is changed to the bit control of "0000000000".

Next, in ST3, bit control is executed for the first output port 61 so as to update and set the light emission signal of the first output port 61 (that is, the light emission signal of the DG of the first DG group). Here, a process of updating and setting the light emission signal of the first output port 61 so as to newly display "1" on the DG2 of the first DG group, that is, a process of causing the segment B and the segment C to emit light is executed. The process of causing these segments to emit light outputs the light emission signal S2 and the light emission signal S3 from the first output port 61, and prevents the other light emission signals S from being output. That is, as the bit control for the first output port 61, the bit control of "00000011" is executed by updating from "0000000000".

Next, in ST4, the light emission signal of the second output port 62 is cleared. Specifically, the bit control of "11000111" for the second output port 62 is changed to the bit control of "0000000000".

Next, in ST5, bit control is executed for the second output port 62 so as to update and set the light emission signal of the second output port 62 (that is, the light emission signal of the DG of the second DG group). Here, the process for newly displaying "2" on the DG2 of the second DG group, that is, the segment A, the segment B, the segment D, the segment E, the segment G, and the segment DP are emitted. Execute the process to make it. The process of causing these segments to emit light outputs a light emitting signal S10, a light emitting signal S11, a light emitting signal S13, a light emitting signal S14, a light emitting signal S16, and a light emitting signal S17 from the second output port 62, and outputs another light emitting signal S. Do not let it. That is, as the bit control for the second output port 62, the bit control of "11011011" is executed by updating from "0000000000".

Next, in ST6, bit control is executed for the third output port 63 so as to update and set the selection signal DG. Here, as the bit control for the third output port 63, the bit control of "00000010" is executed by updating from "0000000000".

By executing such a process, "4" is displayed in the first digit of the credit display and "3" is displayed in the first digit of the game information display, and the process is executed after 0.56 ms has elapsed. By the signal switching process, the display of the first digit "4" of the credit display is finished, and the display of "1" is displayed in the second digit of the credit display. At the same time, the display of the first digit "3" of the game information display ends, and the display of "2" is displayed in the second digit of the game information display.

Then, the next signal switching process is executed 0.56 ms after the start of the DG signal switching process. In the signal switching process, DG3 of the first DG group (first-digit 7-segment display of the payout display) and DG3 of the second DG group (third-digit 7-segment display of the game information display) are new. A numerical value (in this case, "8" is displayed for DG3 of the first DG group, and "7" is displayed for DG4 of the second DG group.

FIG. 5 is a diagram for explaining switching of the selection signal DG. 5 (A) to 5 (F) show the outputs of the selection signals DG1 to DG5 from the output terminals D0 to D5 of the third output port 63, respectively.

As shown in FIGS. 5A to 5F, the main CPU 41a has the selection signal DG1 (00000001) → the selection signal DG2 (000000010) → the selection signal DG3 (00000100) → the selection signal DG4 (00001000) → the selection signal. The output selection signal DG is switched in the order of DG5 (00010000) → selection signal DG6 (0010000) → selection signal DG1 (000000001) → selection signal DG2 (00000010) ... (predetermined order). The period during which one selection signal DG is output is a predetermined period, which is 0.56 ms in the present embodiment. That is, the main CPU 41a switches the output selection signal DG every 0.56 ms elapse. For example, when the selection signal DG1 is output, DG1 of the first DG group and DG1 of the second DG group are selected (designated).

In each of FIGS. 5A to 5F, the process of lowering the selection signal corresponds to ST1 of FIG. 4, and the process of raising the selection signal corresponds to ST6.

Further, the main CPU 41a switches the output of the light emission signal S from the first output port 61 in synchronization with the switching of the output of the selection signal DG from the third output port 63 (ST2 and ST3), and the second output. The output of the light emission signal S from the port 62 is also switched (ST4 and ST5).

When any of the selection signals DG1 to DG4 is output from the third output port 63, the DG corresponding to the output selection signal DG among the DGs of the first DG group can emit light, and the second DG group can emit light. The DG corresponding to the output selection signal DG among the DGs of is capable of emitting light.

Further, regarding the selection signal DG5 and the selection signal DG6 from the third output port 63, DG5 and DG6 are present as corresponding DGs in the first DG group. However, there is no corresponding DG in the second DG group. The bit control of the second output port 62 when the selection signal DG5 or the selection signal DG6 is output will be described. When the selection signal DG5 or the selection signal DG6 is output, the non-emission bit control is executed so that none of the segments of the DG in the second DG group emit light. This non-emission bit control is a bit control of "00000000" in which all are 0. Therefore, when the selection signal DG5 or the selection signal DG6 is output, the segment included in the second DG group is turned off.

Further, in the normal state, the DG6 (set value display) of the first DG is in a non-light emitting state. Therefore, in the normal state, the non-emission bit control is executed for the first output port 61 during the period when the signal DG6 is output from the third output port 63.

Further, in the setting confirmation state and the setting change state, the DGs 1 to DG5 of the first DG group are in the non-light emitting state. Therefore, in the setting confirmation state and the setting change state, the non-emission bit control is executed for the first output port 61 during the period when the signals DG1 to DG5 are output from the third output port 63.

As described with reference to FIGS. 4 and 5, a method of making a plurality of DGs appear to emit light at the same time by switching the DG that causes the light emitting unit to emit light every short time (0.56 ms) is described. Hereinafter, it is also referred to as "dynamic emission". In order to enable all DGs to emit light at the same time without adopting a configuration that executes dynamic light emission, it is necessary to provide independent wiring for each DG and each light emitting unit. However, when set in this way, the number of wires increases, the cost increases, and the assembly load also increases. In the present embodiment, such a problem can be solved by executing dynamic light emission.

Further, by executing the dynamic light emission of the present embodiment, the DG to be emitted by the signal switching process, which is the interrupt process executed every short period (0.56 ms in the present embodiment), is sequentially switched. As a result, it is possible to make it appear to be substantially the same as the state in which a plurality of DGs are simultaneously emitting light (as if they are simultaneously emitting light to the human eye). Further, if the LED that emits light is different for each interrupt process, power consumption can be suppressed and seizure of the light emitting portion can be suppressed. Further, the brightness can be increased by repeating the point emission as compared with the LED that always emits light.

[About specific state]
Next, the specific state will be described. The specific state is one of the error state and the above-mentioned setting confirmation state. The error state is a state in which an error is detected. When an error occurs, the slot machine 1 of the present embodiment and a gaming machine such as a pachinko gaming machine can detect the error. Here, the error includes, for example, an error based on a failure of a device in the game machine, an error based on an increase or decrease in the game medium in the game machine, an error based on a player's fraudulent activity, and the like.

An error caused by a failure of a device in a gaming machine is, for example, an error detected when a movable body (accessory) included in the gaming machine does not operate properly. The error based on the increase or decrease of the game medium in the game machine is, for example, an error detected due to a shortage of the game medium in the storage tank in which the game medium to be paid out is stored. The gaming medium is, for example, a medal in the slot machine 1 and a pachinko ball in the pachinko gaming machine. Further, in the slot machine 1, the storage tank is also called a hopper, and an error based on an increase or decrease in the game medium in the game machine is also called a hopper error.

An error based on a player's fraudulent activity is, for example, a game medium fraudulent payout error. The game medium illegal payout error is an error detected by illegally paying out the game medium by performing an illegal operation on the storage unit in which the game medium is stored. As described above, the error state is a state in which an error is detected.

[Timing chart when transitioning to a specific state]
Next, with reference to FIG. 6, a timing chart at the time of transition to a specific state will be described. FIG. 6A is a diagram showing that the state has been shifted to a specific state. ON indicates that the state has been shifted to the specific state, and OFF indicates that the state has not been shifted to the specific state. FIG. 6B is a diagram showing a specific state notification process for notifying that the state has been changed to the specific state. ON indicates that the specific state notification process has been executed, and OFF indicates that the specific state notification process has not been executed. FIG. 6C is a diagram showing light emission of the BET LED, the advantageous section LED, and the turn-on request LED. ON indicates that the BET LED, the advantageous section LED, and the turn-on request LED are emitting light, and OFF indicates that the BET LED, the advantageous section LED, and the turn-on request LED are not emitting light. FIG. 6D is a diagram showing light emission between the turn-on request LED and the start effective LED. ON indicates that the ON request LED and the start effective LED are emitting light, and OFF indicates that the ON request LED and the start effective LED are not emitting light.

As shown in FIG. 6B, the specific state notification process is executed at the timing T1 when the state is shifted to the specific state. Further, as shown in FIG. 6C, at the timing T1, the light emission of the BET LED, the advantageous section LED, and the turn-on request LED is maintained. Further, as shown in FIG. 6D, at the timing T1, the turn-on request LED and the start effective LED are turned off.

As shown in FIG. 6A, it is assumed that a power interruption occurs at timing T2 (power supply is stopped) and the power supply is restored at timing T3 (power supply is restarted). As shown in FIG. 6B, the specific state notification process ends at the timing T2 when the power failure occurs, and the specific state notification process returns at the timing T3 when the power failure is restored. As shown in FIG. 6C, the BET LED, the advantageous section LED, and the turn-on request LED are turned off at the timing T2 when the power failure occurs, and the BET LED and the advantageous section LED are turned off at the timing T3 when the power failure is restored. And the turn-in request LED emits light. Further, as shown in FIG. 6D, the turn-off request LED and the start effective LED are kept off even at the timing T2 and the timing T3.

[About gaming machines]
The gaming machine to which the above-described technical idea of the present embodiment is applied is not limited to the slot machine 1, and may be applied to other gaming machines. For example, among the above-mentioned technical ideas, the ideas applicable to pachinko gaming machines may be applied to pachinko gaming machines.

For example, it may be a pachinko gaming machine having a 7-segment display composed of a plurality of segments (for example, a display for displaying a special figure) and a plurality of LEDs for notifying the state of the game. Further, the signals and wirings to the plurality of LEDs and the plurality of segments are, for example, in the embodiment shown in FIG. Further, the pachinko gaming machine may execute the above-mentioned dynamic light emission. Further, when the pachinko gaming machine shifts to a specific state (for example, an error state), the processing according to the timing chart shown in FIG. 6 may be executed.

[About the effect of the gaming machine of this embodiment]
(1) As shown in FIGS. 6 (C) and 6 (D), a plurality of LEDs including a turn-on request LED, a start effective LED, and another LED (for example, a BET LED) are emitting light. In the state, when the state shifts to a specific state, the turn-on request LED and the start effective LED are turned off, while the light emission of the other LEDs is maintained.

Further, as shown in FIG. 3, in the first output port 61, the output terminal D5 corresponding to the start effective LED and the output terminal D6 corresponding to the turn-on request LED are provided adjacent to each other. The output terminal corresponding to the start-enabled LED is an output terminal D5 that outputs a light-emitting signal S5 for controlling the light-emitting mode of the start-enabled LED. The output terminal corresponding to the on-request LED is an output terminal D6 that outputs a light-emitting signal S6 for controlling the light-emitting mode of the on-request LED.

As described above, since the output terminal D5 and the output terminal D6 are adjacent to each other, it is possible to reduce the processing load of the light emitting stop processing of the light emitting means when the state is shifted to the specific state. For example, in the bit control executed for the first output port 61 when the state is shifted to a specific state, "0", which is a bit indicating turning off, can be continuously set. Therefore, it is possible to reduce the processing load of the light emitting means for turning off the light when the state is changed to the specific state.

Further, a gaming machine (first comparison target) that employs a configuration in which output terminals corresponding to LEDs to be turned off (hereinafter, also referred to as LEDs to be turned off) are separated (not adjacent to each other). A game machine), for example, a case where the output terminal corresponding to the start effective LED is D0 and the output terminal corresponding to the input request LED is D4 will be described. In this case, noise may occur if bit control is performed to turn off D0 and D4, respectively, when the selection signal DG5 is output after shifting to a specific state. When the noise is generated, noise is also generated in the output terminal adjacent to D0, for example, the output terminal D1, and there is a possibility that bit inversion occurs in the output terminal D1.

On the other hand, the output terminal corresponding to the start effective LED and the output terminal corresponding to the turn-on request LED are adjacent to each other (D5 and D6). Therefore, even if noise is generated by executing bit control for turning off the output terminal D5 and the output terminal D6, it is less likely to be affected by the noise as compared with the first comparison target gaming machine. can do.

(2) A gaming machine in which the two LEDs to be turned off when the state is shifted to a specific state are included in the first DG and the second DG, which are different DGs (hereinafter, the second comparison target gaming machine). In), it is necessary to perform bit control for turning off the first output port even when the first DG is selected by the selection signal DG, and even when the second DG is selected by the selection signal DG, the first It is necessary to perform bit control to turn off the output port, which complicates the process.

On the other hand, in the present embodiment, the two LEDs to be turned off when the state is shifted to the specific state are included in one DG (DG5). Therefore, only when DG5 is selected by the selection signal DG, the bit control for turning off the first output port needs to be performed, so that the LED is turned off as compared with the second comparison target gaming machine. The process to be performed can be simplified.

(3) Further, the two LEDs to be turned off are LEDs suggesting that the operation by the player is effective, that is, the turn-on request LED and the start effective LED. When the state is changed to the specific state, the ON request LED and the start enable LED are turned off. Therefore, when the state is shifted to the specific state, the notification that the operation by the player is effective ends, so that it is possible to prevent the player from misunderstanding that the operation by the player is effective.

(4) The specific state includes a state (error state) that is shifted when an abnormality (error) occurs in the gaming machine. Further, the error state is a state in which the game does not proceed. Therefore, when an abnormality occurs in the gaming machine, it shifts to a specific state, so that the gaming can be prevented from progressing.

(5) Further, the LEDs to be subject to light emission maintenance (hereinafter, also referred to as light emission maintenance target LEDs) are the first to third BET LEDs, the replaying LED, and the advantageous section LED even when the state is shifted to the specific state. Further, the output terminals D0 to D4 corresponding to the first to third BET LEDs, the replaying LED, and the advantageous section LED are adjacent to each other (see FIG. 3).

As a result, in the bit control executed for the first output port 61 when the state is shifted to the specific state, "1" indicating a bit for maintaining light emission can be continuously set. Therefore, it is possible to reduce the processing load of the light emission maintaining process of the light emitting means when the state is shifted to the specific state.

If the output terminal corresponding to the LED to be turned off when the state shifts to a specific state is sandwiched between the two output terminals corresponding to each of the two LEDs that maintain light emission, for example, it corresponds to the LED to be turned off. About a gaming machine (hereinafter, referred to as a third comparison target gaming machine) adopting a configuration in which the output terminal to be used is D1 and the two output terminals corresponding to the two LEDs that maintain light emission are D0 and D2. explain.

In this gaming machine, when the state is shifted to a specific state, bit control that maintains light emission for D0 and D2, that is, "1" is set, and bit control that turns off D1, that is, "0" is set. The bit control to be set will be executed. Then, in the case of the bit control, for example, the bit control for setting "1" is executed for D1 due to the bit inversion due to the generation of noise, so that the light emission of the LED that should be turned off is maintained. In some cases.

On the other hand, in the present embodiment, two or more output terminals corresponding to each of the two LEDs that maintain light emission are adjacent to each other. Therefore, even if noise is generated, for example, the fact that the light emission of the LED that should be originally turned off is maintained can be made less likely to occur as compared with the third comparison gaming machine.

Further, as shown in the first output port 61 of FIG. 3, the output terminals D0 to D4 corresponding to the LED for maintaining light emission are a group of 1 adjacent to each other, and the output terminal D5 corresponding to the LED to be turned off is used. , It can be said that the output terminals D6 are one terminal group adjacent to each other.

(6) Further, as shown in FIG. 6C, the light emission of the advantageous section LED is maintained at the timing T1 when the state is shifted to the specific state. Therefore, it is possible to suggest to the player that the section has been shifted to the advantageous section even if the shift to the specific state has been made.

(7) Further, as shown in FIG. 3, the first output port 61 has an output terminal D7 which is an unused output terminal. Further, the unused output terminal D7 is adjacent to the output terminal D6 corresponding to the turn-on request LED which is the LED to be turned off. Further, for the unused output terminal D7, bit control for turning off the light, that is, "0" is set. Therefore, it is possible to reduce the fact that the output terminal D6, which should originally be set to the bit "0" to be turned off, is set to "1" due to a malfunction or the like when the state is shifted to the specific state.

(8) When the transition to the advantageous section is performed, the advantageous section LED emits light. As shown in FIGS. 6 (B) and 6 (C), when the transition to the advantageous section is performed, that is, when the advantageous section LED is emitting light and the specific state is shifted, the notification of the specific state is notified. Is executed, and the light emission of the advantageous section LED continues. Therefore, even if the specific state is changed while the advantageous section LED is emitting light, the store clerk, the player, and the like can be made to recognize that the specific state has been changed, and the player can be made to recognize that the advantageous section is used. can.

(9) Further, as shown in FIGS. 6A to 6C, the specific state notification process is terminated at the timing T2 when the power failure occurs when the state is shifted to the specific state, and the power failure is restored. At the timing T3, the completed specific state notification process is restarted. Further, when the power failure occurs during the light emission of the advantageous section LED, the advantageous section LED is turned off, and when the power failure is restored, the light emission of the finished advantageous section LED is restarted. Therefore, even if a power failure occurs in a specific state, the store clerk, the player, or the like can be made to recognize that the power is in the specific state when the power failure is restored. Further, even if a power failure occurs during the transition to the advantageous section, the player can be made to recognize that the section is advantageous when the power failure is restored.

(10) If the light emission time of the DG of 1 is shortened, even if the DG of 1 emits light, the brightness due to the light emission becomes low, so that it looks dark to the player or the like. Then, it becomes difficult for the player or the like to recognize the information notified by the DG. On the other hand, in the present embodiment, as shown in FIG. 3, the light emitting unit is divided into a first DG group and a second DG group. Therefore, it is possible to secure the light emitting time of each of the light emitting unit included in the first DG group and the light emitting unit included in the second DG group. Therefore, the brightness due to the light emission of 1 DG can be guaranteed. Further, by adopting a configuration in which the DG is divided into DG groups, even if the DG increases due to, for example, improvement of the gaming machine, the brightness due to the light emission of the increased DG can be guaranteed. Further, the number of the first DG group is 6 (DG1 to DG6), and the number of the 2nd DG group is 4 (DG1 to DG4). Even if they are different, the selection signal DG1 to the selection signal DG4 can be shared between the first DG group and the second DG group. In other words, any one of DG1 to DG4 in the first DG group and any one of DG1 to DG4 in the second DG group can be selected by a common selection signal. Therefore, even if the DG increases due to the improvement of the gaming machine or the like, it is possible to prevent the number of selection signals from increasing too much.

(11) The light emitting unit included in the first DG group of FIG. 3 constitutes each of the segments constituting the two 7-segment displays constituting the credit display and the two 7-segment displays constituting the payout display. Includes segment and status LED. That is, the light emitting unit included in the first DG group is a light emitting unit that updates the light emitting state according to the progress of the game (so that the progress of the game can be specified).

On the other hand, the light emitting unit included in the second DG group includes a light emitting unit (segment) constituting each of the four 7-segment displays constituting the game information display. That is, the light emitting unit included in the second DG group is a light emitting unit different from the light emitting unit included in the first DG group. In other words, it is not a light emitting unit that updates the light emitting state according to the progress of the game (so that the progress of the game can be specified).

Therefore, the first DG group and the second DG group are separated depending on whether or not the light emitting state is updated according to the progress of the game. Therefore, the processing load of bit control of the main CPU 41a can be reduced.

(12) Further, when the selection signal DG5 or the selection signal DG6, which is the selection signal DG that is not shared between the first DG group and the second DG group, is output, any of the DGs in the second DG group is output. Non-emission bit control that does not cause the segment to emit light is executed. Therefore, it is possible to prevent the light emitting portion included in the second DG group, which should not emit light, from being erroneously emitted.

Further, depending on the state, there is a DG that does not emit light. For example, in the normal state, DG6 of the first DG group is non-emission. The non-emission bit control is also executed for the first output port 61 of the non-emission DG6. As described above, the non-emission bit control is the DG of the second DG group when the selection signal DG5 or the selection signal DG6 is output.
It is also executed by bit control for DG, and is also executed by bit control for DG which is made non-emission depending on the state. Therefore, since the processing can be standardized, the processing load can be reduced.

(13) Further, as shown in the signal switching process described with reference to FIG. 4, first, the selection signal DG clear process (ST1) for clearing the selection signal DG is executed. After the selection signal DG clearing process is completed, the light emitting signal of the first output port and the light emitting signal of the second output port are updated (ST3, ST5). After that, the selection signal DG is updated and set (ST6). According to such a configuration, it is possible to prevent erroneous light emission due to an error of the selected DG or the like by executing the selection signal DG clearing process or the like for clearing the selection signal DG.

(14) Further, the light emission signal of the first output port is cleared in ST2 before the light emission signal of the first output port is updated and set. Further, the light emission signal of the second output port is cleared in ST4 before the light emission signal of the second output port is updated and set. According to such a configuration, the light emitting portion included in the selected DG is erroneously emitted by executing the light emitting signal clearing process for clearing the light emitting signal of the first output port and the light emitting signal of the second output port. It can be prevented from being stowed.

Further, even when the selection signal DG5 or the selection signal DG6 is output, the light emission signal of the second output port 62 is cleared in the same manner as when any of the selection signal DG1 to the selection signal DG4 is output. The process (ST4) and the update setting process (ST5) of the light emission signal of the second output port 62 are executed. Therefore, the signal switching process can be standardized regardless of the type of the selection signal DG.

(15) Further, as shown in FIG. 3, among the eight output terminals of the first output port 61, the output terminal D7 is an unused output terminal. Further, in all the DGs included in the first DG group, all the light emitting units corresponding to the output terminal D7, which is an unused output terminal, are unused. No signal line is connected between the unused output terminal D7 and the light emitting unit corresponding to the output terminal D7. In other words, of the eight output terminals of the first output port 61, the unused output terminal D7 is not provided with a light emitting unit corresponding to any of the DGs (DG1 to DG6 of the first DG group). Therefore, it is possible to appropriately control the issuing mode of all the light emitting units included in the first DG group, and to eliminate the need for wiring from the output terminal D7 of the first output port 61 to each of the DGs included in the first DG group. can. Therefore, the wiring pattern can be simplified.

(16) Further, the first output port 61 is mounted on the main control board 40, the DGs 1 to DG5 included in the first DG group are mounted on the display board, and the DG6 included in the first DG group is mounted on the relay board. That is, the first output port 61 mounted on the main control board 40 includes an unused output terminal D7, and the unused output terminal D7 is any of DG1 to DG6 mounted on the display board and the relay board. The DG is also not provided with a corresponding light emitting unit. Therefore, it is possible to eliminate the need for a wiring pattern from the unused output terminal D7 mounted on the main control board 40 to the light emitting unit included in each of the plurality of DGs. Therefore, the wiring pattern from the main control board 40 to the display board can be simplified, and the wiring pattern from the main control board 40 to the relay board can also be simplified.

(17) Further, DG1 to DG4 and DG6 of the first DG group are DGs (7-segment displays) for displaying numbers, respectively. Further, the DG 5 of the first DG group is a DG for displaying different game information from each of the plurality of LEDs constituting the DG 5. Since the role of the DG can be clarified in this way, the main CPU 41a can control the light emitting mode of the light emitting unit according to the role.

(18) Among the output terminals of the first output port 61, for the output terminals D0 to D6 used, bits (0 or 1) are set according to the light emitting unit to emit light. Further, regardless of which DG of DG1 to DG6 is selected by the selection signal DG, the bit control for the unused output terminal D7 of the first output port 61 is set to "0", which is a bit that does not emit light. Set. In this way, the light emitting signals S to be output from all eight output terminals D0 to D7 including the unused output terminals are generated. Therefore, the generation process of the light emitting signal S can be simplified as compared with a gaming machine that does not generate a signal from the unused output terminal but generates a light emitting signal S output from an output terminal other than the unused output terminal.

(19) Further, the unused output terminal D7 is an output terminal located on the end side of the eight output terminals. Therefore, since the unused output terminal D7 that does not require the wiring pattern is located on the end side, the wiring pattern can be simplified. Further, since the detection process for detecting while shifting the created 8-digit bit signal can be executed and the 8th-digit bit can be set to "0", it can be easily handled in the program.

(20) Further, as shown in FIG. 3, all the DGs in the first DG group have unused light emitting parts, while all the DGs in the second DG group have unused light emitting parts. not exist. As described above, in the present embodiment, the DG group is divided, that is, the output port is divided depending on whether or not there is an unused light emitting unit. Therefore, the bit control to the first output port 61 always sets "0" for the output terminal D7, while the bit control to the second output port 62 always sets "1" for the output terminal D7. .. Therefore, the output terminal D7 can fix the set number of bits in both the first output port 61 and the second output port. Therefore, the burden of bit control on the first output port 61 and bit control on the second output port 62 can be reduced.

(21) Further, the processing to the first output port 61 is executed in the in-capacity processing, and the processing to the second output port 62 is executed in the out-capacity processing. In this way, since the in-capacity processing and the out-capacity processing can be separated according to the output port, it is compared with the gaming machine in which the in-capacity processing and the out-capacity processing are mixed for one output port. , The processing load can be reduced.

(22) In the process of FIG. 4, a flowchart is created in which the clearing process of the light emitting signal of the output port is collectively executed, and then the update setting process of the light emitting signal of the output port is collectively executed, that is, ST1 → ST2 → ST4. It is also conceivable to configure a gaming machine (a fourth comparison target gaming machine) in which the order is ST3 → ST5 → ST6. However, when this configuration is adopted, the processing flow is as follows: in-capacity processing (ST2) → out-of-capacity processing (ST4) → in-capacity processing (ST3) → out-of-capacity processing (ST5). That is, the in-capacity processing and the out-capacity processing must be executed alternately, which complicates the processing.

On the other hand, in the present embodiment, ST2 and ST3 are executed by the in-capacity processing, and ST4 and ST5 are executed by the out-of-capacity processing. can do.

[Modification example]
Although the main embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various modifications and applications are possible. Hereinafter, modifications of the above-described embodiment applicable to the present invention will be described.

(1) FIG. 7 is a diagram showing a modified example of the timing chart described with reference to FIG. The difference between FIGS. 6 and 7 is that the notification of the advantageous section can be executed by both the main control unit 41 (main side) and the sub control unit 91 (sub side). As shown in FIG. 7 (E), the notification of the advantageous section performed by the main control unit 41 (main side) is referred to as "main side advantageous section notification", and the notification of the advantageous section performed by the sub control unit 91 (sub side) is performed. It is called "sub-side advantageous section notification".

The main side advantageous section notification is a notification using the advantageous section LED, and for example, the advantageous section LED is made to emit light when the section is shifted to the advantageous section. The sub-side advantageous section notification is a notification using the liquid crystal display 51. For example, when the section is shifted to the advantageous section, the liquid crystal display 51 displays information that can identify that the section is shifted to the advantageous section. do.

Further, the display area of the liquid crystal display 51 is larger than that of the advantageous section LED. Therefore, the sub-side advantageous section notification can execute the advantageous section notification in a more conspicuous manner than the main-side advantageous section notification.

In this modification, as shown in FIGS. 7 (E) and 7 (F), at the timing T1 when the state shifts to the specific state, the main side advantageous section notification which is not so noticeable to the player is terminated, while the player On the other hand, the conspicuous sub-side advantageous section notification is maintained. According to such a configuration, even if the player shifts to the specific state, the player can be made to recognize that the shift to the advantageous section is performed by the maintained sub-side advantageous section notification.

Further, as a modification of FIG. 7, at the timing T1 when the state shifts to the specific state, the sub-side advantageous section notification that is conspicuous to the player is terminated, while the main side advantageous section notification that is not so conspicuous to the player is maintained. You may do so. According to such a configuration, the main side advantageous section notification that is not so conspicuous is maintained, so that the player can be made to recognize that the section has been shifted to the advantageous section for the time being. Further, since the sub-side advantageous section notification that is conspicuous to the player ends, the notification of the specific state (FIG. 7B) can be made conspicuous. Therefore, it is possible to make it easier for the player and the clerk of the game store to recognize that the state has been changed to a specific state.

(2) Further, in the present embodiment, in the signal switching process of FIG. 4, the process of clearing the selection signal DG and the light emission signal S has been described as a process of setting "0" for 8 bits. However, the process of clearing the selection signal DG and the light emission signal S may be a process of stopping the output of the selection signal DG and the light emission signal S.

(3) In the present embodiment, it has been described that the number of DGs contained in the first DG group is different from the number of DGs contained in the second DG group. However, the number of DGs contained in the first DG group and the number of DGs contained in the second DG group may be the same. Even with such a configuration, the selection signal DG can be shared between the first DG group and the second DG group, which is an advantageous effect.

(4) Further, in the present embodiment, the advantageous section LED is exemplified as the LED for notifying that the LED has been shifted to the advantageous section. However, it is possible to shift to any of a plurality of types of advantageous sections as an advantageous section, and an LED corresponding to the type may be provided. For example, CZ (chance zone) and AT (assist time) may exist as advantageous sections. For example, as the advantageous section LED, a CZ lamp for notifying that the LED has been shifted to the CZ and an AT lamp for notifying that the LED has been shifted to the AT may be provided.

(5) In the example of FIG. 3, one of the eight light emitting parts is unused for all the DGs included in the first DG group. However, two or more unused DGs may be included for at least one DG among all the DGs included in the first DG group. Even with such a configuration, the same effect as that of the present embodiment can be obtained.

(6) In the example of FIG. 6, as shown in FIG. 6D, it has been described that the number of LEDs to be turned off is two. However, the number of LEDs to be turned off may be three or more. In this case, it is preferable that the output terminals corresponding to the three or more LEDs to be turned off are adjacent to each other. Even with such a configuration, the same effect as that of the present embodiment can be obtained.

(7) In the present embodiment, as shown in DG5 of the first DG group in FIG. 3, a predetermined event, that is, a set number of bets, being replayed, being an advantageous section, and a start operation are effective. It was explained that all the facts and the possibility of inserting medals are notified by the light emission of the LED. However, at least one of the predetermined events may be notified by other means together with the light emission of the LED or in place of the light emission of the LED. The other means is, for example, at least one of a liquid crystal display 51 capable of displaying predetermined information and a sound output means capable of outputting predetermined sound.

(8) In the present embodiment, by outputting a light emitting signal from the output terminal of the output port, the light emitting unit corresponding to the output terminal is made to emit light, and by not outputting the light emitting signal from the output terminal, the output terminal is used. It has been described that the light emitting unit corresponding to the above is not made to emit light. However, other control may be used to switch between light emission and non-light emission of the light emitting unit. For example, by not outputting the non-emission signal from the output terminal of the output port, the light emitting unit corresponding to the output terminal is made to emit light, and by outputting the non-emission signal from the output terminal, the light emission corresponding to the output terminal is emitted. The part may not emit light.

(9) It has been described that all of the plurality of light emitting units of the present embodiment either emit light or turn off. However, there may be two or more types of light emitting modes of at least one light emitting unit among the plurality of light emitting units. For example, at least one light emitting unit among the plurality of light emitting units may be capable of emitting light to any of the plurality of colors. For example, the light emitting unit may be capable of emitting light in red or may be capable of emitting light in blue. In this case, the light emitting signal that specifies the light emitting mode of the light emitting unit may be a signal that specifies the light emitting color.

It should be considered that the embodiments disclosed this time are exemplary in all respects and not restrictive. The scope of the present invention is shown by the scope of claims rather than the above description, and it is intended to include all modifications within the meaning and scope equivalent to the scope of claims.

1 slot machine, 2L, 2C, 2R reel, 8L, 8C, 8R stop switch, 12 payout display, 41 main control unit, 41c RAM, 51 liquid crystal display, 56 production switch, 91 sub control unit, 91c RAM.

Claims (1)

It is a gaming machine that can play games,
Advantage setting means that can set the advantage for the player,
The advantage confirmation state control means for controlling the advantage confirmation state for confirming the advantage set by the advantage setting means, and the advantage confirmation state control means.
The first advantageous notification execution control means for controlling the execution of the first advantageous notification for notifying the advantageous state, and
A second advantageous notification execution control means for controlling the execution of the second advantageous notification for notifying the advantageous state, and
An error state control means for controlling an error state in which the game cannot proceed when an abnormality occurs in the game machine, and an error state control means.
And an error notification execution control means for controlling the execution of an error notification to notify that it is controlled by the error condition,
The first advantageous notification execution control means continues the execution of the first advantageous notification when the advantage confirmation state control means controls the advantage confirmation state in the advantageous state.
When the error condition control means is controlled on the error condition in the preferred state,
The error notification execution control means to start execution of said error notification,
The first advantage notification execution control means, to continue the execution of the first preferred notification,
The second advantageous notification execution control means interrupts the execution of the second advantageous notification.
When the error state control means controls the error state in the advantageous state, when a power failure occurs and recovers from the power failure,
The error state control means resumes control of the error state and
The error notification execution control means restarts the execution of the error notification.
The first advantageous notification execution control means is a gaming machine that restarts the execution of the first advantageous notification.

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