JP6942511B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device having a transistor structure and a constant voltage diode in one chip.

Conventionally, elements for protecting ICs (Integrated Circuits) are incorporated in various control circuits. For example, Patent Documents 1 and 2 disclose a diode as such an IC protection element.

Japanese Unexamined Patent Publication No. 2012-154119 Japanese Unexamined Patent Publication No. 2014-17701

As the functions of sensors controlled by ICs, displays for mobile devices, cameras, and the like increase, the current consumption of ICs tends to increase. Therefore, when a diode is used as the protection element of the IC, the chip size of the protection element must be increased according to the current consumption of the IC, and it is difficult to meet the demand for miniaturization of the device.
On the other hand, a transistor has a potential as a substitute element for a diode because it can achieve low power consumption even if it is smaller than a diode. However, it is difficult for the transistor alone to exhibit the reverse voltage prevention and overvoltage protection characteristics required to protect the IC.

An object of the present invention is to provide a semiconductor device in which a transistor and a constant voltage diode are integrated into one chip, which has low power consumption and can exhibit reverse voltage prevention and overvoltage protection for an external device such as an IC. It is to be.

The semiconductor device according to the embodiment of the present invention faces the p-type source region, the p-type drain region, the n-type body region between the p-type source region and the p-type drain region, and the n-type body region. A semiconductor layer having a transistor structure including a gate electrode and a constant voltage diode provided in the semiconductor layer, an n-type portion connected to the p-type source region and a p-type portion connected to the gate electrode. The transistor structure and the constant voltage diode are integrated into one chip, including the constant voltage diode having the above.

The transistor structure of this semiconductor device is directly under the gate electrode by applying a negative voltage to the source or a positive voltage (the gate is ground (0V)) to the source. It contains a p-channel type MISFET that induces holes in the n-type body region to turn it on.
For example, when a voltage is applied in which the p-type drain region is positive (+) and the p-type source region is negative (-) while the gate electrode is grounded to the ground potential, a parasitic diode (p-type drain) built into the transistor structure is applied. A forward bias is applied to the pn diode) consisting of the pn junction between the region and the n-type body region. As a result, a current flows from the drain side to the source side via the parasitic diode. The flow of current from the drain side to the source side causes the source to have a positive potential with respect to the gate (that is, the gate has a negative potential with respect to the source), which causes holes in the n-type body region directly below the gate electrode. Is induced and the transistor is turned on. Therefore, when used by connecting to an external device such as an IC, a forward current can be passed through a transistor structure having less loss and lower power consumption than a diode, so that a small chip can be adopted. As a result, space can be saved in electronic devices and the like.

On the other hand, when the load controlled by the IC is inductive, if the current flowing through the load is cut off, a counter electromotive force is generated in the load. Due to this counter electromotive force, a voltage that makes the p-type source region side positive (+) may be applied between the p-type source region and the p-type drain region. In such a case, since a reverse bias is applied to the parasitic diode, no current flows through the internal circuit of the IC, and the IC can be protected. At this time, a reverse bias is also applied to the pn junction between the p-type portion and the n-type portion of the constant voltage diode. Therefore, when the countercurrent force of the load is large or when a large voltage such as static electricity or surge voltage is applied, the constant voltage diode Zener breakdowns and the reverse current passes through the constant voltage diode on the gate side (ground potential side). ), Therefore, it is possible to prevent a large current from flowing to the IC.

From the above, if the semiconductor device according to the embodiment of the present invention is used as a protection element for an IC such as an electronic device, reverse voltage prevention and overvoltage protection for an external device such as an IC can be realized while having low power consumption. Therefore, the protective function as a protective element can be maintained. Moreover, since the transistor structure and the constant voltage diode are integrated into one chip, further space saving can be achieved as compared with the case where these are mounted as separate chips in the device.

In the semiconductor device according to the embodiment of the present invention, the semiconductor layer includes an active region including the transistor structure and an outer peripheral region surrounding the active region, and the zener diode is arranged along the outer peripheral region. The outer peripheral diode may be included.
According to this configuration, the junction area between the p-type portion and the n-type portion of the constant voltage diode can be increased, so that the resistance value of the constant voltage diode can be reduced and the power consumption can be reduced. As a result, the loss in the constant voltage diode can be reduced and thermal destruction can be prevented.

In the semiconductor device according to the embodiment of the present invention, in the outer peripheral diode, the p-type portion and the n-type portion may be formed in a shape surrounding the active region, respectively.
According to this configuration, since the pn junction between the p-type portion and the n-type portion of the constant voltage diode has an integrated structure surrounding the active region, the loss in the constant voltage diode can be further reduced.

In the semiconductor device according to the embodiment of the present invention, the p-type portion and the n-type portion may have the same width as each other.
In the semiconductor device according to the embodiment of the present invention, in the outer peripheral diode, the n-type portion may be arranged inside the p-type portion.
In the semiconductor device according to the embodiment of the present invention, the zener diode may be made of polysilicon laminated on the semiconductor layer.

According to this configuration, the gate electrode and the constant voltage diode can be formed in the same process by configuring the constant voltage diode with polysilicon, which is generally used as the material of the gate electrode.
In the semiconductor device according to the embodiment of the present invention, the transistor structure may include a trench gate structure made of polysilicon in which the gate electrode is embedded in a gate trench formed in the semiconductor layer.

In the semiconductor device according to the embodiment of the present invention, the zener diode may consist of an impurity region arranged in the semiconductor layer.
In the semiconductor device according to the embodiment of the present invention, the yield voltage of the constant voltage diode may be 8 V or less.
The semiconductor device according to the embodiment of the present invention may have a vertical and horizontal chip size of 0.6 mm × 0.4 mm or less.

With a semiconductor device of this size, it is possible to reduce the size of the electronic device on which the semiconductor device is mounted.

FIG. 1 is a schematic plan view of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a schematic bottom view of the semiconductor device according to the embodiment of the present invention. FIG. 3 is a schematic plan view of the semiconductor element of FIG. FIG. 4 is a diagram showing a cross section of the IV-IV cut surface of FIG. FIG. 5 is a schematic view for explaining the planar shape of the constant voltage diode. FIG. 6 is a diagram showing a part of a protection circuit to which the semiconductor device of FIG. 1 is connected. FIG. 7 is a diagram for comparing the power consumption of the MOSFET and the Schottky barrier diode (SBD). FIG. 8 is a diagram for explaining the difference in the effective area between the outer peripheral diode and the pad diode. FIG. 9 is a diagram for comparing the power consumption of the outer peripheral diode and the pad diode. 10A and 10B are diagrams for explaining the structural difference between the zener diode and the ESD protection diode. FIG. 11 is a diagram for explaining the effect of reducing the power consumption of the MOSFET after reducing the space of the outer peripheral diode. FIG. 12 is a diagram for comparing the yield voltage of the constant voltage diode and the ESD protection diode. FIG. 13 is a diagram showing another form of the semiconductor element of FIG. FIG. 14 is a diagram showing another form of the semiconductor device of FIG. FIG. 15 is a perspective view of a semiconductor device according to another embodiment of the present invention. FIG. 16 is a front view of the semiconductor device of FIG. FIG. 17 is a rear view of the semiconductor device of FIG. FIG. 18 is a plan view of the semiconductor device of FIG. FIG. 19 is a bottom view of the semiconductor device of FIG. FIG. 20 is a right side view of the semiconductor device of FIG. FIG. 21 is a left side view of the semiconductor device of FIG. FIG. 22 is a diagram showing a cross section of the cut surface of XXII-XXII of FIG. FIG. 23 is a diagram for comparing the chip sizes of the semiconductor device of FIG. 15 and the semiconductor device according to the reference embodiment.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a schematic plan view of a semiconductor device 1 according to an embodiment of the present invention. FIG. 2 is a schematic bottom view of the semiconductor device 1 according to the embodiment of the present invention. In FIG. 1, the inside of the package is seen through so that the structure of the semiconductor device 1 can be easily understood.
The semiconductor device 1 is configured as a so-called surface mountable relatively small semiconductor device. As an example of the size of the semiconductor device 1, the dimension L in the vertical direction is about 0.6 mm, the dimension W in the width direction is about 0.4 mm, and the dimension in the thickness direction is about 0.36 mm.

The semiconductor device 1 includes a semiconductor element 2, a main lead 3, a first sub-lead 4, a second sub-lead 5, a first wire 6, a second wire 7, and a resin package 8.
The semiconductor element 2 is configured as a so-called transistor. A gate metal 9 and a source metal 10 are formed on the surface of the semiconductor element 2. Although not shown in FIGS. 1 and 2, a drain electrode 11 (described later) is formed on the back surface of the semiconductor element 2.

The main reed 3 is arranged at one end in the longitudinal direction of the resin package 8. At the other end in the longitudinal direction on the opposite side, the first sub-lead 4 and the second sub-lead 5 are arranged at both corners of the resin package 8, respectively.
The main reed 3 supports the semiconductor element 2 from the back surface side and is electrically connected to the drain electrode 11 (described later). The main lead 3 includes a substantially quadrangular main portion 12 and a plurality of projecting portions 13 that selectively project from the end faces of the main portion 12 in a plan view.

The semiconductor element 2 is bonded to the front surface 14 of the main portion 12, and the back surface 15 of the main portion 12 is exposed from the outer surface of the resin package 8. As is clear from FIG. 1, when the sizes of the front surface 14 and the back surface 15 of the main portion 12 are compared, the front surface 14 is larger than the back surface 15. For example, the back surface 15 is configured to have a size slightly larger than the semiconductor element 2 so that its outer edge surrounds the semiconductor element 2, and the front surface 14 is configured to have a size even larger than the back surface 15. That is, in the main portion 12, the support region of the semiconductor element 2 constituting the back surface 15 is selectively formed to be thick, and a part of this region is exposed from the outer surface of the resin package 8 as the back surface 15. The back surface 15 is used as a drain terminal of the semiconductor device 1.

The projecting portion 13 projects from, for example, the opposite end faces of the first sub-lead 4 and the second sub-lead 5 in the main portion 12 and the side end faces of the end faces. That is, in this embodiment, the protruding portion 13 projects from all the end faces of the main portion 12 except the end faces facing the first sub-lead 4 and the second sub-lead 5. Each protrusion 13 is exposed from the outer surface of the resin package 8.

The first sub-lead 4 is formed in a quadrangular shape in a plan view. The first wire 6 is connected to the surface 16 of the first sub-lead 4. The first wire 6 is connected to the gate metal 9. As a result, the first sub-lead 4 is electrically connected to the gate metal 9 via the first wire 6. Similar to the main portion 12, the first sub-lead 4 is selectively formed to have a thick region forming the back surface 17, and a part of this region is exposed from the outer surface of the resin package 8 as the back surface 17. Further, the two side surfaces 18 and 18 of the first sub-lead 4 are exposed from the outer surface of the resin package 8 so as to form the corners of the resin package 8. The back surface 17 and the side surfaces 18 and 18 exposed from the outer surface of the resin package 8 are used as gate terminals of the semiconductor device 1.

The second sub-lead 5 is formed in a quadrangular shape in a plan view. A second wire 7 is connected to the surface 19 of the second sub-lead 5. The second wire 7 is connected to the source metal 10. As a result, the second sub-lead 5 is electrically connected to the source metal 10 via the second wire 7. Similar to the main portion 12, the second sub-lead 5 is selectively formed to have a thick region forming the back surface 20, and a part of this region is exposed from the outer surface of the resin package 8 as the back surface 20. Further, the two side surfaces 21 and 21 of the second secondary lead 5 are exposed from the outer surface of the resin package 8 so as to form the corners of the resin package 8. The back surface 20 and the side surfaces 21 and 21 exposed from the outer surface of the resin package 8 are used as source terminals of the semiconductor device 1.

The main reed 3, the first sub-lead 4, and the second sub-lead 5 can be collectively formed by, for example, patterning a metal plate made of Cu by etching or the like.
The resin package 8 covers the semiconductor element 2, a part of each of the main lead 3, the first sub-lead 4, and the second sub-lead 5, the first wire 6, and the second wire 7, for example, black. It consists of epoxy resin.

FIG. 3 is a schematic plan view of the semiconductor element 2 of FIG. FIG. 4 is a diagram showing a cross section of the IV-IV cut surface of FIG. FIG. 5 is a schematic view for explaining the planar shape of the zener diode 29.
The semiconductor element 2 is an element provided with a p-type channel MISFET having a trench gate structure, and is a semiconductor layer 22, a p ^- type drain region 23, an n-type body region 24, a p ⁺ type source region 25, and an n ⁺ type body contact region. 26, a gate insulating film 27, a gate electrode 28, a constant voltage diode 29, an interlayer insulating film 30, a gate metal 9, a source metal 10 and a drain electrode 11.

The semiconductor layer 22 may include, for example, a p ⁺ type substrate 31 and ^{a p −} type epitaxial layer 32 formed by growing a semiconductor crystal on the ^{p + type substrate 31.} The p ⁺ type substrate 31 and the p ⁻ type epitaxial layer 32 are made of silicon (Si) in this embodiment, but may be made of other semiconductors (for example, SiC, GaN, etc.). regard p ⁺ -type substrate 31, the thickness thereof may be about 40Myuemu～250myuemu, the p-type impurity concentration may be about ^{1 × 10 21 cm -3 ~1 ×} 10 22 cm -3. On the other hand, ^{the thickness of the p-} type epitaxial layer 32 may be about 3 μm to 8 μm, and the p-type impurity concentration is about 1 × 10 ¹⁶ cm ^-3 to 1 × 10 ¹⁷ cm ^-3. May be good. Further, the semiconductor layer 22 is set with an active region 40 in which a transistor structure is mainly arranged and an outer peripheral region 41 surrounding the active region 40.

The p ^- type drain region 23 is an ^{impurity region that occupies most of the p-} type epitaxial layer 32 in the active region 40. As will be described later, in this embodiment, ^{impurity regions such as the n-type body region 24, the p +} -type source region 25, and the n ⁺ -type body contact region 26 are ^{selectively formed in the p-} type epitaxial layer 32. ^{The p-} type region excluding these impurity regions 24 to 26 may be the p ^- type drain region 23. Therefore, the p ^- type drain region 23 may have a p-type impurity concentration of ^{1 × 10 16} cm ^-3 to 1 × 10 ¹⁷ cm ^-3.

The n-type body region 24 is an impurity region selectively formed on the surface portion ^{of the p-type epitaxial layer 32 in the active region 40.} As a result, the semiconductor element 2 contains a pn diode (parasitic diode 51) including a pn junction between the ^{p-type drain region 23 and the n-type body region 24.} Further, the n-type body region 24 may have an n-type impurity concentration of ^{2 × 10 16} cm ^-3 to 2 × 10 ¹⁷ cm ^-3.

The p ⁺ type source region 25 is an impurity region formed on the surface of the n-type body region 24. Further, the p ⁺ type source region 25 may have a p-type impurity concentration of ^{1 × 10 21} cm ^{-3 to} 5 × 10 ²¹ cm ^-3.
n ⁺ -type body contact region 26, p ^- through the ^{p +} -type source region 25 from the surface of the type epitaxial layer 32 is an impurity region reaching n-type body region 24. As a result, the n-type body region 24 can be electrically connected from the surface side of ^{the p- type epitaxial layer 32 via the n +} type body contact region 26. Further, the n ⁺ type body contact region 26 may have an n-type impurity concentration of ^{1 × 10 21} cm ^{-3 to} 5 × 10 ²¹ cm ^-3.

The semiconductor layer 22 is formed with a gate trench 59 ^{that penetrates the p +} type source region 25 and the n-type body region 24 from the surface of the semiconductor layer 22 ^{and reaches the p − type drain region 23.} The gate trench 59, p ^- may be formed in a lattice shape in the surface portion of the type epitaxial layer 32, it may be formed in a stripe shape. As a result, the plurality of n-type body regions 24 may be arranged in a matrix or stripe in a plan view. In the n-type body region 24, a channel region 33 is formed on a side surface portion of the gate trench 59.

The gate insulating film 27 is made of, for example, silicon oxide (SiO ₂ ) and is formed on the inner surface of the gate trench 59. The gate insulating film 27 is formed so as to extend to the outer peripheral region 41 in addition to the active region 40. That is, an insulating film formed in the same process is formed in the active region 40 and the outer peripheral region 41. In this embodiment, the insulating film on the outer peripheral region 41 is also referred to as the gate insulating film 27, but since the gate insulating film 27 does not contribute to the switching of the transistor structure, it may be referred to by another name.

The gate electrode 28 is made of polysilicon, for example, and is embedded in the gate trench 59 via the gate insulating film 27. The gate electrode 28 faces the channel region 33 via the gate insulating film 27.
The zener diode 29 is made of polysilicon in this embodiment and is formed on the gate insulating film 27. The constant voltage diode 29 can be formed in the same process as the gate electrode 28. As shown in FIG. 5, the constant voltage diode 29 is configured as an outer peripheral diode formed on the peripheral edge of the semiconductor element 2 along the outer peripheral region 41. The entire constant voltage diode 29 as the outer peripheral diode may be arranged in the outer peripheral region 41, or as shown in FIGS. 4 and 5, a part thereof is arranged in the outer peripheral region 41 and the rest is arranged in the outer peripheral region 41. It may be arranged in the active region 40. That is, the constant voltage diode 29 may be formed so as to straddle between the active region 40 and the outer peripheral region 41.

The zener diode 29 includes a p-type portion 34 and an n-type portion 35. The p-type portion 34 and the n-type portion 35 are each composed of impurity regions in the polysilicon film, and the zener diode 29 is composed of a pair of p-type portions 34 and n-type portions 35 adjacent to each other. There is. The p-type portion 34 and the n-type portion 35 are each formed in an annular shape surrounding the active region 40. As a result, the pn junction 36 between them has an annular integral structure surrounding the active region 40. Further, in this embodiment, the p-type portion 34 and the n-type portion 35 may have the same width W ₁ and width W ₂ , respectively. Further, regarding the arrangement form, the n-type portion 35 may be arranged inside the p-type portion 34. As will be described later, since the p-type portion 34 is connected to the gate metal 9, by keeping the p-type portion 34 on the outside, the gate finger 42 (described later) routed to the peripheral portion of the semiconductor element 2 and the gate finger 42 (described later). The connection structure of can be simplified. For example, it is only necessary to extend the contact directly below the gate finger 42.

The yield voltage Vz of the constant voltage diode 29 is set to, for example, 10 V or less, preferably 6.8 V to 8 V. The yield voltage Vz in this range can be realized, for example, by appropriately setting the p-type impurity concentration of the p-type portion 34 and the n-type impurity concentration of the n-type portion 35. For example, the p-type impurity concentration of the p-type portion 34 is 1 × 10 ¹⁶ cm ^-3 to 1 × 10 ¹⁷ cm ^-3, and the n-type impurity concentration of the n-type portion 35 is 1 × 10 ²¹ cm ^{-3 to} 5 × 10. ^This can be achieved by setting the size to 21 cm- ^3.

The interlayer insulating film 30 is made of, for example, silicon oxide (SiO ₂ ), and is formed on the ^p- type epitaxial layer 32 so as to cover the gate electrode 28 and the constant voltage diode 29. The interlayer insulating film 30 includes ^{a contact hole 37 that exposes the p +} type source region 25 and the n ⁺ type body contact region 26, a contact hole 38 that exposes the p-type portion 34 of the constant voltage diode 29, and a constant voltage diode 29. A contact hole 39 that exposes the n-type portion 35 is formed.

The gate metal 9 and the source metal 10 are composed of an electrode film formed on the interlayer insulating film 30. For the gate metal 9 and the source metal 10, the electrode film material (for example, a metal containing Al) is deposited on the interlayer insulating film 30 by a sputtering method or the like, and then the electrode film is patterned by etching or the like. Can be formed by. That is, the gate metal 9 and the source metal 10 may be formed in the same process.

The gate metal 9 includes a gate finger 42 and a gate pad 43.
As shown in FIG. 3, the gate finger 42 is formed in a substantially square ring along the peripheral edge of the semiconductor element 2 in a plan view, and an active region 40 is set in a region surrounded by the gate finger 42. ing. The gate finger 42 is connected to the p-shaped portion 34 of the constant voltage diode 29 via the contact hole 38. The gate finger 42 is also connected to the gate electrode 28 via a contact hole (not shown) formed in the interlayer insulating film 30.

The gate pad 43 is provided at one corner of the gate finger 42. The gate pad 43 is formed so as to be integrally connected to the gate finger 42. The first wire 6 described above is connected to the gate pad 43.
The source metal 10 is arranged in the area surrounded by the gate finger 42 and the gate pad 43. The source metal 10 and the gate finger 42 and the gate pad 43 are separated by a removal region 44 formed by etching the electrode film. ^{The source metal 10 is connected to the p +} type source region 25 and the n ⁺ type body contact region 26 via the contact hole 37, and is connected to the n-type portion 35 of the constant voltage diode 29 via the contact hole 39. There is.

The drain electrode 11 is made of, for example, the same material as the gate metal 9 and the source metal 10, and may be formed on the entire back surface of the ^{p + type substrate 31.}
The semiconductor device 1 described above can be suitably used as a protective element for an IC (Integrated Circuit) mounted on all electronic devices such as mobile phones, smartphones, digital cameras, and video cameras, and is particularly small in size. Since it is a semiconductor device of the above, it is most suitable for mobile phones and smartphones where miniaturization is promoted.

Next, the operation of circuit protection by the semiconductor device 1 will be described with reference to FIG. FIG. 6 is a diagram showing a part of a protection circuit to which the semiconductor device 1 of FIG. 1 is connected. The protection circuit diagram of FIG. 6 is shown in FIG.
This is merely an example of use of the semiconductor device 1, and the connection form of the semiconductor device 1 is not limited to the configuration shown in FIG.
The protection circuit 45 shown in FIG. 6 includes an IC 46 and a semiconductor device 1.
The IC 46 may be various general-purpose ICs such as a power management IC for smartphones and a transmission / reception control IC. The IC 46 has, for example, a power supply terminal 47 (Vcc), an output terminal 48 (OUT), and a ground terminal 49 (GND). The power supply terminal 47 is connected to the power supply 50, and the ground terminal 49 is grounded to the ground potential.

The drain terminal D (main reed 3 in FIG. 2) of the semiconductor device 1 is connected to the output terminal 48 of the IC 46, and the source terminal S (second sub reed 5 in FIG. 2) is loaded as the output terminal OUT of the semiconductor device 1. It is connected to (not shown). Further, the gate terminal G (first sub-reed 4 in FIG. 2) of the semiconductor device 1 is grounded to the ground potential.
According to FIG. 6, in the protection circuit 45, a voltage is applied in which the drain terminal D is positive (+) and the source terminal S is negative (−). That is, since ^{a voltage is applied in which the p −} type drain region 23 is positive (+) and the p ⁺ type source region 25 is negative (−), the voltage is forward to the parasitic diode 51 built in the semiconductor element 2. A bias will be applied. As a result, a current flows from the drain terminal D side to the source terminal S side via the parasitic diode 51. When a current flows from the drain terminal D side to the source terminal S side, the source becomes a positive potential with respect to the gate (that is, the gate becomes negative with respect to the source), whereby the n-type directly under the gate electrode 28 is formed. Holes are induced in the channel region 33 (see FIG. 4) of the above, and the transistor is turned on.

Here, FIG. 7 is a diagram for comparing the power consumption of the MOSFET and the Schottky barrier diode (SBD). In FIG. 7, the solid lines of (1), (2) and (3) are 1006 size (length x width = 1.0 mm x 0.6 mm) Schottky barrier diodes and 2512 size (length x width = 2), respectively. The relationship between the current and power consumption of a Schottky barrier diode (0.5 mm × 1.2 mm) and a p-channel MOSFET of 0604 size (length × width = 0.6 mm × 0.4 mm) is shown. As shown in FIG. 7, the Schottky barrier diodes (1) and (2) need to be increased in size from 1006 size to 2512 size in order to suppress power consumption in accordance with the increasing current consumption of ICs. On the other hand, the MOSFET has low power consumption even in the 0604 size, which is considerably smaller than the 2512 size.

Therefore, if the semiconductor device 1 is connected to the IC 46 and used, a forward current can be passed through the transistor structure having less loss and lower power consumption than the diode, so that a small chip can be adopted. As a result, space saving can be achieved by using the semiconductor device 1 as a protective element for the IC 46 of an electronic device or the like.
On the other hand, when the load controlled by the IC 46 is inductive, if the current flowing through the load is cut off, a counter electromotive force is generated in the load. Due to this counter electromotive force, a voltage at which the p ⁺ type source region 25 side becomes positive (+) may be applied between the p ⁺ type source region 25 − p ⁻ type drain region 23. In such a case, since a reverse bias is applied to the parasitic diode 51, no current flows through the internal circuit of the IC 46, and the IC 46 can be protected. At this time, a reverse bias is also applied to the pn junction 36 of the constant voltage diode 29. Therefore, when the countercurrent force of the load is large or when a large voltage such as static electricity or surge voltage is applied, the constant voltage diode 29 Zener breakdowns and the reverse current passes through the constant voltage diode 29 on the gate side (ground). Since it flows to the potential side), it is possible to prevent a large current from flowing to the IC46.

From the above, if the semiconductor device 1 is used as a protection element for an IC 46 of an electronic device or the like, it is possible to exhibit reverse voltage prevention and overvoltage protection related to the IC 46 while consuming low power consumption. Can be maintained. Moreover, since the transistor structure and the constant voltage diode 29 are integrated into one chip, further space saving can be achieved as compared with the case where these are mounted as separate chips.

On the other hand, as shown in FIG. 7, the smaller the diode, the larger the power consumption. Therefore, in the miniaturized semiconductor device 1, it is preferable to consider the power consumption (loss) of the constant voltage diode 29.
Here, the loss reduction of the constant voltage diode 29 in the semiconductor device 1 according to this embodiment will be described with reference to FIGS. 8 and 9. FIG. 8 is a diagram for explaining the difference in the effective area between the outer peripheral diode and the pad diode. FIG. 9 is a diagram for comparing the power consumption of the outer peripheral diode and the pad diode. Note that FIG. 8 emphasizes the planar configuration of the semiconductor element 2 necessary for the description in this section, and therefore the size, shape, and the like do not match those of FIG.

As shown in FIG. 8, in the semiconductor element 61 on the left side of the paper surface, the constant voltage diode 29 is configured as a pad diode formed on the outer periphery of the gate pad 43, while the semiconductor element 2 on the right side of the paper surface is used as the above-mentioned outer peripheral diode. It is configured. In this case, although it depends on the size of the semiconductor element 2 and the gate pad 43, if the constant voltage diode 29 is configured as an outer peripheral diode, the pn junction 36 is compared with the case where it is configured as a pad diode, for example. The area (see FIGS. 4 and 5) is increased by 50%. As a result, the junction resistance of the pn junction 36 can be reduced, so that the power consumption can be reduced from 101 mW to 84 mW as shown in FIG. That is, since the loss in the constant voltage diode 29 can be reduced, the thermal destruction of the constant voltage diode 29 can be prevented, and the reliability of the semiconductor device 1 can be improved. The specific numerical value of the power consumption shown in FIG. 9 is an example given to explain the effect of loss reduction.

While the loss of the constant voltage diode 29 can be reduced, since the constant voltage diode 29 is arranged so as to surround the active region 40, the arrangement area of the cell of the transistor structure is limited as compared with the case where the pad diode is adopted. For example, increasing the area of the pn junction by 50% is expected to reduce the area of the active region 40 by 20%.
However, the estimated value of the area reduction amount of the active region 40 in FIG. 8 is a semiconductor device equipped with a bidirectional Zener diode 52 in order to protect the transistor structure, such as the ESD protection diode shown as the reference structure in FIG. 10A. It is based on the structure of. In this structure, since the bidirectional Zener diode 52 has a repeating structure of a plurality of p-type portions 53 and n-type portions 54, a relatively wide diode arrangement space is required.

On the other hand, as shown in FIG. 10B, the constant voltage diode 29 of this embodiment is composed of a pair of p-type portions 34 and n-type portions 35 adjacent to each other, so that the diode arrangement space can be narrowed. The reduced space can be allocated to the cell arrangement space of the transistor structure. As a result, as shown in FIG. 11, the power consumption of the transistor (MOSFET) can be reduced by, for example, 17%, and the low power consumption of the transistor can be maintained. Further, by using the constant voltage diode 29 composed of a pair of p-type portions 34 and n-type portions 35, the breakdown voltage Vz can be lowered as compared with the bidirectional Zener diode 52.

The constant voltage diode according to the embodiment of the present invention is, for example, ^{a pair of p +} type impurity regions 55 and n type ^{arranged in the p −} type epitaxial layer 32 as in the semiconductor element 62 of FIG. The constant voltage diode 58 composed of the impurity region 56 may be used. In FIG. 13, the n ⁺ type impurity region 57 formed on the surface of the n-type impurity region 56 is an impurity region for contacting the n-type impurity region 56.

Further, as shown in FIG. 14, the constant voltage diode 29 may have a configuration in which p-type portions 34 and n-type portions 35 are alternately arranged along the outer peripheral region 41. In this case, it is necessary to contact the plurality of p-type portions 34 and the plurality of n-type portions 35 separated from each other from the source side and the gate side, respectively.
Further, the structure of the transistor of the semiconductor element 2 is not limited to the trench gate structure, and may be a trench planar gate structure.

Next, other embodiments of the semiconductor device will be described. FIG. 15 is a perspective view of the semiconductor device 71 according to another embodiment of the present invention. FIG. 16 is a front view of the semiconductor device 71. FIG. 17 is a rear view of the semiconductor device 71. FIG. 18 is a plan view of the semiconductor device 71. FIG. 19 is a bottom view of the semiconductor device 71. FIG. 20 is a right side view of the semiconductor device 71. FIG. 21 is a left side view of the semiconductor device 71. FIG. 22 is a diagram showing a cross section of the cut surface of XXII-XXII of FIG.

The semiconductor device 71 has a WL-CSP (Wafer Level-Chip Size Package) package structure. That is, the semiconductor device 71 has the above-mentioned semiconductor element 2 configured as a chip size level package, and has a plan-view rectangular semiconductor substrate 72 as an example of the above-mentioned semiconductor layer 22. The size is almost the same as the outer size of the semiconductor substrate 72.

For example, as shown in FIG. 15, the length L of the semiconductor device 71 is less than 0.50 mm (preferably 0.40 mm or more), and the width W is less than 0.40 mm (preferably 0.30 mm or more). Yes, the thickness D is less than 0.15 mm (preferably 0.10 mm or more).
For example, when the length L of the semiconductor device 71 is 0.50 mm and the width W is 0.40 mm, the plane area of the semiconductor device 71 is 0.20 mm ² . Further, when the length L of the semiconductor device 71 is 0.40 mm and the width W is 0.30 mm, the plane area of the semiconductor device 71 is 0.12 mm ² . That is, the semiconductor device 71 has a very small package structure of 0403 size.

Further, since the thickness of the semiconductor device 71 is less than 0.15 mm, even if the semiconductor device 71 is mounted at an angle, the amount of protrusion of the side surface of the semiconductor device 71 from the normal position can be reduced. As a result, even when the semiconductor device 71 is mounted at high density, contact with the adjacent semiconductor device can be suppressed.
Since the semiconductor device 71 has a WL-CSP package structure, when the shapes and sizes of the semiconductor device 71 and the semiconductor substrate 72, the arrangement positions of other components, and the like are described below, the subject of the description is It may be replaced with the other. For example, the plane-viewing quadrangular semiconductor substrate 72 may be replaced with the plan-viewing quadrangular semiconductor device 71, and the description that the pad is arranged on the peripheral edge of the semiconductor substrate 72 is described in the peripheral portion of the semiconductor device 71. It may be replaced with the explanation that the pad is arranged in.

The rectangular parallelepiped semiconductor substrate 72 has a front surface 72A, a back surface 72B on the opposite side of the front surface 72A, and four side surfaces 72C, 72D, 72E, 72F between the front surface 72A and the back surface 72B, and the front surface 72A and the side surface. 72C to 72F may be covered with a surface insulating film (not shown). Of the four side surfaces 72C to 72F of the semiconductor substrate 72, the side surfaces 72C and 72E are side surfaces along the long side 121 of the semiconductor substrate 72, and the side surfaces 72D and 72F are side surfaces along the short side 122 of the semiconductor substrate 72. Corner portions 74CD, 74DE, 74EF, 74FC of the semiconductor substrate 72 are formed at the intersections of the adjacent side surfaces 72C to 72F.

On the surface 72A of the semiconductor substrate 72, a drain pad 77 (first pad) is arranged on the first peripheral edge portion 75 along one side surface 72C on the long side 121 side. The drain pad 77 is formed at a central portion spaced from both end corner portions 74CD and 74FC of the first peripheral edge portion 75, and is formed at a fixed interval (for example, between the drain pad 77 and each corner portion 74CD and 74FC). , About 0.1 mm to 0.15 mm) is provided.

On the other hand, a source pad 78 (second pad) is arranged at one end corner portion 74EF of the second peripheral edge portion 76 of the semiconductor substrate 72 facing the first peripheral edge portion 75, and the other end corner portion 74DE of the second peripheral edge portion 76 is arranged. A gate pad 79 (third pad) is arranged in the.
Next, the layout and shape of the drain pad 77, the source pad 78, and the gate pad 79 will be described.

As shown in FIG. 18, the drain pad 77 has the apex V1 of one end corner portion 74EF of the second peripheral edge portion 76 as the center, and the length of the short side 122 of the semiconductor substrate 72 (width W in FIG. 15) as the radius. The first arc 80 and the second arc 81 centered on the apex V2 of the other end corner 74DE of the second peripheral edge 76 and having the length of the short side 122 of the semiconductor substrate 72 (width W in FIG. 15) as the radius. Is drawn on the surface 72A of the semiconductor substrate 72, it is located in the outer region of the first arc 80 and in the outer region of the second arc 81. The drain pad 77 has two sides of a pair of tangents drawn from the intersection 82 of the first arc 80 and the second arc 81 with respect to each of the first arc 80 and the second arc 81 in the outer region. It is formed in a triangular shape.

On the other hand, the source pad 78 is formed in a fan shape having the same center as the first arc 80. The radius R1 of the source pad 78 is, for example, 0.07 mm to 0.13 mm (preferably 0.10 mm or more). For example, when the radius R1 is 0.07 mm, the area of the source pad 78 is 3.85 × 10 ^-3 mm ² , and when the radius R1 is 0.10 mm, the area of the source pad 78 is 7.85 ×. It is 10 ^-3 mm ² .

Further, the gate pad 79 is formed in a fan shape having the same center as the second arc 81. The radius R2 of the gate pad 79 is, for example, 0.07 mm to 0.13 mm (preferably 0.10 mm or more). For example, when the radius R2 is 0.07 mm, the area of the gate pad 79 is 3.85 × 10 ^-3 mm ² , and when the radius R2 is 0.10 mm, the area of the gate pad 79 is 7.85 ×. It is 10 ^-3 mm ² .

Further, a drain wiring film 83, a source wiring film 84, and a gate wiring film 85 are provided between the drain pad 77, the source pad 78, and the gate pad 79 and the semiconductor substrate 72, respectively. These are made of, for example, a metal layer such as AlCu, and a barrier layer (for example, Ti, TiN, etc.) may be formed on the front and back surfaces thereof, if necessary. Further, the drain wiring film 83, the source wiring film 84, and the gate wiring film 85 may ^{be electrically connected to the above-mentioned p −} type drain region 23, p ⁺ type source region 25, and gate electrode 28, respectively.

As shown in FIG. 18, the gate wiring film 85 is formed in a similar plan view fan shape larger than the gate pad 79.
As shown in FIG. 18, the source wiring film 84 is formed so as to cover substantially half of the region on the second peripheral edge portion 76 side of the semiconductor substrate 72. Specifically, it is formed on the side surface 72F side in the longitudinal direction and on the side surface 72C side in the width direction with respect to the gate wiring film 85 so as to avoid the gate wiring film 85. Therefore, the arc portion of the plan view fan-shaped gate wiring film 85 is adjacent to the source wiring film 84.

As shown in FIG. 18, the drain wiring film 83 is formed so as to cover substantially half of the region on the first peripheral edge portion 75 side of the semiconductor substrate 72. As a result, the source wiring film 84 and the drain wiring film 83 are formed of wiring films having substantially the same area as each other, and the wiring resistance on the source side and the wiring resistance on the drain side can be made substantially the same.
Next, how much the mounting area of the semiconductor device 71 can be reduced by the layout and shape of the drain pad 77, the source pad 78, and the gate pad 79 described above will be described with reference to FIG. 23.

FIG. 23 is a diagram for comparing the chip sizes of the semiconductor device 71 and the semiconductor device 100 according to the reference embodiment. In FIG. 23, among the reference codes shown in FIGS. 15 to 22, only the reference codes necessary for comparison are shown, and the other reference codes are omitted for the sake of clarity.
First, when the source pad 78 and the gate pad 79 are arranged next to each other on the short side 122 of the semiconductor substrate 72 as in the semiconductor device 100 of the reference embodiment, the package size of the semiconductor device 100 is, for example, the length L. = 0.6 mm, width W = 0.4 mm. This is to secure at least a pitch P = 0.2 mm as the distance between the source pad 78 and the gate pad 79 in order to avoid a short circuit between the source and the gate in the short side direction. Further, the drain pad 77 is formed in a shape extending from one end corner portion to the other end corner portion of the short side 122. Therefore, if the package size is reduced without changing the pad layout, the pitch P between the source and the gate is less than 0.2 mm, which causes a problem of a short circuit between the source and the gate at the time of mounting. On the other hand, even if the source pad 78 and the gate pad 79 are arranged so as to be adjacent to each other on the long side 121, it is difficult to solve the problem of short circuit between the pads. This is because, in this pad layout, the drain pad 77 has a shape extending from one end corner to the other end corner of the long side 121 as shown by the reference code “77 ′” and the broken line. Therefore, as the package size decreases, the problem of short circuit between the source and the drain or between the gate and the drain arises.

On the other hand, in the configuration of the semiconductor device 71 described above, the source pad 78 and the gate pad 79 are arranged so as to be adjacent to each other on the long side 121. Further, the drain pad 77 is arranged at the center of the long side 121 of the semiconductor substrate 72, and a fixed interval region is provided between the drain pad 77 and both end corners 74CD and 74FC of the long side 121. ing. As a result, the distance between the drain pad 77 and the source pad 78 (pitch P1) and the distance between the drain pad 77 and the gate pad 79 (pitch P2) can be made longer than those of the semiconductor device 100 of the reference embodiment. Therefore, even if the package size of the semiconductor device 71 is reduced to, for example, a length L = 0.44 mm and a width W = 0.32 mm, the pitch P1 and the pitch P2 are the pitch P between the source and the gate in the semiconductor device 100. Can be maintained at 0.2 mm, which is equivalent to. That is, the distance secured between the pads is 0.20 / 0.32 = 62.5% or more of the short side 122 of the package of the semiconductor device 71. At least, when the short side 122 of the package is 0.40 mm, the distance secured between the pads is 0.20 / 0.40 = 50% or more of the short side 122 of the package of the semiconductor device 71. Further, when the package size of the semiconductor device 71 is 1.41 × 10 ^-1 mm ² and the pad radiuses R1 and R2 are 0.10 mm ^{, the pad area is 7.85 × 10 -3 mm 2} , so that the source The area (pad area) of the pad 78 and the gate pad 79 is 5% or more of the package size. Therefore, the size of the semiconductor substrate can be made smaller than that of the semiconductor device 100 while avoiding a short circuit at the time of mounting. This makes it possible to provide a miniaturized semiconductor device.

Further, in the semiconductor device 71, as shown in FIG. 18, the drain pads 77 are arranged in the outer regions of the first arc 80 and the second arc 81 having the length of the short side 122 as the radius, respectively. Therefore, as the pitch P1 and the pitch P2, it is possible to secure at least a length corresponding to the difference between the length of the short side 122 of the semiconductor device 71 and the size (width) of the source pad 78 and the gate pad 79. Further, the drain pad 77 is formed in a triangular shape having a pair of tangents drawn from the intersection 82 of the first arc 80 and the second arc 81 with respect to each of the first arc 80 and the second arc 81 as two sides. ing. As a result, it is possible to secure a sufficient bonding area for the drain pad 77 while reducing the size of the semiconductor device 71. Therefore, it is possible to suppress a decrease in the fixing strength at the time of mounting the semiconductor device 71.

Regarding ensuring the fixing strength at the time of mounting the semiconductor device 71, the source pad 78 and the gate pad 79 are further formed in a fan shape having the same center as the first arc 80 and the second arc 81, respectively. As a result, it is possible to secure a sufficient joining area for the source pad 78 and the gate pad 79 while ensuring a length of 0.2 mm as the pitch P1 and the pitch P2.

As described above, according to the semiconductor device 71, the mounting area can be reduced by about 40% as compared with the semiconductor device 100 of the reference form while sufficiently securing the pitch between adjacent pads and the bonding area of the pads. Although one embodiment of the present invention has been described above, the present invention can also be implemented in other embodiments.
For example, in the case of the package form shown in FIGS. 15 to 22, a horizontal MISFET in which the source region and the drain region are arranged at intervals in the lateral direction along the surface 72A is formed on the semiconductor substrate 72. You may.

In addition, various design changes can be made within the scope of the matters described in the claims.

1 Semiconductor device 2 Semiconductor element 22 Semiconductor layer 23 p ^- type drain region 24 n-type body region 25 p ⁺ type source region 28 Gate electrode 29 Constant voltage diode 31 p ⁺ type substrate 32 p ^- type epitaxial layer 34 p-type part 35 n Mold part 36 pn junction 40 Active area 41 Outer peripheral area 51 Parasitic diode 55 p ⁺ type impurity area 56 n type impurity area 57 n ⁺ type impurity area 58 Constant voltage diode 59 Gate trench 62 Semiconductor element 71 Semiconductor device 72 Semiconductor substrate

Claims (11)

A semiconductor layer having a transistor structure including a p-type source region, a p-type drain region, an n-type body region between the p-type source region and the p-type drain region, and a gate electrode facing the n-type body region. ,
A constant voltage diode provided on the semiconductor layer, each of which is composed of a pair of p-type portions and n-type portions adjacent to each other forming an end portion of the constant voltage diode, and the n-type portion is formed by the n-type portion. A zener diode in which a p-type source region is connected and the gate electrode is connected to the p-type portion is included.
A semiconductor device in which the transistor structure and the constant voltage diode are integrated into a single chip. The semiconductor layer includes an active region including the transistor structure and an outer peripheral region surrounding the active region.
The semiconductor device according to claim 1, wherein the zener diode includes an outer peripheral diode arranged along the outer peripheral region. The semiconductor device according to claim 2, wherein in the outer peripheral diode, the p-type portion and the n-type portion are each formed in a shape surrounding the active region. The semiconductor device according to claim 3, wherein the p-type portion and the n-type portion have the same width as each other. The semiconductor device according to claim 3 or 4, wherein in the outer peripheral diode, the n-type portion is arranged inside the p-type portion. The outer peripheral diode includes a repeating structure of the p-type portion and the n-type portion alternately arranged along the outer peripheral region.
The semiconductor device according to claim 2, wherein the gate electrode and the p-type source region are connected to each of the plurality of p-type portions and the plurality of n-type portions separated from each other. The semiconductor device according to any one of claims 1 to 6 , wherein the zener diode is made of polysilicon laminated on the semiconductor layer. The semiconductor device according to claim 7 , wherein the transistor structure includes a trench gate structure in which the gate electrode is made of polysilicon embedded in a gate trench formed in the semiconductor layer. The semiconductor device according to any one of claims 1 to 6 , wherein the zener diode comprises an impurity region arranged in the semiconductor layer. The semiconductor device according to any one of claims 1 to 9 , wherein the yield voltage of the constant voltage diode is 8 V or less. The semiconductor device according to any one of claims 1 to 10 , which has a vertical and horizontal chip size of 0.6 mm × 0.4 mm or less.

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