JP2004327538A - Semiconductor chip - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor chip which is kept high enough in resistance to ESD of a power supply system without reducing a user design region. <P>SOLUTION: A semiconductor integrated circuit having a plurality of power supply systems is mounted on a rectangular semiconductor chip 10. The semiconductor chip 10 includes I/O regions 11_1 and 11_2 and a chip corner 13_2 sandwiched between the I/O regions 11_1 and 11_2. An ESD protective region 13_20 equipped with an ESD protective circuit 13_21 composed of NMOS transistors 13_21a and 13_21b, and a resistor element 13_21c is provided in the above chip corner 13_2 to absorb a high voltage induced by an electrostatic discharge applied across power supply interconnecting lines 14_1, 14_2, and 14_3 of power supply systems having different voltages. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a rectangular semiconductor chip on which a semiconductor integrated circuit having a plurality of power supply systems is mounted.
[0002]
[Prior art]
2. Description of the Related Art In recent years, as a semiconductor integrated circuit is miniaturized and speeded up, a lower voltage is required in a core region formed in a central portion of a semiconductor chip on which the semiconductor integrated circuit is mounted. In the 1 / O region formed in the peripheral portion of the semiconductor chip, a dedicated power supply line for driving an output buffer circuit provided in the I / O region is provided independently, or a circuit of a circuit relatively weak to noise is provided. For this reason, power supply wiring of another system is often provided. In this case, an ESD protection circuit for avoiding destruction due to electrostatic discharge (ESD) is used corresponding to a plurality of different power supply wirings. As such an ESD protection circuit, a so-called gate-coupled protection NMOS circuit, an NTNMOS (NMOS TRIGGERED NMOS) circuit, an RC clamp circuit, and the like are known (see Non-Patent Document 1). In each of these circuits, an NMOS transistor is used as a protection element. In addition, these circuits are provided with a capacitor element and a resistance element for controlling the operation of the NMOS transistor according to the magnitude of the discharge voltage generated by the electrostatic discharge, and the capacitance value and the resistance value of these elements are provided. , And the transistor size of the NMOS transistor, etc. are each optimized according to the manufacturing process to be used. Non-Patent Document 1 also proposes a technique for protecting a circuit element from a surge current due to electrostatic discharge by the action of a parasitic NPN bipolar transistor formed by an NMOS transistor included in an ESD protection circuit.
[0003]
Here, a semiconductor chip equipped with a master slice type semiconductor integrated circuit such as a gate array or an embedded array, which has a short delivery time and easy design change, has a structure in which fixed basic cells are arranged in an array. In order to form the above-described ESD protection circuit on such a semiconductor chip, an existing transistor region in a core region or an I / O region of the semiconductor chip is used, or the ESD protection circuit is used. For example, a dedicated area for forming a protection circuit is newly provided (for example, see Patent Document 1).
[0004]
In addition, when an ESD protection circuit is provided on a semiconductor chip that employs a technique of covering the transistor surface with a compound of metal and silicon called a silicide (silicide film) in order to reduce the resistance value of the electrode surface of the transistor, the ESD protection circuit has a static electricity. There is disclosed a technique in which a region not covered with a silicide film is provided and an ESD protection circuit is formed in that region so that a large current due to discharge does not damage the ESD protection circuit itself (for example, see Patent Document 2). ).
[0005]
[Non-patent document 1]
"ESD in Silicon Integrated Circuits" (Ajith Amerasekera, Charvaka Davvery, "ESD in Silicon Integrated Circuits" Second Edition, John & Sons.
[Patent Document 1]
JP 2000-208706 A [Patent Document 2]
JP 2000-12788 A
[Problems to be solved by the invention]
However, in a semiconductor chip on which a master slice type semiconductor integrated circuit is mounted, in the above-described technology for forming an ESD protection circuit in an existing transistor area portion of a core area and an I / O area, the design of the ESD protection circuit is free. Therefore, it is difficult to secure a sufficiently large transistor size of the NMOS transistor constituting the ESD protection circuit. Therefore, there is a problem that it is difficult to ensure a sufficiently high ESD resistance.
[0007]
In addition, in the technique of newly providing a dedicated area for forming an ESD protection circuit, a user design area for the same chip size is reduced, resulting in a disadvantage in cost.
[0008]
Furthermore, in the technique of forming an ESD protection circuit in a region of a semiconductor chip that is not covered with a silicide film, generally, the characteristics (parameters) of all transistors in that region are designed to be the same, and are therefore handled by the ESD protection circuit. The magnitude of the surge current is uniformly restricted, so that it is difficult to secure an effective electrostatic discharge path for surge currents of various magnitudes, and there is a surface lacking in ESD resistance. Further, removing the silicide film may increase the resistance of the transistor electrode, and may cause a disadvantage that circuit performance is deteriorated.
[0009]
In view of the above circumstances, an object of the present invention is to provide a semiconductor chip having sufficiently high ESD resistance without reducing a user design area.
[0010]
[Means for Solving the Problems]
A semiconductor chip of the present invention that achieves the above object is a rectangular semiconductor chip on which a semiconductor integrated circuit having a plurality of power supply systems is mounted.
An I / O region arranged along each side for inputting / outputting a signal to / from the outside, and a central region formed by the I / O region and surrounded by the I / O region. And a plurality of power supply systems formed at least in one corner between two I / O regions formed along two adjacent sides, and a core region for performing a desired circuit function by performing input / output of And an ESD protection area having an ESD protection circuit for protecting at least one of any combination between the power supply and the power supply and the ground from static electricity.
[0011]
Here, it is preferable that the ESD protection region includes an NMOS transistor for ESD protection.
[0012]
The semiconductor chip of the present invention has an ESD protection circuit formed at at least one corner between two I / O regions formed along two adjacent sides and protecting between different power sources from static electricity. An ESD protection area is provided. Here, the above-mentioned ESD protection area is an area where wiring of a power supply and the like is provided, which is not generally used as a user design area of the semiconductor chip. Since the ESD protection circuit is formed in such a region, the size of the NMOS transistor constituting the ESD protection circuit can be sufficiently large without reducing the user design region in the semiconductor chip. Therefore, a sufficiently high ESD resistance is secured.
[0013]
It is also a preferable embodiment that the ESD protection NMOS transistor has a larger gate width per finger than the signal output NMOS transistor formed in the I / O region.
[0014]
As described above, when the gate width per finger of the NMOS transistor for ESD protection is increased, the capacitance value of the diode formed by the source / drain of the NMOS transistor and the substrate can be set large. For this reason, it is possible to give higher ESD resistance to a surge voltage due to electrostatic discharge.
[0015]
Further, it is also preferable that the ESD protection NMOS transistor is a transistor having a larger distance between the source and drain gate contacts than the signal output NMOS transistor formed in the I / O region.
[0016]
As described above, when the distance between the gate contact of the source and the drain of the NMOS transistor for ESD protection is increased, the series parasitic resistance value between the gate contact of the source and the drain can be set large. For this reason, it is possible to give higher ESD resistance to a surge voltage due to electrostatic discharge.
[0017]
Further, it is preferable that a source and a drain of the ESD protection NMOS transistor are connected to one of a power supply wiring and a ground wiring, and a gate is connected to one of the ground wirings via a resistor.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described.
[0019]
FIG. 1 is a schematic diagram of a first embodiment of a semiconductor chip of the present invention.
[0020]
The semiconductor chip 10 shown in FIG. 1 is a rectangular semiconductor chip on which a plurality of general-purpose transistors are built, and a master slice type semiconductor integrated circuit that realizes a desired circuit function by customized wiring is mounted.
[0021]
The semiconductor chip 10 includes I / O regions 11_1, 11_2, 11_3, and 11_4 that are arranged along each side and that perform input and output of signals to and from the outside.
[0022]
The semiconductor chip 10 has a signal input between the I / O regions 11_1, 11_2, 11_3, and 11_4 formed in a central region surrounded by the I / O regions 11_1, 11_2, 11_3, and 11_4. A core region 12 for outputting and realizing a desired circuit function is provided.
[0023]
Further, in this semiconductor chip 10, each chip corner portion sandwiched between two I / O regions 11_1, 11_4; 11_1, 11_2; 11_2, 11_3; 11_3, 11_4 formed along each two adjacent sides. 13_1, 13_2, 13_3, 13_4 (corresponding to an example of a corner according to the present invention) are formed. Further, the chip corner portion 13_2 is provided with an ESD protection region having an ESD circuit for avoiding electrostatic destruction, which will be described below.
[0024]
FIG. 2 is an enlarged view showing the chip corner portion 13_2 shown in FIG.
[0025]
The chip corner 13_2 shown in FIG. 2 is provided with an ESD protection area 13_20. In the chip corner portion 13_2, power supply lines 14_1, 14_2, and 14_3 of a power supply system having different power supply voltages are arranged. Further, in the present embodiment, the ground wiring of these three power supply systems is common, and is disposed in the chip corner portion 13_2 similarly to the power supply wiring, but is not shown. The ESD protection area 13_20 has an ESD protection circuit 13_21. The ESD protection circuit 13_21 has an NMOS transistor 13_21a having a drain connected to the power supply wiring 14_1 and a source connected to the power supply wiring 14_2, and a drain connected to the power supply wiring 14_2 and a source connected to the power supply wiring 14_3. NMOS transistor 13_21b, and a resistance element 13_21c provided between the gates of both NMOS transistors 13_21a and 13_21b and a ground wiring GND (not shown).
[0026]
In the ESD protection circuit 13_21, in a normal state in which a high voltage is not applied between the power supply lines 14_1, 14_2, and 14_3 due to electrostatic discharge, the gates of the NMOS transistors 13_21a and 13_21b are connected to the ground line GND via the resistance element 13_21c. Therefore, the gates of the NMOS transistors 13_21a and 13_21b are at the “L” level, and therefore, the NMOS transistors 13_21a and 13_21b are both in the off state.
[0027]
Here, it is assumed that a high voltage is applied between the power supply wirings 14_1 and 14_2 by electrostatic discharge, for example. Then, an “H” level voltage is applied to the gate of the NMOS transistor 13_21a via the parasitic capacitance of the NMOS transistor 13_21a, and the NMOS transistor 13_21a is turned on, and the high voltage applied between the power supply wirings 14_1 and 14_2. Voltage is absorbed. Further, when a high voltage is applied between the power supply lines 14_2 and 14_3, the NMOS transistor 13_21b is turned on, and the high voltage applied between the power supply lines 14_2 and 14_3 is absorbed. Further, when a high voltage is applied between the power supply lines 14_1 and 14_3, both the NMOS transistors 13_21a and 13_21b are turned on, and the high voltage applied between the power supply lines 14_1 and 14_3 is absorbed. At this time, the operation of the NPN bipolar Tr formed as a strange element of 13_21a, 13_21b, and 13_21c also contributes to ESD mitigation.
[0028]
Here, the example of the ESD protection circuit 13_21 including the NMOS transistors 13_21a and 13_21b and the resistance element 13_21c has been described. However, the present invention is not limited to this, and the configuration of the ESD protection circuit according to the present invention for avoiding electrostatic breakdown. May employ any of the above-described gate-coupled protection NMOS circuit, NTNMOS (NMOS TRIGGERED NMOS) circuit, RC clamp circuit, and the like, if necessary. Further, the number of NMOS transistors may be increased as much as the area allows, depending on the number of combinations of power supply systems to be protected. Further, the power supply systems to be protected may have independent ground lines.
[0029]
As described above, the semiconductor chip 10 of the first embodiment is a rectangular semiconductor chip on which a semiconductor integrated circuit having a plurality of power supply systems is mounted, and the semiconductor chip 10 is formed along two adjacent sides. An ESD protection area 13_20 having an ESD protection circuit 13_21 for avoiding electrostatic destruction is provided at a chip corner 13_2 sandwiched between the two I / O areas 11_1 and 11_2. The ESD protection area 13_20 is an area where the power supply wirings 14_1, 14_2, 14_3 and the ground wiring GND are not disposed as a user design area of the semiconductor chip 10, and the ESD protection area 13_20 is provided in such an area. A protection circuit 13_21 is formed. Therefore, when the semiconductor chip 10 is provided with the ESD protection area 13_20 having the ESD protection circuit 13_21, the NMOS transistors 13_21a and 13_21b constituting the ESD protection circuit 13_21 do not reduce the user design area in the semiconductor chip 10. Transistor size can be secured sufficiently large. Therefore, a sufficiently high ESD resistance is secured.
[0030]
FIG. 3 is a schematic diagram of a chip corner portion in a second embodiment of the semiconductor chip of the present invention.
[0031]
The semiconductor chip 20 of the second embodiment is a rectangular semiconductor chip on which a master slice type semiconductor integrated circuit is mounted, similarly to the semiconductor chip 10 shown in FIG. 2 shows a core region 22, two I / O regions 21_1 and 21_2, and a chip corner portion 23_2 sandwiched between the I / O regions 21_1 and 21_2.
[0032]
In the I / O region 21_1, NMOS transistors 21_11, 21_12, 21_13 for signal output are provided. The I / O region 21_2 is also provided with NMOS transistors 21_21, 21_22, 21_23 for signal output.
[0033]
The chip corner portion 23_2 is provided with an NMOS transistor 23_21 for an ESD protection circuit for preventing electrostatic breakdown. This NMOS transistor 23_21 has an N ⁺ region 23_21a and gates 23_21b and 23_21c.
[0034]
Here, the transistor size (gate width) W per finger of the NMOS transistor 23_21 is larger than the transistor size (gate width) W1 per finger of the NMOS transistors 21_1, 21_12, 21_13 and the NMOS transistors 21_21, 21_22, 21_23. Thereby, the capacitance value of the diode formed by the source / drain of the NMOS transistor 23_21 and the substrate (P well) is set large. For this reason, higher ESD resistance can be provided for a high voltage due to electrostatic discharge generated between a plurality of different power supply wirings having different power supply voltages.
[0035]
Note that, here, although FIG. 3 is omitted for simplicity, power supply lines of a power supply system having different power supply voltages are connected to the source and drain of the NMOS transistor and the gate is Is also connected to the ground wiring via a resistance element.
[0036]
FIG. 4 is a schematic diagram of a chip corner portion in a third embodiment of the semiconductor chip of the present invention.
[0037]
The semiconductor chip 30 of the third embodiment is also a rectangular semiconductor chip on which a semiconductor integrated circuit having a plurality of power supply systems is mounted, and FIG. 4 shows the chip corner portions 33_2 and I / The O region 31_2 is shown.
[0038]
In the I / O region 31_2, an NMOS transistor 31_21 for signal output is provided. This NMOS transistor 31_21 has an N ⁺ region 31_21a and gates 31_21b and 31_21c. A plurality of contacts 31_21d are provided on the source side of the N ⁺ region 31_21a. Also, a plurality of contacts 31_21e are provided on the drain side of the N ⁺ region 31_21a.
[0039]
The chip corner portion 33_2 is provided with an NMOS transistor 33_21 for an ESD circuit to avoid electrostatic breakdown. This NMOS transistor 33_21 has an N ⁺ region 33_21a and gates 33_21b and 33_21c. A plurality of contacts 33_21d are provided on the source side of the N ⁺ region 33_21a. Also, a plurality of contacts 33_21e are provided on the drain side of the N ⁺ region 33_21a.
[0040]
Here, the source-side gate contact distance WS and the drain-side gate contact distance WD of the NMOS transistor 33_21 are larger than the source-side gate contact distance W1S and the drain-side gate contact distance W1D of the NMOS transistor 31_21, respectively. As a result, the series parasitic resistance value between the gate and the contact is set large. For this reason, it is possible to give higher ESD resistance to a surge voltage due to electrostatic discharge generated between a plurality of different power supply wirings having different power supply voltages.
[0041]
In the present embodiment, an example of the ESD protection region having an ESD protection circuit for avoiding electrostatic destruction formed at one chip corner has been described. However, the present invention is not limited to this. Provided that the device includes an ESD protection region formed at at least one corner between two I / O regions formed along two adjacent sides and having an ESD protection circuit for preventing electrostatic breakdown. Good.
[0042]
【The invention's effect】
As described above, according to the present invention, it is possible to provide a semiconductor chip having sufficiently high ESD resistance without reducing a user design area.
[Brief description of the drawings]
FIG. 1 is a schematic diagram of a first embodiment of a semiconductor chip of the present invention.
FIG. 2 is an enlarged view showing a chip corner portion 13_2 shown in FIG. 1;
FIG. 3 is a schematic diagram of a chip corner portion in a second embodiment of the semiconductor chip of the present invention.
FIG. 4 is a schematic view of a chip corner portion in a third embodiment of the semiconductor chip of the present invention.
[Explanation of symbols]
10, 20, 30 Semiconductor chips 11_1, 11_2, 11_3, 11_4, 21_1, 21_2, 31_2 I / O area 12, 22 Core areas 13_1, 13_2, 13_3, 13_4, 23_2, 33_2 Chip corner 13_20 ESD protection area 13_21 ESD protection circuit 13_21a, 13_21b NMOS transistor 13_21c resistive element 14_1,14_2,14_3 power wiring 21_11,21_12,21_13,21_21,21_22,21_23,23_21,31_21,33_21 NMOS transistor 23_21a, 31_21a, 33_21a N ⁺ region 23_21b, 23_21c, 31_21b, 31_21c , 33 — 21b, 33 — 21c Gates 31 — 21d, 31 — 21e, 33 — 21d, 33 — 21e contact

Claims (3)

In a rectangular semiconductor chip on which a semiconductor integrated circuit having a plurality of power supply systems is mounted,
An I / O region arranged along each side for inputting / outputting a signal to / from the outside, and a central region surrounded by the I / O region to form a signal between the I / O region and the I / O region. And a plurality of power supply systems formed at at least one corner between two I / O regions formed along two adjacent sides and a core region for performing a desired circuit function by performing input / output of And an ESD protection area having an ESD protection circuit for protecting at least one of any combination between the power supply and the power supply and the ground from static electricity. An ESD transistor for protecting the ESD is provided in the ESD protection region, and the NMOS transistor has a larger gate width per finger than a signal output NMOS transistor formed in the I / O region. The semiconductor chip according to claim 1, wherein: The ESD protection region includes an NMOS transistor for ESD protection, and the NMOS transistor has a larger distance between a source and a drain contact than a signal output NMOS transistor formed in the I / O region. The semiconductor chip according to claim 1, wherein:

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