JP6941948B2 - バイアスされた縦方向フィールドプレートを使用したldmosトランジスタのドリフト領域フィールド制御、ldmosトランジスタ、及びldmosトランジスタを製造する方法 - Google Patents
バイアスされた縦方向フィールドプレートを使用したldmosトランジスタのドリフト領域フィールド制御、ldmosトランジスタ、及びldmosトランジスタを製造する方法 Download PDFInfo
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- 238000009792 diffusion process Methods 0.000 claims description 2
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Description
Claims (14)
- 活性領域上に相互接続領域を有する半導体ダイを備える横方向拡散金属酸化膜半導体(LDMOS)トランジスタであって、
前記相互接続領域は、
前記LDMOSトランジスタのゲートであって、誘電体によって前記活性領域から絶縁された、ゲート
を備え、
前記活性領域は、
前記ゲートの端に縦方向で位置合わせされた前記LDMOSトランジスタのソースと、
前記LDMOSトランジスタのドレインであって、
ドレインコンタクト領域と、
前記誘電体によって前記ゲートから鉛直方向で絶縁されたドリフト領域と
を備える、ドレインと、
前記LDMOSトランジスタのボディであって、
ボディコンタクト領域と、
前記ソースと前記ドリフト領域との間に縦方向で並置されたチャネル領域であって、前記誘電体によって前記ゲートから鉛直方向で絶縁された、チャネル領域と
を備える、ボディと、
実質的に前記ドリフト領域に平行でありかつ前記ドリフト領域から鉛直方向で分離された、下部RESURF領域と、
上の前記ドリフト領域と下の前記下部RESURF領域との両方に隣接しかつそれらの間に鉛直方向で噛み合った、上部RESURF領域と
を備え、
前記ドレインコンタクト領域と前記ボディコンタクト領域との間の第1の縦方向距離は、前記ドレインコンタクト領域と前記下部RESURF領域の端との間の第2の縦方向距離より大きく、
前記下部RESURF領域の前記端から、かつ前記ボディコンタクト領域の下を延在する拡張領域を更に備え、前記拡張領域は、前記下部RESURF領域の導電率型と同じ導電率型を有し、前記拡張領域は、前記下部RESURF領域の正味ドーパント濃度より低い正味ドーパント濃度を有する、
LDMOSトランジスタ。 - 前記活性領域は、基板上に成長されるエピタキシャル層を備える、請求項1に記載のLDMOSトランジスタ。
- 前記下部RESURF領域の前記端は、前記下部RESURF領域の正味ドーパント濃度が所定の閾値にある縦方向位置として規定される、請求項1又は請求項2に記載のLDMOSトランジスタ。
- 前記所定の閾値は、エピタキシャル層の正味ドーパント濃度の10倍として規定される、請求項3に記載のLDMOSトランジスタ。
- 前記所定の閾値は、基板の正味ドーパント濃度の10倍として規定される、請求項3に記載のLDMOSトランジスタ。
- 前記上部RESURF領域は、前記ボディに導電的に結合される、請求項1〜請求項5の何れか1項に記載のLDMOSトランジスタ。
- 前記下部RESURF領域は、鉛直電導経路を介して前記ドレインに導電的に結合される、請求項1〜請求項6の何れか1項に記載のLDMOSトランジスタ。
- 前記鉛直電導経路は、前記下部RESURF領域の正味ドーパント濃度及び前記ドリフト領域の前記正味ドーパント濃度の両方より低い正味ドーパント濃度を有する、請求項7に記載のLDMOSトランジスタ。
- 基板は第1の導電率型を有し、前記エピタキシャル層は第2の導電率型を有する、請求項2に記載のLDMOSトランジスタ。
- 前記ボディは第1の導電率型を有し、前記ソース及び前記ドレインは両方とも第2の導電率型を有する、請求項1〜請求項9の何れか1項に記載のLDMOSトランジスタ。
- 前記拡張領域は、エピタキシャル層の正味ドーパント濃度と実質的に等しい正味ドーパント濃度を有する、請求項1に記載のLDMOSトランジスタ。
- 請求項1に記載のLDMOSトランジスタを製造する方法であって、前記方法は、
第1の型のドーパント種の基板を備え、
第2の型のドーパント種を使用して前記基板内に前記下部RESURF領域を注入し、
前記第2の型のドーパント種のエピタキシャル層を成長させ、
前記第1の型のドーパント種を使用して前記エピタキシャル層内に前記上部RESURF領域を注入すること、
を含む方法。 - 前記上部RESURF領域を注入することは、500,000ボルトより大きな注入エネルギーを使用する、請求項12に記載の方法。
- 前記上部RESURF領域を注入することは、1,000,000ボルトより大きな注入エネルギーを使用する、請求項12に記載の方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/065,204 | 2016-03-09 | ||
US15/065,204 US10153366B2 (en) | 2016-03-09 | 2016-03-09 | LDMOS transistor with lightly-doped annular RESURF periphery |
Publications (2)
Publication Number | Publication Date |
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JP2017163142A JP2017163142A (ja) | 2017-09-14 |
JP6941948B2 true JP6941948B2 (ja) | 2021-09-29 |
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