JP6938621B2 - 量子コンピューティングアセンブリ - Google Patents
量子コンピューティングアセンブリ Download PDFInfo
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- JP6938621B2 JP6938621B2 JP2019510859A JP2019510859A JP6938621B2 JP 6938621 B2 JP6938621 B2 JP 6938621B2 JP 2019510859 A JP2019510859 A JP 2019510859A JP 2019510859 A JP2019510859 A JP 2019510859A JP 6938621 B2 JP6938621 B2 JP 6938621B2
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Images
Classifications
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/071—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next and on each other, i.e. mixed assemblies
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
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- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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- Thin Film Transistor (AREA)
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Description
量子コンピューティングとは、量子力学的な現象を用いてデータを操作する、コンピューテーションシステムに関連する研究分野を指す。重ね合わせ(量子変数が複数の異なる状態において同時に存在してよい)、およびもつれ(複数の量子変数が空間または時間における量子変数間の距離に関わらず関連する状態を有する)等のこれらの量子力学的現象は、従来のコンピューティング世界においては類似性を有さず、このため、従来のコンピューティングデバイスを用いては実装できない。
(項目1)
複数のキュビットを生成するための量子デバイスダイと、
前記量子デバイスダイの動作を制御するための制御回路ダイと、
基板と、を備え、
前記量子デバイスダイおよび前記制御回路ダイは、前記基板上に配置されている、量子コンピューティングアセンブリ。
(項目2)
前記基板はパッケージ基板であり、前記量子デバイスダイおよび前記制御回路ダイは、共通のパッケージに含まれる、項目1に記載の量子コンピューティングアセンブリ。
(項目3)
前記基板はインターポーザである、項目1に記載の量子コンピューティングアセンブリ。
(項目4)
前記基板はプリント回路基板である、項目1に記載の量子コンピューティングアセンブリ。
(項目5)
前記量子デバイスダイおよび前記制御回路ダイは、パッケージ‐オン‐パッケージ構造に含まれる、項目1に記載の量子コンピューティングアセンブリ。
(項目6)
前記基板は、前記量子デバイスダイと前記制御回路ダイとの間に少なくとも1つのマイクロ波送信ラインを含む、項目1に記載の量子コンピューティングアセンブリ。
(項目7)
前記基板は、前記制御回路ダイが結合される前記基板の面と、前記基板の対向する面との間に少なくとも1つの導電性経路を含む、項目1に記載の量子コンピューティングアセンブリ。
(項目8)
前記制御回路ダイは、処理デバイスまたはメモリ素子を含む、項目1に記載の量子コンピューティングアセンブリ。
(項目9)
前記量子デバイスダイおよび前記制御回路ダイはそれぞれ、ソルダ接続を用いて前記基板に結合されている、項目1に記載の量子コンピューティングアセンブリ。
(項目10)
前記量子デバイスダイは、複数のゲートを含み、前記制御回路ダイは、前記基板を通して、前記複数のゲートに電圧を供給する、項目1から9のいずれか一項に記載の量子コンピューティングアセンブリ。
(項目11)
前記量子デバイスダイは、1または複数のマグネットラインを含み、前記制御回路ダイは、前記基板を通して、前記1または複数のマグネットラインに電気パルスを供給する、項目1から9の何れか一項に記載の量子コンピューティングアセンブリ。
(項目12)
前記制御回路ダイは、読み取りまたは書き込みをするために、前記キュビットのうち1または複数を選択するためのスイッチングマトリクスを含む、項目1から9の何れか一項に記載の量子コンピューティングアセンブリ。
(項目13)
前記キュビットは、量子ドットベースのキュビットである、項目1から9の何れか一項に記載の量子コンピューティングアセンブリ。
(項目14)
前記基板は、前記量子デバイスダイと前記制御回路ダイとの間に電気的経路を含み、前記電気的経路が超導電性材料を含む、項目1から9の何れか一項に記載の量子コンピューティングアセンブリ。
(項目15)
前記量子デバイスダイの動作中に、前記制御回路ダイにより生成されるデータを格納するためのメモリデバイスをさらに備える、項目1から9の何れか一項に記載の量子コンピューティングアセンブリ。
(項目16)
前記制御回路ダイから、データを受信および送信するための有線または無線のネットワークコントローラをさらに備える、項目1から9の何れか一項に記載の量子コンピューティングアセンブリ。
(項目17)
基板を設ける段階であって、前記基板は、第1の組のコンタクトと第2の組のコンタクトとの間に1または複数の電気的経路を含む、段階と、
量子デバイスダイが前記基板上に配置されるように、前記量子デバイスダイを前記第1の組のコンタクトに結合する段階と、
1または複数の制御ダイが前記基板上に配置されるように、前記1または複数の制御ダイを前記第2の組のコンタクトに結合する段階であって、前記1または複数の制御ダイは、前記1または複数の電気的経路を通して、前記量子デバイスダイの1または複数のコンポーネントに電圧を供給する、段階と、を備える、量子コンピューティングアセンブリを製造する方法。
(項目18)
前記1または複数の電気的経路は、コプレーナ導波管、ストリップラインまたはマイクロストリップラインを含む、項目17に記載の方法。
(項目19)
前記量子デバイスダイは、中間構造上に配置され、前記量子デバイスダイを前記第1の組のコンタクトに結合する段階は、前記中間構造を前記第1の組のコンタクト上に物理的に固定する段階を含む、項目17に記載の方法。
(項目20)
1または複数の制御ダイは、中間構造上に配置され、前記1または複数の制御ダイを前記第2の組のコンタクトに結合する段階は、前記中間構造を前記第2の組のコンタクト上に物理的に固定する段階を含む、項目17から19のいずれか一項に記載の方法。
(項目21)
制御回路ダイによって、基板を通して、1または複数の電圧を量子デバイスダイに供給する段階であって、前記基板上に、前記量子デバイスダイおよび前記制御回路ダイが配置される、段階と、
前記1または複数の電圧に少なくとも部分的に応答して、前記量子デバイスダイにおけるキュビットの状態を変更する段階と、を備える、量子コンピューティングアセンブリを動作させる方法。
(項目22)
前記1または複数の電圧を前記量子デバイスダイに供給する段階は、前記量子デバイスダイのマグネットラインまたは1若しくは複数のゲートに、電子スピン共鳴(ESR)パルスを供給する段階を含む、項目21に記載の方法。
(項目23)
前記キュビットの前記状態を変更する段階は、量子ドットベースのキュビットのスピン状態を変更する段階を含む、項目21に記載の方法。
(項目24)
前記制御回路ダイにより、前記量子デバイスダイにおける前記キュビットの前記状態を検出する段階をさらに備える、項目21から23のいずれか一項に記載の方法。
(項目25)
前記制御回路ダイにより、前記基板を通して、前記キュビットの前記状態を伝達する段階をさらに備える、項目24に記載の方法。
Claims (34)
- 複数のキュビットを生成するための量子デバイスダイと、
前記量子デバイスダイの動作を制御するための制御回路ダイと、
基板と、を備え、
前記量子デバイスダイおよび前記制御回路ダイは、前記基板上に配置されている、量子コンピューティングアセンブリであって、
前記量子デバイスダイは、1または複数のマグネットラインを含み、前記制御回路ダイは、前記基板を通して、前記1または複数のマグネットラインに電気パルスを供給する、量子コンピューティングアセンブリ。 - 複数のキュビットを生成するための量子デバイスダイと、
前記量子デバイスダイの動作を制御するための制御回路ダイと、
基板と、を備え、
前記量子デバイスダイおよび前記制御回路ダイは、前記基板上に配置されている、量子コンピューティングアセンブリであって、
前記制御回路ダイは、読み取りまたは書き込みをするために、前記キュビットのうち1または複数を選択するためのスイッチングマトリクスを含む、量子コンピューティングアセンブリ。 - 複数のキュビットを生成するための量子デバイスダイと、
前記量子デバイスダイの動作を制御するための制御回路ダイと、
基板と、を備え、
前記量子デバイスダイおよび前記制御回路ダイは、前記基板上に配置されており、前記量子デバイスダイは、1または複数のマグネットラインを含み、個々のマグネットラインは、キュビットの量子ドットのスピン状態に影響を及ぼすための磁場生成構造である、量子コンピューティングアセンブリ。 - 複数のキュビットを生成するための量子デバイスダイと、
前記量子デバイスダイの動作を制御するための制御回路ダイであって、制御回路ダイは、読み取りまたは書き込みをするために、前記キュビットのうちの1または複数を選択するためのスイッチングマトリックスを含み、前記スイッチングマトリックスは、少なくとも1つのワードラインおよび少なくとも1つのビットラインを含む、制御回路ダイと、
基板と、を備え、
前記量子デバイスダイおよび前記制御回路ダイは前記基板上に配置されている、量子コンピューティングアセンブリ。 - 複数のキュビットを生成するための量子デバイスダイと、
前記量子デバイスダイの動作を制御するための制御回路ダイであって、制御回路ダイは、読み取りまたは書き込みをするために、前記キュビットのうちの1または複数を選択するためのスイッチングマトリックスを含む、制御回路ダイと、
基板と、を備え、
前記量子デバイスダイおよび前記制御回路ダイは前記基板上にあり、前記量子デバイスダイは、1または複数のマグネットラインを含む、量子コンピューティングアセンブリ。 - 個々のマグネットラインは、磁性材料を含む、請求項1、3および5のいずれか一項に記載の量子コンピューティングアセンブリ。
- 前記基板はパッケージ基板であり、前記量子デバイスダイおよび前記制御回路ダイは、共通のパッケージに含まれる、請求項1から6のいずれか一項に記載の量子コンピューティングアセンブリ。
- 前記基板はインターポーザである、請求項1から6のいずれか一項に記載の量子コンピューティングアセンブリ。
- 前記基板はプリント回路基板である、請求項1から6のいずれか一項に記載の量子コンピューティングアセンブリ。
- 前記量子デバイスダイおよび前記制御回路ダイは、パッケージ‐オン‐パッケージ構造に含まれる、請求項1から7のいずれか一項に記載の量子コンピューティングアセンブリ。
- 前記基板は、前記量子デバイスダイと前記制御回路ダイとの間に少なくとも1つのマイクロ波送信ラインを含む、請求項1から10のいずれか一項に記載の量子コンピューティングアセンブリ。
- 前記基板は、前記制御回路ダイが結合される前記基板の面と、前記基板の対向する面との間に少なくとも1つの導電性経路を含む、請求項1から11のいずれか一項に記載の量子コンピューティングアセンブリ。
- 前記制御回路ダイは、処理デバイスまたはメモリ素子を含む、請求項1から12のいずれか一項に記載の量子コンピューティングアセンブリ。
- 前記量子デバイスダイおよび前記制御回路ダイはそれぞれ、ソルダ接続を用いて前記基板に結合されている、請求項1から13のいずれか一項に記載の量子コンピューティングアセンブリ。
- 前記量子デバイスダイは、複数のゲートを含み、前記制御回路ダイは、前記基板を通して、前記複数のゲートに電圧を供給する、請求項1から14のいずれか一項に記載の量子コンピューティングアセンブリ。
- 前記キュビットは、量子ドットベースのキュビットである、請求項1から15の何れか一項に記載の量子コンピューティングアセンブリ。
- 前記基板は、前記量子デバイスダイと前記制御回路ダイとの間に電気的経路を含み、前記電気的経路が超導電性材料を含む、請求項1から16の何れか一項に記載の量子コンピューティングアセンブリ。
- 前記量子デバイスダイの動作中に、前記制御回路ダイにより生成されるデータを格納するためのメモリデバイスをさらに備える、請求項1から17の何れか一項に記載の量子コンピューティングアセンブリ。
- 前記量子デバイスダイおよび前記制御回路ダイの温度を所望の範囲に維持するための冷却装置をさらに備える、請求項1から18の何れか一項に記載の量子コンピューティングアセンブリ。
- 前記制御回路ダイから、データを受信および送信するための有線または無線のネットワークコントローラをさらに備える、請求項1から19の何れか一項に記載の量子コンピューティングアセンブリ。
- 基板を設ける段階であって、前記基板は、第1の組のコンタクトと第2の組のコンタクトとの間に1または複数の電気的経路を含む、段階と、
量子デバイスダイが前記基板上に配置されるように、前記量子デバイスダイを前記第1の組のコンタクトに結合する段階と、
1または複数の制御ダイが前記基板上に配置されるように、前記1または複数の制御ダイを前記第2の組のコンタクトに結合する段階であって、前記1または複数の制御ダイは、前記1または複数の電気的経路を通して、前記量子デバイスダイの1または複数のコンポーネントに電圧を供給する、段階と、を備える、量子コンピューティングアセンブリを製造する方法であって、
前記量子デバイスダイは、1または複数のマグネットラインを含み、前記制御ダイは、前記1または複数の電気的経路を通して、前記1または複数のマグネットラインに電気パルスを供給する、量子コンピューティングアセンブリを製造する方法。 - 基板を設ける段階であって、前記基板は、第1の組のコンタクトと第2の組のコンタクトとの間に1または複数の電気的経路を含む、段階と、
量子デバイスダイが前記基板上に配置されるように、前記量子デバイスダイを前記第1の組のコンタクトに結合する段階と、
1または複数の制御ダイが前記基板上に配置されるように、前記1または複数の制御ダイを前記第2の組のコンタクトに結合する段階であって、前記1または複数の制御ダイは、前記1または複数の電気的経路を通して、前記量子デバイスダイの1または複数のコンポーネントに電圧を供給する、段階と、を備える、量子コンピューティングアセンブリを製造する方法であって、
前記制御ダイは、読み取りまたは書き込みをするために、前記量子デバイスダイで生成されるキュビットのうち1または複数を選択するためのスイッチングマトリクスを含む、量子コンピューティングアセンブリを製造する方法。 - 前記1または複数の電気的経路は、コプレーナ導波管、ストリップラインまたはマイクロストリップラインを含む、請求項21または22に記載の方法。
- オーバーモールド材料を前記量子デバイスダイおよび前記1または複数の制御ダイに設ける段階、または
アンダーフィル材料を前記量子デバイスダイおよび前記1または複数の制御ダイの下方に設ける段階をさらに備える、請求項21から23のいずれか一項に記載の方法。 - 前記量子デバイスダイは、中間構造上に配置され、前記量子デバイスダイを前記第1の組のコンタクトに結合する段階は、前記中間構造を前記第1の組のコンタクト上に物理的に固定する段階を含む、請求項21から24の何れか一項に記載の方法。
- 前記1または複数の制御ダイは、中間構造上に配置され、前記1または複数の制御ダイを前記第2の組のコンタクトに結合する段階は、前記中間構造を前記第2の組のコンタクト上に物理的に固定する段階を含む、請求項21から25のいずれか一項に記載の方法。
- 制御回路ダイによって、基板を通して、1または複数の電圧を量子デバイスダイに供給する段階であって、前記基板上に、前記量子デバイスダイおよび前記制御回路ダイが配置される、段階と、
前記1または複数の電圧に少なくとも部分的に応答して、前記量子デバイスダイにおけるキュビットの状態を変更する段階と、を備える、量子コンピューティングアセンブリを動作させる方法であって、
前記量子デバイスダイは、1または複数のマグネットラインを含み、前記制御回路ダイは、前記基板を通して、前記1または複数のマグネットラインに電気パルスを供給する、量子コンピューティングアセンブリを動作させる方法。 - 制御回路ダイによって、基板を通して、1または複数の電圧を量子デバイスダイに供給する段階であって、前記基板上に、前記量子デバイスダイおよび前記制御回路ダイが配置される、段階と、
前記1または複数の電圧に少なくとも部分的に応答して、前記量子デバイスダイにおけるキュビットの状態を変更する段階と、を備える、量子コンピューティングアセンブリを動作させる方法であって、
前記制御回路ダイは、読み取りまたは書き込みをするために、前記キュビットのうち1または複数を選択するためのスイッチングマトリクスを含む、量子コンピューティングアセンブリを動作させる方法。 - 前記1または複数の電圧を前記量子デバイスダイに供給する段階は、前記量子デバイスダイのマグネットラインまたは1若しくは複数のゲートに、電子スピン共鳴(ESR)パルスを供給する段階を含む、請求項27または28に記載の方法。
- 前記キュビットの前記状態を変更する段階は、量子ドットベースのキュビットのスピン状態を変更する段階を含む、請求項27から29のいずれか一項に記載の方法。
- 前記制御回路ダイにより、前記量子デバイスダイにおける前記キュビットの前記状態を検出する段階をさらに備える、請求項27から30のいずれか一項に記載の方法。
- 前記制御回路ダイにより、前記基板を通して、前記キュビットの前記状態を伝達する段階をさらに備える、請求項27から31のいずれか一項に記載の方法。
- 前記制御回路ダイは、シリコンベースの処理デバイスを含む、請求項27から32の何れか一項に記載の方法。
- 前記基板は、インタポーザを含む、請求項27から33の何れか一項に記載の方法。
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CN109791924A (zh) | 2019-05-21 |
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