JP6936091B2 - DC / DC converter - Google Patents

Description

The present invention relates to a DC / DC converter that switches between a PWM method and a PFM method according to the lightness and weight of a load.

Conventionally, a battery is mounted as a drive power source in a portable electronic device. Since the output voltage of a battery decreases due to the use or discharge of the device, the electronic device is provided with a DC voltage conversion circuit (DC / DC converter) that converts the voltage of the battery into a constant voltage. A small-sized synchronous rectification type DC / DC converter with good conversion efficiency is used for a portable electronic device. A synchronous rectification type DC / DC converter is generally a PWM (Pulse Width Modulation) type DC / DC converter, which includes a main switching transistor and a synchronous transistor, and alternately controls both transistors on and off. That is, the main switching transistor is turned on to supply energy from the input side to the output side, and the main switching transistor is turned off to release the energy stored in the choke inductor. At this time, the synchronization transistor is turned off in synchronization with the timing when the energy stored in the choke inductor is released to the load side. Then, the pulse width of the pulse signal that drives the main switching transistor is controlled according to the output voltage or the output current, so that the output voltage is kept substantially constant.

By the way, in the DC / DC converter, when converting the voltage of a battery, high conversion efficiency is required in a wide range of load regions from a heavy load having a large amount of power supply to a light load having a small amount of power supply. However, when the load is light, the power loss of the DC / DC converter generated when driving the main switching transistor is relatively large compared to the power consumption under the load, so that the conversion efficiency may be significantly reduced. It is generally known.

Therefore, in order to improve the decrease in conversion efficiency at the time of light load, a DC / DC converter that switches from the PWM method to the PFM (Pulse Frequency Modulation) method at the time of light load has been proposed. In this DC / DC converter, it is driven by the PWM method during normal operation including heavy load, and is driven by the PFM method during light load. The PFM method includes a true PFM method that controls the switching frequency of the drive signal supplied to the main switching transistor according to the output voltage of the DC / DC converter, and a constant switching frequency of the drive signal supplied to the main switching transistor. , There is a pseudo PFM method in which the switching operation is thinned out according to the output voltage of the DC / DC converter. In any of the PFM methods, the switching frequency at the time of light load is smaller than that of the PWM method, so that the power loss of the DC / DC converter can be reduced and the decrease in conversion efficiency at the time of light load can be suppressed. ..

Patent Document 1 can be mentioned as a prior art relating to the above.

Further, conventionally, in order to realize high efficiency in a DC / DC converter, in addition to PWM control, SLLM [Simple Light Load Mode] control at the time of no load or light load has been introduced. According to the DC / DC converter that employs this SLLM control technology, by applying an offset voltage to the current detection voltage that represents the detection value of the current flowing through the inductor, the difference between the output voltage and the reference voltage becomes smaller when there is no load or when it is light. At the time of loading, it is confirmed in the comparator that the magnitude of the current detection voltage is larger than the difference between the output voltage and the reference voltage. At this time, since the oscillator signal of the oscillator that turns on the switching element can be invalidated, the switching operation of the switching element can be intermittently controlled until the difference between the output voltage and the reference voltage becomes large. Therefore, since it is not necessary to add a comparator for intermittent control, the efficiency is improved as compared with the DC / DC converter by PWM control in the current mode at the time of light load or no load, and the device is equipped with. It is possible to reduce the size.

Patent Document 2 can be mentioned as a prior art relating to the above.

Further, conventionally, it is known to provide a switching regulator having high efficiency even at a light load. For example, the oscillation frequency of the oscillator is controlled by the output signal of the error amplifier, and the on / off of the switching element is controlled by using the output signal of the oscillator to keep the oscillation frequency low and reduce the switching loss at the time of light load. be able to.

Patent Document 3 can be mentioned as a prior art relating to the above.

Japanese Unexamined Patent Publication No. 2012-60883 International Publication WO2005 / 078910 Japanese Unexamined Patent Publication No. 2012-257408

However, in the switching between the PWM method and the PFM method in the DC / DC converter of Patent Document 1, there is a problem that the magnitude of the load current varies depending on the input / output setting (difference between the input voltage and the output voltage).

Further, in the DC / DC converter adopting the SLLM control technology of Patent Document 2, it is difficult to maintain the high efficiency of the DC / DC converter at the time of light load or no load, and the smaller the output current value, the more. There is a decrease in efficiency.

Further, in the method disclosed in Patent Document 3, the load current is not directly detected and the oscillation frequency is not controlled, but the asynchronous control causes a problem that quantitative control cannot be realized. As a result, regular shaking may occur, and when entering the audible area, there is a problem that sound can be heard.

An object of the present invention is to solve the above-mentioned problems, by quantitatively detecting the load current, determining the light and heavy state of the load by controlling the internal clock, and switching between the PWM method and the PFM method. In addition to providing a DC / DC converter capable of improving the conversion efficiency of a power source, a space-saving DC / DC converter that does not produce sound is provided.

The DC / DC converters (1, 2) of the present invention are coupled to an input voltage (Vin) to perform on / off operation, and on / off control of switching elements (T11, T21) and switching elements (T11, T21). (3) is provided. Further, the inductors (L1, L2) whose current is controlled by the switching elements (T11, T21) and the smoothing capacitors (C1, C2) which are connected to the inductors (L1, L2) and perform rectification operation together with the inductors (L1, L2). And the rectangular wave signal (oscillator (9) that generates CLK that operates the drive circuit (3), and the output that detects the output detection current (Issence) that flows through the switching elements (T11, T21) or inductors (L1, L2). The oscillator (9) includes a current detection unit (4). When the output detection current (Isense) is equal to or higher than a predetermined value, the oscillator (9) generates a rectangular wave signal (CLK) at a fixed oscillation frequency and outputs the output detection current (Isense). ) Is equal to or less than a predetermined value, a rectangular wave signal (CLK) is generated at an oscillation frequency (Fosc) lower than the fixed oscillation frequency and proportional to the output detection current (Isense).

Further, in the DC / DC converters (1 and 2) of the present invention, the oscillator (9) is a constant current source (CC) that generates a constant constant current (Icc) regardless of the magnitude of the output detection current (Isense). And a linear current source (CL) that generates a linear current (Icl) that responds to the magnitude of the output detection current (Isens).

Further, in the DC / DC converters (1, 2) of the present invention, the oscillator currents (Iosc1, Iosc2) set by the sum (+) of the constant current (Icc) and the linear current (Icl) or the difference (−) between the two. ), The oscillation frequency (Fosc) of the oscillator (9) is set.

Further, the DC / DC converters (1, 2) of the present invention perform PWM control when the output detection current (Isense) is equal to or higher than a predetermined value, and perform PFM control when the output detection current is equal to or lower than a predetermined value. ..

Further, in the case of performing PFM control in the DC / DC converters (1 and 2) of the present invention, the setting of the oscillation frequency (Fosc) of the oscillator (9) is governed by the linear current (Icl).

Further, in the DC / DC converter (1, 2) of the present invention, when PFM control is performed, the lower limit value of the oscillation frequency (Fosc) is set to be equal to or higher than the audible frequency band.

Further, the DC / DC converter (1, 2) of the present invention further has a feedback voltage (Vfb) generated based on the voltage generated in the smoothing capacitors (C1, C2) and a reference set in advance to a predetermined magnitude. It is provided with an error amplifier (7) that compares with a voltage (Vref) and outputs the difference between the two voltages as an error signal (Verr). In addition, a slope circuit (11) that generates a slope signal (Vsl) based on a square wave signal generated by the oscillator (9) and a drive circuit that drives a comparison result signal between an error signal (Verr) and a slope signal (Vsl). It is provided with a PWM comparator (10) that outputs to (3).

Further, the DC / DC converters (1, 2) of the present invention are a current mode type in which a current component corresponding to an output detection current (Isense) is superimposed on a slope signal (Vsl).

Further, in the DC / DC converter (1, 2) of the present invention, in order to supply a current to the inductors (L1, L2) when the switching elements (T11, T21) are turned off, the switching elements (T11, T21) A rectifying element (T12, D12, T22, D22) coupled to a common node (N1) between the inductor (L1, L2) and the inductor (L1 and L2) is provided.

Further, the DC / DC converters (1, 2) of the present invention include a reverse current detection circuit (5) that detects a reverse current flowing from the ground potential (GND) toward the common node (N1), and reverse current detection. When the circuit (5) detects a predetermined reverse current, the operation of the rectifying element (T12) or the switching element (T21) coupled to the ground potential (GND) is turned off.

The DC / DC converter of the present invention detects the magnitude of the load current, and when the load current falls below a predetermined magnitude, the switching drive method of the DC / DC converter is switched from PWM control to PFM control, and the load is further increased. Since the oscillation frequency is automatically controlled to be lowered in proportion to the current, it is possible to suppress a decrease in power efficiency when the load current is small and the load is light or no load.

The circuit diagram of the current mode synchronous rectification step-down type DC / DC converter relating to the DC / DC converter of the present invention is shown. The signal waveform diagram of the output part of the DC / DC converter of FIG. 1 is shown. A circuit diagram of a current mode synchronous rectification boost type DC / DC converter according to the DC / DC converter of the present invention is shown. It is a figure which shows the relationship between the oscillation frequency Fosc of an oscillator, and the load current IL in FIGS. 1 and 2. 1 and 2 are diagrams showing a case where the oscillator current Iosc1 generated in response to a change in the output detection current Issue is determined by the sum of the constant current Icc and the linear current Icl. 1 and 2 are diagrams showing a case where the oscillator current Iosc2 generated in response to a change in the output detection current Issue is determined by the difference between the linear current Icl and the constant current Icc. 1 and 2 are diagrams showing the relationship between the oscillator currents Iosc1 and Iosc2 and the oscillation frequency Fosc of the clock signal CLK generated by the oscillator 9. It is a figure which shows one configuration example of an oscillator part OSCr. It is a timing chart for demonstrating the operation of the oscillator part OSCr. It is a figure which shows the 1st configuration example of the current source CS11. It is a figure which shows the 2nd configuration example of the current source CS11. It is a figure which shows the 3rd configuration example of the current source CS11. It is a figure which shows the 4th structural example of the current source CS11.

<First Embodiment of the present invention>
FIG. 1 is a circuit diagram showing a current mode synchronous rectification step-down DC / DC converter according to the present invention. The DC / DC converter 1 of this configuration example lowers the input voltage Vin supplied to the input terminal VIN to generate a desired output voltage Vout at the output terminal VOUT.

The DC / DC converter 1 of this configuration example includes a switching element T11, a rectifier element T12, a drive circuit 3, an output current detection unit 4, a reverse current detection circuit 5, a feedback voltage generation circuit 6, an error amplifier 7, and a phase compensation circuit 8. It includes an oscillator 9, a PWM comparator 10, a slope voltage generation circuit 11, an inductor L1, and a smoothing capacitor C1.

The switching element T11 is a P-channel type MOS [Metal Oxide Semiconductor] field effect transistor connected to the drive circuit 3, the output current detection unit 4, and the rectifier element T12, and is repeatedly turned on / off to connect to the inductor L1. It functions as a switching transistor that controls the flowing current. The source S of the switching element T11 is connected to the output current detection unit 4. The drain D of the switching element T11 is connected to the drain D of the rectifying element T12. A gate signal GH is applied to the gate G of the switching element T11 from the drive circuit 3. The switching element T11 is turned off when the gate signal GH is at a high level and turned on when the gate signal GH is at a low level. The rectifying element T12 supplies a current toward the inductor L1 when the switching element T11 is off.

The rectifying element T12 is an N-channel type MOS field effect transistor connected to the switching element T11 and the drive circuit 3, and operates complementarily in synchronization with the switching element T11 as a synchronous rectifying transistor. The drain D of the rectifying element T12 is connected to the drain D of the switching element T11. The common connection point between the rectifying element T12 and the switching element T11 is shown as a node N1. The rectifying element T12 is turned on when the switching element T11 is off, and is placed off when the switching element T11 is on. The source S of the rectifying element T12 is connected to the ground potential GND. A gate signal GL is applied to the gate G of the rectifying element T12 from the drive circuit 3. The rectifying element T12 is turned on when the gate signal GL is at a high level and turned off when the gate signal GL is at a low level.

By turning on / off the switching element T11 and the rectifying element T12 in a complementary manner, a rectangular wave-shaped switching voltage Vsw appears at the node N1. By smoothing this switching voltage Vsw with the inductor L1 and the smoothing capacitor C1, the output voltage Vout is taken out to the output terminal VOUT. The inductor L1 and the smoothing capacitor C1 are connected in series between the node N1 and the ground potential GND, and their common connection point is indicated by the node N2. At node N2, the voltage generated in the smoothing capacitor C1, that is, the output voltage Vout is generated.

In the DC / DC converter 1 of this configuration example, the switching element T11, the rectifying element T12, the inductor L1, and the smoothing capacitor C1 are used to step down the input voltage Vin supplied to the input terminal VIN to lower the desired output voltage. A step-down switch output stage that generates Vout at the output terminal VOUT is formed.

When the components of the DC / DC converter 1 (reference numerals 3 to 11 and the like) are integrated in the IC, the switching element T11 and the rectifying element T12 may be built in the IC or may be externally attached to the IC. It is possible. When externally attached to the IC, an external terminal for externally outputting the gate signal GH and the gate signal GL is required. It is also possible to use an N-channel type MOS field effect transistor as the switching element T11. It is also possible to use an IGBT [Insulated Gate Bipolar Transistor] or the like as the switching element T11 or the rectifying element T12. Further, the switching element T11 and the rectifying element T12 may be configured by a bipolar transistor.

Further, as the rectification method of the switch output stage, an asynchronous rectification method can be adopted instead of the synchronous rectification method using the rectifying element T12. In that case, the rectifier diode D12 is used as an alternative to the rectifier element T12. In this case, the cathode K of the rectifying diode D12 may be connected to the node N1 and the anode A of the rectifying diode D12 may be connected to the ground potential GND.

In the drive circuit 3, in order to prevent an excessive through current flowing from the switching element T11 toward the rectifying element T12, the gate signal GH is at a low level and the gate signal GL is not at a high level. A section (so-called dead time) in which the gate signal GH is at a high level and the gate signal GL is at a low level is provided.

Further, the drive circuit 3 has a function of forcibly stopping the switching operation of the switch output stage in response to an abnormality protection signal (not shown) (the gate signal GH output to the switching element T11 is set to a high level and is output to the rectifying element T12. It also has a function to set the gate signal GL to a low level).

The output current detection unit 4 detects the output detection current Sense flowing from the input terminal VIN toward the switching element T11. The output detection current Sense is a current proportional to the load current IL flowing through the load RL, and is a current that reflects the state of the load RL. Therefore, by detecting the magnitude of the output detection current Sense, it is possible to determine whether the load RL is placed in a state of no load, light load, medium load, or heavy load.

The reverse current detection circuit 5 detects the reverse current to the rectifying element T12, that is, the current flowing from the inductor L1 to the ground potential GND via the rectifying element T12. The presence or absence of the reverse current is determined by detecting a so-called zero cross point in which the switching voltage Vsw switches from negative to positive while the rectifying element T12 is on. When a reverse current of a predetermined value or more is detected, the zero cross detection signal Szc is output from the reverse current detection circuit 5, and a gate signal GL is generated based on the zero cross detection signal Szc so as to turn off the rectifying element T12.

The feedback voltage generation circuit 6 is composed of resistors R1 and R2 connected in series between the output terminal VOUT and the ground potential GND, and outputs the feedback voltage Vfb from the node N3 which is a common connection point between them. The feedback voltage Vfb is a voltage proportional to the voltage generated in the smoothing capacitor C1 and is also a DC voltage proportional to the output voltage Vout generated in the output terminal VOUT.

The error amplifier 7 generates an error voltage Verr according to the difference between the reference voltage Vref input to the non-inverting input terminal (+) and the feedback voltage Vfb input to the inverting input terminal (−). The error voltage Verr increases when the feedback voltage Vfb is lower than the reference voltage Vref, and decreases when the feedback voltage Vfb is higher than the reference voltage Vref. The error voltage Verr is output from the output side of the error amplifier 7. It should be noted that the output side of the error amplifier 7 can be converted into a current instead of a voltage and output. An error amplifier having such a configuration is known as a transconductance error amplifier.

The phase compensation circuit 8 is composed of a series circuit of a resistor R3 and a capacitor C3 connected in series between the output end of the error amplifier 70 and the ground potential GND. It is well known that such a phase compensation circuit is used in a DC / DC converter. The phase compensation circuit 8 is used to increase the difference with respect to the phase delay of 180 degrees in the DC / DC converter 1, that is, the phase margin. For example, if the phase of the DC / DC converter 1 when the loop gain is 0 db (gain 1 times) is 120 degrees, the phase margin is 180 degrees −120 degrees = 60 degrees. It is said that this phase margin is sufficient if it is, for example, 45 degrees or more.

The oscillator 9 is composed of a constant current source CC coupled to a power supply voltage Vcc, a linear current source CL, and an oscillator unit OSCr. The oscillator unit OSCr is composed of, for example, a well-known CR oscillator, or a circuit in which an inverter or a differential amplifier is connected in a ring shape. Regardless of the circuit configuration, in the present invention, the sum (+) of the constant current Icc generated by the constant current source CC and the linear current Icl generated by the linear current source CL, or the difference between them (-). The oscillation frequency Fosc of the clock signal CLK generated by the oscillator unit OSCr is controlled based on the oscillator currents (Iosc1 and Iosc2) set by.

The magnitude of the constant current Icc generated by the constant current source CC is always a constant current value regardless of whether the DC / DC converter 1 is PWM controlled or PFM controlled. This is why it is called a constant current source. On the other hand, the linear current Icl generated by the linear current source CL has a constant current value when the DC / DC converter 1 is driven by the PWM method, but is detected by the switching element T11 when driven by the PFM. The variable current value has a magnitude proportional to the output detection current Sense. This is why it is called a linear current. The linear current Icl generated by the linear current source CL is set to a magnitude obtained by multiplying the output detection current Sense by a predetermined coefficient m, that is, Icl = m * Sense.

In generating the linear current Icl that responds to the output detection current Sense and the constant current Icc that does not respond to the output detection current Sense, adding or subtracting them, and setting these current ratios, for example, a current mirror circuit is used. Good to use.

The PWM comparator 10 compares the error voltage Verr applied to the inverting input terminal (−) with the slope voltage Vsl applied to the non-inverting input terminal (+) to generate a pulse width modulation signal pwm. PWM control is performed in the DC / DC converter 1 based on the pulse width modulation signal pwm.

The pulse width modulation signal pwm output from the PWM comparator 10 is applied to the drive circuit 3 in the subsequent stage to complementarily turn on / off the switching element T11 and the rectifying element T12. A sequential circuit (for example, RS flip-flop) (not shown) is prepared inside the drive circuit 3. A clock signal CLK, which is a square wave signal generated by the oscillator 9, is applied to the set terminal of the RS flip-flop, and a pulse width modulation signal pwm is applied to the reset terminal. In this case, the clock signal CLK corresponds to the set signal of the RS flip-flop, and the pulse width modulation signal pwm corresponds to the reset signal of the RS flip-flop.

The slope voltage generation circuit 11 generates a slope signal Vsl in order to operate the PWM comparator 10 by pulse width modulation. The slope signal Vsl is a triangular wave-shaped signal generated based on the clock signal CLK generated by the oscillator 9. A voltage reflecting the magnitude of the switching voltage Vsw taken out from the node N1 is superimposed on the slope voltage generation circuit 11. More precisely, the slope voltage generation circuit 11 accepts the input of the input voltage Vin and the switching voltage Vsw, and the voltage between both ends of the switching element T11 (= Vin-Vsw = Sense × Ron (T11), but Ron (T11) generates a slope signal Vsl that reflects the on-resistance value of the switching element T11). As a result, the voltage waveform of the slope signal Vsl is superposed with the voltage reflecting the output detection current Sense or the load current IL, and constitutes a well-known current mode type DC / DC converter. In the present invention, the current mode type DC / DC converter is not an indispensable configuration requirement, and is also applied to the voltage mode type.

FIG. 2 shows a signal waveform taken out from the output stage of the DC / DC converter 1 shown in FIG. 1, that is, the node N1 and the output terminal VOUT. Hereinafter, FIG. 2 will be described with reference to FIG.

(A1) and (a2) of FIG. 2 are cases where the DC / DC converter 1 is controlled by the frequency modulation (PFM) method when the DC / DC converter 1 is in a light load state, and (a1) of FIG. 2 is a node. The switching voltage Vsw (referred to as the switching voltage SW1 here) taken out from N1 is shown. The frequency of the switching voltage SW1 is indicated by fosc1. The discontinuous signal components shown between the rectangular signals are caused by the phenomenon of zero crossing that occurs when there is no load or when there is a light load. The zero cross means a state in which the minimum value of the triangular wave current flowing through the node N1 is lower than the ground potential GND after the switching element T11 on period shown in FIG. 1 is switched to the rectifying element T12 on period.

With the conventional control method, fluctuations appear periodically in the output voltage Vout, and the ripple component becomes large. In addition to this, when there is current exchange between the input capacitor and the output capacitor, it becomes a so-called switching noise signal. When the frequency of this switching noise signal is placed in the audible frequency band, it causes audible discomfort to the human ear. INDUSTRIAL APPLICABILITY According to the present invention, it is possible to prevent noise due to switching noise at the time of light load and noise due to fluctuation of output voltage Vout and fluctuation of input voltage Vin immediately before switching between light load and heavy load by synchronous control. In order to suppress such switching noise, the oscillator 9 is controlled so that the frequency used in the PFM method is equal to or higher than the audible frequency band (for example, the oscillation frequency is 20 KHz or higher).

FIG. 2A2 shows an output voltage Vout (hereinafter referred to as an output voltage Vout1) output to the output terminal VOUT under the condition of the above (a1). The output voltage Vout1 generated at the output terminal VOUT has a ripple component superimposed on it. This ripple component is shown by enlarging the vertical width for convenience of drawing, but it is actually several tens of mV to 100 mV.

2 (b1) and (b2) of FIG. 2 are the cases where the DC / DC converter 1 is controlled by the frequency modulation (PFM) method when the DC / DC converter 1 is in a light load state, as in the case of (a1) and (a2) of FIG. The switching voltage Vsw (referred to as the switching voltage SW2 here) is shown. The frequency of the switching voltage SW2 shown in FIG. 2 (b1) is shown by fosc2, but this frequency fosc2 is higher than the frequency fosc1 of the switching voltage SW1 shown in FIG. 2 (a1). However, under the condition of (b1) above, the output voltage Vout (referred to as the output voltage Vout2 here) output to the output terminal VOUT contains a ripple component having a frequency fosc21 lower than the frequency fosc1. show. For example, the frequency fosc2 is 100 KHz, and even if it is sufficiently higher than the audible frequency band, the frequency fosc21 may be lower than the audible frequency band. When such an event occurs, the so-called "swelling sound" generated in the smoothing capacitor C1 is heard by the human ear or affects other electronic devices to become noise, which causes discomfort to the human being. In order to solve such a problem, in the present invention, the output detection current Sense is detected and the oscillation frequency Fosc of the oscillator 9 is controlled. As a result, stable switching is achieved, and frequency components such as the frequency fosc21 are not generated.

FIG. 2B1 shows a case where the DC / DC converter 1 is controlled by the frequency modulation (PFM) method as in FIG. 2A, and the load state is higher than that in FIG. 2A1. The switching voltage Vsw (referred to as switching voltage SW3 here) in a heavy medium load state is shown. The frequency of the switching voltage SW3 is indicated by fosc3. The frequency fosc3 is higher than the frequency fosc1 shown in FIG. 2 (a1), and is placed in the relationship of fosc3> fosc1. Therefore, even with the same PFM method, the oscillation frequency Fosc of the clock signal CLK generated by the oscillator 9 increases as the load becomes heavier, and the oscillation frequency Fosc of the clock signal CLK generated by the oscillator 9 increases as the load becomes lighter. Indicates that it is controlled to be low. The period and amplitude in which the discontinuous signal components are generated, which are shown between the rectangular wavy signals of the switching voltages SW2 and SW3, correspond to zero cross.

FIG. 2 (c2) shows the output voltage Vout (hereinafter referred to as the output voltage Vout3) output to the output terminal VOUT under the condition of the above (c1). The output voltage Vout3 generated at the output terminal VOUT has a ripple component superimposed on it, as in (a2) of FIG.

In (d1) and (d2) of FIG. 2, unlike (a1), (a2), (b1), (b2), (c1) and (c2) of FIG. 2, the DC / DC converter 1 has a pulse width. The switching voltage Vsw (referred to as the switching voltage SW4 here) when controlled by the modulation (PWM) method, that is, when the load state is a heavy load is shown. The frequency of the switching voltage SW4 is indicated by fosc4. It should be noted that there is no period during which a discontinuous signal component is generated between the rectangular signal of the switching voltage SW4. This is because, in the heavy load state, the minimum value of the triangular wave-shaped current (coil current) is sufficiently higher than the ground potential GND, and zero crossing does not occur.

(D2) of FIG. 2 shows an output voltage Vout (here, referred to as an output voltage Vout4) output to the output terminal VOUT under the condition of the above (d1). The output voltage Vout4 generated at the output terminal VOUT has a ripple component superimposed on it, as in (a2), (b2) and (c2) of FIG.

<Second Embodiment of the present invention>
FIG. 3 is a circuit diagram showing a current mode synchronous rectification boost type DC / DC converter according to the present invention. The DC / DC converter 2 boosts the input voltage Vin supplied to the input terminal VIN and takes out a desired output voltage Vout to the output terminal VOUT.

The DC / DC converter 2 of this configuration example includes a switching element T21, a rectifier element T22, a drive circuit 3, an output current detection unit 4, a reverse current detection circuit 5, a feedback voltage generation circuit 6, an error amplifier 7, and a phase compensation circuit 8. It includes an oscillator 9, a PWM comparator 10, a slope voltage generation circuit 11, an inductor L2, and a smoothing capacitor C2.

The DC / DC converter 2 is different from the step-down type shown in FIG. 1 in the circuit portion in the subsequent stage of the drive circuit 3. Other circuit parts are the same. Here, a circuit section in which the two are different will be described.

The switching element T21 is an N-channel type MOS field effect transistor connected to the rectifying element T22, the drive circuit 3, and the inductor L2, and functions as a switching transistor that controls the current flowing through the inductor L2 by repeating on / off. do. The switching element T21 operates complementarily in synchronization with the rectifying element T22. The source S of the switching element T21 is connected to the ground potential GND. The drain D of the switching element T21 is commonly connected to the drain D of the rectifying element T22 and one end of the inductor L2. This common connection point is indicated by node N1. A gate signal GL is applied to the gate G of the switching element T21 from the drive circuit 3. The switching element T21 is turned on when the gate signal GL is at a high level and turned off when the gate signal GL is at a low level.

The other end of the inductor L2 is connected to the input terminal VIN to which the input voltage Vin is supplied via the output current detection unit 4. That is, the switching element T21 is coupled to the input voltage Vin via the inductor L2. The switching element T21 controls the current flowing through the inductor L2.

The drain D of the rectifying element T22 is connected to the drain D of the switching element T21 and one end of the inductor L2. The source S of the rectifying element T22 is connected to the node N2, that is, the output terminal VOUT. A gate signal GH is applied to the gate G of the rectifying element T22 from the drive circuit 3. The rectifying element T22 is turned off when the gate signal GH is at a high level and turned on when the gate signal GH is at a low level.

A smoothing capacitor C2 is connected between the node N2, that is, the output terminal VOUT, and the ground potential GND. The smoothing capacitor C2 performs rectifying and smoothing operations together with the inductor L2 and the rectifying element T22.

It is also possible to adopt an asynchronous rectification method instead of the synchronous rectification method using the rectifying element T22. In that case, the rectifier diode D22 is used as a substitute for the rectifier element T22. In this case, the anode A of the rectifier diode D22 may be connected to the node N1, and the cathode K of the rectifier diode D22 may be connected to the node N2 (output terminal VOUT).

The above description is that the second embodiment of the present invention, that is, the synchronous rectification step-up type DC / DC converter 2, is different from the synchronous rectification step-down type DC / DC converter 1 shown in FIG. Since the other circuit parts are the same as those in FIG. 1, the description is omitted. Also in the DC / DC converter 2, the oscillator 9 provided with the constant current source CC and the linear current source CL will be applied. In the first embodiment of the present invention, the step-down type is exemplified, and in the second embodiment, the step-up type is exemplified, but the so-called buck-boost type DC / that switches between the step-down type and the step-up type. Needless to say, it can be applied to a DC converter.

FIG. 4 shows oscillation of the clock signal CLK of the oscillator 9 in response to the magnitude of the load current IL flowing through the load RL in each of the DC / DC converter 1 of FIG. 1 and the DC / DC converter 2 of FIG. It is a figure which shows the state which the frequency Fosc changes. From IL1 to IL2 where the load current IL is relatively small, frequency modulation (PFM) control is performed in which the oscillation frequency Fosc changes according to the magnitude of the load current IL. On the other hand, when the load current IL exceeds IL2, it is switched to pulse width modulation (PWM) control in which the oscillation frequency Fosc is fixed. When the load current IL falls below IL1, the oscillation frequency Fosc is maintained at fosc (a), and the constant current Icc and linear current Icl of the oscillator 9 shown in FIGS. 1 and 2 are prevented so that the oscillation frequency does not become lower than this. Is controlled. The oscillation frequency fosc (a) is set to the upper limit of the audible frequency band (for example, around 20 KHz).

As described above, when the load current IL (or output detection current Sense) is larger than the predetermined value IL2, the oscillator 9 sets the oscillation frequency Fosc of the rectangular wave signal CLK as a fixed value and sets the load current IL (or output detection current Sense). When is smaller than the predetermined value IL2, the oscillation frequency of the rectangular wave signal CLK is lowered from the fixed value as the load current IL (or output detection current Sense) becomes smaller.

5 shows the constant current Icc, the linear current Icl, and the oscillator current Iosc1 set by the oscillator 9 and the output detection in each of the DC / DC converter 1 of FIG. 1 and the DC / DC converter 2 of FIG. It is a figure which shows the relationship with the electric current Sense. The output detection current Sense has a magnitude proportional to the load current IL. FIG. 5 shows a case where the oscillator current Iosc1 is determined by the sum (+) of the constant current Icc and the linear current Icl.

In FIG. 5, the constant current Icc is always maintained at a constant magnitude without responding to the output detection current Sense. On the other hand, the linear current Icl is increased or decreased in proportion to the output detection current Sense in the section where the output detection current Sense is Is10 to Is20, but is maintained constant when the output detection current Sense exceeds Is20. NS. As a result, the oscillator current Iosc1 set by the sum of these two responds to the linear current Icl. The control of the oscillator current Iosc1 is the basis for controlling the oscillation frequency Fosc of the clock signal CLK generated by the oscillator 9, and eventually switching between PFM control and PWM control. When the output detection current Issue is lower than Is10, the oscillator current Iosc1 is fixed to a predetermined magnitude. As a result, the decrease in the oscillation frequency Fosc of the clock signal CLK generated by the oscillator 9 is suppressed. In any case, when the PFM control is entered, the linear current Icl becomes dominant in the control of the oscillation frequency Fosc.

FIG. 6 shows the output detection of the constant current Icc, the linear current Icl, and the oscillator current Iosc2 set by the oscillator 9 in each of the DC / DC converter 1 of FIG. 1 and the DC / DC converter 2 of FIG. It is a figure which shows the relationship with the electric current Sense. The output detection current Sense has a magnitude proportional to the load current IL. FIG. 6 shows a case where the oscillator current Iosc2 is determined by the difference (−) between the constant current Icc and the linear current Icl.

In FIG. 6, the constant current Icc is always maintained at a constant magnitude without responding to the output detection current Sense. It shows the same characteristics as that of FIG. On the other hand, the linear current Icl is increased or decreased in proportion to the output detection current Sense in the section where the output detection current Sense exceeds Is2, but is maintained constant when the output detection current Sense exceeds Is2. .. These characteristics are also the same as in FIG. As a result, the oscillator current Iosc2 set by the difference between the two responds to the linear current Icl. In FIG. 6, the constant current Icc is subtracted from the linear current Icl, but the linear current Icl may be subtracted from the constant current Icc. In such a case, the circuit configuration of the oscillator 9 is formed so that the linear current Icl decreases as the output detection current Issue increases from Is1 to Is2.

FIG. 7 is a diagram showing the relationship between the oscillator currents Iosc1 and Iosc2 shown in FIGS. 5 and 6, respectively, and the oscillation frequency Fosc of the clock signal CLK generated by the oscillator 9. Note that FIG. 7 is substantially the same as that shown in FIG. That is, FIG. 4 shows how the change in the oscillation frequency Fosc depends on the load current IL, but FIG. 7 shows how the oscillation frequency Fosc is controlled depending on the oscillator currents Iosc1 and Iosc2. .. In the section where the oscillator currents Iosc1 and Iosc2 are from Iosc12a to Iosc12b, PFM control is performed. On the other hand, when the oscillator currents Iosc1 and Iosc2 exceed Iosc12b, PWM control is performed.

<Oscillator>
FIG. 8 is a diagram showing a configuration example of the oscillator unit OSCr. The oscillator unit OSCr in this figure includes P-channel type MOS electric field effect transistors P11 to P16, N-channel type MOS electric field effect transistors N11 to N15, capacitors C11 and C12, and resistors R11 and R12, and includes a current source CS11. It is a kind of CR oscillator that generates a rectangular wave signal CLK with an oscillation frequency of Fosc by periodically repeating charging and discharging of capacitors C11 and C12 using the oscillator current Iosc generated in.

The current source CS11 corresponds to the above-mentioned constant current source CC and the above-mentioned linear current source CL, and the oscillator current Iosc corresponds to the above-mentioned oscillator current Iosc1 or Iosc2. The configuration and operation of the current source CS11 will be described in detail later.

The sources of the transistors P11 to P16 are all connected to the application end of the power supply voltage Vcc. The gates of the transistors P11 to P16 are all connected to the drain of the transistor P11. The drain of the transistor P11 is connected to the first end (= output end of the oscillator current Iosc) of the current source CS11.

As described above, the transistors P11 to P16 make the oscillator current Iosc flowing through the drain of the transistor P11 a predetermined mirror ratio A to E (for example, A = 4, B = 4, C = 2, D = 4, E = 1). By copying each of them, a current mirror circuit for generating mirror currents IP12 to IP16 of a plurality of systems (5 systems in this figure) is formed.

The drain of the transistor P12 is connected to the first end of the capacitor C11, the drain of the transistor N11, and the gate of the transistor N12. The drain of the transistor P13 is connected to the drain of the transistor N12 and the gate of the transistor N13. The drain of the transistor P14 is connected to the first end of the capacitor C12, the drain of the transistor N13, and the gate of the transistor N14. The drain of the transistor P15 is connected to the drain of the transistor N14 and the gate of the transistor N15. The drain of the transistor P16 is connected to the drain of the transistor N15 and the gate of the transistor N11.

The source of the transistor N12 is connected to the first end of the resistor R11. The source of transistor N14 is connected to the first end of resistor R12. The second end of the current source CS11, the source of the transistor N11, the second end of the capacitor C11, the second end of the resistor R11, the source of the transistor N13, the second end of the capacitor C12, the second end of the resistor R12, and the transistor N15. The second end of each is connected to the grounding end.

FIG. 9 is a timing chart for explaining the operation of the oscillator unit OSCr, and the node voltage V11, the node voltage V13, the node voltage V12, the node voltage V14, and the node voltage V15 are drawn in order from the top.

The node voltage V11 is the gate voltage of the transistor N12. The node voltage V12 is the gate voltage of the transistor N13. The node voltage V13 is the gate voltage of the transistor N14. The node voltage V14 is the gate voltage of the transistor N15. The node voltage V15 is the gate voltage of the transistor N11. For example, the node voltage V15 is output as a rectangular wave signal CLK. Before the power supply voltage Vcc is applied to the oscillator unit OSCr, the node voltages V11 to V15 are all at a low level.

When the power supply voltage Vcc is applied to the oscillator unit OSCr, charging of the capacitor C11 by the mirror current IP12 is started, so that the node voltage V11 starts to rise. However, when the node voltage V11 is lower than the threshold voltage Vtri1 (= VGS (N12) + R11 × IP13, VGS (N12) is the on-threshold voltage of the transistor N12), the transistor N12 is not turned on. As a result, the node voltage V12 becomes high level and the transistor N13 turns on. When the transistor N13 is on, both ends of the capacitor C12 are short-circuited, so that the node voltage V13 becomes low level and the transistor N14 turns off. Therefore, since the node voltage V14 becomes high level and the transistor N15 turns on, the node voltage V15 becomes low level and the transistor N11 turns off. When the transistor N11 is off, both ends of the capacitor C11 are open, so that the charging of the capacitor C11 is continued.

After that, when the node voltage V11 rises and exceeds the threshold voltage Vtri1, the transistor N12 is turned on, so that the node voltage V12 becomes a low level and the transistor N13 is turned off. When the transistor N13 is off, both ends of the capacitor C12 are opened, and charging of the capacitor C12 by the mirror current IP14 is started, so that the node voltage V13 starts to rise. However, when the node voltage V13 is lower than the threshold voltage Vtri2 (= VGS (N14) + R12 × IP15, where VGS (N14) is the on-threshold voltage of the transistor N14), the transistor N14 does not turn on. As a result, the node voltage V14 is maintained at a high level, so that the transistor N15 remains on. Therefore, the node voltage V15 is maintained at a low level, so that the transistor N11 remains off. As described above, when the transistor N11 is off, both ends of the capacitor C11 are open, so that the charging of the capacitor C11 is continued.

The time t1 required from when the node voltage V11 starts to rise until when the threshold voltage Vtri1 is exceeded can be expressed by t1 = C11 × Vtri1 / IP12. That is, the larger the mirror current IP12 (and thus the oscillator current Iosc), the shorter the time t1.

After that, when the node voltage V13 rises and exceeds the threshold voltage Vtri2, the transistor N14 turns on, the node voltage V14 becomes a low level, and the transistor N15 turns off, so that the node voltage V15 becomes a high level. As a result, when the transistor N11 is turned on and both ends of the capacitor C11 are short-circuited, the node voltage V11 becomes low level and the transistor N12 is turned off, so that the node voltage V12 becomes high level and the transistor N13 turns on. At this time, since both ends of the capacitor C12 are short-circuited, the node voltage V13 becomes low level and the transistor N14 is turned off again. Therefore, since the node voltage V14 rises to a high level and the transistor N15 turns on, the node voltage V15 falls to a low level and the transistor N11 turns off.

The time t2 required from the start of the node voltage V12 to exceeding the threshold voltage Vtri2 can be expressed by t2 = C12 × Vtri2 / IP14. That is, the larger the mirror current IP14 (and thus the oscillator current Iosc), the shorter the time t2.

By repeating the above series of operations, a rectangular wave signal CLK (= node voltage V15) having an oscillation frequency of Fosc (= 1 / (t1 + t2)) can be generated. The larger the oscillator current Iosc, the shorter the times t1 and t2, and the higher the oscillation frequency Fosc. On the contrary, as the oscillator current Iosc becomes smaller, the times t1 and t2 become longer, so that the oscillation frequency Fosc becomes lower.

<Current source>
FIG. 10 is a diagram showing a first configuration example of the current source CS11. The current source CS11 of the first configuration example includes a constant current source CC that generates a constant current Icc and a linear current source CL that generates a linear current Icl.

The constant current source CC includes a constant voltage source 111, an npn type bipolar transistor 112, and a resistor 113.

The constant voltage source 111 is a circuit unit that generates a constant voltage V111, and a bandgap reference voltage source or the like can be preferably used.

The transistor 112 and the resistor 113 function as a voltage / current converter that converts the constant voltage V111 into a constant current Icc. Specifically describing the connection relationship, the base of the transistor 112 is connected to the output end (= application end of the constant voltage V111) of the constant voltage source 111. The emitter of the transistor 112 is connected to the first end of the resistor 113. The second end of the resistor 113 is connected to the ground end. The collector of the transistor 112 corresponds to the output end of the constant current Icc.

The linear current source CL includes a voltage output type differential amplifier 121, an npn type bipolar transistor 122, and a resistor 123.

The differential amplifier 121 has a difference between the input voltage Vin input to the non-inverting input terminal (+) and the switch voltage Vsw input to the inverting input terminal (-) (= voltage between both ends during the ON period of the switching element T11). ), A linear voltage V121 is generated. The larger the output detection current Issue that flows during the ON period of the switching element T11, the lower the switch voltage Vsw, and the higher the linear voltage V121. In this way, if the switch voltage Vsw is used not only for the current mode control but also for the variable control of the oscillation frequency Fosc, the output current detection unit 4 is omitted (= slope voltage generation circuit 11 and linear current source). Since the output detection unit 4 can be shared by both CLs), the circuit scale of the DC / DC converter 1 can be reduced.

The transistor 122 and the resistor 123 function as a voltage / current converter that converts the linear voltage V121 into a linear current Icl. Specifically describing the connection relationship, the base of the transistor 122 is connected to the output end (= application end of the linear voltage V121) of the differential amplifier 121. The emitter of the transistor 122 is connected to the first end of the resistor 123. The second end of the resistor 123 is connected to the ground end. The collector of the transistor 122 corresponds to the output end of the linear current Icl. The linear current Icl fluctuates in proportion to the linear voltage V121 (and thus the output detection current Sense).

In the current source CS11 of this configuration example, the collectors of both the transistors 112 and 122 are commonly connected to the output end of the oscillator current Iosc. Therefore, the oscillator current Iosc (= Icc + Icl) can be generated by adding the constant current Icc and the linear current Icl. This oscillator current Iosc corresponds to the oscillator current Iosc1 in FIG.

FIG. 11 is a diagram showing a second configuration example of the current source CS11. The current source CS11 of the second configuration example is based on the first configuration example (FIG. 10), and the configuration of the linear current source CL has been changed. Therefore, the same components as those in the first configuration example are designated by the same reference numerals as those in FIG. 10 and duplicated description is omitted, and the feature portions of the second configuration example will be mainly described below.

Unlike the first configuration example (FIG. 10), the linear current source CL includes a current output type differential amplifier 124 and a current mirror circuit 125.

The differential amplifier 124 has a difference between the input voltage Vin input to the non-inverting input end (+) and the switch voltage Vsw input to the inverting input terminal (-) (= voltage between both ends of the switching element T11 during the ON period). ) Is directly generated. The larger the output detection current Sense that flows during the ON period of the switching element T11, the larger the linear current Icl1 is in proportion to this. As described above, the output current detection unit 4 can be omitted if the switch voltage Vsw is used not only for the current mode control but also for the variable control of the oscillation frequency Fosc. Therefore, the DC / DC converter 1 can be used. It is possible to reduce the circuit scale. This point is the same as that of the first configuration example (FIG. 10).

The current mirror circuit 125 is connected between the output end and the ground end of the differential amplifier 124, and turns back the direction in which the linear current Icl flows. More specifically, the current mirror circuit 125 draws the linear current Icl from the output end of the oscillator current Iosc by mirroring the linear current Icl that flows into itself.

In the current source CS11 of this configuration example, the collector of the transistor 112 and the output end of the current mirror circuit 125 are commonly connected to the output end of the oscillator current Iosc. Therefore, the oscillator current Iosc (= Icc + Icl) can be generated by adding the constant current Icc and the linear current Icl. This oscillator current Iosc corresponds to the oscillator current Iosc1 in FIG. This point is the same as that of the first configuration example (FIG. 10).

FIG. 12 is a diagram showing a third configuration example of the current source CS11. The current source CS11 of the third configuration example is based on the first configuration example (FIG. 10), and a current mirror circuit 130 is added. Therefore, the same components as those in the first configuration example are designated by the same reference numerals as those in FIG. 10, and duplicated explanations are omitted. Hereinafter, the characteristic portions of the third configuration example will be mainly described.

The current mirror circuit 130 is connected between the output end and the power supply end of the constant current source CC, and turns back the direction in which the constant current Icc flows. More specifically, the current mirror circuit 130 causes a linear current Icl to flow into the output end of the oscillator current Iosc by mirroring the constant current Icc drawn into the constant current source CC.

In the current source CS11 of this configuration example, the collector of the transistor 122 and the output end of the current mirror circuit 130 are commonly connected to the output end of the oscillator current Iosc. Therefore, the oscillator current Iosc (= Icl-Icc) can be generated by subtracting the constant current Icc from the linear current Icl. This oscillator current Iosc corresponds to the oscillator current Iosc2 in FIG.

FIG. 13 is a diagram showing a fourth configuration example of the current source CS11. The current source CS11 of the fourth configuration example is based on the third configuration example (FIG. 12), and the same linear current source CL as that of the second configuration example (FIG. 11) is used. Even if such a modification is applied, the oscillator current Iosc (= Icl-Icc) obtained by subtracting the constant current Icc from the linear current Icl can be generated. This point is the same as that of the third configuration example (FIG. 12).

In the oscillator 9, the current mirror circuit is used as a means for generating the constant current Icc and the linear current Icl, adding or subtracting them, and setting the current ratios thereof, as described above. It is desirable to use it.

As described above, since the DC / DC converter of the present invention adjusts the oscillation frequency of the oscillator based on the output detection current proportional to the load current, it is possible to smoothly switch between PWM control and PFM control. As a result, it can be applied to a wide range of DC / DC converters regardless of the difference between the voltage mode type and the current mode type, and the step-down type, the step-up type, and the step-up / down type, so that it has high industrial applicability.

1, 2 DC / DC converter 3 Drive circuit 4 Output current detector 5 Reverse current detection circuit 6 Feedback voltage generation circuit 7 Error amplifier 8 Phase compensation circuit 9 Oscillator 10 PWM comparator 11 Slope voltage generation circuit C1, C2 Smoothing capacitor C3 Capacitor CC Constant current source CL Linear current source D12, D22 Rectifier diode GH, GL Gate signal OSCr Oscillator CLK Clock signal Fosc Oscillation frequency Szc Zero cross detection signal Icc Constant current Icl Linear current pwm Pulse width modulation signal Iosc1, Iosc2 Oscillator current IL Output detection current L1, L2 inductor N1 to N3 node R1 to R3 resistance RL load T11, T21 switching element T12, T22 rectifying element Vcc power supply voltage VIN input terminal Vin input voltage Vsw switching voltage VOUT output terminal Vout output voltage Vfb feedback voltage Vref reference Voltage Verr error signal Vsl slope signal P11-P16 P-channel type MOS electric field effect transistor N11-N15 N-channel type MOS electric field effect transistor C11, C12 capacitor R11, R12 resistance CS11 current source 111 constant voltage source 112 npn type bipolar transistor 113 resistance 121 Differential amplifier (voltage output type)
122 npn type bipolar transistor 123 resistance 124 differential amplifier (current output type)
125 Current mirror circuit 130 Current mirror circuit

Claims (18)

A switching element that is connected to the input voltage and performs on / off operation,
A drive circuit that controls on / off of the switching element and
An inductor whose current is controlled by the switching element and
A smoothing capacitor connected to the inductor and performing a rectifying operation together with the inductor,
An oscillator that generates a square wave signal that operates the drive circuit,
The output current detection unit for detecting the output detection current flowing through the switching element or the inductor is provided.
The oscillator generates the square wave signal at a fixed oscillation frequency when the output detection current is equal to or higher than a predetermined value, and when the output detection current is equal to or lower than a predetermined value, the oscillator is higher than the fixed oscillation frequency. The square wave signal is generated at an oscillation frequency that is low and proportional to the output detection current.
The oscillator includes a constant current source that generates a constant constant current regardless of the magnitude of the output detection current, and a linear current source that generates a linear current that responds to the magnitude of the output detection current.
The oscillation frequency of the oscillator is set based on the oscillator current set by the sum of the constant current and the linear current or the difference between the two.
The linear current source includes a voltage output type differential amplifier that generates a linear voltage corresponding to the voltage between both ends of the switching element, and a voltage / current converter that converts the linear voltage into the linear current. DC converter. A switching element that is connected to the input voltage and performs on / off operation,
A drive circuit that controls on / off of the switching element and
An inductor whose current is controlled by the switching element and
A smoothing capacitor connected to the inductor and performing a rectifying operation together with the inductor,
An oscillator that generates a square wave signal that operates the drive circuit,
The output current detection unit for detecting the output detection current flowing through the switching element or the inductor is provided.
The oscillator generates the square wave signal at a fixed oscillation frequency when the output detection current is equal to or higher than a predetermined value, and when the output detection current is equal to or lower than a predetermined value, the oscillator is higher than the fixed oscillation frequency. The square wave signal is generated at an oscillation frequency that is low and proportional to the output detection current.
The oscillator includes a constant current source that generates a constant constant current regardless of the magnitude of the output detection current, and a linear current source that generates a linear current that responds to the magnitude of the output detection current.
The oscillation frequency of the oscillator is set based on the oscillator current set by the sum of the constant current and the linear current or the difference between the two.
The linear current source is a DC / DC converter including a current output type differential amplifier that generates the linear current according to a voltage between both ends of the switching element. The linear current is fixed to the first current value when the output detection current is smaller than the first threshold value, and is large when the output detection current is larger than the first threshold value and smaller than the second threshold value. It is is variably controlled from the first current value in response to the second current value, when the output detection current is greater than said second threshold according to claim 1 or 2 is fixed to the second current value DC / DC converter. The DC / DC converter according to claim 1 or 2, wherein PWM control is performed when the output detection current is equal to or more than a predetermined value, and PFM control is performed when the output detection current is equal to or less than a predetermined value. The DC / DC converter according to claim 4 , wherein when the PFM control is performed, the setting of the oscillation frequency of the oscillator is controlled by the linear current. The DC / DC converter according to claim 4 , wherein when the PFM control is performed, the lower limit value of the oscillation frequency is equal to or higher than the audible frequency band. The DC / DC converter further compares the feedback voltage generated based on the voltage generated in the smoothing capacitor with the reference voltage preset to a predetermined magnitude, and outputs the difference between the two voltages as an error signal. A claim including an error amplifier, a slope circuit that generates a slope signal based on a square wave signal generated by the oscillator, and a PWM comparator that outputs a comparison result signal between the error signal and the slope signal to the drive circuit. The DC / DC converter according to any one of items 1 to 6. The DC / DC converter according to claim 7 , wherein a voltage component corresponding to the output detection current is superimposed on the slope signal. Claims 1 to claim that the DC / DC converter further includes a rectifying element coupled to a common node of the switching element and the inductor in order to supply a current to the inductor when the switching element is turned off. Item 2. The DC / DC converter according to any one of Item 8. The DC / DC converter further comprises a reverse current detection circuit for detecting a reverse current flowing toward the common node from the ground potential, when the reverse current detector circuit detects the predetermined said reverse current, the The DC / DC converter according to claim 9 , wherein the operation of the rectifying element or the switching element coupled to the ground potential is turned off. The DC / DC converter according to claim 7 or 8, wherein the error amplifier is a transconductance type. The DC / DC converter according to any one of claims 1 to 11 , wherein the DC / DC converter is a current mode type or a voltage mode type. The DC / DC converter according to any one of claims 1 to 12 , wherein the DC / DC converter is any one of a step-down type, a step-up type, and a buck-boost type. The DC / DC converter according to any one of claims 1 to 13, further comprising an oscillator unit that generates the square wave signal by repeating charging and discharging of a capacitor using the oscillator current. The DC / according to any one of claims 1 to 14, wherein the constant current source includes a constant voltage source that generates a constant voltage and a voltage / current converter that converts the constant voltage into the constant current. DC converter. 13. The DC / DC converter described. It has an oscillator that generates a square wave signal and a drive circuit that drives the switch output stage of the DC / DC converter in synchronization with the square wave signal.
When the output detection current flowing through the switch output stage is larger than a predetermined value, the oscillator sets the oscillation frequency of the square wave signal as a fixed value, and when the output detection current is smaller than the predetermined value, the output detection current. the higher the smaller Ki have reduced the oscillation frequency of the rectangular wave signal from the fixed value,
The oscillator includes a constant current source that generates a constant constant current regardless of the magnitude of the output detection current, and a linear current source that generates a linear current that responds to the magnitude of the output detection current.
The oscillation frequency of the oscillator is set based on the oscillator current set by the sum of the constant current and the linear current or the difference between the two.
The linear current source is a voltage output type differential amplifier that generates a linear voltage corresponding to the voltage between both ends of the switching element included in the switch output stage, and a voltage / current conversion that converts the linear voltage into the linear current. Power control device including the part. It has an oscillator that generates a square wave signal and a drive circuit that drives the switch output stage of the DC / DC converter in synchronization with the square wave signal.
When the output detection current flowing through the switch output stage is larger than a predetermined value, the oscillator sets the oscillation frequency of the square wave signal as a fixed value, and when the output detection current is smaller than the predetermined value, the output detection current. the higher the smaller Ki have reduced the oscillation frequency of the rectangular wave signal from the fixed value,
The oscillator includes a constant current source that generates a constant constant current regardless of the magnitude of the output detection current, and a linear current source that generates a linear current that responds to the magnitude of the output detection current.
The oscillation frequency of the oscillator is set based on the oscillator current set by the sum of the constant current and the linear current or the difference between the two.
The linear current source is a power supply control device including a current output type differential amplifier that generates the linear current according to the voltage between both ends of the switching element included in the switch output stage.

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