JP6927673B2 - Built-in PLL device and PLL interference prevention method - Google Patents

Description

The present invention relates to a PLL built-in device and a PLL interference prevention method that include at least two PLL circuits and prevent interference of the PLL circuits by changing the settings of the PLL circuits.

The PLL (Phase Locked Loop) circuit inputs the phase difference between the input signal as the reference frequency and the output signal of the voltage controlled oscillator (VCO) that changes the frequency according to the voltage to the voltage controlled oscillator. This is a circuit that synchronizes the phases of the input signal and the output signal. The PLL circuit is called a phase-locked loop. The PLL circuit is used for applications such as multiplication, phase synchronization, and clock extraction. Some electronic devices are provided with a plurality of PLL circuits.

When a plurality of PLL circuits for multiplication (that is, a PLL circuit that generates a high frequency clock signal from a low frequency reference clock signal) are provided in one board, the voltage control oscillator included in the plurality of PLL circuits The frequency of the output signal is transmitted to other PLL circuits as conduction noise via the printed circuit board, and is transmitted to other PLL circuits as radiation noise via space. Then, each PLL circuit may malfunction due to noise interference between the PLL circuits. In addition, devices such as FPGA (field-programmable gate array), ADC (analog to digital converter), and DAC (digital to analog converter) also have built-in PLL circuits, and these PLL circuits also generate noise interference. However, each device may malfunction.

As a method for preventing noise interference between PLL circuits, for example, there is one described in Patent Document 1. In Patent Document 1, the frequency of the output signal in one of the PLL circuits is changed so that the frequency bands of the output signals in the two PLL circuits do not overlap.

Japanese Unexamined Patent Publication No. 2007-295363 (0021, FIG. 2, etc.)

In the method described in Patent Document 1, the frequencies of the output signals of the PLL circuits are changed so that the frequency bands of the output signals of the two PLL circuits do not overlap. However, the frequency of the output signal of the PLL circuit is predetermined by the specifications of the device and cannot be easily changed in many cases. Further, in the method described in Patent Document 1, the individual difference between the device (the PLL circuit itself, the device having the PLL circuit built-in) and the board on which the PLL circuit is mounted is not taken into consideration. Therefore, noise interference between the PLL circuits may occur depending on the device or board.

The present invention has been made in view of the above-mentioned circumstances, and it is possible to prevent interference between PLL circuits without changing the frequency of the output signal of the PLL circuit and regardless of individual differences of devices and the like. It is an object of the present invention to provide a built-in device and a method for preventing PLL interference.

In order to achieve the above object, the present invention is a PLL built-in device including at least two PLL circuits including a first PLL circuit and a second PLL circuit, and preventing interference of the PLL circuits by changing the settings of the PLL circuits. Each of the PLL circuits has a configuration in which a frequency divider is connected between the output of the VCO and the input of the phase comparator, and is included in the frequencies fc1 and the second PLL circuit of the first VCO included in the first PLL circuit. The frequency fc2 of the second VCO, the bandwidth fw1 of the frequency of the first VCO, the bandwidth fw2 of the frequency of the second VCO, and the interval α between the frequency band of the first VCO and the frequency band of the second VCO are {| fc1-fc2. | -(Fw1 + fw2) / 2 ≧ α}, and the built-in PLL is provided with a first setting unit for setting the frequencies of the first VCO and the second VCO so as to satisfy the relationship of | fc1-fc2 | ≧ 400 MHz. Provide the device.

Further, in the present invention, α may be a value obtained by adding a margin to the value of | fc1-fc2 | when the spurious generation rate becomes 0.

Further, in the present invention, the first charge pump and the first charge pump and the first charge pump so that the difference between the phase of the first charge pump included in the first PLL circuit and the phase of the second charge pump included in the second PLL circuit is π / 6 or more. 2 The configuration may include a second setting unit for setting the phase of the charge pump.

Further, in the present invention, the first charge pump and the first charge pump and the first charge pump so that the switching frequency of the second charge pump included in the second PLL circuit becomes 1 / (4n + 1) of the switching frequency of the first charge pump included in the first PLL circuit. 2 The configuration may include a third setting unit for setting the switching frequency of the charge pump.

Further, the present invention is a PLL interference prevention method in which at least two PLL circuits including a first PLL circuit and a second PLL circuit are provided, and interference of the PLL circuits is prevented by changing the settings of the PLL circuits. Each of the above has a configuration in which a frequency divider is connected between the output of the VCO and the input of the phase-locked loop, and the frequency fc1 of the first VCO included in the first PLL circuit and the frequency of the second VCO included in the second PLL circuit. The interval α between fc2, the frequency bandwidth fw1 of the first VCO, the frequency bandwidth fw2 of the second VCO, and the frequency band of the first VCO and the frequency band of the second VCO is {| fc1-fc2 |-(fw1 + fw2). Provided is a PLL built-in device comprising a first step of setting the frequencies of the first VCO and the second VCO so as to satisfy the relationship of | fc1-fc2 | ≧ 400 MHz with / 2 ≧ α}. ..

Further, in the present invention, α may be a value obtained by adding a margin to the value of | fc1-fc2 | when the spurious generation rate becomes 0.

Further, in the present invention, the first charge pump and the first charge pump and the first charge pump so that the difference between the phase of the first charge pump included in the first PLL circuit and the phase of the second charge pump included in the second PLL circuit is π / 6 or more. 2 The configuration may include a second step of setting the phase of the charge pump.

Further, in the present invention, the first charge pump and the first charge pump and the first charge pump so that the switching frequency of the second charge pump included in the second PLL circuit becomes 1 / (4n + 1) of the switching frequency of the first charge pump included in the first PLL circuit. 2 The configuration may include a third step of setting the switching frequency of the charge pump.

According to the present invention, the frequency fc1 of the first VCO included in the first PLL circuit, the frequency fc2 of the second VCO included in the second PLL circuit, the bandwidth fw1 of the frequency of the first VCO, and the bandwidth fw2 of the frequency of the second VCO are { The frequencies of the first VCO and the second VCO are set so as to satisfy the relationship of | fc1-fc2 |-(fw1 + fw2) / 2 ≧ α}. According to such a configuration, since the frequency of the first VCO and the second VCO is set so that the first setting unit satisfies the above equation, the interference between the PLL circuits is not changed without changing the frequency of the output signal of the PLL circuit. Can be prevented. Further, since the oscillation frequency of the voltage controlled oscillator and the oscillation frequency of the voltage controlled oscillator are spaced by α, interference between the PLL circuits can be prevented regardless of individual differences of the device or the like. As a result, it is possible to surely prevent the malfunction of the plurality of PLL circuits.

Further, α is a value obtained by adding a margin to the value of | fc1-fc2 | when the spurious generation rate becomes 0, so that it is between the PLL circuits regardless of the device temperature, the device temperature, the device lot, and the like. Interference can be prevented.

Further, the first charge pump has a difference of π / 6 or more between the phase of the switching frequency of the first charge pump included in the first PLL circuit and the phase of the switching frequency of the second charge pump included in the second PLL circuit. And the phase of the switching frequency of the second charge pump is set. According to such a configuration, even if noise interference occurs despite the above measures, noise interference can be prevented by shifting the phase of the switching frequency of the charge pump. It is possible to avoid malfunction of the PLL circuit.

Further, the first charge pump and the second charge pump are set so that the switching frequency of the second charge pump included in the second PLL circuit is 1 / (4n + 1) of the switching frequency of the first charge pump included in the first PLL circuit. Set the switching frequency. According to such a configuration, even if noise interference occurs even after the above measures are taken, noise interference can be prevented by shifting the switching frequency (that is, the period) of the charge pump. This makes it possible to more reliably avoid malfunction of the PLL circuit.

It is a block diagram which shows the structure of the PLL built-in apparatus which concerns on embodiment. It is a block diagram which shows the structure of the 1st PLL circuit and the 2nd PLL circuit shown in FIG. It is a figure which shows the waveform of the frequency spectrum characteristic at the time of the interference of a voltage control oscillator. It is a figure for demonstrating the interference measures of a voltage control oscillator. It is a table which shows the verification result of the interference measures of a voltage control oscillator. It is a graph which shows the verification result of the interference measures of a voltage control oscillator. It is a figure which shows the waveform at the time of noise interference of a charge pump. It is a figure for demonstrating the charge pump interference measure by changing the phase. It is a table which shows the verification result of the charge pump interference measures by changing the phase. It is a graph which shows the verification result of the charge pump interference measures by changing the phase. It is a figure for demonstrating the charge pump interference measures by changing the frequency. It is a table which shows the verification result of the charge pump interference measures by changing the frequency.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention is not limited to this. Further, in the drawings, in order to explain the embodiment, the scale may be changed as appropriate, such as drawing a part in a large or emphasized manner.

FIG. 1 is a block diagram showing a configuration of a PLL built-in device 1 according to an embodiment. Further, FIG. 2 is a block diagram showing the configurations of the first PLL circuit 10 and the second PLL circuit 20 shown in FIG. In the PLL built-in device 1 shown in FIG. 1, the PLL circuit is a device including a plurality of PLL circuits. An example of the PLL built-in device 1 is a communication device. As shown in FIG. 1, the PLL built-in device 1 includes a first PLL circuit 10, a second PLL circuit 20, and a control unit 30. The PLL built-in device 1 is configured to include two PLL circuits 10 and 20, but may be configured to include three or more PLL circuits. Further, the PLL built-in device 1 is provided with, for example, a first PLL circuit 10, a second PLL circuit 20, and a control unit 30 in one board.

The first PLL circuit 10 is a circuit that generates a new signal synchronized with the phase of the input signal. As shown in FIG. 2, the first PLL circuit 10 includes a reference male oscillator 11, a frequency divider (R counter) 12, a frequency divider (N counter) 13, a phase comparator (PD) 14, and a charge pump. It has a (CP; Charge Pump) 15, a loop filter (LP) 16, and a voltage controlled oscillator (VCO) 17. In the present embodiment, the charge pump 15 is the first charge pump and the voltage controlled oscillator 17 is the first VCO.

The reference male oscillator 11 is an oscillator that generates a signal having a reference frequency fr. The reference male oscillator 11 is composed of, for example, an external crystal oscillator that generates a signal having a reference frequency fr with high accuracy. The frequency divider 12 divides the signal of the reference frequency fr from the reference oscillator 11 to a predetermined frequency division ratio (1 / R1), and transmits the divided reference frequency fr / R1 signal to the phase comparator 14. Output. The frequency division ratio of the frequency divider 12 is set by a control signal from the control unit 30. The frequency divider 13 divides the signal of the oscillation frequency fc1 output from the voltage control oscillator 17 to a predetermined frequency division ratio (1 / N1), and divides the divided signal of the oscillation frequency fc1 / N1 to the comparison frequency. It is output to the phase comparator 14 as a signal. The frequency division ratio of the frequency divider 13 is also set by the control signal from the control unit 30.

The phase comparator 14 compares the phases of the signal of the reference frequency fr / R1 from the frequency divider 12 and the signal of the comparison frequency fc1 / N1 from the frequency divider 13, and sends the pulse of the phase difference to the charge pump 15. Output. The charge pump 15 switches the connection state of the plurality of capacitors by using a switch, and outputs a voltage higher than the voltage of the pulse from the phase comparator 14 to the loop filter 16. The phase and period of the switching frequency of the charge pump 15 are set by a control signal from the control unit 30. The loop filter 16 removes the noise component of the pulse from the charge pump 15, converts the pulse into a DC voltage level, and outputs the pulse to the voltage controlled oscillator 17. The time constant of the loop filter 16 is also set by the control signal from the control unit 30.

The voltage controlled oscillator 17 oscillates a signal having a frequency corresponding to the DC voltage value from the loop filter 16, outputs a signal of the oscillation frequency fc1 to the frequency divider 18, and also outputs the frequency divider 13 (divider 13). It feeds back to the phase comparator 14) via. The oscillation frequency fc1 of the voltage controlled oscillator 17 is changed by changing the setting of at least one of the frequency division ratios of the frequency dividers 12 and 13. The frequency divider 18 divides the signal of the oscillation frequency fc1 output from the voltage controlled oscillator 17 into a predetermined frequency division ratio (1 / D1), and outputs the signal of the divided oscillation frequency fc1 / D1 (1 / D1). Output as a clock signal).

The second PLL circuit 20 is also a circuit that generates a new signal synchronized with the phase of the input signal. As shown in FIG. 2, the second PLL circuit 20 includes a reference male oscillator 21, a multiplier (Multiplier) 22, a frequency divider (R counter) 23, a frequency divider (N counter) 24, and a phase comparator (PD). It has 25, a charge pump (CP) 26, a loop filter (LP) 27, a voltage controlled oscillator (VCO) 28, and a prescaler 29. In the present embodiment, the charge pump 26 is the second charge pump and the voltage controlled oscillator 28 is the second VCO.

The reference male oscillator 21 is an oscillator that generates a signal having a reference frequency fr. Like the reference oscillator 11, the reference oscillator 21 is also composed of, for example, an external crystal oscillator that generates a signal having a reference frequency fr with high accuracy. The multiplier 22 converts the signal of the reference frequency fr from the reference oscillator 21 into the signal of the frequency fr · m which is an integral multiple m. An integral multiple of the multiplier 22 is set by a control signal from the control unit 30. The frequency divider 23 divides the signal of the reference frequency fr · m from the multiplier 22 into a predetermined division ratio (1 / R2), and phase-compares the divided signals of the reference frequency fr · m / R2. Output to the device 25. The frequency division ratio of the frequency divider 23 is set by a control signal from the control unit 30. The frequency divider 24 divides the signal of the predetermined frequency fc2 / P output from the prescaler 29 to a predetermined frequency division ratio (1 / N2), and compares the divided signals of the predetermined frequency fc2 / P / N2. It is output to the phase comparator 25 as a frequency signal. The frequency division ratio of the frequency divider 24 is also set by the control signal from the control unit 30.

The phase comparator 25 compares the phases of the signal of the reference frequency fr · m / R2 from the frequency divider 23 and the signal of the comparison frequency fc2 / P · N2 from the frequency divider 24, and calculates the pulse of the phase difference. Output to the charge pump 26. The charge pump 26 switches the connection state of the plurality of capacitors by using a switch, and outputs a voltage higher than the voltage of the pulse from the phase comparator 25 to the loop filter 27. The phase and period of the switching frequency of the charge pump 26 are set by a control signal from the control unit 30. The loop filter 27 removes the noise component of the pulse from the charge pump 26, converts the pulse into a DC voltage level, and outputs the pulse to the voltage controlled oscillator 28. The time constant of the loop filter 27 is also set by the control signal from the control unit 30.

The voltage controlled oscillator 28 oscillates a signal having a frequency corresponding to the DC voltage value from the loop filter 27, outputs a signal of the oscillation frequency fc2 to the frequency divider 30, and also outputs the prescaler 29 (prescaler 29 and the frequency divider 24). It feeds back to the phase comparator 25) via. The oscillation frequency fc2 of the voltage controlled oscillator 28 is changed by changing the setting of at least one of the integral multiple of the multiplier 22, the frequency division ratio of the frequency dividers 23 and 24, and the frequency division ratio of the prescaler 29. The prescaler 29 divides the signal of the oscillation frequency fc2 from the voltage controlled oscillator 28 into a predetermined frequency division ratio (1 / P), and outputs the divided signal of the predetermined frequency fc2 / P to the frequency divider 24. .. The prescaler 29 is inserted between the voltage controlled oscillator 28 and the frequency divider 24 when forming a high frequency PLL circuit. The division ratio of the prescaler 29 is also set by the control signal from the control unit 30. The frequency divider 30 divides the signal of the oscillation frequency fc2 output from the voltage controlled oscillator 28 into a predetermined frequency division ratio (1 / D2), and outputs the signal of the divided oscillation frequency fc2 / D2 (the divided frequency divider 30). Output as a clock signal).

The internal configuration of the first PLL circuit 10 and the second PLL circuit 20 shown in FIG. 2 is an example. For example, the first PLL circuit 10 may have a multiplier or a prescaler, and the second PLL circuit 20 may have a multiplier. It is not necessary to have 22 or the prescaler 29.

Returning to the description of FIG. 1, the control unit 30 outputs a control signal to the first PLL circuit 10 and the second PLL circuit 20, so that each unit (divider, charge pump, etc.) in the first PLL circuit 10 and the second PLL circuit 20 This is a processing unit that sets loop filters, voltage controlled oscillators, etc.). The control unit 30 is composed of, for example, a processor or the like.

The control unit 30 has a first setting unit 31, a second setting unit 32, a third setting unit 33, a fourth setting unit 34, and a storage unit 35. The first setting unit 31 is a processing unit that sets the oscillation frequencies of the voltage controlled oscillator 17 (first VCO) and the voltage controlled oscillator 28 (second VCO). The second setting unit 32 is a processing unit that sets the phase of the switching frequency of the charge pump 15 (first charge pump) and the charge pump 26 (second charge pump). The third setting unit 33 is a processing unit that sets the cycle of the switching frequencies of the charge pump 15 (first charge pump) and the charge pump 26 (second charge pump). The fourth setting unit 34 is a processing unit that sets the time constants of the loop filters 16 and 27.

The storage unit 35 stores various data. A register 35a is provided in the storage unit 35. In the present embodiment, when the user inputs a set value to the register 35a from an input unit (not shown), the setting units 31 to 34 transmit a control signal according to the set value to the first PLL circuit 10 and the second PLL circuit 20. By outputting, each part in the first PLL circuit 10 and the second PLL circuit 20 is set.

Next, the malfunction of the first PLL circuit 10 and the second PLL circuit 20 will be described.

Due to noise interference between the PLL circuits 10 and 20, the following malfunctions of the PLL circuits 10 and 20 also occur. That is,
1. 1. The clock phases of the output signals of the PLL circuits 10 and 20 do not match.
2. Jitter and clock skew occur in the output signals of the PLL circuits 10 and 20.
3. 3. Jitter occurs in the output signals of the reference oscillators 11 and 21 and the PLL circuits 10 and 20.
4. The charge pump circuit does not operate stably, and the clocks of the output signals of the PLL circuits 10 and 20 become unstable.
5. The above-mentioned malfunctions 1 to 4 occur intermittently depending on the device temperature, the device temperature, and the lot of the device.

As a specific example of the above case 2, when noise interference occurs between the oscillation frequency of the voltage controlled oscillator 17 of the first PLL circuit 10 and the oscillation frequency of the voltage controlled oscillator 28 of the second PLL circuit 20, both voltage controlled oscillators Jitter (temporal fluctuation of the signal waveform) occurs in the signals of the oscillation frequencies of 17 and 28. When jitter occurs in the oscillation frequencies of the voltage controlled oscillators 17 and 28, jitter also occurs in the output signals of the first PLL circuit 10 and the second PLL circuit 20, and the high frequency output (RF output) is spurious (mainly composed of harmonics, alternating current). A frequency component contained in a signal that is not intended by design) is generated. In this case, the device (or system) itself will not function.

For example, assume that the voltage controlled oscillator 17 has an oscillation frequency of 2457.6 MHz and a period of about 407 ps. Further, by setting the frequency division ratio of the frequency divider 18 to 1/4, it is assumed that the frequency of the output signal of the first PLL circuit 10 is 614.4 MHz and the period is 1.62 ns. Further, it is assumed that the oscillation frequency of the voltage controlled oscillator 28 is 2457.6 MHz and the period is about 407 ps. Further, by setting the frequency division ratio of the frequency divider 30 to 1/1, it is assumed that the frequency of the output signal of the second PLL circuit 20 is 2457.6 MHz and the period is about 407 ps. In this case, jitter occurs in the signal of the oscillation frequency of the voltage controlled oscillator 17, and jitter also occurs in the output signal of the first PLL circuit 10, and the clock edge of the output signal shifts within the range of 407 ps. Similarly, jitter occurs in the signal of the oscillation frequency of the voltage controlled oscillator 28, jitter also occurs in the output signal of the second PLL circuit 20, and the clock edge of the output signal shifts within the range of 407 ps.

Next, the waveform of the frequency spectrum characteristic at the time of noise interference of the voltage controlled oscillators 17 and 28 will be described.

FIG. 3 is a diagram showing waveforms of frequency spectrum characteristics at the time of noise interference of voltage controlled oscillators 17 and 28. The horizontal axis indicates the frequency, and the vertical axis indicates the output. The waveform 101 is a waveform of the oscillation frequency fc and the bandwidth fw of one of the voltage controlled oscillators (voltage controlled oscillator 17 or 28). The waveform 102 is a waveform of conduction noise transmitted from the other voltage controlled oscillator via the printed circuit board and radiation noise transmitted through space. Further, the waveforms 103 and 104 are waveforms of noise transmitted from the other voltage controlled oscillator while being reflected and attenuated on the printed circuit board or space. As shown in FIG. 3, the waveforms 103 and 104 appear in other bands. As shown in FIG. 3, the waveform 101 of the oscillation frequency of one of the voltage controlled oscillators overlaps with the waveforms 102, 103, 104 caused by noise, so that the waveform 101 is distorted. As a result, the PLL circuits 10 and 20 malfunction.

Next, countermeasures against interference between the voltage controlled oscillators 17 and 28 will be described.

FIG. 4 is a diagram for explaining interference countermeasures for the voltage controlled oscillators 17 and 28. As described with reference to FIG. 2, the oscillation frequency of the voltage controlled oscillator 17 is fc1, the oscillation frequency bandwidth of the voltage controlled oscillator 17 is fw1, the oscillation frequency of the voltage controlled oscillator 28 is fc2, and the oscillation frequency band of the voltage controlled oscillator 28. The width is fw2. In this case, the first setting unit 31 has at least one of the oscillation frequency of the voltage controlled oscillator 17 and the oscillation frequency of the voltage controlled oscillator 28 so as to satisfy the relationship {| fc1-fc2 |-(fw1 + fw2) / 2≥α}. To set.

Here, | fc1-fc2 | is the interval between the oscillation frequency of the voltage controlled oscillator 17 and the oscillation frequency of the voltage controlled oscillator 28. (Fw1 + fw2) / 2 is the sum of the bandwidth fw1 which is half the oscillation frequency of the voltage controlled oscillator 17 and the bandwidth fw2 which is half the oscillation frequency of the voltage controlled oscillator 28. α is the distance between the end of the waveform of the oscillation frequency of the voltage controlled oscillator 17 and the end of the waveform of the oscillation frequency of the voltage controlled oscillator 28. Even when the value of α is 0 Hz, the waveform of the oscillation frequency of the voltage controlled oscillator 17 and the waveform of the oscillation frequency of the voltage controlled oscillator 28 do not overlap. However, the intervals between the waveforms of the oscillation frequencies of the voltage controlled oscillators 17 and 28 are set by the intervals including the margin in consideration of the individual difference of the device and the board.

FIG. 5 is a table showing the verification results of the interference countermeasures of the voltage controlled oscillators 17 and 28. In FIG. 5, the first setting unit 31 sets (locks) the oscillation frequency (VCO1 frequency in FIG. 5) of the voltage controlled oscillator 17 to 2457.6 MHz (period 406.901 ps). At this time, the frequency division ratio of the frequency divider 18 is set to a value corresponding to the frequency of the output signal of the first PLL circuit 10 defined in advance. Further, the first setting unit 31 sets the oscillation frequency (VCO2 frequency in FIG. 5) of the voltage controlled oscillator 28 by setting at least one of the set values of the multiplier 22, the frequency dividers 23 and 24, and the prescaler 29. The transition is made from 2457.6 MHz (period 406.901 ps) by 20 MHz. At this time, the frequency division ratio of the frequency divider 30 is set to a value corresponding to the frequency of the output signal of the second PLL circuit 20 defined in advance.

When the oscillation frequency of the voltage controlled oscillator 28 is changed from 2457.6 MHz to 20 MHz at a time, the interval between the oscillation frequency of the voltage controlled oscillator 17 and the oscillation frequency of the voltage controlled oscillator 28 (VCO frequency interval in FIG. 5; that is, | fc1-fc2 |). Also increases by 20 MHz. The spurious occurrence rate (%) is calculated by the number of activations / the number of spurious occurrences. As shown in FIG. 5, the spurious generation rate (%) gradually decreases as the interval between the oscillation frequency of the voltage controlled oscillator 17 and the oscillation frequency of the voltage controlled oscillator 28 increases. Then, when the interval between the oscillation frequency of the voltage controlled oscillator 17 and the oscillation frequency of the voltage controlled oscillator 28 becomes 400 MHz, the spurious generation rate becomes 0 (%). That is, the spurious has disappeared. However, in the present embodiment, in consideration of individual differences between devices and boards, the frequency is set to 500 MHz by adding a margin (here, 100 MHz) to the interval between the oscillation frequency of the voltage controlled oscillator 17 and the oscillation frequency of the voltage controlled oscillator 28. At this time, α becomes 500 MHz− (fw1 + fw2) / 2.

FIG. 6 is a graph showing the verification results of the interference countermeasures of the voltage controlled oscillators 17 and 28. FIG. 6 is a graph of a table showing the verification results of FIG. In FIG. 6, the horizontal axis represents the oscillation frequency of the voltage controlled oscillator 28 (VCO frequency in FIG. 6), and the vertical axis represents the spurious generation rate (%). When the oscillation frequency of the voltage controlled oscillator 28 reaches 2057.6 MHz (that is, the interval between the oscillation frequency of the voltage controlled oscillator 17 and the oscillation frequency of the voltage controlled oscillator 28 is 400 MHz), the spurious generation rate becomes 0 (%). ..

Next, the time of noise interference of the charge pumps 15 and 26 will be described.

FIG. 7 is a diagram showing waveforms of the charge pumps 15 and 26 at the time of noise interference. In FIG. 7, the horizontal axis represents time and the vertical axis represents the voltage of the charge pump (for example, the charge pump 15 of the first PLL circuit 10). When the spurious described with reference to FIG. 3 occurs, not only the noise interference of the voltage controlled oscillators 17 and 28 but also the phase and period (frequency) of the switching frequencies of the charge pumps 15 and 26 are the same, so that one of the PLL circuits is charged. Noise (conduction noise, radiation noise) is transmitted from the pump (for example, the charge pump 26 of the second PLL circuit 20) to the charge pump of the other PLL circuit (for example, the charge pump 15 of the first PLL circuit 10) via the printed circuit board or space. Noise interference occurs between the PLL circuits 10 and 20. In this case, as shown in FIG. 7, the voltage of the charge pump is superimposed, a voltage (v1 + v2) higher than the normal voltage v1 is applied to the voltage controlled oscillator in the PLL circuit, and the signal of the oscillation frequency of the voltage controlled oscillator is applied. Jitter occurs. In FIG. 7, t1 is the cycle of the switching frequency of the charge pump. Although not shown in FIG. 7, the switching frequency when the period of the switching frequency of the charge pump is t1 is f1 (= 1 / t1).

Next, countermeasures against interference between the charge pumps 15 and 26 by changing the phase will be described.

FIG. 8 is a diagram for explaining the countermeasures against interference of the charge pumps 15 and 26 due to the phase change. In order to prevent the interference of the charge pumps 15 and 26 described with reference to FIG. 7, the second setting unit 32 switches one of the charge pumps (for example, the charge pump 26 of the second PLL circuit 20) as shown in FIG. The frequency phase is set to shift by π / 6 “rad” (ie, 30 °) or more. As a result, the peak voltage of the charge pump is deviated, and the superposition of the voltage of the charge pump is avoided, and as a result, the spurious is reduced. In FIG. 8, the thick line shows the waveform of the switching frequency of the charge pump 15 included in the first PLL circuit 10, and the thin line shows the waveform of the switching frequency of the charge pump 26 included in the second PLL circuit 20. Further, the phase of the switching frequency of the charge pump 26 is changed by π / 6 [rad].

FIG. 9 is a table showing the verification results of the interference countermeasures of the charge pumps 15 and 26 due to the phase change. In FIG. 9, the second setting unit 32 sets (locks) the phase of the switching frequency of the charge pump 15 (CP1 phase in FIG. 9) to 0 [rad]. Further, the second setting unit 32 shifts the phase of the switching frequency of the charge pump 26 (CP2 phase in FIG. 9) from 0 [rad] to π / 12 [rad] (that is, 15 °). The CP phase in FIG. 9 represents the difference between the phase of the switching frequency of the charge pump 15 and the phase of the switching frequency of the charge pump 26.

When the switching frequency of the charge pump 26 is changed from 0 [rad] to π / 12 [rad], the spurious generation rate (%) decreases, and the phase of the switching frequency of the charge pump 26 is π / 6 [rad]. When it reaches (that is, 30 °), the spurious occurrence rate becomes 0% (that is, the number of spurious occurrences becomes 0).

FIG. 10 is a graph showing the verification results of the interference countermeasures of the charge pumps 15 and 26 due to the phase change. FIG. 10 is a graph of a table showing the verification results of FIG. In FIG. 10, the horizontal axis represents the switching frequency of the charge pump 26 (CP phase in FIG. 10), and the vertical axis represents the spurious generation rate (%). When the switching frequency of the charge pump 26 reaches 30 °, the spurious generation rate becomes 0 (%).

FIG. 11 is a diagram for explaining measures against interference of the charge pumps 15 and 26 due to a change in frequency. In order to prevent the interference of the charge pumps 15 and 26 described with reference to FIG. 7, the third setting unit 33 switches one of the charge pumps (for example, the charge pump 26 of the second PLL circuit 20) as shown in FIG. The frequency f2 (the cycle of the switching frequency at this time is t2) is changed to the switching frequency f1 of the other charge pump (for example, the charge pump 15 of the first PLL circuit 10) (the cycle of the switching frequency at this time is t1). The switching frequency of the charge pump 26 is set so as to be 1 / (4n + 1) of. That is, the third setting unit 33 sets the switching frequency of the charge pump 15 of the first PLL circuit 10 and the switching frequency of the charge pump 26 of the second PLL circuit 20 so as to satisfy the relationship of f2 = f1 / (4n + 1). Note that n is a prime number (n = 2, 3, 5, ...). By shifting the switching frequency of the charge pump 15 and the switching frequency of the charge pump 26 in this way, superposition of the voltage of the charge pump is avoided, and as a result, spurious is reduced. In FIG. 11, the thick line shows the waveform of the switching frequency of the charge pump 15 included in the first PLL circuit 10, and the thin line shows the waveform of the switching frequency of the charge pump 26 included in the second PLL circuit 20.

FIG. 12 is a table showing the verification results of the interference countermeasures of the charge pumps 15 and 26 due to the change of frequency. In FIG. 12, the third setting unit 33 sets (locks) the switching frequency f1 of the charge pump 15 (CP1 frequency in FIG. 12; the period t1 is 1 / switching frequency f1) to 150 [kHz]. .. Further, the third setting unit 33 sets the value of n of f1 / (4n + 1) to 0,2 so that the switching frequency f2 (CP2 frequency in FIG. 12) of the charge pump 26 is gradually lowered from 150 [kHz]. , 3, 5, 7, 11, 13, 17, 19, 23) Transition. When the switching frequency f2 of the charge pump 26 reaches 160 [kHz], the spurious generation rate becomes 0% (that is, the number of spurious generations becomes 0).

In the present embodiment, as measures to prevent noise interference between the first PLL circuit 10 and the second PLL circuit 20, (1) the oscillation frequencies of the voltage controlled oscillators 17 and 28 are spaced apart (see FIG. 4), and (2) the charge is charged. It has been described that the phase of the switching frequency of the pumps 15 and 26 is shifted (see FIG. 8), and (3) the switching frequency (that is, the period) of the charge pumps 15 and 26 is shifted (see FIG. 11). In this case, if the noise interference is prevented by the measures (1), only the measures (1) are executed, and if the measures (1) do not prevent the noise interference, the measures (2) are executed and (2). If the measures in) do not prevent noise interference, take the measures in (3). That is, countermeasures are executed in the order of priority of (1), (2), and (3) to prevent noise interference. The priority order is not limited to (1), (2), and (3), and may be in a different order.

As described above, in the present embodiment, at least two PLL circuits including the first PLL circuit 10 and the second PLL circuit 20 are provided, and interference of the PLL circuits is prevented by changing the settings of the PLL circuits 10 and 20. In the PLL built-in device 1, the frequency fc1 of the first VCO17 included in the first PLL circuit 10, the frequency fc2 of the second VCO28 included in the second PLL circuit 20, the bandwidth fw1 of the frequency of the first VCO17, and the frequency of the second VCO28. A first setting unit 31 for setting the frequencies of the first VCO 17 and the second VCO 28 is provided so that the bandwidth fw2 satisfies the relationship of {| fc1-fc2 | − (fw1 + fw2) / 2 ≧ α}. According to such a configuration, since the first setting unit 31 sets the frequencies of the first VCO 17 and the second VCO 28 so as to satisfy the above equation, the PLL without changing the frequencies of the output signals of the PLL circuits 10 and 20 is used. Interference between the circuits 10 and 20 can be prevented. Further, since the oscillation frequency of the voltage controlled oscillator 17 and the oscillation frequency of the voltage controlled oscillator 28 are spaced by α, interference between the PLL circuits 10 and 20 can be prevented regardless of individual differences in the devices and the like. As a result, it is possible to surely prevent the malfunction of the plurality of PLL circuits 10 and 20 (and the PLL built-in device 1 including the plurality of PLL circuits 10 and 20).

Further, in the present embodiment, α is a value obtained by adding a margin to the value of | fc1-fc2 | when the spurious generation rate becomes 0, so that it is related to the device temperature, the device temperature, the device lot, and the like. It is possible to prevent interference between the PLL circuits 10 and 20.

Further, in the present embodiment, the difference between the phase of the switching frequency of the first charge pump 15 included in the first PLL circuit 10 and the phase of the switching frequency of the second charge pump 26 included in the second PLL circuit 20 is π / 6 [. rad] or more, the second setting unit 32 for setting the phase of the switching frequency of the first charge pump 15 and the second charge pump 26 is provided. According to such a configuration, even if noise interference occurs despite the above measures, noise interference can be prevented by shifting the phase of the switching frequency of the charge pump. It is possible to avoid malfunction of the PLL circuits 10 and 20.

Further, in the present embodiment, the switching frequency (that is, period) of the second charge pump 26 included in the second PLL circuit 20 is 1 / (that is, the period) of the switching frequency (that is, period) of the first charge pump 15 included in the first PLL circuit 10. A third setting unit 33 for setting the switching frequencies of the first charge pump 15 and the second charge pump 26 is provided so as to be 4n + 1). According to such a configuration, even if noise interference occurs even after the above measures are taken, noise interference can be prevented by shifting the switching frequency (that is, the period) of the charge pump. This makes it possible to more reliably avoid malfunctions of the PLL circuits 10 and 20.

Although the embodiments of the present invention have been described above, the technical scope of the present invention is not limited to the scope described in the above embodiments. Various changes or improvements can be made to the above embodiments without departing from the spirit of the present invention. In addition, one or more of the requirements described in the above embodiments may be omitted. Such modifications, improvements, or omitted forms are also included in the technical scope of the present invention. Further, it is also possible to appropriately combine and apply the configurations of the above-described embodiments and modifications.

In the above-described embodiment, the oscillation frequencies of the voltage-controlled oscillators 17 and 28 are spaced by changing the oscillation frequency of the voltage-controlled oscillator 28 included in the second PLL circuit 20 (see FIGS. 4 to 6). The oscillation frequency of the voltage controlled oscillators 17 and 28 may be spaced by changing the oscillation frequency of the voltage controlled oscillator 17 included in the first PLL circuit 10. Further, the oscillation frequencies of the voltage controlled oscillators 17 and 28 may be spaced by changing any of the oscillation frequencies of the voltage controlled oscillators 17 and 28.

Further, the phase of the switching frequency of the charge pumps 15 and 26 was shifted by changing the phase of the switching frequency of the charge pump 26 included in the second PLL circuit 20 (see FIGS. 8 to 10). Not limited to the configuration, the phase of the switching frequency of the charge pumps 15 and 26 may be shifted by changing the phase of the switching frequency of the charge pump 15 included in the first PLL circuit 10. Further, the phases of the switching frequencies of the charge pumps 15 and 26 may be shifted by changing any of the phases of the switching frequencies of the charge pumps 15 and 26.

Further, the switching frequencies (that is, cycles) of the charge pumps 15 and 26 were shifted by changing the switching frequency (that is, the cycle) of the charge pump 26 included in the second PLL circuit 20 (see FIGS. 11 to 12). The switching frequency of the charge pumps 15 and 26 may be shifted by changing the switching frequency of the charge pump 15 included in the first PLL circuit 10. Further, the switching frequencies of the charge pumps 15 and 26 may be shifted by changing any of the switching frequencies of the charge pumps 15 and 26.

In the above-described embodiment, the PLL built-in device 1 includes two PLL circuits 10 and 20, but may include three or more PLL circuits. In this case as well, those PLL circuits so as to satisfy the above-mentioned conditional expressions (conditional expression regarding the oscillation frequency of the voltage control oscillator, conditional expression regarding the phase of the switching frequency of the charge pump, conditional expression regarding the switching frequency of the charge pump). The oscillation frequency of the voltage control oscillator included in the above is spaced, the phase of the switching frequency of the charge pump is shifted, and the switching frequency of the charge pump is shifted.

Further, in the above-described embodiment, in addition to the noise interference countermeasures executed by the first setting unit 31, the second setting unit 32, and the third setting unit 33 described above, the first setting unit 31 is an integral multiple of the multiplier 22. By changing the division ratio of the prescaler 29 or the prescaler 29, the settings of the phase comparators 14 and 25 between the PLL circuits 10 and 20 may be changed to avoid interference of the comparison frequencies. Further, the fourth setting unit 34 may change the constants of the loop filters 16 and 27 to suppress the frequency superimposed on the charge pumps 15 and 26 and transmitted to the printed circuit board. Further, an inductor or a capacitor that attenuates the oscillation frequency of the voltage controlled oscillator of another PLL circuit or the oscillation frequency of the voltage controlled oscillator of the own PLL circuit may be selected in the board. Further, a voltage controlled oscillator and an inductor and a capacitor corresponding to the frequencies of each clock signal (output signal) may be mounted on each power supply (not shown).

1 PLL built-in device 10 1st PLL circuit 15 Charge pump (1st charge pump)
17 Voltage Control Oscillator (1st VCO)
20 2nd PLL circuit 26 Charge pump (2nd charge pump)
28 Voltage Control Oscillator (2nd VCO)
30 Control unit 31 1st setting unit 32 2nd setting unit 33 3rd setting unit

Claims (4)

A PLL built-in device that includes at least two PLL circuits including a first PLL circuit and a second PLL circuit, and prevents interference of the PLL circuits by changing the settings of the PLL circuits.
Each of the PLL circuits has a configuration in which a frequency divider is connected between the output of the VCO and the input of the phase comparator.
The frequency fc1 of the first VCO included in the first PLL circuit, the frequency fc2 of the second VCO included in the second PLL circuit, the bandwidth fw1 of the frequency of the first VCO, and the bandwidth fw2 of the frequency of the second VCO are {| fc1. −fc2 | − (fw1 + fw2) / 2 ≧ α} , where α is the value of | fc1-fc2 | plus a margin when the spurious rate is 0, so as to satisfy the relationship. The first setting unit for setting the frequencies of the first VCO and the second VCO is provided .
The first charge pump and the second charge so that the difference between the phase of the first charge pump included in the first PLL circuit and the phase of the second charge pump included in the second PLL circuit is π / 6 or more. A PLL built-in device including a second setting unit for setting the phase of the pump. The first charge pump and the second charge so that the switching frequency of the second charge pump included in the second PLL circuit is 1 / (4n + 1) of the switching frequency of the first charge pump included in the first PLL circuit. The PLL built-in device according to claim 1 , further comprising a third setting unit for setting the switching frequency of the pump. It is a PLL interference prevention method that includes at least two PLL circuits including a first PLL circuit and a second PLL circuit, and prevents interference of the PLL circuit by changing the settings of the PLL circuits.
Each of the PLL circuits has a configuration in which a frequency divider is connected between the output of the VCO and the input of the phase comparator.
The frequency fc1 of the first VCO included in the first PLL circuit, the frequency fc2 of the second VCO included in the second PLL circuit, the bandwidth fw1 of the frequency of the first VCO, and the bandwidth fw2 of the frequency of the second VCO are {| fc1. −fc2 | − (fw1 + fw2) / 2 ≧ α} , where α is the value of | fc1-fc2 | plus a margin when the spurious rate is 0, so as to satisfy the relationship. The first step of setting the frequencies of the first VCO and the second VCO is provided .
The first charge pump and the second charge so that the difference between the phase of the first charge pump included in the first PLL circuit and the phase of the second charge pump included in the second PLL circuit is π / 6 or more. A PLL interference prevention method comprising a second step of setting the phase of the pump. The first charge pump and the second charge so that the switching frequency of the second charge pump included in the second PLL circuit is 1 / (4n + 1) of the switching frequency of the first charge pump included in the first PLL circuit. The PLL interference prevention method according to claim 3 , further comprising a third step of setting the switching frequency of the pump.

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