JP6916243B2 - Lead-free solder alloys, electronic circuit boards and electronic control devices - Google Patents

Description

The present invention relates to a lead-free solder alloy, and an electronic circuit board and an electronic control device having a solder joint formed by using the lead-free solder alloy.

In order to join an electronic component to an electronic circuit formed on a substrate such as a printed wiring board or a silicon wafer, a solder joining method using a solder alloy is adopted. Conventionally, lead has been generally used for this solder alloy. However, since the use of lead is restricted by the RoHS Directive from the viewpoint of environmental load, a solder joining method using a so-called lead-free solder alloy that does not contain lead is becoming common in recent years.
As the lead-free solder alloy, for example, Sn-Cu-based, Sn-Ag-Cu-based, Sn-Bi-based, Sn-Zn-based solder alloy and the like are well known. Among them, Sn-3Ag-0.5Cu solder alloy is often used in consumer electronic devices used in televisions, mobile phones, etc., and in-vehicle electronic devices mounted in automobiles.
Although lead-free solder alloys are slightly inferior in solderability to lead-containing solder alloys, this problem of solderability is covered by improvements in flux and soldering equipment. Therefore, for example, even if it is an in-vehicle electronic circuit board, if it is placed in a relatively calm environment such as an automobile interior, although there is a temperature difference, Sn-3Ag-0.5Cu solder alloy is used. No major problem has occurred in the formed solder joint.

However, in recent years, as in the case of electronic circuit boards used in electronic control devices, temperature differences such as engine compartments, direct mounting on engines, and integration of mechanical and electrical equipment with motors are particularly severe (for example, from -30 ° C to 110 ° C and -40 ° C). The arrangement of electronic circuit boards has been studied and put into practical use in a harsh environment such as 125 ° C., a temperature difference of -40 ° C. to 150 ° C.), and a vibration load. In such an environment where the temperature difference is extremely large, thermal displacement of the solder joint due to the difference in linear expansion coefficient between the mounted electronic component and the substrate and the stress associated therewith are likely to occur. Repeated plastic deformation due to temperature difference tends to cause cracks in the solder joint, and the stress repeatedly applied with the passage of time concentrates near the tip of the crack, so that the crack is transverse to the deep part of the solder joint. It becomes easy to progress to. Such a significantly extended crack causes a break in the electrical connection between the electronic component and the electronic circuit formed on the substrate. In an environment where vibration is applied to the electronic circuit board in addition to a particularly severe temperature difference, the above-mentioned cracks and their growth are more likely to occur.
Therefore, as the number of in-vehicle electronic circuit boards and electronic control devices placed in the above-mentioned harsh environment increases, the demand for solder alloys capable of exerting a sufficient crack growth suppressing effect is expected to increase in the future. Will be done.

Further, as an in-vehicle electronic circuit board, a substrate (hereinafter referred to as "CuOSP substrate" in the present specification) in which a surface of a substrate coated with a copper foil is subjected to a water-soluble preservative treatment (Organic Solderbility Preservative) is widely used. Has been done. Since the CuOSP substrate is inferior in the wettability of the solder alloy, when an electronic component is mounted on the CuOSP substrate, there is a problem that voids are likely to be generated in the solder joint portion formed on the substrate. Therefore, it is expected that there will be a growing demand for solder alloys that suppress the generation of voids even when they are used for mounting electronic components on CuOSP substrates.

Furthermore, the lead parts of electronic components such as QFP (Quad Flat Package) and SOP (Small Outline Package) mounted on an in-vehicle electronic circuit board have been conventionally plated with Ni / Pd / Au or Ni / Au. Many parts were used. However, with the recent cost reduction of electronic components and downsizing of substrates, electronic components whose lead portions are replaced with Sn plating and electronic components having Sn-plated bottom electrodes have been studied and put into practical use.
For example, an electronic component in which the lead portion is replaced with Sn plating or an electronic component having a Sn-plated bottom electrode is a combination of Sn contained in the Sn-plated and solder joint portion and Cu contained in the lead portion and the bottom electrode. It is easy to generate mutual diffusion. Therefore, in the region near the interface between the solder joint portion and the lead portion or the bottom electrode (hereinafter, referred to as “near the interface” in the present specification), the Cu ₃ Sn layer, which is an intermetallic compound, becomes uneven. Easy to grow big. The Cu ₃ Sn layer originally has a hard and brittle property, and the Cu ₃ Sn layer that has grown large in an uneven shape becomes more brittle. Therefore, particularly in the above-mentioned harsh environment, cracks are likely to occur in the vicinity of the interface as compared with the solder joint, and the generated cracks grow at once from this point, so that an electrical short circuit is likely to occur.
Therefore, in the future, even when electronic parts not plated with Ni / Pd / Au or Ni / Au are used under the above-mentioned harsh environment, a solder alloy capable of suppressing crack growth in the vicinity of the interface can be exhibited. It is expected that the demand for the product will also increase.

Until now, for the purpose of suppressing crack growth in solder joints, there have been methods of adding elements such as Ag and Bi to Sn-Ag-Cu solder alloys in order to improve the strength of solder joints and the associated thermal fatigue characteristics. Some are disclosed (see Patent Documents 1 to 8).

Japanese Unexamined Patent Publication No. 5-228685 Japanese Unexamined Patent Publication No. 9-326554 Japanese Unexamined Patent Publication No. 2000-19090 Japanese Unexamined Patent Publication No. 2000-349433 Japanese Unexamined Patent Publication No. 2008-28413 International pamphlet WO2009 / 011341 Japanese Unexamined Patent Publication No. 2012-81521 Japanese Patent No. 3353640

For example, when Bi is added to a solder alloy, Bi enters the lattice of the atomic arrangement of the solder alloy and replaces it with Sn, thereby distorting the lattice of the atomic arrangement. As a result, the Sn matrix is strengthened and the alloy strength is improved, so that the addition of Bi is expected to improve the solder crack growth characteristics to a certain extent.
However, the lead-free solder alloy whose strength has been increased by the addition of Bi has a demerit that the stretchability deteriorates and the brittleness increases. When the applicant solder-bonded the substrate and the chip resistor component using a conventional lead-free solder alloy to which Bi was added and placed this in an environment with a large temperature difference, the chip was found in the fillet portion on the chip resistor component side. A crack entered in a straight line from a direction of about 45 ° with respect to the longitudinal direction of the resistance component, and an electrical short circuit occurred. Therefore, especially in an in-vehicle substrate placed in an environment where there is a large difference in temperature, the effect of suppressing crack growth is not sufficient only by increasing the strength by adding Bi or the like as in the past, and in addition to increasing the strength, new crack growth The emergence of suppression methods is desired.

Further, for example, by adding Ni to the solder alloy, the thermal fatigue characteristics of the solder can be improved and _{the formation of an intermetallic compound (Cu 3} Sn) can be suppressed, but on the other hand, a large amount of Ni (for example, 0.5) can be suppressed. When it is added (% by mass), there is a problem that voids are likely to be generated at the solder joint.

Furthermore, in the above-mentioned prior art, void suppression of solder joints that are likely to occur when electronic components are mounted on a CuOSP substrate, and electronic components that are not Ni / Pd / Au plated or Ni / Au plated are mounted on the substrate. There is no mention of suppressing crack growth near the interface due to the growth of the _{Cu 3} Sn layer, which is particularly likely to occur in this case.

The present invention solves the above problems, can suppress the growth of cracks in the solder joint even in a harsh environment where the temperature difference is large and vibration is applied, and when the electronic component is mounted on the CuOSP substrate. Suppresses voids in solder joints that are likely to occur, and near the interface due to the growth of the _{Cu 3} Sn layer, which is likely to occur when electronic components that are not Ni / Pd / Au plated or Ni / Au plated are mounted on a substrate. An object of the present invention is to provide a lead-free solder alloy capable of suppressing crack growth, and an electronic circuit board and an electronic control device having a solder joint formed by using the lead-free solder alloy.

(1) In the lead-free solder alloy of the present invention, Ag is 1% by mass or more and 4% by mass or less, Sb is 1% by mass or more and 5% by mass or less, and Ni is 0.01% by mass or more and 0.03% by mass or less. It is characterized in that it contains and the balance consists of Sn.

(2) In the configuration described in (1) above, the lead-free solder alloy of the present invention is characterized in that the Sb content is 3% by mass or more and 5% by mass or less.

(3) In the configuration described in (1) or (2) above, the lead-free solder alloy of the present invention is characterized by further containing 4.5% by mass or less of Bi.

(4) In the configuration according to any one of (1) to (3) above, the lead-free solder alloy of the present invention further contains Co in 0.001% by mass or more and 0.15% by mass or less. It is a feature.

(5) In the configuration described in (4) above, the lead-free solder alloy of the present invention is characterized in that the Co content is 0.008% by mass or more and 0.01% by mass or less.

(6) In the configuration according to any one of (1) to (5) above, the lead-free solder alloy of the present invention is characterized by further containing 6% by mass or less of In.

(7) In the configuration according to any one of (1) to (6) above, the lead-free solder alloy of the present invention further contains at least one of P, Ga, and Ge in a total mass of 0.001. It is characterized by containing% or more and 0.05% by mass or less.

(8) In the configuration according to any one of (1) to (7) above, the lead-free solder alloy of the present invention further contains at least one of Fe, Mn, Cr, and Mo in total of 0. It is characterized by containing 001% by mass or more and 0.05% by mass or less.

(9) The electronic circuit board of the present invention is characterized by having a solder joint formed by using the lead-free solder alloy of the present invention according to any one of (1) to (8) above. ..

(10) The electronic control device of the present invention is characterized by having the electronic circuit board described in (9) above.

The lead-free solder alloy of the present invention, and an electronic circuit board and an electronic control device having a solder joint formed by using the lead-free solder alloy, are subjected to a harsh environment in which a large temperature difference is applied and vibration is applied. Also, it is possible to suppress the growth of cracks in the solder joint, suppress the voids in the solder joint that are likely to occur when electronic components are mounted on the CuOSP substrate, and the electrons that are not Ni / Pd / Au plated or Ni / Au plated. It is possible to suppress the growth of cracks near the interface due to the growth of the _{Cu 3} Sn layer, which tends to occur when the components are mounted on the substrate.

A partial cross-sectional view showing a part of an electronic circuit board according to an embodiment of the present invention. An electron micrograph showing a cross section in which a void is generated in a fillet portion of a chip component in a test substrate according to a comparative example of the present invention. Photographs taken from the chip component side using an X-ray transmission device showing a region under the electrode of the chip component and a region where a fillet is formed in the test substrate according to the examples and comparative examples of the present invention.

Hereinafter, an embodiment of the lead-free solder alloy of the present invention, an electronic circuit board, and an electronic control device will be described in detail. It goes without saying that the present invention is not limited to the following embodiments.

(1) Lead-free solder alloy The lead-free solder alloy of the present embodiment may contain Ag of 1% by mass or more and 4% by mass or less. _{By adding Ag, the Ag 3} Sn compound can be precipitated in the Sn grain boundaries of the lead-free solder alloy to impart mechanical strength.
However, when the Ag content is less than 1% by mass _{, the precipitation of the Ag 3} Sn compound is small, and the mechanical strength and thermal shock resistance of the lead-free solder alloy are lowered, which is not preferable. Further, if the Ag content exceeds 4% by mass, the stretchability of the lead-free solder alloy is hindered, and the solder joint formed by using the Ag content may cause an electrode peeling phenomenon of electronic parts, which is not preferable.
Further, when the Ag content is 2% by mass or more and 3.8% by mass or less, the balance between the strength and the stretchability of the lead-free solder alloy can be improved. A more preferable content of Ag is 2.5% by mass or more and 3.8% by mass or less.

The lead-free solder alloy of the present embodiment can contain Sb of 1% by mass or more and 5% by mass or less. By adding Sb within this range, the effect of suppressing crack growth at the solder joint can be improved without impairing the stretchability of the solder alloy. When the Sb content is 2% by mass or more and 4% by mass or less, the crack growth suppressing effect can be further improved.

Here, in order to withstand the external stress of being exposed to a harsh environment with a large temperature difference for a long time, the toughness of the lead-free solder alloy (the size of the area surrounded by the stress-strain curve) is increased and the drawing is performed. It is considered effective to improve the properties and to strengthen the solid solution by adding an element that dissolves in the Sn matrix. Then, Sb is the optimum element for solid solution strengthening of the lead-free solder alloy while ensuring sufficient toughness and stretchability.
That is, by adding Sb in the above range to a lead-free solder alloy whose base material (referred to in this specification as the main component of the lead-free solder alloy; the same applies hereinafter) is substantially Sn. A part of the crystal lattice is replaced with Sb, and the crystal lattice is distorted. Therefore, in the solder joint formed by using such a lead-free solder alloy, the energy required for the transition in the crystal is increased by Sb substitution of a part of the Sn crystal lattice, and the metal structure thereof is strengthened. .. Furthermore, by precipitating fine SnSb, ε-Ag ₃ (Sn, Sb) compounds at the Sn grain boundaries, slip deformation of the Sn grain boundaries is prevented, and the growth of cracks generated at the solder joint is suppressed. obtain.

Further, as compared with the Sn-3Ag-0.5Cu solder alloy, the structure of the solder joint formed by using the lead-free solder alloy to which Sb is added in the above range is exposed for a long time in a harsh environment where the temperature difference is large. It was confirmed that the Sn crystal was kept in a fine state even after the soldering, and the structure was such that cracks did not easily grow. This is because the SnSb, ε-Ag ₃ (Sn, Sb) compounds precipitated at the Sn grain boundaries are finely dispersed in the solder joint even after being exposed to a harsh environment with a large temperature difference for a long time. Therefore, it is considered that the coarsening of Sn crystals is suppressed. That is, in the solder joint using the lead-free solder alloy to which Sb is added within the above range, the solid solution of Sb in the Sn matrix at high temperature is SnSb, ε-Ag ₃ (Sn, Sb) at low temperature. Due to compound precipitation, even when exposed for a long time in a harsh environment with a large temperature difference, the process of solid solution strengthening at high temperature and precipitation strengthening at low temperature is repeated, resulting in excellent cold resistance. It is considered that impact resistance can be ensured.

Further, the lead-free solder alloy to which Sb is added in the above range can improve the strength of the solder alloy without lowering the stretchability, so that sufficient toughness against external stress can be ensured and the residual stress is also relaxed. be able to.
Here, when the solder joint formed by using a solder alloy having low stretchability is placed in an environment where the temperature difference is large, the stress repeatedly generated tends to be accumulated on the electronic component side of the solder joint. Therefore, deep cracks often occur at solder joints near the electrodes of electronic components. As a result, stress is concentrated on the electrodes of the electronic component in the vicinity of the crack, and a phenomenon may occur in which the solder joint portion peels off the electrodes on the electronic component side. However, since the lead-free solder alloy of the present embodiment contains an element that affects the stretchability of the solder alloy, such as Bi, by adding Sb in the above range, the stretchability of the lead-free solder alloy itself is not easily impaired. Therefore, even when the electronic component is exposed to the harsh environment for a long time as described above, the electrode peeling phenomenon of the electronic component can be suppressed.

However, if the Sb content exceeds 5% by mass, the melting temperature of the lead-free solder alloy rises, and Sb does not re-solidify at a high temperature. Therefore, when exposed to a harsh environment with a large temperature difference for a long time, _{only precipitation strengthening by SnSb, ε-Ag 3} (Sn, Sb) compounds is performed, and these intermetallic compounds become coarse with the passage of time. The effect of suppressing the slip deformation of the Sn grain boundary is lost. Further, in this case, the heat resistant temperature of the electronic component becomes a problem due to the increase in the melting temperature of the lead-free solder alloy, which is not preferable.

Due to its configuration, the lead-free solder alloy in the present embodiment suppresses an excessive rise in the melting temperature of the lead-free solder alloy even if the Sb content is 1% by mass or more and 5% by mass or less, and the solder formed. Gives good strength to the joint. Therefore, in the lead-free solder alloy of the present embodiment, the effect of suppressing crack growth of the formed solder joint can be sufficiently exhibited even if Bi is not used as the essential composition.

The lead-free solder alloy of the present embodiment can contain 0.01% by mass or more and 0.15% by mass or less of Ni.
When Cu is not added to the lead-free solder alloy, the melt viscosity of the alloy can be lowered, so that the gas caused by the flux is easily discharged at the solder joint formed by using the Cu, and it is difficult to remain as voids. However, since there is no Cu on the molten lead-free solder alloy side, there is a problem that Cu on the electrode is likely to diffuse to the molten solder alloy side, and the Cu ₃ Sn layer near the interface is more likely to grow.
However, in the case of the configuration of the lead-free solder alloy of the present embodiment, by adding Ni in the above range, excessive diffusion of Cu on the electrode side into the molten lead-free solder alloy without adding Cu to the Ni is prevented. Since it can be suppressed and fine (Cu, Ni) ₆ Sn ₅ is formed near the interface and dispersed in the base metal, the growth of cracks at the solder joint is suppressed and the heat and fatigue characteristics are further improved. Can be made to.

Further, in the lead-free solder alloy of the present embodiment, even when solder-bonding electronic parts that are not Ni / Pd / Au-plated or Ni / Au-plated, Ni moves to the vicinity of the interface at the time of solder bonding. Since fine (Cu, Ni) ₆ Sn ₅ is formed, _{the growth of the Cu 3} Sn layer in the vicinity of the interface can be suppressed, and the crack growth suppressing effect in the vicinity of the interface can be improved.

Here, since Ni accelerates the solidification timing of the molten solder alloy, in the fillet of the formed solder joint, the gas that tried to escape to the outside during the melting of the solder alloy tends to solidify while remaining in the fillet. , Holes (voids) due to gas are likely to occur in the fillet. The voids in the fillet deteriorate the heat and fatigue characteristics of the solder joint, particularly in an environment where the temperature difference is large, such as −40 ° C. to 140 ° C. and −40 ° C. to 150 ° C.
However, in the lead-free solder alloy of the present embodiment, the generation of such voids can be suppressed by keeping the Ni content within the above range and balancing the content with other elements.

Further, as described above, since the lead-free solder alloy of the present embodiment does not contain Cu, the addition of Ni suppresses the growth of cracks at the solder joint, and the substrate is inferior in solder wettability and spreadability, such as a CuOSP substrate. Even so, the generation of the above voids can be suppressed.

However, if the Ni content is less than 0.01% by mass, the effect of modifying the intermetallic compound is insufficient, and it is difficult to sufficiently obtain the effect of suppressing cracks near the interface. Further, when the Ni content exceeds 0.15% by mass, the above-mentioned voids are likely to occur particularly in the fillet, which is not preferable.

The lead-free solder alloy of the present embodiment can contain 0.001% by mass or more and 0.15% by mass or less of Co in addition to Ni. In the case of the configuration of the lead-free solder alloy of the present embodiment, by adding Co in this range, the above effect due to the addition of Ni is enhanced and excessive diffusion of Cu on the electrode side into the melted lead-free solder alloy is suppressed. Since fine (Cu, Co) ₆ Sn ₅ is formed near the interface and dispersed in the base metal, it suppresses creep deformation of the solder joint and crack growth, and especially the temperature difference. It is possible to improve the heat and fatigue characteristics of the solder joint even in a severe environment.

Further, the lead-free solder alloy to which Co is added enhances the above-mentioned effect by adding Ni even when soldering electronic parts that are not Ni / Pd / Au plated or Ni / Au plated, and Co is added. Since it moves to the vicinity of the interface to form fine (Cu, Co) ₆ Sn ₅ during solder bonding, the growth of the Cu ₃ Sn layer in the vicinity of the interface can be suppressed, and the effect of suppressing crack growth in the vicinity of the interface can be suppressed. Can be improved.

Here, since Co accelerates the solidification timing of the molten solder alloy in the same manner as Ni, in the fillet of the formed solder joint, the gas that tried to escape to the outside remains in the fillet during the melting of the solder alloy. It becomes easy to solidify, and holes (voids) due to gas are likely to occur in the fillet. The voids in the fillet reduce the heat and fatigue characteristics of the solder joint in an environment with a large temperature difference.
However, in the lead-free solder alloy of the present embodiment, the generation of such voids can be suppressed by keeping the Co content within the above range and balancing the content with other elements including Ni. ..

Further, since Co can suppress the growth of cracks in the solder joint together with Ni, the adverse effect of not adding Cu to the solder alloy is further suppressed, and the substrate having poor solder wettability and spreading property such as CuOSP substrate is further suppressed. Even so, the generation of the above voids can be suppressed.

However, if the content of Co is less than 0.001% by mass, the effect of modifying the intermetallic compound by Co is insufficient.

To the lead-free solder alloy of the present embodiment, 4.5% by mass or less of Bi can be added.
In the lead-free solder alloy of the present embodiment, by adding Bi within this range, good thermal shock resistance can be maintained without impairing the stretchability of the solder alloy. However, if the Bi content exceeds 4.5% by mass, the stretchability of the lead-free solder alloy is hindered and the thermal shock resistance is lowered, which is not preferable.
When the Bi content is 3% by mass or more and 4% by mass or less, the thermal shock resistance can be further improved without impairing the stretchability.

Here, when the lead-free solder alloy of the present embodiment contains Ag, Sb, Ni, Bi, and Co, the respective contents (mass%) of Ag, Sb, Ni, Bi, and Co are given by the following formula (A). It is preferable to satisfy all of (C).
(A) 3.6 ≤ Ag content + Sb content ≤ 9.0
(B) 0.17 <(Ag content / 3) + (Bi content / 4.5) ≤ 2.10
(C) 0 <(Ni content / 0.15) + (Co content / 0.15) ≤ 1.3
By setting the contents of Ag, Sb, Ni, Bi, and Co within the above range, the effect of suppressing crack growth at the solder joint in a harsh environment and the solder joint that tends to occur when electronic components are mounted on the CuOSP substrate. The effect of suppressing voids in the part and the suppression of crack growth near the interface due to the growth of the _{Cu 3} Sn layer, which tends to occur when electronic components that are not Ni / Pd / Au plated or Ni / Au plated are mounted on the substrate. All of the effects can be exhibited in a well-balanced manner, and the reliability of the solder joint can be further improved.

Further, the lead-free solder alloy of the present embodiment can contain 6% by mass or less of In. By adding In within this range, the melting temperature of the lead-free solder alloy raised by the addition of Sb can be lowered and the crack growth suppressing effect can be improved. That is, since In also dissolves in the Sn matrix in the same manner as Sb, not only can the lead-free solder alloy be further strengthened, but also AgSnIn and InSb compounds are formed and deposited at the Sn grain boundaries to cause Sn. It has the effect of suppressing slip deformation of grain boundaries.
However, if the In content exceeds 6% by mass, the stretchability of the lead-free solder alloy is hindered, and γ-InSn ₄ is formed during long-term exposure to a harsh environment with a large temperature difference. , It is not preferable because the lead-free solder alloy self-deforms.
The more preferable content of In is 4% by mass or less, and 1% by mass to 2% by mass is particularly preferable.

Further, the lead-free solder alloy of the present embodiment may contain at least one of P, Ga, and Ge in an amount of 0.001% by mass or more and 0.05% by mass or less. Oxidation of the lead-free solder alloy can be prevented by adding at least one of P, Ga, and Ge within this range. However, if these contents exceed 0.05% by mass, the melting temperature of the lead-free solder alloy rises, or voids are likely to occur at the joints, which is not preferable.

Further, the lead-free solder alloy of the present embodiment may contain at least one of Fe, Mn, Cr, and Mo in an amount of 0.001% by mass or more and 0.05% by mass or less. By adding at least one of Fe, Mn, Cr, and Mo within this range, the crack growth suppressing effect of the lead-free solder alloy can be improved. However, if these contents exceed 0.05% by mass, the melting temperature of the lead-free solder alloy rises, or voids are likely to occur at the joints, which is not preferable.

The lead-free solder alloy of the present embodiment contains other components (elements) such as Cd, Tl, Se, Au, Ti, Si, Al, Mg, Zn and the like as long as the effect is not impaired. be able to. Further, the lead-free solder alloy of the present embodiment naturally contains unavoidable impurities.

Further, it is preferable that the balance of the lead-free solder alloy of the present embodiment is Sn. The preferable Sn content is 80.1% by mass or more and 97.99% by mass or less.

The solder joints of the present embodiment may be formed by any method as long as the solder joints can be formed, such as a flow method, mounting with solder balls, and a reflow method using a solder paste composition. .. Among them, a reflow method using a solder paste composition is particularly preferably used.

(2) Solder Paste Composition Such a solder paste composition is produced, for example, by kneading the powdered lead-free solder alloy and flux to form a paste.

As such a flux, for example, a flux containing a synthetic resin, a thixotropic agent, an activator, and a solvent is used.

Examples of the synthetic resin include rosins such as tall oil rosin, gum rosin, and wood rosin, and rosin-based resins containing hydrogenated rosins, polymerized rosins, heterogeneous rosins, acrylic acid-modified rosins, maleic acid-modified rosins, and other rosin derivatives; acrylic. Acids, methacrylic acid, various esters of acrylic acid, various esters of methacrylic acid, crotonic acid, itaconic acid, maleic acid, maleic anhydride, maleic acid ester, maleic anhydride ester, acrylonitrile, methacrylnitrile, acrylamide, methacryl Acrylic resin formed by polymerizing at least one monomer such as amide, vinyl chloride, vinyl acetate and the like; epoxy resin; phenol resin and the like can be mentioned. These can be used alone or in combination of two or more.
Among these, rosin-based resins, particularly hydrogenated acid-modified rosins obtained by hydrogenating acid-modified rosins are preferably used.

The acid value of the synthetic resin is preferably 10 mgKOH / g or more and 250 mgKOH / g or less, and the blending amount thereof is preferably 10% by mass or more and 90% by mass or less with respect to the total amount of the flux.

Examples of the thixotropy include hydrogenated castor oil, fatty acid amides, and oxyfatty acids. These can be used alone or in combination of two or more. The blending amount of the thixotropy is preferably 3% by mass or more and 15% by mass or less with respect to the total amount of the flux.

As the activator, for example, an amine salt (inorganic acid salt or organic acid salt) such as a hydrohalide hydrogen salt of an organic amine, an organic acid, an organic acid salt, or an organic amine salt can be blended. More specifically, diphenylguanidine hydrobromide, cyclohexylamine hydrobromide, diethylamine salt, acid salt, succinic acid, adipic acid, sebacic acid and the like can be mentioned. These can be used alone or in combination of two or more. The blending amount of the activator is preferably 5% by mass or more and 15% by mass or less with respect to the total amount of the flux.

As the solvent, for example, isopropyl alcohol, ethanol, acetone, toluene, xylene, ethyl acetate, ethyl cellosolve, butyl cellosolve, glycol ether and the like can be used. These can be used alone or in combination of two or more. The blending amount of the solvent is preferably 20% by mass or more and 40% by mass or less with respect to the total amount of the flux.

An antioxidant can be added to the flux for the purpose of suppressing the oxidation of the lead-free solder alloy. Examples of this antioxidant include hindered phenol-based antioxidants, phenol-based antioxidants, bisphenol-based antioxidants, polymer-type antioxidants, and the like. Among them, a hindered phenol-based oxidizing agent is particularly preferably used. These can be used alone or in combination of two or more. The blending amount of the antioxidant is not particularly limited, but is generally preferably 0.5% by mass or more and about 5% by mass or less with respect to the total amount of the flux.

Other resins and additives such as halogens, matting agents, defoaming agents and inorganic fillers may be added to the flux.
The blending amount of the additive is preferably 10% by mass or less with respect to the total amount of the flux. Further, a more preferable blending amount of these is 5% by mass or less with respect to the total amount of the flux.

In the solder paste composition of the present embodiment, various esters of acrylic acid, methacrylic acid, and acrylic acid, various esters of methacrylic acid, crotonic acid, itaconic acid, maleic acid, maleic anhydride, and maleic anhydride, and anhydrous. Acrylic resin obtained by polymerizing at least one monomer of maleic anhydride, acrylonitrile, methacrylic nitrile, acrylamide, methacrylic amide, vinyl chloride and vinyl acetate, rosin-based resin having a carboxyl group and dimer acid derivative flexible alcohol compound. A flux solidified product containing at least one of the resins of the derivative compound obtained by dehydration-condensing the mixture, a thixo agent, an activator, and a solvent, and heated to form a flux solidified product at -40 ° C./30 minutes to 125 ° C. ^{A flux having an adhesive strength of 0.2 N / mm 2} or more after 2000 cycles of a thermal shock test with 1 cycle of / 30 minutes is preferably used. The adhesive strength is measured in accordance with the standard number JIS C6000068-2-21.

The blending ratio of the lead-free solder alloy and the flux is preferably a solder alloy: flux ratio of 65:35 to 95: 5. A more preferred blending ratio is 85:15 to 93: 7, and a particularly preferred blending ratio is 87:13 to 92: 8.

(3) Electronic Circuit Board The configuration of the electronic circuit board of the present embodiment will be described with reference to FIG. The electronic circuit board 100 of the present embodiment includes a substrate 1, an insulating layer 2, an electrode portion 3, an electronic component 4, and a solder joint 10. The solder joint 10 has a solder joint 6 and a flux residue 7, and the electronic component 4 has an external electrode 5 and an end 8.
The substrate 1 is not limited to those used for mounting and mounting electronic components such as printed wiring boards, silicon wafers, and ceramic package substrates, and can be used as the substrate 1.
The electrode portion 3 is electrically joined to the external electrode 5 of the electronic component 4 via the solder joint portion 6.
Further, the solder joint portion 6 is formed by using the solder alloy according to the present embodiment.

Since the electronic circuit board 100 of the present embodiment having such a configuration has an alloy composition in which the solder joint portion 6 exerts a crack growth suppressing effect, even if a crack occurs in the solder joint portion 6, the crack is formed. Can restrain the progress of. Further, even when the substrate 1 is a CuOSP substrate, the generation of voids in the solder joint portion 6 can be suppressed.
Further, in the electronic circuit board 100 of the present embodiment, even when the electronic component 4 is not plated with Ni / Pd / Au or Ni / Au, the vicinity of the interface between the solder joint 6 and the electronic component 4 is provided. It is also possible to exert the effect of suppressing crack growth in the above.

Such an electronic circuit board 100 is manufactured as follows, for example.
First, the solder paste composition is printed according to the above pattern on a substrate 1 provided with an insulating layer 2 and an electrode portion 3 formed so as to have a predetermined pattern.
Next, the electronic component 4 is mounted on the printed circuit board 1, and the electronic component 4 is reflowed at a temperature of 230 ° C. to 260 ° C. By this reflow, a solder joint 10 having a solder joint 6 and a flux residue 7 is formed on the substrate 1, and an electronic circuit board 100 in which the substrate 1 and the electronic component 4 are electrically bonded is manufactured.

Further, by incorporating such an electronic circuit board 100, the electronic control device of the present embodiment is manufactured.

Hereinafter, the present invention will be described in detail with reference to Examples and Comparative Examples. The present invention is not limited to these examples.

Preparation of Flux Each of the following components was kneaded to obtain flux according to Examples and Comparative Examples.
Hydrogenated acid-modified rosin (product name: KE-604, manufactured by Arakawa Chemical Industry Co., Ltd.) 51% by mass
Hardened castor oil 6% by mass
Dodecanedioic acid 10% by mass (Product name: SL-12, manufactured by Okamura Oil Co., Ltd.)
Malonic acid 1% by mass
Diphenylguanidine hydrobromide 2% by mass
Hindered phenolic antioxidant (Product name: Irganox 245, manufactured by BASF Japan Ltd.) 1% by mass
Diethylene glycol monohexyl ether 29% by mass

Preparation of Solder Paste Composition The flux 11.0% by mass and the powder of each lead-free solder alloy shown in Tables 1 and 2 (powder particle size 20 μm to 38 μm) 89.0% by mass were mixed and used in Examples. Each solder paste composition according to 2 to 8, 10 to 16, 18 to 27 , Reference Examples 1, 9, 17 and Comparative Examples 1 to 17 was prepared.

(1) Solder crack test (-40 ° C to 125 ° C)
-3.2 mm x 1.6 mm chip parts (chip A)
A chip component (Ni / Sn plating) with a size of 3.2 mm x 1.6 mm, a solder resist having a pattern on which the chip component of that size can be mounted, and an electrode (1.6 mm x 1.2 mm) for connecting the chip component. A glass epoxy substrate (CuOSP substrate) provided with the above and a metal mask having the same pattern and a thickness of 150 μm were prepared.
Each solder paste composition was printed on the glass epoxy substrate using the metal mask, and the chip components were mounted on the glass epoxy substrate.
After that, each glass epoxy substrate is heated using a reflow furnace (product name: TNP-538EM, manufactured by Tamura Seisakusho Co., Ltd.), and the glass epoxy substrate and the chip component are electrically bonded to each solder joint. A portion was formed and the chip component was mounted. The reflow conditions at this time were preheating at 170 ° C. to 190 ° C. for 110 seconds, a peak temperature of 245 ° C., a time of 200 ° C. or higher for 65 seconds, a time of 220 ° C. or higher for 45 seconds, and a peak temperature of 200 ° C. The cooling rate was set to 3 ° C. to 8 ° C./sec, and the oxygen concentration was set to 1500 ± 500 ppm.
Next, using a thermal shock tester (product name: ES-76LMS, manufactured by Hitachi Appliances, Inc.) set under the conditions of -40 ° C (30 minutes) to 125 ° C (30 minutes), the thermal shock cycle was set to 1, Each of the glass epoxy substrates was exposed to an environment in which 000, 1,500, 2,000, 2,500, and 3,000 cycles were repeated, and then taken out to prepare each test substrate.
Next, the target portion of each test substrate was cut out and sealed with an epoxy resin (product name: Epomount (main agent and curing agent), manufactured by Refine Tech Co., Ltd.). Furthermore, a wet grinding machine (product name: TegraPol-25, Marumoto Struas Co., Ltd.,
The central cross section of the chip component mounted on each test board can be seen using (manufactured by), and whether or not the cracks generated in the formed solder joint completely cross the solder joint and lead to breakage. The solder was observed using a scanning electron microscope (product name: TM-1000, manufactured by Hitachi High-Technologies Corporation) and evaluated according to the following criteria. The results are shown in Tables 3 and 4. The number of evaluation chips in each thermal shock cycle was set to 10.
⊚: No cracks completely crossing the solder joint up to 3,000 cycles ○: Cracks completely crossing the solder joint between 2,501 and 3,000 cycles Δ: 2,001 to 2 , Rhagades completely cross the solder joint in 500 cycles ×: Cracks completely cross the solder joint in less than 2,000 cycles

-2.0 x 1.2 mm chip parts (chip B)
A chip component (Ni / Sn plating) with a size of 2.0 x 1.2 mm, a solder resist having a pattern on which the chip component of the size can be mounted, and an electrode (1.25 mm x 1.0 mm) for connecting the chip component. A test substrate was prepared under the same conditions as the 3.2 mm × 1.6 mm chip component except that a glass epoxy substrate (CuOSP substrate) provided with the above was used, and the test substrate was evaluated by the same method. The results are shown in Tables 3 and 4.

(2) Solder crack test in Sn plating SON 6 mm × 5 mm × 0.8 tmm size 1.3 mm pitch SON (Small Outline Non-led package) parts (8 pins, product name: STL60N3LLH5, manufactured by STMicroelectronics), A glass epoxy substrate (CuOSP substrate) having a solder resist having a pattern on which the SON component can be mounted and an electrode (according to the manufacturer's recommended design) for connecting the SON component, and a metal mask having the same pattern and a thickness of 150 μm are used. I prepared it.
Each solder paste composition was printed on the glass epoxy substrate using the metal mask, and the SON component was mounted on each. After that, the glass epoxy substrate is reflowed and cooled under the same conditions as in (1) Solder Crack Test above except that each glass epoxy substrate is placed in an environment where the thermal shock cycle is repeated 1,000, 2,000, and 3,000 cycles. A shock was applied to prepare each test substrate.
Next, the target portion of each test substrate was cut out and sealed with an epoxy resin (product name: Epomount (main agent and curing agent), manufactured by Refine Tech Co., Ltd.). Furthermore, a wet polishing machine (product name: TegraPol-25, manufactured by Marumoto Struas Co., Ltd.) was used to make the terminal center cross section of the SON component mounted on each test substrate visible, and it occurred at the solder joint. Whether or not the crack completely crossed the solder joint and reached the break was observed using a scanning electron microscope (product name: TM-1000, manufactured by Hitachi High-Technologies Corporation). Based on this observation, regarding the solder joint, the solder base material (in this specification, the solder base material refers to a part of the solder joint other than the interface of the electrode of the SON component and its vicinity. The same shall apply hereinafter. Table 3 And in Table 4, it is simply referred to as "base material") and the cracks generated at the interface between the solder joint and the electrode of the SON component (the metal-to-metal compound) were evaluated as follows. .. The results are shown in Tables 3 and 4. The number of evaluated SONs in each thermal shock cycle was set to 20, and one terminal of the gate electrode was observed for each SON to confirm the cross section of a total of 20 terminals.

・ Cracks generated in the solder base material ◎: No cracks completely crossing the solder base material up to 3,000 cycles ○: Cracks completely crossing the solder base material between 2,001 and 3,000 cycles Occurrence Δ: Cracks completely crossing the solder base material between 1,001 and 2,000 cycles ×: Cracks completely crossing the solder base material in less than 1,000 cycles

-Rhagades generated at the interface between the solder joint and the electrode of the SON component ◎: No cracks completely crossing the interface up to 3,000 cycles ○: Completely the interface between 2,001 and 3,000 cycles Rhagades that completely cross the interface between 1,001 and 2,000 cycles ×: Rhagades that completely cross the interface in less than 1,000 cycles

(3) Solder crack test (-40 ° C to 150 ° C)
Since an in-vehicle substrate or the like is placed in a harsh environment where the temperature difference is extremely large, the solder alloy used for this is required to exhibit a good effect of suppressing crack growth even in such an environment. Therefore, in order to clarify whether the solder alloy according to this embodiment can exert the effect even under such harsher conditions, a liquid tank type thermal shock tester is used to make the temperature between -40 ° C and 150 ° C. A solder crack test was conducted in the temperature difference of. The conditions are as follows.
Liquid tank type thermal shock tester (product name: ETAC WINTECH LT80, Kusumoto) in which each glass epoxy substrate (CuOSP substrate) after forming the solder joint is set to the condition of -40 ° C (30 minutes) to 150 ° C (30 minutes). 3.2 × 1. Each test board on which a 6 mm chip component (chip A) was mounted and a 2.0 × 1.2 mm chip component (chip B) was mounted was produced.
Next, the target portion of each test substrate was cut out and sealed with an epoxy resin (product name: Epomount (main agent and curing agent), manufactured by Refine Tech Co., Ltd.). Furthermore, a wet polishing machine (product name: TegraPol-25, manufactured by Marumoto Struas Co., Ltd.) was used to make the central cross section of the chip component mounted on each test substrate visible, and the formed solder joint was formed. Observe using a scanning electron microscope (product name: TM-1000, manufactured by Hitachi High-Technologies Corporation) to see if the generated cracks completely cross the solder joint and lead to breakage, and use the following criteria. evaluated. The results are shown in Tables 3 and 4. The number of evaluation chips in each thermal shock cycle was set to 10.
⊚: No crack completely crosses the solder joint up to 3,000 cycles ○: Cracks completely cross the solder joint between 2,001 to 3,000 cycles Δ: 1,001 to 2 Rhagades completely cross the solder joint during 1,000 cycles ×: Rhagades completely cross the solder joint in less than 1,000 cycles

(4) Void test A chip component (Ni / Sn plating) having a size of 2.0 × 1.2 mm, a solder resist having a pattern on which the chip component of the size can be mounted, and an electrode (1.25 mm) connecting the chip component. A glass epoxy substrate (CuOSP substrate) provided with (× 1.0 mm) and a metal mask having the same pattern and a thickness of 150 μm were prepared.
Each solder paste composition was printed on the glass epoxy substrate using the metal mask, and the chip components were mounted on the glass epoxy substrate.
After that, each glass epoxy board is heated using a reflow furnace (product name: TNP-538EM, manufactured by Tamura Seisakusho Co., Ltd.), and the glass epoxy board and the chip component are electrically bonded to each solder joint. Each test board was manufactured by forming a portion and mounting the chip component. The reflow conditions at this time were preheating at 170 ° C. to 190 ° C. for 110 seconds, a peak temperature of 245 ° C., a time of 200 ° C. or higher for 65 seconds, a time of 220 ° C. or higher for 45 seconds, and a peak temperature of 200 ° C. The cooling rate was set to 3 ° C. to 8 ° C./sec, and the oxygen concentration was set to 1500 ± 500 ppm.
Next, the surface condition of each test substrate was observed with an X-ray transmission device (product name: SMX-160E, manufactured by Shimadzu Corporation), and in 20 lands in each test substrate, the area under the electrode of the chip component (Fig.) The area ratio of the voids (the ratio of the total area of the voids; the same applies hereinafter) to the area (a) surrounded by the broken line of 3 and the area where the fillet is formed (the area (b) surrounded by the broken line in FIG. 3). The average value of the area ratio of voids in the area was calculated, and each was evaluated as follows. The results are shown in Tables 3 and 4.
⊚: The average value of the area ratio of voids is 3% or less, and the effect of suppressing the generation of voids is extremely good. Good Δ: The average value of the area ratio of voids is more than 5% and 8% or less, and the effect of suppressing the generation of voids is sufficient. insufficient

As shown above, the solder joint formed by using the lead-free solder alloy according to the embodiment does not require the addition of Cu even in a harsh environment where the temperature difference is large and vibration is applied. Regardless of the size of the chip, and whether or not the electrodes are Ni / Pd / Au plated or Ni / Au plated, the solder alloy has the effect of suppressing crack growth near the solder joint and the interface. Even when a CuOSP substrate having poor wet spreadability is used, the effect of suppressing voids can be exhibited both under the electrode and under the fillet. In particular, it can be seen that the solder joints of the examples have a good crack suppressing effect even in a very harsh environment where the temperature difference is -40 ° C to 150 ° C using a liquid tank type thermal shock tester.
Further, it can be seen that the effect of suppressing the void of the fillet is particularly good in Examples 14 to 27 in which Ni and Co are used in combination.

As described above, the lead-free solder alloy of the present invention can be suitably used for electronic circuit boards that require high reliability, such as in-vehicle electronic circuit boards. Further, such an electronic circuit board can be suitably used for an electronic control device that requires even higher reliability.

1 Substrate 2 Insulation layer 3 Electrode 4 Electronic component 5 External electrode 6 Solder joint 7 Flux residue 8 End 10 Solder joint 100 Electronic circuit board

Claims (9)

It is characterized by containing Ag in an amount of 1% by mass or more and 4% by mass or less, Sb in an amount of 3% by mass or more and 5% by mass or less, Ni in an amount of 0.01% by mass or more and 0.03% by mass or less, and the balance consisting of Sn. Lead-free solder alloy for automotive electronic circuit boards. The lead-free solder alloy for an in-vehicle electronic circuit board according to claim 1, further comprising 4.5% by mass or less of Bi. The lead-free solder alloy for an in-vehicle electronic circuit board according to claim 1 or 2, further comprising Co in 0.001% by mass or more and 0.15% by mass or less. The lead-free solder alloy for an in-vehicle electronic circuit board according to claim 3, wherein the Co content is 0.008% by mass or more and 0.01% by mass or less. The lead-free solder alloy for an in-vehicle electronic circuit board according to any one of claims 1 to 4, further comprising 6% by mass or less of In. The vehicle-mounted electron according to any one of claims 1 to 5, further comprising at least one of P, Ga, and Ge in a total amount of 0.001% by mass or more and 0.05% by mass or less. Lead-free solder alloy for circuit boards. The vehicle-mounted vehicle according to any one of claims 1 to 6, further comprising at least one of Fe, Mn, Cr, and Mo in a total amount of 0.001% by mass or more and 0.05% by mass or less. Lead-free solder alloy for electronic circuit boards. Automotive electronic circuit board and having a solder joint formed using the vehicle electronics lead-free solder alloy substrate according to any one of claims 1 to 7. Vehicle electronic control apparatus characterized by having a vehicle electronic circuit board according to claim 8.

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