WO2019235001A1 - Lead-free solder alloy, solder paste, electronic circuit-mounted substrate, and electronic control device - Google Patents
Lead-free solder alloy, solder paste, electronic circuit-mounted substrate, and electronic control device Download PDFInfo
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- WO2019235001A1 WO2019235001A1 PCT/JP2019/007717 JP2019007717W WO2019235001A1 WO 2019235001 A1 WO2019235001 A1 WO 2019235001A1 JP 2019007717 W JP2019007717 W JP 2019007717W WO 2019235001 A1 WO2019235001 A1 WO 2019235001A1
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- free solder
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
- B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
- B23K35/24—Selection of soldering or welding materials proper
- B23K35/26—Selection of soldering or welding materials proper with the principal constituent melting at less than 400 degrees C
- B23K35/268—Pb as the principal constituent
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
- B23K35/22—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by the composition or nature of the material
- B23K35/24—Selection of soldering or welding materials proper
- B23K35/26—Selection of soldering or welding materials proper with the principal constituent melting at less than 400 degrees C
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- C—CHEMISTRY; METALLURGY
- C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
- C22C—ALLOYS
- C22C13/00—Alloys based on tin
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- C—CHEMISTRY; METALLURGY
- C22—METALLURGY; FERROUS OR NON-FERROUS ALLOYS; TREATMENT OF ALLOYS OR NON-FERROUS METALS
- C22C—ALLOYS
- C22C13/00—Alloys based on tin
- C22C13/02—Alloys based on tin with antimony or bismuth as the next major constituent
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K2101/00—Articles made by soldering, welding or cutting
- B23K2101/36—Electric or electronic devices
- B23K2101/42—Printed circuits
Definitions
- the present invention relates to a lead-free solder alloy, a solder paste, an electronic circuit mounting board, and an electronic control device.
- solder joining method using a solder alloy as a method for joining an electronic component to a conductor pattern formed on an electronic circuit board such as a printed wiring board or a module board.
- this solder alloy used lead.
- lead-free solder alloy that does not contain lead is becoming common in recent years.
- solder alloy for example, Sn—Cu, Sn—Ag—Cu, Sn—Bi and Sn—Zn solder alloys are well known.
- consumer electronic devices such as televisions and mobile phones are soldered using Sn-3Ag-0.5Cu solder alloy (a solder joint is formed using Sn-3Ag-0.5Cu solder alloy).
- an electronic circuit mounting board is used.
- the lead-free solder alloy is somewhat inferior in solderability as compared with the lead-containing solder alloy.
- the solderability problem has been overcome by improving the flux and soldering apparatus, the Sn-3Ag-0.5Cu solder is used in a device that is placed in a relatively mild environment such as a consumer electronic device. Even with solder bonding using an alloy, a certain degree of reliability of the electronic circuit mounting board can be maintained.
- the mounted electronic circuit board can be exposed to extremely harsh environments that are subject to severe temperature differences (eg, ⁇ 30 ° C. to 115 ° C., ⁇ 40 ° C. to 125 ° C.) and vibration loads.
- the board before the conductor pattern formation is A board that is formed and can be electrically connected to an electronic component, and a board part that does not include an electronic component among electronic circuit mounting boards on which the electronic component is mounted.
- the strain due to the difference in linear expansion coefficient from "the board portion of the electronic circuit mounting board on which the electronic component is mounted” that does not include the electronic component) and the stress due to the thermal displacement of the solder joint are generated. These are easy to apply and cause a large load on the solder joint. And the load repeatedly given to a solder joint part in the use process of a car causes the plastic deformation of a solder joint part many times, and can become a cause of crack generation of a solder joint part.
- Bi When Bi is added to the solder alloy, Bi enters the lattice of the atomic arrangement of the solder alloy and substitutes Sn to distort the atomic arrangement of the lattice. As a result, the Sn matrix is strengthened and the alloy strength is improved, so that a certain improvement in the crack growth suppressing effect in the bulk portion of the solder joint portion is expected.
- a lead-free solder alloy that has been strengthened by the addition of Bi has the demerit that extensibility deteriorates and brittleness increases. This is presumably because the addition of Bi makes it difficult for slip deformation in a specific crystal orientation to occur.
- the suppression of crack propagation at the solder joint in an environment with a severe temperature difference is still one of the important issues particularly in the on-vehicle electronic control device and the on-vehicle electronic circuit mounting substrate used therefor. Yes. However, if the Bi content is suppressed in order to suppress the brittle fracture, the crack growth suppressing effect is lowered, and if the content is increased, the brittle fracture is likely to occur. In addition, when In is added to a solder alloy together with Bi to increase the strength of the solder alloy, since In is an easily oxidizable alloy element, depending on its content or combination with other alloy elements, etc. There is a problem that voids are easily generated in the solder joints, and that cracks caused by the voids and their progress are likely to occur.
- the present invention solves the above-mentioned problems, and provides a lead-free solder alloy, a solder paste, and an electronic circuit that can achieve both crack growth suppression effect of solder joints and resistance to impact accompanied by high-speed deformation in an environment with a severe temperature difference It is an object of the present invention to provide a mounting board and an electronic control device.
- the lead-free solder alloy according to the present invention comprises 2% by mass to 4% by mass of Ag, 0.3% by mass to 1% by mass Cu, and 1.5% by mass to less than 3% by mass. It contains Bi and 1% by mass or more and less than 3% by mass of In, with the remainder being made of Sn.
- the Bi content is 2% by mass or more and less than 3% by mass
- the In content is 2% by mass or more and less than 3% by mass.
- the Bi content is 2% by mass or more and 2.8% by mass or less
- the In content is 2% by mass or more and 2.8% by mass or less. Its features.
- the Bi content is 2.3 mass% or more and 2.8 mass% or less
- the In content is 2.3 mass% or more and 2.8 mass% or less. It is the feature.
- the Ag content is 2.5% by mass or more and 3.5% by mass or less.
- the content of Cu is 0.4% by mass or more and 0.8% by mass or less.
- the lead-free solder alloy according to the present invention in the configuration described in any one of (1) to (6) above, further includes at least one of Ni and Co in a total of 0.001% by mass or more. It is characterized by containing 10% by mass or less.
- the lead-free solder alloy according to the present invention in the configuration described in any one of (1) to (7) above, further includes at least one of Fe, Mn, Cr, and Mo in total 0.001 mass. % To 0.05% by mass or less.
- the lead-free solder alloy according to the present invention is the structure described in any one of (1) to (8) above, and at least one of P, Ga, and Ge is further 0.001% by mass or more in total. It is characterized by containing 0.05 mass% or less.
- the solder paste according to the present invention is a powdered lead-free solder alloy, the lead-free solder alloy according to any one of (1) to (9), a base resin, a thixotropic agent, It is characterized by having a flux containing an activator and a solvent.
- An electronic circuit mounting board according to the present invention has a solder joint formed by using the lead-free solder alloy described in any one of (1) to (9).
- An electronic control device includes the electronic circuit mounting board described in (11) above.
- the lead-free solder alloy and solder paste of the present invention can achieve both the effect of suppressing the crack growth of the solder joint and the resistance to impact accompanied by high-speed deformation under an environment where the temperature difference is severe.
- the electronic circuit mounting board and the electronic control device having such a solder joint portion can exhibit high reliability even in a severe environment with a severe temperature difference, and particularly the in-vehicle electronic circuit mounting board and the in-vehicle electronic It can be suitably used for a control device.
- a general chip component mounting board is used from the chip component side using an X-ray transmission device. Photo taken.
- the lead-free solder alloy of this embodiment can contain 2 mass% or more and 4 mass% or less of Ag. By adding Ag to the lead-free solder alloy within this range, it is possible to precipitate the Ag 3 Sn compound in its Sn grain boundary and impart mechanical strength, as well as thermal shock resistance, thermal fatigue characteristics and high speed. It is possible to exhibit resistance to impact accompanied by deformation.
- the Ag content is 2% by mass or more and 3.8% by mass or less, the mechanical strength and the strength, ductility, and cost balance of the lead-free solder alloy are improved while improving the stretchability of the lead-free solder alloy. It is possible to improve the resistance to impact accompanied by high-speed deformation.
- the particularly preferable Ag content is 2.5% by mass or more and 3.5% by mass or less.
- the lead-free solder alloy of this embodiment can contain 0.3 mass% or more and 1 mass% or less of Cu.
- Cu By adding Cu to the lead-free solder alloy within this range, an effect of preventing copper erosion to the Cu land of the conductor pattern (electronic circuit) on the substrate is exhibited and Cu 6 Sn 5 compound is added to the Sn grain boundary. Precipitation can improve the thermal shock resistance of the lead-free solder alloy. Moreover, the heat-resistant fatigue characteristics of the solder joint part formed using this can be improved without inhibiting the stretchability of the lead-free solder alloy.
- More preferable Cu content is 0.4 mass% or more and 0.8 mass% or less, and particularly preferable content is 0.5 mass% or more and 0.8 mass% or less.
- the lead-free solder alloy of this embodiment can contain Bi.
- Bi When Bi is added to a lead-free solder alloy, a part of the Sn crystal lattice is replaced with Bi, and distortion occurs in the crystal lattice.
- the metal structure of the solder joint formed using such a lead-free solder alloy can be strengthened by solid solution and the Young's modulus can be increased. Therefore, even when the solder joint is subjected to external stress due to temperature difference over a long period of time, deformation of the solder joint can be suppressed and good external stress resistance can be exhibited.
- the mechanical strength and thermal shock resistance of the lead-free solder alloy are improved by setting the Bi content to 1.5 mass% or more and less than 3 mass%, and solder joining It is possible to obtain solid solution strengthening of the metal composition of the part, and to exhibit good ductility and resistance to impact accompanied by high-speed deformation.
- the Bi content is 3% by mass or more, a solder joint formed using the Bi is likely to break due to an impact accompanied by high-speed deformation.
- the lead-free solder alloy can be strengthened (crack progress suppressing effect) and the resistance to impact with high-speed deformation can be improved, and the balance between the two can be further exhibited.
- the more preferable content of Bi is 2% by mass or more and 2.8% by mass or less, and the particularly preferable content thereof is 2.3% by mass or more and 2.8% by mass or less.
- the lead-free solder alloy of this embodiment can contain 1% by mass or more and less than 3% by mass of In.
- the solder structure of the lead-free solder alloy can be polycrystallized to cancel anisotropy. Therefore, the embrittlement phenomenon in a specific crystal orientation in a lead-free solder alloy can be suppressed, and even when an impact accompanied by high-speed deformation is applied to a solder joint formed using this, the occurrence of breakage is prevented. Can be suppressed.
- the In content is 3% by mass or more, voids are likely to be generated in a solder joint portion formed using the solder paste, and the crack growth suppressing effect may be hindered.
- the preferable content of In is 2% by mass or more and less than 3% by mass, the more preferable content is 2% by mass or more and 2.8% by mass or less, and the particularly preferable content is 2.3% by mass or more and 2. It is 8 mass% or less.
- the crack of the solder joint portion in an environment with a severe temperature difference is achieved by balancing the contents of Bi and In, and other alloy elements and these contents. It is possible to achieve both the effect of suppressing the progress and the resistance to impact accompanied by high-speed deformation, or the effect of suppressing the void at the soldered joint.
- the lead-free solder alloy of this embodiment preferably contains 2% by mass or more and less than 3% by mass of Bi and 2% by mass or more and less than 3% by mass of In, and preferably 2% by mass or more and less than 3% by mass of Bi. It is more preferable to contain 2% by mass to 2.8% by mass of In, and 2.3% by mass to 2.8% by mass of Bi and 2.3% by mass to 2.8% by mass of In. It is particularly preferable to contain.
- the lead-free solder alloy of this embodiment can contain 0.001% by mass or more and 0.10% by mass or less of at least one of Ni and Co. By adding at least one of Ni and Co to the lead-free solder alloy within this range, it is possible to improve the crack growth suppressing effect of the solder joint while suppressing the generation of voids.
- the lead-free solder alloy of this embodiment can contain 0.001% by mass or more and 0.05% by mass or less of at least one of Fe, Mn, Cr, and Mo in total. By adding at least one of Fe, Mn, Cr, and Mo within this range, it is possible to improve the crack growth suppressing effect of the solder joint portion while suppressing the generation of voids.
- the lead-free solder alloy of this embodiment can contain 0.001% by mass or more and 0.05% by mass or less of at least one of P, Ga, and Ge in total. By adding at least one of P, Ga and Ge within this range, it is possible to prevent oxidation of the lead-free solder alloy while suppressing the generation of voids.
- the lead-free solder alloy of this embodiment contains other components (elements) such as Cd, Tl, Se, Au, Ti, Si, Al, Mg, Zn, and the like as long as the effect is not hindered. be able to.
- the lead-free solder alloy of this embodiment naturally includes unavoidable impurities.
- the remainder of the lead-free solder alloy of this embodiment is made of Sn.
- solder joint portion of this embodiment any method may be used as long as the solder joint portion can be formed, such as a flow method, mounting with a solder ball, and a reflow method using a solder paste. Of these, a reflow method using solder paste is particularly preferred.
- solder paste Such a solder paste is produced by, for example, kneading the powdered lead-free solder alloy and flux into a paste.
- a flux for example, a flux containing a base resin, a thixotropic agent, an activator, and a solvent is used.
- the base resin examples include rosin resins including rosin derivatives such as rosin such as tall oil rosin, gum rosin and wood rosin, hydrogenated rosin, polymerized rosin, heterogeneous rosin, acrylic acid modified rosin and maleic acid modified rosin; Acid, methacrylic acid, various esters of acrylic acid, various esters of methacrylic acid, crotonic acid, itaconic acid, maleic acid, maleic anhydride, maleic acid ester, maleic anhydride ester, acrylonitrile, methacrylonitrile, acrylamide, methacrylic acid
- acrylic resins obtained by polymerizing at least one monomer such as amide, vinyl chloride, vinyl acetate; epoxy resins; phenol resins.
- rosin resins particularly hydrogenated acid-modified rosin obtained by hydrogenating acid-modified rosin, are preferably used.
- a combined use of a hydrogenated acid-modified rosin and an acrylic resin is also preferred.
- the acid value of the base resin is preferably 10 mgKOH / g or more and 250 mgKOH / g or less. Moreover, it is preferable that the compounding quantity of the said base resin is 10 to 90 mass% with respect to the flux whole quantity.
- thixotropic agent examples include hydrogenated castor oil, fatty acid amides, and oxy fatty acids. These can be used alone or in combination.
- the blending amount of the thixotropic agent is preferably 3% by mass or more and 15% by mass or less with respect to the total amount of the flux.
- an amine salt such as an organic amine hydrogen halide salt, an organic acid, an organic acid salt, an organic amine salt, or the like
- an amine salt such as an organic amine hydrogen halide salt, an organic acid, an organic acid salt, an organic amine salt, or the like
- diphenylguanidine hydrobromide, cyclohexylamine hydrobromide, diethylamine salt, acid salt, succinic acid, adipic acid, sebacic acid, malonic acid, dodecanedioic acid and the like can be mentioned. These can be used alone or in combination.
- the blending amount of the activator is preferably 5% by mass or more and 15% by mass or less with respect to the total amount of the flux.
- the solvent for example, isopropyl alcohol, ethanol, acetone, toluene, xylene, ethyl acetate, ethyl cellosolve, butyl cellosolve, glycol ether, diethylene glycol monohexyl ether, or the like can be used. These can be used alone or in combination.
- the amount of the solvent is preferably 20% by mass or more and 40% by mass or less based on the total amount of the flux.
- ⁇ An antioxidant may be added to the flux for the purpose of suppressing oxidation of the lead-free solder alloy.
- the antioxidant include hindered phenolic antioxidants, phenolic antioxidants, bisphenolic antioxidants, and polymer-type antioxidants. Among these, a hindered phenol antioxidant is particularly preferably used. These can be used alone or in combination.
- the blending amount of the antioxidant is not particularly limited, but generally it is preferably about 0.5% by mass or more and about 5% by mass or less based on the total amount of the flux.
- Additives such as halogens, matting agents, antifoaming agents and inorganic fillers may be added to the flux.
- the blending amount of the additive is preferably 10% by mass or less with respect to the total amount of the flux.
- these more preferable compounding quantities are 5 mass% or less with respect to the flux whole quantity.
- the compounding ratio of the lead-free solder alloy powder and the flux is preferably 65:35 to 95: 5 in the ratio of solder alloy: flux.
- a more preferred blending ratio is 85:15 to 93: 7, and a particularly preferred blending ratio is 87:13 to 92: 8.
- the particle diameter of the alloy powder is preferably 1 ⁇ m or more and 40 ⁇ m or less, more preferably 5 ⁇ m or more and 35 ⁇ m or less, and particularly preferably 10 ⁇ m or more and 30 ⁇ m or less.
- solder joint part of this embodiment is formed by, for example, printing the solder paste at a predetermined position on the substrate and performing reflowing at a temperature of, for example, 220 ° C to 250 ° C. This reflow forms a solder residue and a flux residue derived from the flux on the substrate.
- An electronic circuit mounting board having such a solder joint is formed by using, for example, a mask having a predetermined pattern by forming electrodes and insulating layers at predetermined positions on the board. This solder paste is printed, an electronic component conforming to the pattern is mounted at a predetermined position, and this is reflowed.
- solder joint is formed on the electrode, and the solder joint electrically joins the electrode and the electronic component. And on the said board
- solder joint part concerning this embodiment can exhibit the favorable crack progress inhibitory effect, and also has the tolerance to the impact accompanied by high-speed deformation. Therefore, an electronic circuit mounting board having such a solder joint can be suitably used for an electronic circuit mounting board that is required to have high reliability, such as an in-vehicle electronic circuit mounting board.
- a highly reliable electronic control device is manufactured by incorporating such an electronic circuit mounting board. And such an electronic control apparatus can be used suitably for the vehicle-mounted electronic control apparatus by which especially high reliability is calculated
- solder crack test The following tools were prepared. A chip component having a size of 3.2 mm ⁇ 1.6 mm A solder resist having a pattern capable of mounting the chip component of the size and an electrode connecting the chip component (1.6 mm ⁇ 1.0 mm, gap between Cu electrodes) : 150 mm thick metal mask having the above pattern, each solder paste is printed on the printed wiring board using the metal mask, and each of the 10 chip components is mounted. did. Thereafter, each of the printed wiring boards is heated using a reflow furnace (product name: TNP-538EM, manufactured by Tamura Corporation), and each of them has a solder joint for electrically joining the electrode and each chip component. An electronic circuit mounting board was produced.
- a reflow furnace product name: TNP-538EM, manufactured by Tamura Corporation
- the reflow conditions at this time are: preheating from 170 ° C. to 190 ° C. for 110 seconds, peak temperature of 245 ° C., time of 200 ° C. or higher for 65 seconds, time of 220 ° C. or higher for 45 seconds, peak temperature to 200 ° C.
- the cooling rate was 3 ° C. to 8 ° C./second, and the oxygen concentration was set to 1,500 ⁇ 500 ppm.
- a liquid tank type thermal shock test apparatus product name: ETAC WINTECH LT80, manufactured by Enomoto Kasei Co., Ltd.
- each electronic circuit mounting substrate is set to a condition of ⁇ 40 ° C. (5 minutes) to 125 ° C. (5 minutes).
- the “crack rate” is an index for determining how many cracks actually occur with respect to the assumed crack length.
- Crack rate (%) (total length of cracks / total length of assumed line cracks) x 100 Of the solder joints formed under the two electrodes of each chip component, the one with the longer crack length was used as the target for calculating the crack rate of the chip component.
- the “total length of cracks” is the sum of the lengths of a plurality of cracks generated at each solder joint to be evaluated (calculated) on each test substrate.
- the “assumed total crack length” is the total length of the expected crack propagation paths (cracks that have reached complete fracture) in each solder joint to be evaluated (calculated) in each test substrate.
- the jig is abutted against the side of the chip part and parallel to each electronic circuit mounting board at a predetermined shear rate.
- the maximum test force was calculated and this value was taken as the shear strength.
- the shear height in the measurement was 1 ⁇ 4 or less of the component height, and the shear rate was 100 mm / min.
- an average value (total of calculated share strengths ⁇ 5 (number of chip components)) was calculated and evaluated based on the following criteria for the measured share strength of each electronic circuit mounting board. The results are shown in Tables 3 and 4.
- ⁇ Average value of share strength is 7.0N or more
- Average value of share strength is 6.5N or more and less than 7.0N
- Average value of share strength is less than 6.5N
- the reflow conditions at this time are: preheating from 170 ° C. to 190 ° C. for 110 seconds, peak temperature of 245 ° C., time of 200 ° C. or higher for 65 seconds, time of 220 ° C. or higher for 45 seconds, peak temperature to 200 ° C.
- the cooling rate was 3 ° C. to 8 ° C./second, and the oxygen concentration was set to 1,500 ⁇ 500 ppm.
- the surface state of each test substrate was observed with an X-ray transmission device (product name: SMX-160E, manufactured by Shimadzu Corporation), and the area under each chip component electrode on each test substrate (enclosed by the broken line in FIG. 1).
- under-electrode area The ratio of the total area of voids generated in the area (a), hereinafter referred to as “under-electrode area”) to the land area (void area ratio of under-electrode area: total void area of under-electrode area / land area ⁇ 100) ) And the ratio of the total area of voids generated in the area where the fillet is formed (area (b) surrounded by the broken line in FIG. 1, hereinafter referred to as “fillet area”) to the land area (void area of the fillet area) Rate: total void area of fillet region / land area ⁇ 100) was measured and calculated.
- the solder joint formed using the lead-free solder alloy according to the example exhibits an effect of suppressing crack growth even in an environment where the temperature difference is severe, and at the same time has resistance to impact accompanied by high-speed deformation.
- a “liquid tank type” thermal shock test apparatus is used as described above.
- This liquid tank-type thermal shock test apparatus alternates test substrates in two liquid tanks (set at -40 ° C and 125 ° C in the above (1) Solder crack test), which can quickly transfer the test substrate. It is immersed and gives a rapid temperature change to the test substrate. This is a very severe test content compared to other test conditions (for example, “air tank type”). And the lead-free solder alloy which concerns on an Example can exhibit the crack growth inhibitory effect also under such very severe conditions.
- JIS standard C60068-2-21 does not specify the shear rate, but for example, the conditions of the shear test of other metals (the method of tensile shear test and bending of thin clad steel) (Test method: JIS standard Z2288, etc.) specifies a shear (tensile) speed of 1 mm to 5 mm / min. Usually, a shear test is performed within this range. On the other hand, in the above (2) high-speed shear test, the test is performed under the condition of “100 mm / min”, which is at least 20 times the normal shear rate. And the lead-free solder alloy which concerns on an Example can exhibit the tolerance with respect to the impact accompanying a high-speed deformation also under such severe conditions.
- the lead-free solder alloy according to this example can exhibit a void suppressing effect in both the “under-electrode region” and the “fillet region” in the solder joint formed by using this, and the copper corrosion It turns out that a crack suppression effect can be demonstrated.
- the electronic circuit mounting board and the electronic control device having the solder joint portion formed by using the lead-free solder alloy according to the present invention can exhibit high reliability even in a severe environment with a severe temperature difference.
- it can be suitably used for a vehicle-mounted electronic mounting substrate and a vehicle-mounted electronic control device.
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Abstract
Provided are: a lead-free solder alloy, which is a means that can achieve both of a cracking propagation prevention effect and resistance to impact associated with high-speed deformation at a solder joint part under an environment where the temperature difference is extreme, and which can be used suitably particularly in an in-vehicle electronic mounted substrate and an in-vehicle electronic control device, the lead-free solder alloy being characterized by containing 2 to 4% by mass inclusive of Ag, 0.3 to 1% by mass inclusive of Cu, 1.5% by mass or more and less than 3% by mass of Bi, and 1% by mass or more and less than 3% by mass of In, with the remainder made up by Sn; a solder paste; an electronic circuit-mounted substrate; and an electronic control device.
Description
本発明は、鉛フリーはんだ合金、ソルダペースト、電子回路実装基板及び電子制御装置に関する。
The present invention relates to a lead-free solder alloy, a solder paste, an electronic circuit mounting board, and an electronic control device.
プリント配線板やモジュール基板といった電子回路基板に形成される導体パターンに電子部品を接合する方法として、はんだ合金を用いたはんだ接合方法がある。以前はこのはんだ合金には鉛が使用されていた。しかし環境負荷の観点からRoHS指令等によって鉛の使用が制限されたため、近年では鉛を含有しない、所謂鉛フリーはんだ合金によるはんだ接合方法が一般的になりつつある。
There is a solder joining method using a solder alloy as a method for joining an electronic component to a conductor pattern formed on an electronic circuit board such as a printed wiring board or a module board. Previously, this solder alloy used lead. However, since the use of lead is restricted by the RoHS directive or the like from the viewpoint of environmental load, a solder joining method using a so-called lead-free solder alloy that does not contain lead is becoming common in recent years.
この鉛フリーはんだ合金としては、例えばSn-Cu系、Sn-Ag-Cu系、Sn-Bi系及びSn-Zn系はんだ合金等がよく知られている。その中でも、テレビ及び携帯電話等の民生用電子機器には、Sn-3Ag-0.5Cuはんだ合金を用いてはんだ接合された(Sn-3Ag-0.5Cuはんだ合金を用いてはんだ接合部が形成された)電子回路実装基板が多く使用されている。
ここで鉛フリーはんだ合金は、鉛含有はんだ合金と比較してはんだ付性が多少劣る。しかしフラックスやはんだ付装置の改良によってこのはんだ付性の問題は克服されているため、民生用電子機器のように比較的穏やかな環境下に置かれるものにおいては、Sn-3Ag-0.5Cuはんだ合金によるはんだ接合でも、電子回路実装基板の一定程度の信頼性を保つことができる。 As this lead-free solder alloy, for example, Sn—Cu, Sn—Ag—Cu, Sn—Bi and Sn—Zn solder alloys are well known. Among them, consumer electronic devices such as televisions and mobile phones are soldered using Sn-3Ag-0.5Cu solder alloy (a solder joint is formed using Sn-3Ag-0.5Cu solder alloy). In many cases, an electronic circuit mounting board is used.
Here, the lead-free solder alloy is somewhat inferior in solderability as compared with the lead-containing solder alloy. However, since the solderability problem has been overcome by improving the flux and soldering apparatus, the Sn-3Ag-0.5Cu solder is used in a device that is placed in a relatively mild environment such as a consumer electronic device. Even with solder bonding using an alloy, a certain degree of reliability of the electronic circuit mounting board can be maintained.
ここで鉛フリーはんだ合金は、鉛含有はんだ合金と比較してはんだ付性が多少劣る。しかしフラックスやはんだ付装置の改良によってこのはんだ付性の問題は克服されているため、民生用電子機器のように比較的穏やかな環境下に置かれるものにおいては、Sn-3Ag-0.5Cuはんだ合金によるはんだ接合でも、電子回路実装基板の一定程度の信頼性を保つことができる。 As this lead-free solder alloy, for example, Sn—Cu, Sn—Ag—Cu, Sn—Bi and Sn—Zn solder alloys are well known. Among them, consumer electronic devices such as televisions and mobile phones are soldered using Sn-3Ag-0.5Cu solder alloy (a solder joint is formed using Sn-3Ag-0.5Cu solder alloy). In many cases, an electronic circuit mounting board is used.
Here, the lead-free solder alloy is somewhat inferior in solderability as compared with the lead-containing solder alloy. However, since the solderability problem has been overcome by improving the flux and soldering apparatus, the Sn-3Ag-0.5Cu solder is used in a device that is placed in a relatively mild environment such as a consumer electronic device. Even with solder bonding using an alloy, a certain degree of reliability of the electronic circuit mounting board can be maintained.
しかし、例えばエンジンルーム内等に実装される電子制御装置及びモーター等に実装(機電一体化)される電子制御装置(所謂、車載用電子制御装置)に用いられる電子回路実装基板、並びにエンジンに直載される電子回路実装基板は、激しい寒暖差(例えば-30℃から115℃、-40℃から125℃)及び振動負荷を受けるような非常に過酷な環境に晒され得る。
そしてこのような寒暖差の非常に激しい環境下では、電子回路実装基板において、実装された電子部品と基板(本明細書において単に「基板」という場合は、導体パターン形成前の板、導体パターンが形成され電子部品と電気的接続が可能な板、及び電子部品が実装された電子回路実装基板のうち電子部品を含まない板部分のいずれかであり、場合に応じて適宜いずれかを指し、この場合は「電子部品が実装された電子回路実装基板のうち電子部品を含まない板部分」を指す。)との線膨張係数の差によるひずみと、はんだ接合部の熱変位による応力とが発生し易く、これらははんだ接合部に大きな負荷を与える。
そして自動車の使用過程ではんだ接合部に繰り返し与えられる負荷は、はんだ接合部の塑性変形を何度も引き起こすため、はんだ接合部の亀裂発生の原因となり得る。 However, for example, an electronic circuit mounting board used for an electronic control device mounted in an engine room or the like, an electronic control device mounted on a motor or the like (mechanical integration) (so-called onboard electronic control device), and an engine directly. The mounted electronic circuit board can be exposed to extremely harsh environments that are subject to severe temperature differences (eg, −30 ° C. to 115 ° C., −40 ° C. to 125 ° C.) and vibration loads.
In such an environment where the temperature difference is extremely severe, in the electronic circuit mounting substrate, the mounted electronic component and the substrate (in the case of simply referred to as “substrate” in this specification, the board before the conductor pattern formation, the conductor pattern is A board that is formed and can be electrically connected to an electronic component, and a board part that does not include an electronic component among electronic circuit mounting boards on which the electronic component is mounted. In this case, the strain due to the difference in linear expansion coefficient from "the board portion of the electronic circuit mounting board on which the electronic component is mounted" that does not include the electronic component) and the stress due to the thermal displacement of the solder joint are generated. These are easy to apply and cause a large load on the solder joint.
And the load repeatedly given to a solder joint part in the use process of a car causes the plastic deformation of a solder joint part many times, and can become a cause of crack generation of a solder joint part.
そしてこのような寒暖差の非常に激しい環境下では、電子回路実装基板において、実装された電子部品と基板(本明細書において単に「基板」という場合は、導体パターン形成前の板、導体パターンが形成され電子部品と電気的接続が可能な板、及び電子部品が実装された電子回路実装基板のうち電子部品を含まない板部分のいずれかであり、場合に応じて適宜いずれかを指し、この場合は「電子部品が実装された電子回路実装基板のうち電子部品を含まない板部分」を指す。)との線膨張係数の差によるひずみと、はんだ接合部の熱変位による応力とが発生し易く、これらははんだ接合部に大きな負荷を与える。
そして自動車の使用過程ではんだ接合部に繰り返し与えられる負荷は、はんだ接合部の塑性変形を何度も引き起こすため、はんだ接合部の亀裂発生の原因となり得る。 However, for example, an electronic circuit mounting board used for an electronic control device mounted in an engine room or the like, an electronic control device mounted on a motor or the like (mechanical integration) (so-called onboard electronic control device), and an engine directly. The mounted electronic circuit board can be exposed to extremely harsh environments that are subject to severe temperature differences (eg, −30 ° C. to 115 ° C., −40 ° C. to 125 ° C.) and vibration loads.
In such an environment where the temperature difference is extremely severe, in the electronic circuit mounting substrate, the mounted electronic component and the substrate (in the case of simply referred to as “substrate” in this specification, the board before the conductor pattern formation, the conductor pattern is A board that is formed and can be electrically connected to an electronic component, and a board part that does not include an electronic component among electronic circuit mounting boards on which the electronic component is mounted. In this case, the strain due to the difference in linear expansion coefficient from "the board portion of the electronic circuit mounting board on which the electronic component is mounted" that does not include the electronic component) and the stress due to the thermal displacement of the solder joint are generated. These are easy to apply and cause a large load on the solder joint.
And the load repeatedly given to a solder joint part in the use process of a car causes the plastic deformation of a solder joint part many times, and can become a cause of crack generation of a solder joint part.
また上述したはんだ接合部に繰り返し与えられる負荷、特に応力ははんだ接合部に発生した亀裂の先端付近に集中するため、はんだ接合部の深部にまで亀裂が横断的に進展し易くなる。このように著しく進展した亀裂は、電子部品と基板上に形成された導体パターンとの電気的接続の切断を引き起こしてしまう。
特に激しい寒暖差に加え電子回路実装基板に振動が負荷される環境下にあっては、上記亀裂及びその進展は更に発生し易いという問題がある。 In addition, since the load, particularly stress, repeatedly applied to the solder joint described above is concentrated near the tip of the crack generated in the solder joint, the crack is easily propagated transversely to the deep part of the solder joint. The crack that has progressed remarkably in this way causes a break in the electrical connection between the electronic component and the conductor pattern formed on the substrate.
In particular, in an environment where vibration is loaded on the electronic circuit mounting substrate in addition to a severe temperature difference, there is a problem that the crack and its progress are more likely to occur.
特に激しい寒暖差に加え電子回路実装基板に振動が負荷される環境下にあっては、上記亀裂及びその進展は更に発生し易いという問題がある。 In addition, since the load, particularly stress, repeatedly applied to the solder joint described above is concentrated near the tip of the crack generated in the solder joint, the crack is easily propagated transversely to the deep part of the solder joint. The crack that has progressed remarkably in this way causes a break in the electrical connection between the electronic component and the conductor pattern formed on the substrate.
In particular, in an environment where vibration is loaded on the electronic circuit mounting substrate in addition to a severe temperature difference, there is a problem that the crack and its progress are more likely to occur.
これまでも、このようなはんだ接合部の亀裂進展を抑制すべく、熱疲労特性や強度の向上を目的としてSn-Ag-Cu系はんだ合金にBi及びInといった元素を添加する方法はいくつか開示されている(特許文献1から特許文献5参照)。
Until now, several methods for adding elements such as Bi and In to Sn—Ag—Cu based solder alloys for the purpose of improving thermal fatigue characteristics and strength in order to suppress such crack growth in solder joints have been disclosed. (See Patent Document 1 to Patent Document 5).
はんだ合金にBiを添加した場合、Biははんだ合金の原子配列の格子に入り込みSnと置換することで原子配列の格子を歪ませる。これによりSnマトリックスが強化されて合金強度が向上するため、はんだ接合部のうちバルク部における亀裂進展抑制効果の一定の向上は見込まれる。
しかしBiの添加により高強度化した鉛フリーはんだ合金は延伸性が悪化し、脆性が強まるというデメリットがある。これはBiの添加により特定の結晶方位でのすべり変形が発生し難くなることが原因と考えられる。従って、このようなはんだ合金により形成されるはんだ接合部においては、例えば落下衝撃といった高速変形を伴う衝撃を加えた場合、Biを添加しないはんだ合金を用いた場合と比較してすべり変形による塑性変形が起こり難く、そのため塑性変形を伴わない脆性破壊が発生し易いという問題がある。 When Bi is added to the solder alloy, Bi enters the lattice of the atomic arrangement of the solder alloy and substitutes Sn to distort the atomic arrangement of the lattice. As a result, the Sn matrix is strengthened and the alloy strength is improved, so that a certain improvement in the crack growth suppressing effect in the bulk portion of the solder joint portion is expected.
However, a lead-free solder alloy that has been strengthened by the addition of Bi has the demerit that extensibility deteriorates and brittleness increases. This is presumably because the addition of Bi makes it difficult for slip deformation in a specific crystal orientation to occur. Accordingly, in a solder joint formed by such a solder alloy, when an impact accompanied by high-speed deformation such as a drop impact is applied, plastic deformation due to slip deformation is compared with a case where a solder alloy not containing Bi is used. Therefore, there is a problem in that brittle fracture without plastic deformation is likely to occur.
しかしBiの添加により高強度化した鉛フリーはんだ合金は延伸性が悪化し、脆性が強まるというデメリットがある。これはBiの添加により特定の結晶方位でのすべり変形が発生し難くなることが原因と考えられる。従って、このようなはんだ合金により形成されるはんだ接合部においては、例えば落下衝撃といった高速変形を伴う衝撃を加えた場合、Biを添加しないはんだ合金を用いた場合と比較してすべり変形による塑性変形が起こり難く、そのため塑性変形を伴わない脆性破壊が発生し易いという問題がある。 When Bi is added to the solder alloy, Bi enters the lattice of the atomic arrangement of the solder alloy and substitutes Sn to distort the atomic arrangement of the lattice. As a result, the Sn matrix is strengthened and the alloy strength is improved, so that a certain improvement in the crack growth suppressing effect in the bulk portion of the solder joint portion is expected.
However, a lead-free solder alloy that has been strengthened by the addition of Bi has the demerit that extensibility deteriorates and brittleness increases. This is presumably because the addition of Bi makes it difficult for slip deformation in a specific crystal orientation to occur. Accordingly, in a solder joint formed by such a solder alloy, when an impact accompanied by high-speed deformation such as a drop impact is applied, plastic deformation due to slip deformation is compared with a case where a solder alloy not containing Bi is used. Therefore, there is a problem in that brittle fracture without plastic deformation is likely to occur.
一方で、上述するように寒暖差の激しい環境下におけるはんだ接合部の亀裂進展抑制は、特に車載用電子制御装置及びこれに用いられる車載用電子回路実装基板において依然として重要な課題の一つとなっている。
しかし、上記脆性破壊を抑制するためにBiの含有量を抑えれば亀裂進展抑制効果は低下し、またその含有量を増やせば脆性破壊は起き易くなる。またBiと併せてInをはんだ合金に添加することによりはんだ合金の強度化を図る場合においても、Inは酸化し易い合金元素であることからその含有量や他の合金元素との組合せ等によってははんだ接合部にボイドが発生し易く、当該ボイドを起因とした亀裂及びその進展を引き起こし易いという問題がある。 On the other hand, as described above, the suppression of crack propagation at the solder joint in an environment with a severe temperature difference is still one of the important issues particularly in the on-vehicle electronic control device and the on-vehicle electronic circuit mounting substrate used therefor. Yes.
However, if the Bi content is suppressed in order to suppress the brittle fracture, the crack growth suppressing effect is lowered, and if the content is increased, the brittle fracture is likely to occur. In addition, when In is added to a solder alloy together with Bi to increase the strength of the solder alloy, since In is an easily oxidizable alloy element, depending on its content or combination with other alloy elements, etc. There is a problem that voids are easily generated in the solder joints, and that cracks caused by the voids and their progress are likely to occur.
しかし、上記脆性破壊を抑制するためにBiの含有量を抑えれば亀裂進展抑制効果は低下し、またその含有量を増やせば脆性破壊は起き易くなる。またBiと併せてInをはんだ合金に添加することによりはんだ合金の強度化を図る場合においても、Inは酸化し易い合金元素であることからその含有量や他の合金元素との組合せ等によってははんだ接合部にボイドが発生し易く、当該ボイドを起因とした亀裂及びその進展を引き起こし易いという問題がある。 On the other hand, as described above, the suppression of crack propagation at the solder joint in an environment with a severe temperature difference is still one of the important issues particularly in the on-vehicle electronic control device and the on-vehicle electronic circuit mounting substrate used therefor. Yes.
However, if the Bi content is suppressed in order to suppress the brittle fracture, the crack growth suppressing effect is lowered, and if the content is increased, the brittle fracture is likely to occur. In addition, when In is added to a solder alloy together with Bi to increase the strength of the solder alloy, since In is an easily oxidizable alloy element, depending on its content or combination with other alloy elements, etc. There is a problem that voids are easily generated in the solder joints, and that cracks caused by the voids and their progress are likely to occur.
このように、寒暖差の激しい環境下におけるはんだ接合部の亀裂進展抑制効果と高速変形を伴う衝撃への耐性を両立し得る鉛フリーはんだ合金の実現が望まれている。
しかしこのような効果の両立については、上記特許文献においては言及も示唆もされていない。 Thus, it is desired to realize a lead-free solder alloy that can achieve both the effect of suppressing the crack growth of a solder joint in an environment with a severe temperature difference and the resistance to impact accompanied by high-speed deformation.
However, there is no mention or suggestion in the above-mentioned patent document about such a balance of effects.
しかしこのような効果の両立については、上記特許文献においては言及も示唆もされていない。 Thus, it is desired to realize a lead-free solder alloy that can achieve both the effect of suppressing the crack growth of a solder joint in an environment with a severe temperature difference and the resistance to impact accompanied by high-speed deformation.
However, there is no mention or suggestion in the above-mentioned patent document about such a balance of effects.
本発明は上記課題を解決するものであり、寒暖差の激しい環境下におけるはんだ接合部の亀裂進展抑制効果及び高速変形を伴う衝撃への耐性を両立し得る鉛フリーはんだ合金、ソルダペースト、電子回路実装基板及び電子制御装置を提供することをその目的とする。
SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems, and provides a lead-free solder alloy, a solder paste, and an electronic circuit that can achieve both crack growth suppression effect of solder joints and resistance to impact accompanied by high-speed deformation in an environment with a severe temperature difference It is an object of the present invention to provide a mounting board and an electronic control device.
(1)本発明に係る鉛フリーはんだ合金は、2質量%以上4質量%以下のAgと、0.3質量%以上1質量%以下のCuと、1.5質量%以上3質量%未満のBiと、1質量%以上3質量%未満のInとを含み、残部がSnからなることをその特徴とする。
(1) The lead-free solder alloy according to the present invention comprises 2% by mass to 4% by mass of Ag, 0.3% by mass to 1% by mass Cu, and 1.5% by mass to less than 3% by mass. It contains Bi and 1% by mass or more and less than 3% by mass of In, with the remainder being made of Sn.
(2)上記(1)に記載の構成において、Biの含有量は2質量%以上3質量%未満であり、Inの含有量が2質量%以上3質量%未満であることをその特徴とする。
(2) In the configuration described in (1) above, the Bi content is 2% by mass or more and less than 3% by mass, and the In content is 2% by mass or more and less than 3% by mass. .
(3)上記(1)に記載の構成において、Biの含有量は2質量%以上2.8質量%以下であり、Inの含有量が2質量%以上2.8質量%以下であることをその特徴とする。
(3) In the configuration described in (1) above, the Bi content is 2% by mass or more and 2.8% by mass or less, and the In content is 2% by mass or more and 2.8% by mass or less. Its features.
(4)上記(1)に記載の構成において、Biの含有量は2.3質量%以上2.8質量%以下であり、Inの含有量が2.3質量%以上2.8質量%以下であることをその特徴とする。
(4) In the configuration described in (1) above, the Bi content is 2.3 mass% or more and 2.8 mass% or less, and the In content is 2.3 mass% or more and 2.8 mass% or less. It is the feature.
(5)上記(1)から(4)のいずれか1に記載の構成において、Agの含有量は2.5質量%以上3.5質量%以下であることをその特徴とする。
(5) In the configuration described in any one of (1) to (4) above, the Ag content is 2.5% by mass or more and 3.5% by mass or less.
(6)上記(1)から(5)のいずれか1に記載の構成において、Cuの含有量は0.4質量%以上0.8質量%以下であることをその特徴とする。
(6) In the configuration according to any one of (1) to (5), the content of Cu is 0.4% by mass or more and 0.8% by mass or less.
(7)本発明に係る鉛フリーはんだ合金は、上記(1)から(6)のいずれか1に記載の構成において、更にNi及びCoの少なくともいずれかを合計で0.001質量%以上0.10質量%以下含むことをその特徴とする。
(7) The lead-free solder alloy according to the present invention, in the configuration described in any one of (1) to (6) above, further includes at least one of Ni and Co in a total of 0.001% by mass or more. It is characterized by containing 10% by mass or less.
(8)本発明に係る鉛フリーはんだ合金は、上記(1)から(7)のいずれか1に記載の構成において、更にFe、Mn、Cr及びMoの少なくともいずれかを合計で0.001質量%以上0.05質量%以下含むことをその特徴とする。
(8) The lead-free solder alloy according to the present invention, in the configuration described in any one of (1) to (7) above, further includes at least one of Fe, Mn, Cr, and Mo in total 0.001 mass. % To 0.05% by mass or less.
(9)本発明に係る鉛フリーはんだ合金は、上記(1)から(8)のいずれか1に記載の構成において、更にP、Ga及びGeの少なくともいずれかを合計で0.001質量%以上0.05質量%以下含むことをその特徴とする。
(9) The lead-free solder alloy according to the present invention is the structure described in any one of (1) to (8) above, and at least one of P, Ga, and Ge is further 0.001% by mass or more in total. It is characterized by containing 0.05 mass% or less.
(10)本発明に係るソルダペーストは、粉末状の鉛フリーはんだ合金であって上記(1)から(9)のいずれか1に記載の鉛フリーはんだ合金と、ベース樹脂と、チキソ剤と、活性剤と、溶剤とを含むフラックスを有することをその特徴とする。
(10) The solder paste according to the present invention is a powdered lead-free solder alloy, the lead-free solder alloy according to any one of (1) to (9), a base resin, a thixotropic agent, It is characterized by having a flux containing an activator and a solvent.
(11)本発明に係る電子回路実装基板は、上記(1)から(9)のいずれか1に記載の鉛フリーはんだ合金を用いて形成されるはんだ接合部を有することをその特徴とする。
(11) An electronic circuit mounting board according to the present invention has a solder joint formed by using the lead-free solder alloy described in any one of (1) to (9).
(12)本発明に係る電子制御装置は、上記(11)に記載の電子回路実装基板を有することをその特徴とする。
(12) An electronic control device according to the present invention includes the electronic circuit mounting board described in (11) above.
本発明の鉛フリーはんだ合金及びソルダペーストは、寒暖差の激しい環境下におけるはんだ接合部の亀裂進展抑制効果及び高速変形を伴う衝撃への耐性を両立することができる。そしてこのようなはんだ接合部を有する電子回路実装基板及び電子制御装置は、寒暖差の激しい過酷な環境下においても高い信頼性を発揮することができ、特に車載用電子回路実装基板及び車載用電子制御装置に好適に用いることができる。
The lead-free solder alloy and solder paste of the present invention can achieve both the effect of suppressing the crack growth of the solder joint and the resistance to impact accompanied by high-speed deformation under an environment where the temperature difference is severe. The electronic circuit mounting board and the electronic control device having such a solder joint portion can exhibit high reliability even in a severe environment with a severe temperature difference, and particularly the in-vehicle electronic circuit mounting board and the in-vehicle electronic It can be suitably used for a control device.
以下、本発明の鉛フリーはんだ合金、ソルダペースト、電子回路実装基板及び電子制御装置の一実施形態を詳述する。なお、本発明が以下の実施形態に限定されるものではないことはもとよりである。
Hereinafter, an embodiment of the lead-free solder alloy, solder paste, electronic circuit mounting board, and electronic control device of the present invention will be described in detail. Of course, the present invention is not limited to the following embodiments.
(1)鉛フリーはんだ合金
本実施形態の鉛フリーはんだ合金には、2質量%以上4質量%以下のAgを含有させることができる。この範囲内で鉛フリーはんだ合金にAgを添加することにより、そのSn粒界中にAg3Sn化合物を析出させ、機械的強度を付与することができると共に、耐熱衝撃性、耐熱疲労特性及び高速変形を伴う衝撃への耐性を発揮させることができる。 (1) Lead-free solder alloy The lead-free solder alloy of this embodiment can contain 2 mass% or more and 4 mass% or less of Ag. By adding Ag to the lead-free solder alloy within this range, it is possible to precipitate the Ag 3 Sn compound in its Sn grain boundary and impart mechanical strength, as well as thermal shock resistance, thermal fatigue characteristics and high speed. It is possible to exhibit resistance to impact accompanied by deformation.
本実施形態の鉛フリーはんだ合金には、2質量%以上4質量%以下のAgを含有させることができる。この範囲内で鉛フリーはんだ合金にAgを添加することにより、そのSn粒界中にAg3Sn化合物を析出させ、機械的強度を付与することができると共に、耐熱衝撃性、耐熱疲労特性及び高速変形を伴う衝撃への耐性を発揮させることができる。 (1) Lead-free solder alloy The lead-free solder alloy of this embodiment can contain 2 mass% or more and 4 mass% or less of Ag. By adding Ag to the lead-free solder alloy within this range, it is possible to precipitate the Ag 3 Sn compound in its Sn grain boundary and impart mechanical strength, as well as thermal shock resistance, thermal fatigue characteristics and high speed. It is possible to exhibit resistance to impact accompanied by deformation.
またAgの含有量を2質量%以上3.8質量%以下とすると、鉛フリーはんだ合金の延伸性を良好にしつつ、機械的強度及び鉛フリーはんだ合金の強度、延性及びコストバランスをより良好にでき、高速変形を伴う衝撃への耐性も向上し得る。特に好ましいAgの含有量は、2.5質量%以上3.5質量%以下である。
Moreover, when the Ag content is 2% by mass or more and 3.8% by mass or less, the mechanical strength and the strength, ductility, and cost balance of the lead-free solder alloy are improved while improving the stretchability of the lead-free solder alloy. It is possible to improve the resistance to impact accompanied by high-speed deformation. The particularly preferable Ag content is 2.5% by mass or more and 3.5% by mass or less.
本実施形態の鉛フリーはんだ合金には、0.3質量%以上1質量%以下のCuを含有させることができる。この範囲内で鉛フリーはんだ合金にCuを添加することにより、基板上の導体パターン(電子回路)のCuランドに対する銅食われ防止効果を発揮すると共にそのSn粒界中にCu6Sn5化合物を析出させ、鉛フリーはんだ合金の耐熱衝撃性を向上し得る。また鉛フリーはんだ合金の延伸性を阻害せず、これを用いて形成されるはんだ接合部の耐熱疲労特性を向上させることができる。
The lead-free solder alloy of this embodiment can contain 0.3 mass% or more and 1 mass% or less of Cu. By adding Cu to the lead-free solder alloy within this range, an effect of preventing copper erosion to the Cu land of the conductor pattern (electronic circuit) on the substrate is exhibited and Cu 6 Sn 5 compound is added to the Sn grain boundary. Precipitation can improve the thermal shock resistance of the lead-free solder alloy. Moreover, the heat-resistant fatigue characteristics of the solder joint part formed using this can be improved without inhibiting the stretchability of the lead-free solder alloy.
より好ましいCuの含有量は0.4質量%以上0.8質量%以下であり、特に好ましいその含有量は0.5質量%以上0.8質量%以下である。Cuの含有量をこの範囲内とすることで、はんだ接合部の亀裂進展抑制効果、高速変形を伴う衝撃に対する耐性、ボイド抑制及び銅食われ抑制効果のバランスをより図ることができる。
More preferable Cu content is 0.4 mass% or more and 0.8 mass% or less, and particularly preferable content is 0.5 mass% or more and 0.8 mass% or less. By making the content of Cu within this range, it is possible to further balance the effect of suppressing the progress of cracks in the solder joint, the resistance to impact accompanied by high-speed deformation, the suppression of voids, and the effect of suppressing copper erosion.
本実施形態の鉛フリーはんだ合金には、Biを含有させることができる。鉛フリーはんだ合金にBiを添加した場合、Snの結晶格子の一部がBiに置換されてその結晶格子に歪みが発生する。そしてこの結晶中の転位に必要なエネルギーが増大することにより、このような鉛フリーはんだ合金を用いて形成するはんだ接合部の金属組織が固溶強化されると共に、ヤング率を高め得る。そのため、当該はんだ接合部が長期間に渡り寒暖差による外部応力を受ける場合であっても、はんだ接合部の変形を抑制し、良好な耐外部応力性を発揮し得る。
The lead-free solder alloy of this embodiment can contain Bi. When Bi is added to a lead-free solder alloy, a part of the Sn crystal lattice is replaced with Bi, and distortion occurs in the crystal lattice. And by increasing the energy required for dislocations in this crystal, the metal structure of the solder joint formed using such a lead-free solder alloy can be strengthened by solid solution and the Young's modulus can be increased. Therefore, even when the solder joint is subjected to external stress due to temperature difference over a long period of time, deformation of the solder joint can be suppressed and good external stress resistance can be exhibited.
そして本実施形態の鉛フリーはんだ合金においては、Biの含有量を1.5質量%以上3質量%未満とすることにより、鉛フリーはんだ合金の機械的強度及び耐熱衝撃性を向上し、はんだ接合部の金属組成の固溶強化を得ることができると共に、良好な延性と高速変形を伴う衝撃への耐性を発揮することができる。
一方、Biの含有量を3質量%以上とすると、これを用いて形成されるはんだ接合部において、高速変形を伴う衝撃による破断が生じ易くなる。 In the lead-free solder alloy of this embodiment, the mechanical strength and thermal shock resistance of the lead-free solder alloy are improved by setting the Bi content to 1.5 mass% or more and less than 3 mass%, and solder joining It is possible to obtain solid solution strengthening of the metal composition of the part, and to exhibit good ductility and resistance to impact accompanied by high-speed deformation.
On the other hand, when the Bi content is 3% by mass or more, a solder joint formed using the Bi is likely to break due to an impact accompanied by high-speed deformation.
一方、Biの含有量を3質量%以上とすると、これを用いて形成されるはんだ接合部において、高速変形を伴う衝撃による破断が生じ易くなる。 In the lead-free solder alloy of this embodiment, the mechanical strength and thermal shock resistance of the lead-free solder alloy are improved by setting the Bi content to 1.5 mass% or more and less than 3 mass%, and solder joining It is possible to obtain solid solution strengthening of the metal composition of the part, and to exhibit good ductility and resistance to impact accompanied by high-speed deformation.
On the other hand, when the Bi content is 3% by mass or more, a solder joint formed using the Bi is likely to break due to an impact accompanied by high-speed deformation.
またBiの含有量を2質量%以上3質量%未満とすると、鉛フリーはんだ合金の強化(亀裂進展抑制効果)と高速変形を伴う衝撃への耐性を向上でき、両者のバランスをより発揮することができる。
Biの更に好ましい含有量は2質量%以上2.8質量%以下であり、特に好ましいその含有量は2.3質量%以上2.8質量%以下である。 Moreover, when the Bi content is 2% by mass or more and less than 3% by mass, the lead-free solder alloy can be strengthened (crack progress suppressing effect) and the resistance to impact with high-speed deformation can be improved, and the balance between the two can be further exhibited. Can do.
The more preferable content of Bi is 2% by mass or more and 2.8% by mass or less, and the particularly preferable content thereof is 2.3% by mass or more and 2.8% by mass or less.
Biの更に好ましい含有量は2質量%以上2.8質量%以下であり、特に好ましいその含有量は2.3質量%以上2.8質量%以下である。 Moreover, when the Bi content is 2% by mass or more and less than 3% by mass, the lead-free solder alloy can be strengthened (crack progress suppressing effect) and the resistance to impact with high-speed deformation can be improved, and the balance between the two can be further exhibited. Can do.
The more preferable content of Bi is 2% by mass or more and 2.8% by mass or less, and the particularly preferable content thereof is 2.3% by mass or more and 2.8% by mass or less.
本実施形態の鉛フリーはんだ合金には、1質量%以上3質量%未満のInを含有させることができる。この範囲内でInを添加することにより、鉛フリーはんだ合金のはんだ組織を多結晶化させて異方性を打ち消すことができる。そのため鉛フリーはんだ合金における特定の結晶方位での脆化現象を抑制でき、これを用いて形成されるはんだ接合部に対して高速変形を伴う衝撃を加えた場合であっても、破断の発生を抑制し得る。
一方、Inの含有量を3質量%以上とすると、特にソルダペースト化した場合においてこれを用いて形成されるはんだ接合部にボイドが発生し易く、亀裂進展抑制効果を妨げる虞がある。 The lead-free solder alloy of this embodiment can contain 1% by mass or more and less than 3% by mass of In. By adding In within this range, the solder structure of the lead-free solder alloy can be polycrystallized to cancel anisotropy. Therefore, the embrittlement phenomenon in a specific crystal orientation in a lead-free solder alloy can be suppressed, and even when an impact accompanied by high-speed deformation is applied to a solder joint formed using this, the occurrence of breakage is prevented. Can be suppressed.
On the other hand, when the In content is 3% by mass or more, voids are likely to be generated in a solder joint portion formed using the solder paste, and the crack growth suppressing effect may be hindered.
一方、Inの含有量を3質量%以上とすると、特にソルダペースト化した場合においてこれを用いて形成されるはんだ接合部にボイドが発生し易く、亀裂進展抑制効果を妨げる虞がある。 The lead-free solder alloy of this embodiment can contain 1% by mass or more and less than 3% by mass of In. By adding In within this range, the solder structure of the lead-free solder alloy can be polycrystallized to cancel anisotropy. Therefore, the embrittlement phenomenon in a specific crystal orientation in a lead-free solder alloy can be suppressed, and even when an impact accompanied by high-speed deformation is applied to a solder joint formed using this, the occurrence of breakage is prevented. Can be suppressed.
On the other hand, when the In content is 3% by mass or more, voids are likely to be generated in a solder joint portion formed using the solder paste, and the crack growth suppressing effect may be hindered.
またInの好ましい含有量は2質量%以上3質量%未満であり、更に好ましい含有量は2質量%以上2.8質量%以下であり、特に好ましいその含有量は2.3質量%以上2.8質量%以下である。
Moreover, the preferable content of In is 2% by mass or more and less than 3% by mass, the more preferable content is 2% by mass or more and 2.8% by mass or less, and the particularly preferable content is 2.3% by mass or more and 2. It is 8 mass% or less.
本実施形態に係る鉛フリーはんだ合金は、Biの含有量とInの含有量、並びに他の合金元素とこれらの含有量のバランスを図ることにより、寒暖差の激しい環境下におけるはんだ接合部の亀裂進展抑制効果と高速変形を伴う衝撃への耐性を両立することができ、またはんだ接合部におけるボイド抑制効果も発揮し得る。
In the lead-free solder alloy according to the present embodiment, the crack of the solder joint portion in an environment with a severe temperature difference is achieved by balancing the contents of Bi and In, and other alloy elements and these contents. It is possible to achieve both the effect of suppressing the progress and the resistance to impact accompanied by high-speed deformation, or the effect of suppressing the void at the soldered joint.
本実施形態の鉛フリーはんだ合金は、2質量%以上3質量%未満のBi及び2質量%以上3質量%未満のInを含有させることが好ましく、2質量%以上2.8質量%以下のBi及び2質量%以上2.8質量%以下のInを含有させることが更に好ましく、2.3質量%以上2.8質量%以下のBi及び2.3質量%以上2.8質量%以下のInを含有させることが特に好ましい。
BiとInの含有量をこの範囲とし、また他の合金元素とこれらの含有量のバランスを図ることにより、寒暖差の激しい環境下におけるはんだ接合部の亀裂進展抑制効果と高速変形を伴う衝撃への耐性を両立すると共に、これらの効果をより向上させることができる。 The lead-free solder alloy of this embodiment preferably contains 2% by mass or more and less than 3% by mass of Bi and 2% by mass or more and less than 3% by mass of In, and preferably 2% by mass or more and less than 3% by mass of Bi. It is more preferable to contain 2% by mass to 2.8% by mass of In, and 2.3% by mass to 2.8% by mass of Bi and 2.3% by mass to 2.8% by mass of In. It is particularly preferable to contain.
By limiting the content of Bi and In to this range and balancing the content of these with other alloy elements, the effect of suppressing crack growth in solder joints in environments with severe temperature differences and impact with high-speed deformation These effects can be improved while at the same time satisfying the above-mentioned resistance.
BiとInの含有量をこの範囲とし、また他の合金元素とこれらの含有量のバランスを図ることにより、寒暖差の激しい環境下におけるはんだ接合部の亀裂進展抑制効果と高速変形を伴う衝撃への耐性を両立すると共に、これらの効果をより向上させることができる。 The lead-free solder alloy of this embodiment preferably contains 2% by mass or more and less than 3% by mass of Bi and 2% by mass or more and less than 3% by mass of In, and preferably 2% by mass or more and less than 3% by mass of Bi. It is more preferable to contain 2% by mass to 2.8% by mass of In, and 2.3% by mass to 2.8% by mass of Bi and 2.3% by mass to 2.8% by mass of In. It is particularly preferable to contain.
By limiting the content of Bi and In to this range and balancing the content of these with other alloy elements, the effect of suppressing crack growth in solder joints in environments with severe temperature differences and impact with high-speed deformation These effects can be improved while at the same time satisfying the above-mentioned resistance.
本実施形態の鉛フリーはんだ合金には、Ni及びCoの少なくともいずれかを合計で0.001質量%以上0.10質量%以下含有させることができる。この範囲内で鉛フリーはんだ合金にNi及びCoの少なくとも一方を添加することにより、ボイドの発生を抑制しつつはんだ接合部の亀裂進展抑制効果を向上させることができる。
The lead-free solder alloy of this embodiment can contain 0.001% by mass or more and 0.10% by mass or less of at least one of Ni and Co. By adding at least one of Ni and Co to the lead-free solder alloy within this range, it is possible to improve the crack growth suppressing effect of the solder joint while suppressing the generation of voids.
更に本実施形態の鉛フリーはんだ合金には、Fe、Mn、Cr及びMoの少なくとも1種を合計で0.001質量%以上0.05質量%以下含有させることができる。この範囲内でFe、Mn、Cr及びMoの少なくとも1種を添加することで、ボイドの発生を抑制しつつはんだ接合部の亀裂進展抑制効果を向上させることができる。
Furthermore, the lead-free solder alloy of this embodiment can contain 0.001% by mass or more and 0.05% by mass or less of at least one of Fe, Mn, Cr, and Mo in total. By adding at least one of Fe, Mn, Cr, and Mo within this range, it is possible to improve the crack growth suppressing effect of the solder joint portion while suppressing the generation of voids.
また本実施形態の鉛フリーはんだ合金には、P、Ga及びGeの少なくとも1種を合計で0.001質量%以上0.05質量%以下含有させることができる。この範囲内でP、Ga及びGeの少なくとも1種を添加することで、ボイドの発生を抑制しつつ鉛フリーはんだ合金の酸化を防止することができる。
Moreover, the lead-free solder alloy of this embodiment can contain 0.001% by mass or more and 0.05% by mass or less of at least one of P, Ga, and Ge in total. By adding at least one of P, Ga and Ge within this range, it is possible to prevent oxidation of the lead-free solder alloy while suppressing the generation of voids.
なお、本実施形態の鉛フリーはんだ合金には、その効果を阻害しない範囲において、他の成分(元素)、例えばCd、Tl、Se、Au、Ti、Si、Al、Mg、Zn等を含有させることができる。また本実施形態の鉛フリーはんだ合金には、当然ながら不可避不純物も含まれるものである。
In addition, the lead-free solder alloy of this embodiment contains other components (elements) such as Cd, Tl, Se, Au, Ti, Si, Al, Mg, Zn, and the like as long as the effect is not hindered. be able to. In addition, the lead-free solder alloy of this embodiment naturally includes unavoidable impurities.
また本実施形態の鉛フリーはんだ合金は、その残部はSnからなることが好ましい。
Moreover, it is preferable that the remainder of the lead-free solder alloy of this embodiment is made of Sn.
本実施形態のはんだ接合部の形成は、例えばフロー方法、はんだボールによる実装、ソルダペーストを用いたリフロー方法等、はんだ接合部を形成できるものであればどのような方法を用いても良い。なおその中でも特にソルダペーストを用いたリフロー方法が好ましく用いられる。
For the formation of the solder joint portion of this embodiment, any method may be used as long as the solder joint portion can be formed, such as a flow method, mounting with a solder ball, and a reflow method using a solder paste. Of these, a reflow method using solder paste is particularly preferred.
(2)ソルダペースト
このようなソルダペーストとしては、例えば粉末状にした前記鉛フリーはんだ合金とフラックスとを混練しペースト状にすることにより作製される。 (2) Solder paste Such a solder paste is produced by, for example, kneading the powdered lead-free solder alloy and flux into a paste.
このようなソルダペーストとしては、例えば粉末状にした前記鉛フリーはんだ合金とフラックスとを混練しペースト状にすることにより作製される。 (2) Solder paste Such a solder paste is produced by, for example, kneading the powdered lead-free solder alloy and flux into a paste.
このようなフラックスとしては、例えばベース樹脂と、チキソ剤と、活性剤と、溶剤とを含むフラックスが用いられる。
As such a flux, for example, a flux containing a base resin, a thixotropic agent, an activator, and a solvent is used.
前記ベース樹脂としては、例えばトール油ロジン、ガムロジン、ウッドロジン等のロジン、水添ロジン、重合ロジン、不均一化ロジン、アクリル酸変性ロジン、マレイン酸変性ロジン等のロジン誘導体を含むロジン系樹脂;アクリル酸、メタクリル酸、アクリル酸の各種エステル、メタクリル酸の各種エステル、クロトン酸、イタコン酸、マレイン酸、無水マレイン酸、マレイン酸のエステル、無水マレイン酸のエステル、アクリロニトリル、メタクリロニトリル、アクリルアミド、メタクリルアミド、塩化ビニル、酢酸ビニル等の少なくとも1種のモノマーを重合してなるアクリル樹脂;エポキシ樹脂;フェノール樹脂等が挙げられる。これらは単独でまたは複数を組合せて用いることができる。
これらの中でもロジン系樹脂、その中でも特に酸変性されたロジンに水素添加をした水添酸変性ロジンが好ましく用いられる。また水添酸変性ロジンとアクリル樹脂の併用も好ましい。 Examples of the base resin include rosin resins including rosin derivatives such as rosin such as tall oil rosin, gum rosin and wood rosin, hydrogenated rosin, polymerized rosin, heterogeneous rosin, acrylic acid modified rosin and maleic acid modified rosin; Acid, methacrylic acid, various esters of acrylic acid, various esters of methacrylic acid, crotonic acid, itaconic acid, maleic acid, maleic anhydride, maleic acid ester, maleic anhydride ester, acrylonitrile, methacrylonitrile, acrylamide, methacrylic acid Examples include acrylic resins obtained by polymerizing at least one monomer such as amide, vinyl chloride, vinyl acetate; epoxy resins; phenol resins. These can be used alone or in combination.
Of these, rosin resins, particularly hydrogenated acid-modified rosin obtained by hydrogenating acid-modified rosin, are preferably used. A combined use of a hydrogenated acid-modified rosin and an acrylic resin is also preferred.
これらの中でもロジン系樹脂、その中でも特に酸変性されたロジンに水素添加をした水添酸変性ロジンが好ましく用いられる。また水添酸変性ロジンとアクリル樹脂の併用も好ましい。 Examples of the base resin include rosin resins including rosin derivatives such as rosin such as tall oil rosin, gum rosin and wood rosin, hydrogenated rosin, polymerized rosin, heterogeneous rosin, acrylic acid modified rosin and maleic acid modified rosin; Acid, methacrylic acid, various esters of acrylic acid, various esters of methacrylic acid, crotonic acid, itaconic acid, maleic acid, maleic anhydride, maleic acid ester, maleic anhydride ester, acrylonitrile, methacrylonitrile, acrylamide, methacrylic acid Examples include acrylic resins obtained by polymerizing at least one monomer such as amide, vinyl chloride, vinyl acetate; epoxy resins; phenol resins. These can be used alone or in combination.
Of these, rosin resins, particularly hydrogenated acid-modified rosin obtained by hydrogenating acid-modified rosin, are preferably used. A combined use of a hydrogenated acid-modified rosin and an acrylic resin is also preferred.
前記ベース樹脂の酸価は10mgKOH/g以上250mgKOH/g以下であることが好ましい。また前記ベース樹脂の配合量はフラックス全量に対して10質量%以上90質量%以下であることが好ましい。
The acid value of the base resin is preferably 10 mgKOH / g or more and 250 mgKOH / g or less. Moreover, it is preferable that the compounding quantity of the said base resin is 10 to 90 mass% with respect to the flux whole quantity.
前記チキソ剤としては、例えば水素添加ヒマシ油、脂肪酸アマイド類、オキシ脂肪酸類が挙げられる。これらは単独でまたは複数を組合せて使用することができる。前記チキソ剤の配合量は、フラックス全量に対して3質量%以上15質量%以下であることが好ましい。
Examples of the thixotropic agent include hydrogenated castor oil, fatty acid amides, and oxy fatty acids. These can be used alone or in combination. The blending amount of the thixotropic agent is preferably 3% by mass or more and 15% by mass or less with respect to the total amount of the flux.
前記活性剤としては、例えば有機アミンのハロゲン化水素塩等のアミン塩(無機酸塩や有機酸塩)、有機酸、有機酸塩、有機アミン塩等を配合することができる。更に具体的には、ジフェニルグアニジン臭化水素酸塩、シクロヘキシルアミン臭化水素酸塩、ジエチルアミン塩、酸塩、コハク酸、アジピン酸、セバシン酸、マロン酸、ドデカン二酸等が挙げられる。これらは単独でまたは複数を組合せて使用することができる。前記活性剤の配合量は、フラックス全量に対して5質量%以上15質量%以下であることが好ましい。
As the activator, for example, an amine salt (inorganic acid salt or organic acid salt) such as an organic amine hydrogen halide salt, an organic acid, an organic acid salt, an organic amine salt, or the like can be blended. More specifically, diphenylguanidine hydrobromide, cyclohexylamine hydrobromide, diethylamine salt, acid salt, succinic acid, adipic acid, sebacic acid, malonic acid, dodecanedioic acid and the like can be mentioned. These can be used alone or in combination. The blending amount of the activator is preferably 5% by mass or more and 15% by mass or less with respect to the total amount of the flux.
前記溶剤としては、例えばイソプロピルアルコール、エタノール、アセトン、トルエン、キシレン、酢酸エチル、エチルセロソルブ、ブチルセロソルブ、グリコールエーテル、ジエチレングリコールモノヘキシルエーテル等を使用することができる。これらは単独でまたは複数を組合せて使用することができる。前記溶剤の配合量は、フラックス全量に対して20質量%以上40質量%以下であることが好ましい。
As the solvent, for example, isopropyl alcohol, ethanol, acetone, toluene, xylene, ethyl acetate, ethyl cellosolve, butyl cellosolve, glycol ether, diethylene glycol monohexyl ether, or the like can be used. These can be used alone or in combination. The amount of the solvent is preferably 20% by mass or more and 40% by mass or less based on the total amount of the flux.
前記フラックスには、鉛フリーはんだ合金の酸化を抑える目的で酸化防止剤を配合することができる。この酸化防止剤としては、例えばヒンダードフェノール系酸化防止剤、フェノール系酸化防止剤、ビスフェノール系酸化防止剤、ポリマー型酸化防止剤等が挙げられる。その中でも特にヒンダードフェノール系酸化防止剤が好ましく用いられる。これらは単独でまたは複数を組合せて使用することができる。前記酸化防止剤の配合量は特に限定されないが、一般的にはフラックス全量に対して0.5質量%以上5質量%程度以下であることが好ましい。
¡An antioxidant may be added to the flux for the purpose of suppressing oxidation of the lead-free solder alloy. Examples of the antioxidant include hindered phenolic antioxidants, phenolic antioxidants, bisphenolic antioxidants, and polymer-type antioxidants. Among these, a hindered phenol antioxidant is particularly preferably used. These can be used alone or in combination. The blending amount of the antioxidant is not particularly limited, but generally it is preferably about 0.5% by mass or more and about 5% by mass or less based on the total amount of the flux.
前記フラックスには、ハロゲン、つや消し剤、消泡剤及び無機フィラー等の添加剤を加えてもよい。
前記添加剤の配合量は、フラックス全量に対して10質量%以下であることが好ましい。またこれらの更に好ましい配合量はフラックス全量に対して5質量%以下である。 Additives such as halogens, matting agents, antifoaming agents and inorganic fillers may be added to the flux.
The blending amount of the additive is preferably 10% by mass or less with respect to the total amount of the flux. Moreover, these more preferable compounding quantities are 5 mass% or less with respect to the flux whole quantity.
前記添加剤の配合量は、フラックス全量に対して10質量%以下であることが好ましい。またこれらの更に好ましい配合量はフラックス全量に対して5質量%以下である。 Additives such as halogens, matting agents, antifoaming agents and inorganic fillers may be added to the flux.
The blending amount of the additive is preferably 10% by mass or less with respect to the total amount of the flux. Moreover, these more preferable compounding quantities are 5 mass% or less with respect to the flux whole quantity.
前記鉛フリーはんだ合金の合金粉末とフラックスとの配合比率は、はんだ合金:フラックスの比率で65:35から95:5であることが好ましい。より好ましい配合比率は85:15から93:7であり、特に好ましい配合比率は87:13から92:8である。
The compounding ratio of the lead-free solder alloy powder and the flux is preferably 65:35 to 95: 5 in the ratio of solder alloy: flux. A more preferred blending ratio is 85:15 to 93: 7, and a particularly preferred blending ratio is 87:13 to 92: 8.
なお前記合金粉末の粒子径は1μm以上40μm以下であることが好ましく、5μm以上35μm以下であることがより好ましく、10μm以上30μm以下であることが特に好ましい。
The particle diameter of the alloy powder is preferably 1 μm or more and 40 μm or less, more preferably 5 μm or more and 35 μm or less, and particularly preferably 10 μm or more and 30 μm or less.
(3)はんだ接合部
本実施形態のはんだ接合部は、例えば前記ソルダペーストを基板上の所定位置に印刷し、これを例えば220℃から250℃の温度でリフローを行うことにより形成される。なお、このリフローにより基板上にははんだ接合部とフラックスを由来としたフラックス残さが形成される。 (3) Solder joint part The solder joint part of this embodiment is formed by, for example, printing the solder paste at a predetermined position on the substrate and performing reflowing at a temperature of, for example, 220 ° C to 250 ° C. This reflow forms a solder residue and a flux residue derived from the flux on the substrate.
本実施形態のはんだ接合部は、例えば前記ソルダペーストを基板上の所定位置に印刷し、これを例えば220℃から250℃の温度でリフローを行うことにより形成される。なお、このリフローにより基板上にははんだ接合部とフラックスを由来としたフラックス残さが形成される。 (3) Solder joint part The solder joint part of this embodiment is formed by, for example, printing the solder paste at a predetermined position on the substrate and performing reflowing at a temperature of, for example, 220 ° C to 250 ° C. This reflow forms a solder residue and a flux residue derived from the flux on the substrate.
(4)電子回路実装基板
またこのようなはんだ接合部を有する電子回路実装基板は、例えば基板上の所定の位置に電極及び絶縁層を形成し、所定のパターンを有するマスクを用いて本実施形態のソルダペーストを印刷し、当該パターンに適合する電子部品を所定の位置に搭載し、これをリフローすることにより作製される。 (4) Electronic circuit mounting board An electronic circuit mounting board having such a solder joint is formed by using, for example, a mask having a predetermined pattern by forming electrodes and insulating layers at predetermined positions on the board. This solder paste is printed, an electronic component conforming to the pattern is mounted at a predetermined position, and this is reflowed.
またこのようなはんだ接合部を有する電子回路実装基板は、例えば基板上の所定の位置に電極及び絶縁層を形成し、所定のパターンを有するマスクを用いて本実施形態のソルダペーストを印刷し、当該パターンに適合する電子部品を所定の位置に搭載し、これをリフローすることにより作製される。 (4) Electronic circuit mounting board An electronic circuit mounting board having such a solder joint is formed by using, for example, a mask having a predetermined pattern by forming electrodes and insulating layers at predetermined positions on the board. This solder paste is printed, an electronic component conforming to the pattern is mounted at a predetermined position, and this is reflowed.
このようにして作製された電子回路実装基板は、前記電極上にはんだ接合部が形成され、当該はんだ接合部は当該電極と電子部品とを電気的に接合する。そして前記基板上には、少なくともはんだ接合部に接着するようにフラックス残さが付着している。
In the electronic circuit mounting board thus manufactured, a solder joint is formed on the electrode, and the solder joint electrically joins the electrode and the electronic component. And on the said board | substrate, the flux residue has adhered so that it may adhere | attach to a solder joint part at least.
そして本実施形態に係るはんだ接合部は、良好な亀裂進展抑制効果を発揮し得ると共に、高速変形を伴う衝撃への耐性も良好である。そのため、このようなはんだ接合部を有する電子回路実装基板は、特に車載用電子回路実装基板といった高い信頼性の求められる電子回路実装基板にも好適に用いることができる。
And the solder joint part concerning this embodiment can exhibit the favorable crack progress inhibitory effect, and also has the tolerance to the impact accompanied by high-speed deformation. Therefore, an electronic circuit mounting board having such a solder joint can be suitably used for an electronic circuit mounting board that is required to have high reliability, such as an in-vehicle electronic circuit mounting board.
(5)電子制御装置
またこのような電子回路実装基板を組み込むことにより、信頼性の高い電子制御装置が作製される。そしてこのような電子制御装置は、特に高い信頼性の求められる車載用電子制御装置に好適に用いることができる。 (5) Electronic control device A highly reliable electronic control device is manufactured by incorporating such an electronic circuit mounting board. And such an electronic control apparatus can be used suitably for the vehicle-mounted electronic control apparatus by which especially high reliability is calculated | required.
またこのような電子回路実装基板を組み込むことにより、信頼性の高い電子制御装置が作製される。そしてこのような電子制御装置は、特に高い信頼性の求められる車載用電子制御装置に好適に用いることができる。 (5) Electronic control device A highly reliable electronic control device is manufactured by incorporating such an electronic circuit mounting board. And such an electronic control apparatus can be used suitably for the vehicle-mounted electronic control apparatus by which especially high reliability is calculated | required.
以下、実施例及び比較例を挙げて本発明を詳述する。なお、本発明はこれらの実施例に限定されるものではない。
Hereinafter, the present invention will be described in detail with reference to Examples and Comparative Examples. The present invention is not limited to these examples.
フラックスの作製
以下の各成分を混練し、実施例及び比較例に係るフラックスを得た。
水添酸変性ロジン(製品名:KE-604、荒川化学工業(株)製) 51質量%
硬化ひまし油 6質量%
ドデカン二酸 10質量%
マロン酸 1質量%
ジフェニルグアニジン臭化水素酸塩 2質量%
ヒンダードフェノール系酸化防止剤(製品名:イルガノックス245、BASFジャパン(株)製) 1質量%
ジエチレングリコールモノヘキシルエーテル 29質量% Production of Flux The following components were kneaded to obtain fluxes according to Examples and Comparative Examples.
Hydrogenated acid-modified rosin (Product name: KE-604, manufactured by Arakawa Chemical Industries, Ltd.) 51% by mass
Hardened castor oil 6% by mass
10% by weight of dodecanedioic acid
Malonic acid 1% by mass
Diphenylguanidine hydrobromide 2% by mass
Hindered phenol antioxidant (Product name: Irganox 245, manufactured by BASF Japan Ltd.) 1% by mass
Diethylene glycol monohexyl ether 29% by mass
以下の各成分を混練し、実施例及び比較例に係るフラックスを得た。
水添酸変性ロジン(製品名:KE-604、荒川化学工業(株)製) 51質量%
硬化ひまし油 6質量%
ドデカン二酸 10質量%
マロン酸 1質量%
ジフェニルグアニジン臭化水素酸塩 2質量%
ヒンダードフェノール系酸化防止剤(製品名:イルガノックス245、BASFジャパン(株)製) 1質量%
ジエチレングリコールモノヘキシルエーテル 29質量% Production of Flux The following components were kneaded to obtain fluxes according to Examples and Comparative Examples.
Hydrogenated acid-modified rosin (Product name: KE-604, manufactured by Arakawa Chemical Industries, Ltd.) 51% by mass
Hardened castor oil 6% by mass
10% by weight of dodecanedioic acid
Malonic acid 1% by mass
Diphenylguanidine hydrobromide 2% by mass
Hindered phenol antioxidant (Product name: Irganox 245, manufactured by BASF Japan Ltd.) 1% by mass
Diethylene glycol monohexyl ether 29% by mass
ソルダペーストの作製
前記フラックス11質量%と、表1及び表2に記載の各鉛フリーはんだ合金の粉末(粉末粒径20μmから38μm)89質量%とを混合し、実施例1から実施例30及び比較例1から比較例18に係る各ソルダペーストを作製した。 Preparation of Solder Paste 11% by mass of the flux and 89% by mass of each lead-free solder alloy powder (powder particle size 20 μm to 38 μm) shown in Tables 1 and 2 were mixed, and Example 1 to Example 30 and Each solder paste according to Comparative Examples 1 to 18 was prepared.
前記フラックス11質量%と、表1及び表2に記載の各鉛フリーはんだ合金の粉末(粉末粒径20μmから38μm)89質量%とを混合し、実施例1から実施例30及び比較例1から比較例18に係る各ソルダペーストを作製した。 Preparation of Solder Paste 11% by mass of the flux and 89% by mass of each lead-free solder alloy powder (powder particle size 20 μm to 38 μm) shown in Tables 1 and 2 were mixed, and Example 1 to Example 30 and Each solder paste according to Comparative Examples 1 to 18 was prepared.
(1)はんだクラック試験
以下の用具を用意した。
・3.2mm×1.6mmのサイズのチップ部品
・上記当該サイズのチップ部品を実装できるパターンを有するソルダレジスト及び前記チップ部品を接続する電極(1.6mm×1.0mm、Cu電極間のギャップ:2.2mm)とを備えたプリント配線板
・上記パターンを有する厚さ150μmのメタルマスク
前記プリント配線板上に前記メタルマスクを用いて各ソルダペーストを印刷し、それぞれ前記チップ部品を10個搭載した。
その後、リフロー炉(製品名:TNP-538EM、(株)タムラ製作所製)を用いて前記各プリント配線板を加熱して、電極と各チップ部品とを電気的に接合するはんだ接合部を有する各電子回路実装基板を作製した。この際のリフロー条件は、プリヒートを170℃から190℃で110秒間、ピーク温度を245℃とし、200℃以上の時間が65秒間、220℃以上の時間が45秒間、ピーク温度から200℃までの冷却速度を3℃から8℃/秒とし、酸素濃度は1,500±500ppmに設定した。
次に、前記各電子回路実装基板を-40℃(5分間)から125℃(5分間)の条件に設定した液槽式冷熱衝撃試験装置(製品名:ETAC WINTECH LT80、楠本化成(株)製)を用い、冷熱衝撃サイクルを3,000サイクル繰り返す環境下に曝した後これを取り出して試験基板とした。
そして、前記各試験基板の対象部分を切り出し、これをエポキシ樹脂(製品名:エポマウント(主剤及び硬化剤)、リファインテック(株)製)を用いて封止した。更に湿式研磨機(製品名:TegraPol-25、丸本ストルアス(株)製)を用いて各試験基板に実装された前記チップ部品の中央断面が分かるような状態とし、200倍に設定した走査電子顕微鏡(製品名:TM-1000、(株)日立ハイテクノロジーズ製)を用いてこれらを観察し、各試験基板の各チップ部品の電極下に形成されたはんだ接合部に発生したクラック率を以下の式に基づき算出した。なおこの「クラック率」とは、想定されるクラック長さに対して実際にどれだけのクラックが生じたかを判断する指標となるものである。
クラック率(%)=(クラックの長さの総和÷想定線クラック全長)×100
なお、各チップ部品の2つの電極下に形成されたはんだ接合部のうち、生じたクラックの長さの大きい方をそのチップ部品のクラック率の算出の対象とした。
「クラックの長さの総和」とは、各試験基板において評価(算出)対象となる各はんだ接合部において発生した複数のクラック長さの合計である。
「想定線クラック全長」とは、各試験基板において評価(算出)対象となる各はんだ接合部におけるクラック予想進展経路(完全破断に至ったクラック)の長さの合計である。
そして各試験基板に搭載した10個のチップ部品のクラック率をそれぞれ算出し、その平均値について以下の基準に基づき評価した。その結果を表3及び表4に表す。
◎:クラック率の平均値が50%以下
○:クラック率の平均値が50%超、70%以下
△:クラック率の平均値が70%超、90%以下
×:クラック率の平均値が90%超、100%以下 (1) Solder crack test The following tools were prepared.
A chip component having a size of 3.2 mm × 1.6 mm A solder resist having a pattern capable of mounting the chip component of the size and an electrode connecting the chip component (1.6 mm × 1.0 mm, gap between Cu electrodes) : 150 mm thick metal mask having the above pattern, each solder paste is printed on the printed wiring board using the metal mask, and each of the 10 chip components is mounted. did.
Thereafter, each of the printed wiring boards is heated using a reflow furnace (product name: TNP-538EM, manufactured by Tamura Corporation), and each of them has a solder joint for electrically joining the electrode and each chip component. An electronic circuit mounting board was produced. The reflow conditions at this time are: preheating from 170 ° C. to 190 ° C. for 110 seconds, peak temperature of 245 ° C., time of 200 ° C. or higher for 65 seconds, time of 220 ° C. or higher for 45 seconds, peak temperature to 200 ° C. The cooling rate was 3 ° C. to 8 ° C./second, and the oxygen concentration was set to 1,500 ± 500 ppm.
Next, a liquid tank type thermal shock test apparatus (product name: ETAC WINTECH LT80, manufactured by Enomoto Kasei Co., Ltd.) in which each electronic circuit mounting substrate is set to a condition of −40 ° C. (5 minutes) to 125 ° C. (5 minutes). ), And was exposed to an environment where the thermal shock cycle was repeated 3,000 cycles.
And the target part of each said test board | substrate was cut out, and this was sealed using the epoxy resin (Product name: Epomount (main agent and hardening | curing agent), refined tech Co., Ltd. product). Further, a scanning electron set to 200 times with a wet polishing machine (product name: TegraPol-25, manufactured by Marumoto Struers Co., Ltd.) in a state in which the center cross section of the chip component mounted on each test substrate can be seen. These were observed using a microscope (product name: TM-1000, manufactured by Hitachi High-Technologies Corporation), and the crack rates generated at the solder joints formed under the electrodes of the chip components of the test substrates were as follows. Calculated based on the formula. The “crack rate” is an index for determining how many cracks actually occur with respect to the assumed crack length.
Crack rate (%) = (total length of cracks / total length of assumed line cracks) x 100
Of the solder joints formed under the two electrodes of each chip component, the one with the longer crack length was used as the target for calculating the crack rate of the chip component.
The “total length of cracks” is the sum of the lengths of a plurality of cracks generated at each solder joint to be evaluated (calculated) on each test substrate.
The “assumed total crack length” is the total length of the expected crack propagation paths (cracks that have reached complete fracture) in each solder joint to be evaluated (calculated) in each test substrate.
And the crack rate of ten chip components mounted in each test board | substrate was calculated, respectively, and the average value was evaluated based on the following references | standards. The results are shown in Tables 3 and 4.
A: Average value of crack rate is 50% or less B: Average value of crack rate is more than 50%, 70% or less Δ: Average value of crack rate is more than 70%, 90% or less ×: Average value of crack rate is 90 Over 100% and below 100%
以下の用具を用意した。
・3.2mm×1.6mmのサイズのチップ部品
・上記当該サイズのチップ部品を実装できるパターンを有するソルダレジスト及び前記チップ部品を接続する電極(1.6mm×1.0mm、Cu電極間のギャップ:2.2mm)とを備えたプリント配線板
・上記パターンを有する厚さ150μmのメタルマスク
前記プリント配線板上に前記メタルマスクを用いて各ソルダペーストを印刷し、それぞれ前記チップ部品を10個搭載した。
その後、リフロー炉(製品名:TNP-538EM、(株)タムラ製作所製)を用いて前記各プリント配線板を加熱して、電極と各チップ部品とを電気的に接合するはんだ接合部を有する各電子回路実装基板を作製した。この際のリフロー条件は、プリヒートを170℃から190℃で110秒間、ピーク温度を245℃とし、200℃以上の時間が65秒間、220℃以上の時間が45秒間、ピーク温度から200℃までの冷却速度を3℃から8℃/秒とし、酸素濃度は1,500±500ppmに設定した。
次に、前記各電子回路実装基板を-40℃(5分間)から125℃(5分間)の条件に設定した液槽式冷熱衝撃試験装置(製品名:ETAC WINTECH LT80、楠本化成(株)製)を用い、冷熱衝撃サイクルを3,000サイクル繰り返す環境下に曝した後これを取り出して試験基板とした。
そして、前記各試験基板の対象部分を切り出し、これをエポキシ樹脂(製品名:エポマウント(主剤及び硬化剤)、リファインテック(株)製)を用いて封止した。更に湿式研磨機(製品名:TegraPol-25、丸本ストルアス(株)製)を用いて各試験基板に実装された前記チップ部品の中央断面が分かるような状態とし、200倍に設定した走査電子顕微鏡(製品名:TM-1000、(株)日立ハイテクノロジーズ製)を用いてこれらを観察し、各試験基板の各チップ部品の電極下に形成されたはんだ接合部に発生したクラック率を以下の式に基づき算出した。なおこの「クラック率」とは、想定されるクラック長さに対して実際にどれだけのクラックが生じたかを判断する指標となるものである。
クラック率(%)=(クラックの長さの総和÷想定線クラック全長)×100
なお、各チップ部品の2つの電極下に形成されたはんだ接合部のうち、生じたクラックの長さの大きい方をそのチップ部品のクラック率の算出の対象とした。
「クラックの長さの総和」とは、各試験基板において評価(算出)対象となる各はんだ接合部において発生した複数のクラック長さの合計である。
「想定線クラック全長」とは、各試験基板において評価(算出)対象となる各はんだ接合部におけるクラック予想進展経路(完全破断に至ったクラック)の長さの合計である。
そして各試験基板に搭載した10個のチップ部品のクラック率をそれぞれ算出し、その平均値について以下の基準に基づき評価した。その結果を表3及び表4に表す。
◎:クラック率の平均値が50%以下
○:クラック率の平均値が50%超、70%以下
△:クラック率の平均値が70%超、90%以下
×:クラック率の平均値が90%超、100%以下 (1) Solder crack test The following tools were prepared.
A chip component having a size of 3.2 mm × 1.6 mm A solder resist having a pattern capable of mounting the chip component of the size and an electrode connecting the chip component (1.6 mm × 1.0 mm, gap between Cu electrodes) : 150 mm thick metal mask having the above pattern, each solder paste is printed on the printed wiring board using the metal mask, and each of the 10 chip components is mounted. did.
Thereafter, each of the printed wiring boards is heated using a reflow furnace (product name: TNP-538EM, manufactured by Tamura Corporation), and each of them has a solder joint for electrically joining the electrode and each chip component. An electronic circuit mounting board was produced. The reflow conditions at this time are: preheating from 170 ° C. to 190 ° C. for 110 seconds, peak temperature of 245 ° C., time of 200 ° C. or higher for 65 seconds, time of 220 ° C. or higher for 45 seconds, peak temperature to 200 ° C. The cooling rate was 3 ° C. to 8 ° C./second, and the oxygen concentration was set to 1,500 ± 500 ppm.
Next, a liquid tank type thermal shock test apparatus (product name: ETAC WINTECH LT80, manufactured by Enomoto Kasei Co., Ltd.) in which each electronic circuit mounting substrate is set to a condition of −40 ° C. (5 minutes) to 125 ° C. (5 minutes). ), And was exposed to an environment where the thermal shock cycle was repeated 3,000 cycles.
And the target part of each said test board | substrate was cut out, and this was sealed using the epoxy resin (Product name: Epomount (main agent and hardening | curing agent), refined tech Co., Ltd. product). Further, a scanning electron set to 200 times with a wet polishing machine (product name: TegraPol-25, manufactured by Marumoto Struers Co., Ltd.) in a state in which the center cross section of the chip component mounted on each test substrate can be seen. These were observed using a microscope (product name: TM-1000, manufactured by Hitachi High-Technologies Corporation), and the crack rates generated at the solder joints formed under the electrodes of the chip components of the test substrates were as follows. Calculated based on the formula. The “crack rate” is an index for determining how many cracks actually occur with respect to the assumed crack length.
Crack rate (%) = (total length of cracks / total length of assumed line cracks) x 100
Of the solder joints formed under the two electrodes of each chip component, the one with the longer crack length was used as the target for calculating the crack rate of the chip component.
The “total length of cracks” is the sum of the lengths of a plurality of cracks generated at each solder joint to be evaluated (calculated) on each test substrate.
The “assumed total crack length” is the total length of the expected crack propagation paths (cracks that have reached complete fracture) in each solder joint to be evaluated (calculated) in each test substrate.
And the crack rate of ten chip components mounted in each test board | substrate was calculated, respectively, and the average value was evaluated based on the following references | standards. The results are shown in Tables 3 and 4.
A: Average value of crack rate is 50% or less B: Average value of crack rate is more than 50%, 70% or less Δ: Average value of crack rate is more than 70%, 90% or less ×: Average value of crack rate is 90 Over 100% and below 100%
(2)高速変形を伴う衝撃に対するシェア強度試験(高速せん断試験)
プリント配線板の電極が1.6mm×0.5mm(Cu電極間のギャップ:2.2mm)であること、及び前記チップ部品を5個搭載する以外は上記(1)はんだクラック試験と同じ条件にて、はんだ接合部を有する各電子回路実装基板を作製した。
そして前記各電子回路実装基板それぞれのチップ部品のシェア強度をオートグラフ(製品名:EZ-L-500N、(株)島津製作所製)を用いて測定した。
なお、当該シェア強度の測定条件はJIS規格C60068-2-21に準拠した。また当該シェア強度の測定に際しては、ジグは端面が平坦で部品寸法と同等以上の幅を持つせん断ジグとし、せん断ジグをチップ部品側面に突き当てて所定のせん断速度で各電子回路実装基板に平行な力を加え、最大試験力を求めてこの値をシェア強度とした。また当該測定におけるせん断高さは部品高さの1/4以下とし、せん断速度は100mm/分とした。
そして測定した各電子回路実装基板のシェア強度についてその平均値(算出したシェア強度の総和÷5(チップ部品数))を算出し、以下の基準に基づき評価した。その結果を表3及び表4に表す。
○:シェア強度の平均値が7.0N以上
△:シェア強度の平均値が6.5N以上7.0N未満
×:シェア強度の平均値が6.5N未満 (2) Shear strength test for impact with high-speed deformation (high-speed shear test)
Except that the printed wiring board electrode is 1.6 mm x 0.5 mm (gap between Cu electrodes: 2.2 mm) and that the five chip components are mounted, the same conditions as in the above (1) solder crack test Thus, each electronic circuit mounting board having a solder joint was produced.
Then, the shear strength of the chip parts of each electronic circuit mounting substrate was measured using an autograph (product name: EZ-L-500N, manufactured by Shimadzu Corporation).
The measurement conditions for the shear strength conformed to JIS standard C60068-2-21. When measuring the shear strength, the jig is a shear jig with a flat end face and a width equal to or greater than the component dimensions. The jig is abutted against the side of the chip part and parallel to each electronic circuit mounting board at a predetermined shear rate. The maximum test force was calculated and this value was taken as the shear strength. In addition, the shear height in the measurement was ¼ or less of the component height, and the shear rate was 100 mm / min.
Then, an average value (total of calculated share strengths ÷ 5 (number of chip components)) was calculated and evaluated based on the following criteria for the measured share strength of each electronic circuit mounting board. The results are shown in Tables 3 and 4.
○: Average value of share strength is 7.0N or more △: Average value of share strength is 6.5N or more and less than 7.0N ×: Average value of share strength is less than 6.5N
プリント配線板の電極が1.6mm×0.5mm(Cu電極間のギャップ:2.2mm)であること、及び前記チップ部品を5個搭載する以外は上記(1)はんだクラック試験と同じ条件にて、はんだ接合部を有する各電子回路実装基板を作製した。
そして前記各電子回路実装基板それぞれのチップ部品のシェア強度をオートグラフ(製品名:EZ-L-500N、(株)島津製作所製)を用いて測定した。
なお、当該シェア強度の測定条件はJIS規格C60068-2-21に準拠した。また当該シェア強度の測定に際しては、ジグは端面が平坦で部品寸法と同等以上の幅を持つせん断ジグとし、せん断ジグをチップ部品側面に突き当てて所定のせん断速度で各電子回路実装基板に平行な力を加え、最大試験力を求めてこの値をシェア強度とした。また当該測定におけるせん断高さは部品高さの1/4以下とし、せん断速度は100mm/分とした。
そして測定した各電子回路実装基板のシェア強度についてその平均値(算出したシェア強度の総和÷5(チップ部品数))を算出し、以下の基準に基づき評価した。その結果を表3及び表4に表す。
○:シェア強度の平均値が7.0N以上
△:シェア強度の平均値が6.5N以上7.0N未満
×:シェア強度の平均値が6.5N未満 (2) Shear strength test for impact with high-speed deformation (high-speed shear test)
Except that the printed wiring board electrode is 1.6 mm x 0.5 mm (gap between Cu electrodes: 2.2 mm) and that the five chip components are mounted, the same conditions as in the above (1) solder crack test Thus, each electronic circuit mounting board having a solder joint was produced.
Then, the shear strength of the chip parts of each electronic circuit mounting substrate was measured using an autograph (product name: EZ-L-500N, manufactured by Shimadzu Corporation).
The measurement conditions for the shear strength conformed to JIS standard C60068-2-21. When measuring the shear strength, the jig is a shear jig with a flat end face and a width equal to or greater than the component dimensions. The jig is abutted against the side of the chip part and parallel to each electronic circuit mounting board at a predetermined shear rate. The maximum test force was calculated and this value was taken as the shear strength. In addition, the shear height in the measurement was ¼ or less of the component height, and the shear rate was 100 mm / min.
Then, an average value (total of calculated share strengths ÷ 5 (number of chip components)) was calculated and evaluated based on the following criteria for the measured share strength of each electronic circuit mounting board. The results are shown in Tables 3 and 4.
○: Average value of share strength is 7.0N or more △: Average value of share strength is 6.5N or more and less than 7.0N ×: Average value of share strength is less than 6.5N
(3)ボイド試験
以下の用具を用意した。
・2.0mm×1.2mmのサイズのチップ部品
・上記当該サイズのチップ部品を実装できるパターンを有するソルダレジスト及び前記チップ部品を接続する電極(1.25mm×1.0mm)とを備えたプリント配線板
・上記パターンを有する厚さ150μmのメタルマスク
前記プリント配線板上に前記メタルマスクを用いて各ソルダペーストを印刷し、それぞれ前記チップ部品を10個搭載した。
その後、リフロー炉(製品名:TNP-538EM、(株)タムラ製作所製)を用いて前記各プリント配線板を加熱して、電極と各チップ部品とを電気的に接合するはんだ接合部を有する各電子回路実装基板(試験基板)を作成した。この際のリフロー条件は、プリヒートを170℃から190℃で110秒間、ピーク温度を245℃とし、200℃以上の時間が65秒間、220℃以上の時間が45秒間、ピーク温度から200℃までの冷却速度を3℃から8℃/秒とし、酸素濃度は1,500±500ppmに設定した。
次いで各試験基板の表面状態をX線透過装置(製品名:SMX-160E、(株)島津製作所製)で観察し、各試験基板の各チップ部品の電極下の領域(図1の破線で囲った領域(a)。以下、「電極下領域」という。)に発生したボイドの総面積がランド面積に占める割合(電極下領域のボイド面積率:電極下領域の総ボイド面積/ランド面積×100)と、フィレットが形成されている領域(図1の破線で囲った領域(b)以下、「フィレット領域」という。)に発生したボイドの総面積がランド面積に占める割合(フィレット領域のボイド面積率:フィレット領域の総ボイド面積/ランド面積×100)をそれぞれ測定及び算出した。
そしてボイド面積率の平均値(算出したボイド面積率の総和÷20(ランドの数))を算出し、以下の基準に基づき評価した。その結果を表3及び表4に表す。
○:ボイド面積率の平均値が3%超5%以下
△:ボイド面積率の平均値が5%超8%以下
×:ボイド面積率の平均値が8%超 (3) Void test The following tools were prepared.
A chip component having a size of 2.0 mm × 1.2 mm. A print including a solder resist having a pattern on which the chip component of the size can be mounted and an electrode (1.25 mm × 1.0 mm) for connecting the chip component. Wiring board A 150 μm thick metal mask having the above pattern Each solder paste was printed on the printed wiring board using the metal mask, and 10 chip components were mounted on each of the solder pastes.
Thereafter, each of the printed wiring boards is heated using a reflow furnace (product name: TNP-538EM, manufactured by Tamura Corporation), and each of them has a solder joint for electrically joining the electrode and each chip component. An electronic circuit mounting board (test board) was prepared. The reflow conditions at this time are: preheating from 170 ° C. to 190 ° C. for 110 seconds, peak temperature of 245 ° C., time of 200 ° C. or higher for 65 seconds, time of 220 ° C. or higher for 45 seconds, peak temperature to 200 ° C. The cooling rate was 3 ° C. to 8 ° C./second, and the oxygen concentration was set to 1,500 ± 500 ppm.
Next, the surface state of each test substrate was observed with an X-ray transmission device (product name: SMX-160E, manufactured by Shimadzu Corporation), and the area under each chip component electrode on each test substrate (enclosed by the broken line in FIG. 1). The ratio of the total area of voids generated in the area (a), hereinafter referred to as “under-electrode area”) to the land area (void area ratio of under-electrode area: total void area of under-electrode area / land area × 100) ) And the ratio of the total area of voids generated in the area where the fillet is formed (area (b) surrounded by the broken line in FIG. 1, hereinafter referred to as “fillet area”) to the land area (void area of the fillet area) Rate: total void area of fillet region / land area × 100) was measured and calculated.
And the average value of the void area ratio (the total of the calculated void area ratios ÷ 20 (number of lands)) was calculated and evaluated based on the following criteria. The results are shown in Tables 3 and 4.
○: Average value of void area ratio is more than 3% and not more than 5% △: Average value of void area ratio is more than 5% and not more than 8% ×: Average value of void area ratio is more than 8%
以下の用具を用意した。
・2.0mm×1.2mmのサイズのチップ部品
・上記当該サイズのチップ部品を実装できるパターンを有するソルダレジスト及び前記チップ部品を接続する電極(1.25mm×1.0mm)とを備えたプリント配線板
・上記パターンを有する厚さ150μmのメタルマスク
前記プリント配線板上に前記メタルマスクを用いて各ソルダペーストを印刷し、それぞれ前記チップ部品を10個搭載した。
その後、リフロー炉(製品名:TNP-538EM、(株)タムラ製作所製)を用いて前記各プリント配線板を加熱して、電極と各チップ部品とを電気的に接合するはんだ接合部を有する各電子回路実装基板(試験基板)を作成した。この際のリフロー条件は、プリヒートを170℃から190℃で110秒間、ピーク温度を245℃とし、200℃以上の時間が65秒間、220℃以上の時間が45秒間、ピーク温度から200℃までの冷却速度を3℃から8℃/秒とし、酸素濃度は1,500±500ppmに設定した。
次いで各試験基板の表面状態をX線透過装置(製品名:SMX-160E、(株)島津製作所製)で観察し、各試験基板の各チップ部品の電極下の領域(図1の破線で囲った領域(a)。以下、「電極下領域」という。)に発生したボイドの総面積がランド面積に占める割合(電極下領域のボイド面積率:電極下領域の総ボイド面積/ランド面積×100)と、フィレットが形成されている領域(図1の破線で囲った領域(b)以下、「フィレット領域」という。)に発生したボイドの総面積がランド面積に占める割合(フィレット領域のボイド面積率:フィレット領域の総ボイド面積/ランド面積×100)をそれぞれ測定及び算出した。
そしてボイド面積率の平均値(算出したボイド面積率の総和÷20(ランドの数))を算出し、以下の基準に基づき評価した。その結果を表3及び表4に表す。
○:ボイド面積率の平均値が3%超5%以下
△:ボイド面積率の平均値が5%超8%以下
×:ボイド面積率の平均値が8%超 (3) Void test The following tools were prepared.
A chip component having a size of 2.0 mm × 1.2 mm. A print including a solder resist having a pattern on which the chip component of the size can be mounted and an electrode (1.25 mm × 1.0 mm) for connecting the chip component. Wiring board A 150 μm thick metal mask having the above pattern Each solder paste was printed on the printed wiring board using the metal mask, and 10 chip components were mounted on each of the solder pastes.
Thereafter, each of the printed wiring boards is heated using a reflow furnace (product name: TNP-538EM, manufactured by Tamura Corporation), and each of them has a solder joint for electrically joining the electrode and each chip component. An electronic circuit mounting board (test board) was prepared. The reflow conditions at this time are: preheating from 170 ° C. to 190 ° C. for 110 seconds, peak temperature of 245 ° C., time of 200 ° C. or higher for 65 seconds, time of 220 ° C. or higher for 45 seconds, peak temperature to 200 ° C. The cooling rate was 3 ° C. to 8 ° C./second, and the oxygen concentration was set to 1,500 ± 500 ppm.
Next, the surface state of each test substrate was observed with an X-ray transmission device (product name: SMX-160E, manufactured by Shimadzu Corporation), and the area under each chip component electrode on each test substrate (enclosed by the broken line in FIG. 1). The ratio of the total area of voids generated in the area (a), hereinafter referred to as “under-electrode area”) to the land area (void area ratio of under-electrode area: total void area of under-electrode area / land area × 100) ) And the ratio of the total area of voids generated in the area where the fillet is formed (area (b) surrounded by the broken line in FIG. 1, hereinafter referred to as “fillet area”) to the land area (void area of the fillet area) Rate: total void area of fillet region / land area × 100) was measured and calculated.
And the average value of the void area ratio (the total of the calculated void area ratios ÷ 20 (number of lands)) was calculated and evaluated based on the following criteria. The results are shown in Tables 3 and 4.
○: Average value of void area ratio is more than 3% and not more than 5% △: Average value of void area ratio is more than 5% and not more than 8% ×: Average value of void area ratio is more than 8%
(4)銅食われ試験
FR-4基板上に厚さ35μmの銅配線を設けた試験用基板を適切な大きさに裁断した。
各試験用基板の銅配線面上にプリフラックスを塗布した後これを60秒間予備加熱し、各試験用基板の温度を約120℃にした。
次いで、実施例及び比較例に係る各鉛フリーはんだ合金を溶融させた噴流はんだ槽の噴流口から2mm上部に予備加熱した各試験用基板を置き、噴流している各溶融はんだ中に3秒間浸漬させた。そしてこの浸漬工程を繰り返し行い、各試験用基板の銅配線のサイズ(面積)が半減するまでの浸漬回数を測定し、以下の基準に基づき評価した。その結果を表3及び表4に表す。
○:浸漬回数4回以上でも銅配線のサイズが半減しない
△:浸漬回数3回で銅配線のサイズが半減した
×:浸漬回数2回以下で銅配線のサイズが半減した (4) Copper erosion test A test substrate provided with a 35 μm thick copper wiring on the FR-4 substrate was cut into an appropriate size.
After applying a preflux on the copper wiring surface of each test substrate, it was preheated for 60 seconds to bring the temperature of each test substrate to about 120 ° C.
Next, each pre-heated test substrate is placed 2 mm above the jet port of the jet solder bath in which the lead-free solder alloys according to the examples and comparative examples are melted, and immersed in each jet of molten solder for 3 seconds. I let you. And this immersion process was repeated, the frequency | count of immersion until the size (area) of the copper wiring of each test board | substrate was halved was measured, and it evaluated based on the following references | standards. The results are shown in Tables 3 and 4.
○: The size of the copper wiring is not halved even when the number of immersions is 4 times or more. Δ: The size of the copper wiring is halved after 3 times of immersion.
FR-4基板上に厚さ35μmの銅配線を設けた試験用基板を適切な大きさに裁断した。
各試験用基板の銅配線面上にプリフラックスを塗布した後これを60秒間予備加熱し、各試験用基板の温度を約120℃にした。
次いで、実施例及び比較例に係る各鉛フリーはんだ合金を溶融させた噴流はんだ槽の噴流口から2mm上部に予備加熱した各試験用基板を置き、噴流している各溶融はんだ中に3秒間浸漬させた。そしてこの浸漬工程を繰り返し行い、各試験用基板の銅配線のサイズ(面積)が半減するまでの浸漬回数を測定し、以下の基準に基づき評価した。その結果を表3及び表4に表す。
○:浸漬回数4回以上でも銅配線のサイズが半減しない
△:浸漬回数3回で銅配線のサイズが半減した
×:浸漬回数2回以下で銅配線のサイズが半減した (4) Copper erosion test A test substrate provided with a 35 μm thick copper wiring on the FR-4 substrate was cut into an appropriate size.
After applying a preflux on the copper wiring surface of each test substrate, it was preheated for 60 seconds to bring the temperature of each test substrate to about 120 ° C.
Next, each pre-heated test substrate is placed 2 mm above the jet port of the jet solder bath in which the lead-free solder alloys according to the examples and comparative examples are melted, and immersed in each jet of molten solder for 3 seconds. I let you. And this immersion process was repeated, the frequency | count of immersion until the size (area) of the copper wiring of each test board | substrate was halved was measured, and it evaluated based on the following references | standards. The results are shown in Tables 3 and 4.
○: The size of the copper wiring is not halved even when the number of immersions is 4 times or more. Δ: The size of the copper wiring is halved after 3 times of immersion.
以上に示す通り、実施例に係る鉛フリーはんだ合金を用いて形成したはんだ接合部は、寒暖差の激しい環境下においても亀裂進展抑制効果を発揮すると共に、高速変形を伴う衝撃への耐性を両立し得ることが分かる。
As shown above, the solder joint formed using the lead-free solder alloy according to the example exhibits an effect of suppressing crack growth even in an environment where the temperature difference is severe, and at the same time has resistance to impact accompanied by high-speed deformation. I can see that
なお上記(1)はんだクラック試験においては、上述の通り「液槽式」の冷熱衝撃試験装置を用いている。この液槽式冷熱衝撃試験装置は、迅速に試験用基板を移し換えできる2つの液槽(上記(1)はんだクラック試験においては-40℃と125℃にそれぞれ設定)に試験用基板を交互に浸漬するものであり、試験用基板に急激な温度変化を与えるものである。これは他の試験条件(例えば「気槽式」)と比較して非常に過酷な試験内容である。
そして実施例に係る鉛フリーはんだ合金は、このような非常に過酷な条件下においても亀裂進展抑制効果を発揮し得るものである。 In the above (1) solder crack test, a “liquid tank type” thermal shock test apparatus is used as described above. This liquid tank-type thermal shock test apparatus alternates test substrates in two liquid tanks (set at -40 ° C and 125 ° C in the above (1) Solder crack test), which can quickly transfer the test substrate. It is immersed and gives a rapid temperature change to the test substrate. This is a very severe test content compared to other test conditions (for example, “air tank type”).
And the lead-free solder alloy which concerns on an Example can exhibit the crack growth inhibitory effect also under such very severe conditions.
そして実施例に係る鉛フリーはんだ合金は、このような非常に過酷な条件下においても亀裂進展抑制効果を発揮し得るものである。 In the above (1) solder crack test, a “liquid tank type” thermal shock test apparatus is used as described above. This liquid tank-type thermal shock test apparatus alternates test substrates in two liquid tanks (set at -40 ° C and 125 ° C in the above (1) Solder crack test), which can quickly transfer the test substrate. It is immersed and gives a rapid temperature change to the test substrate. This is a very severe test content compared to other test conditions (for example, “air tank type”).
And the lead-free solder alloy which concerns on an Example can exhibit the crack growth inhibitory effect also under such very severe conditions.
また上記(2)高速せん断試験のせん断速度について、JIS規格C60068-2-21にはせん断速度の規定はないものの、例えば他の金属のせん断試験の条件(薄板クラッド鋼の引張せん断試験方法及び曲げ試験方法:JIS規格Z2288等)ではせん断(引張)速度を1mmから5mm/分と規定しており、通常はこの範囲内でせん断試験が行われている。一方、上記(2)高速せん断試験では「100mm/分」という、通常のせん断速度の少なくとも20倍の条件で試験を行っており、急激な高速変形を伴う衝撃としては厳しい試験内容である。
そして実施例に係る鉛フリーはんだ合金は、このような厳しい条件下においても、高速変形を伴う衝撃への耐性を発揮し得るものである。 As for the shear rate of the above (2) high-speed shear test, JIS standard C60068-2-21 does not specify the shear rate, but for example, the conditions of the shear test of other metals (the method of tensile shear test and bending of thin clad steel) (Test method: JIS standard Z2288, etc.) specifies a shear (tensile) speed of 1 mm to 5 mm / min. Usually, a shear test is performed within this range. On the other hand, in the above (2) high-speed shear test, the test is performed under the condition of “100 mm / min”, which is at least 20 times the normal shear rate.
And the lead-free solder alloy which concerns on an Example can exhibit the tolerance with respect to the impact accompanying a high-speed deformation also under such severe conditions.
そして実施例に係る鉛フリーはんだ合金は、このような厳しい条件下においても、高速変形を伴う衝撃への耐性を発揮し得るものである。 As for the shear rate of the above (2) high-speed shear test, JIS standard C60068-2-21 does not specify the shear rate, but for example, the conditions of the shear test of other metals (the method of tensile shear test and bending of thin clad steel) (Test method: JIS standard Z2288, etc.) specifies a shear (tensile) speed of 1 mm to 5 mm / min. Usually, a shear test is performed within this range. On the other hand, in the above (2) high-speed shear test, the test is performed under the condition of “100 mm / min”, which is at least 20 times the normal shear rate.
And the lead-free solder alloy which concerns on an Example can exhibit the tolerance with respect to the impact accompanying a high-speed deformation also under such severe conditions.
更には本実施例に係る鉛フリーはんだ合金は、これを用いて形成されるはんだ接合部について、「電極下領域」及び「フィレット領域」の両方におけるボイド抑制効果を発揮し得ること、並びに銅食われ抑制効果を発揮し得ることが分かる。
Furthermore, the lead-free solder alloy according to this example can exhibit a void suppressing effect in both the “under-electrode region” and the “fillet region” in the solder joint formed by using this, and the copper corrosion It turns out that a crack suppression effect can be demonstrated.
そしてBiの含有量が2.3質量%以上2.8質量%以下であり、Inの含有量が2.3質量%以上2.8質量%以下である実施例9から実施例21、その中でも他の合金元素とその含有量のバランスを図った実施例9、10、11、14及び18から20においては、良好な亀裂進展抑制効果、高速変形を伴う衝撃への良好な耐性、良好なボイド抑制及び良好な銅食われ抑制効果を発揮し得ることが分かる。
And the content of Bi is 2.3% by mass or more and 2.8% by mass or less, and the content of In is 2.3% by mass or more and 2.8% by mass or less. In Examples 9, 10, 11, 14, and 18 to 20 in which the balance between the content of other alloy elements and the content thereof was achieved, good crack growth suppressing effect, good resistance to impact with high-speed deformation, good voids It turns out that suppression and the favorable copper erosion suppression effect can be exhibited.
以上から、本発明に係る鉛フリーはんだ合金を用いて形成されるはんだ接合部を有する電子回路実装基板及び電子制御装置は、寒暖差の激しい過酷な環境下においても高い信頼性を発揮することができ、特に車載用電子実装基板及び車載用電子制御装置に好適に用いることができる。
As described above, the electronic circuit mounting board and the electronic control device having the solder joint portion formed by using the lead-free solder alloy according to the present invention can exhibit high reliability even in a severe environment with a severe temperature difference. In particular, it can be suitably used for a vehicle-mounted electronic mounting substrate and a vehicle-mounted electronic control device.
As described above, the electronic circuit mounting board and the electronic control device having the solder joint portion formed by using the lead-free solder alloy according to the present invention can exhibit high reliability even in a severe environment with a severe temperature difference. In particular, it can be suitably used for a vehicle-mounted electronic mounting substrate and a vehicle-mounted electronic control device.
Claims (12)
- 2質量%以上4質量%以下のAgと、0.3質量%以上1質量%以下のCuと、1.5質量%以上3質量%未満のBiと、1質量%以上3質量%未満のInとを含み、残部がSnからなることを特徴とする鉛フリーはんだ合金。 2% by mass or more and 4% by mass or less of Ag, 0.3% by mass or more and 1% by mass or less of Cu, 1.5% by mass or more and less than 3% by mass of Bi, and 1% by mass or more and less than 3% by mass of In A lead-free solder alloy characterized in that the balance is made of Sn.
- Biの含有量が2質量%以上3質量%未満であり、Inの含有量が2質量%以上3質量%未満であることを特徴とする請求項1に記載の鉛フリーはんだ合金。 The lead-free solder alloy according to claim 1, wherein the Bi content is 2% by mass or more and less than 3% by mass, and the In content is 2% by mass or more and less than 3% by mass.
- Biの含有量が2質量%以上2.8質量%以下であり、Inの含有量が2質量%以上2.8質量%以下であることを特徴とする請求項1に記載の鉛フリーはんだ合金。 The lead-free solder alloy according to claim 1, wherein the Bi content is 2% by mass or more and 2.8% by mass or less, and the In content is 2% by mass or more and 2.8% by mass or less. .
- Biの含有量が2.3質量%以上2.8質量%以下であり、Inの含有量が2.3質量%以上2.8質量%以下であることを特徴とする請求項1に記載の鉛フリーはんだ合金。 The Bi content is 2.3% by mass or more and 2.8% by mass or less, and the In content is 2.3% by mass or more and 2.8% by mass or less. Lead-free solder alloy.
- Agの含有量が2.5質量%以上3.5質量%以下であることを特徴とする請求項1から請求項4のいずれか1項に記載の鉛フリーはんだ合金。 The lead-free solder alloy according to any one of claims 1 to 4, wherein an Ag content is 2.5 mass% or more and 3.5 mass% or less.
- Cuの含有量が0.4質量%以上0.8質量%以下であることを特徴とする請求項1から請求項5のいずれか1項に記載の鉛フリーはんだ合金。 The lead-free solder alloy according to any one of claims 1 to 5, wherein a Cu content is 0.4 mass% or more and 0.8 mass% or less.
- 更にNi及びCoの少なくともいずれかを合計で0.001質量%以上0.10質量%以下含むことを特徴とする請求項1から請求項6のいずれか1項に記載の鉛フリーはんだ合金。 The lead-free solder alloy according to any one of claims 1 to 6, further comprising 0.001% by mass or more and 0.10% by mass or less of at least one of Ni and Co.
- 更にFe、Mn、Cr及びMoの少なくともいずれかを合計で0.001質量%以上0.05質量%以下含むことを特徴とする請求項1から請求項7のいずれか1項に記載の鉛フリーはんだ合金。 The lead-free material according to any one of claims 1 to 7, further comprising at least one of Fe, Mn, Cr, and Mo in a total amount of 0.001% by mass to 0.05% by mass. Solder alloy.
- 更にP、Ga及びGeの少なくともいずれかを合計で0.001質量%以上0.05質量%以下含むことを特徴とする請求項1から請求項8のいずれか1項に記載の鉛フリーはんだ合金。 The lead-free solder alloy according to any one of claims 1 to 8, further comprising at least one of P, Ga, and Ge in a total amount of 0.001 mass% to 0.05 mass%. .
- 粉末状の鉛フリーはんだ合金であって請求項1から請求項9のいずれか1項に記載の鉛フリーはんだ合金と、
ベース樹脂と、チキソ剤と、活性剤と、溶剤とを含むフラックスとを有することを特徴とするソルダペースト。 A lead-free solder alloy according to any one of claims 1 to 9, which is a powdered lead-free solder alloy,
A solder paste comprising a flux including a base resin, a thixotropic agent, an activator, and a solvent. - 請求項1から請求項9のいずれか1項に記載の鉛フリーはんだ合金を用いて形成されるはんだ接合部を有することを特徴とする電子回路実装基板。 An electronic circuit mounting board comprising a solder joint formed using the lead-free solder alloy according to any one of claims 1 to 9.
- 請求項11に記載の電子回路実装基板を有することを特徴とする電子制御装置。
An electronic control device comprising the electronic circuit mounting board according to claim 11.
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JP2001168519A (en) * | 1999-12-03 | 2001-06-22 | Hitachi Ltd | Mixed mounting structure, mixed mounting method, and electronic equipment |
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