JP6910198B2 - Ｆｐｇａネットリストを作成する方法 - Google Patents

Ｆｐｇａネットリストを作成する方法 Download PDF

Info

Publication number
JP6910198B2
JP6910198B2 JP2017093906A JP2017093906A JP6910198B2 JP 6910198 B2 JP6910198 B2 JP 6910198B2 JP 2017093906 A JP2017093906 A JP 2017093906A JP 2017093906 A JP2017093906 A JP 2017093906A JP 6910198 B2 JP6910198 B2 JP 6910198B2
Authority
JP
Japan
Prior art keywords
fpga
signal
shadow register
netlist
source code
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2017093906A
Other languages
English (en)
Japanese (ja)
Other versions
JP2017204279A (ja
JP2017204279A5 (enExample
Inventor
カルテ ハイコ
カルテ ハイコ
ルーベライ ドミニク
ルーベライ ドミニク
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dspace Digital Signal Processing and Control Engineering GmbH
Original Assignee
Dspace Digital Signal Processing and Control Engineering GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dspace Digital Signal Processing and Control Engineering GmbH filed Critical Dspace Digital Signal Processing and Control Engineering GmbH
Publication of JP2017204279A publication Critical patent/JP2017204279A/ja
Publication of JP2017204279A5 publication Critical patent/JP2017204279A5/ja
Application granted granted Critical
Publication of JP6910198B2 publication Critical patent/JP6910198B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G06F30/343—Logical level
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/331—Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)
  • Stored Programmes (AREA)
JP2017093906A 2016-05-10 2017-05-10 Ｆｐｇａネットリストを作成する方法 Active JP6910198B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP16168899.9 2016-05-10
EP16168899.9A EP3244326B1 (de) 2016-05-10 2016-05-10 Verfahren zum erstellen einer fpga-netzliste

Publications (3)

Publication Number Publication Date
JP2017204279A JP2017204279A (ja) 2017-11-16
JP2017204279A5 JP2017204279A5 (enExample) 2020-03-26
JP6910198B2 true JP6910198B2 (ja) 2021-07-28

Family

ID=55967104

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2017093906A Active JP6910198B2 (ja) 2016-05-10 2017-05-10 Ｆｐｇａネットリストを作成する方法

Country Status (4)

Country Link
US (1) US10394989B2 (enExample)
EP (1) EP3244326B1 (enExample)
JP (1) JP6910198B2 (enExample)
CN (1) CN107357948B (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10902132B2 (en) 2017-08-25 2021-01-26 Graf Research Corporation Private verification for FPGA bitstreams
EP3647801A1 (de) 2018-10-30 2020-05-06 dSPACE digital signal processing and control engineering GmbH Verfahren zur überprüfung eines fpga-programms
CN109739705A (zh) * 2018-12-29 2019-05-10 西安智多晶微电子有限公司 一种fpga片上实时调试系统及方法
US11216277B2 (en) * 2019-09-26 2022-01-04 Arm Limited Apparatus and method of capturing a register state
DE102021133835A1 (de) * 2021-12-20 2023-06-22 Dspace Gmbh Verfahren und Anordnung zur partiellen Neuprogrammierung einer programmierbaren Gatteranordnung
DE102023100161A1 (de) 2023-01-04 2024-07-04 Dspace Gmbh Überwachungsschaltung für eine programmierbare gatteranordnung, anordnung mit überwachungsschaltung, prozessor und gatteranordnung sowie verfahren zum betrieb einer solchen anordnung

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5764079A (en) * 1996-03-11 1998-06-09 Altera Corporation Sample and load scheme for observability of internal nodes in a PLD
GB2318664B (en) * 1996-10-28 2000-08-23 Altera Corp Embedded logic analyzer for a programmable logic device
DE10196175T1 (de) * 2000-05-11 2003-04-17 Quickturn Design Systems Inc Emulations-Schaltkreis mit einem Haltezeit-Algorithmus, Logikanalysierer und Shadow-Speicher
US7213216B2 (en) * 2002-08-09 2007-05-01 Synplicity, Inc. Method and system for debugging using replicated logic and trigger logic
US8781808B2 (en) * 2005-10-10 2014-07-15 Sei Yang Yang Prediction-based distributed parallel simulation method
CN101933098A (zh) * 2007-09-18 2010-12-29 明导公司 使用线性反馈移位寄存器在存储器内建自测试环境中的故障诊断
US9262303B2 (en) * 2008-12-05 2016-02-16 Altera Corporation Automated semiconductor design flaw detection system
US9576092B2 (en) * 2009-02-24 2017-02-21 Mentor Graphics Corporation Synthesis using multiple synthesis engine configurations
US8972923B2 (en) * 2011-02-08 2015-03-03 Maxeler Technologies Ltd. Method and apparatus and software code for generating a hardware stream processor design
EP2765528B1 (de) 2013-02-11 2018-11-14 dSPACE digital signal processing and control engineering GmbH Wahlfreier Zugriff auf Signalwerte eines FPGA zur Laufzeit
JP6436916B2 (ja) * 2013-02-11 2018-12-12 ディスペース デジタル シグナル プロセッシング アンド コントロール エンジニアリング ゲゼルシャフト ミット ベシュレンクテル ハフツングｄｓｐａｃｅ ｄｉｇｉｔａｌ ｓｉｇｎａｌ ｐｒｏｃｅｓｓｉｎｇ ａｎｄ ｃｏｎｔｒｏｌ ｅｎｇｉｎｅｅｒｉｎｇ ＧｍｂＨ ランタイムにｆｐｇａの信号値を変更するための方法、当該方法を実施するためのデータ処理装置、コンピュータプログラムおよびディジタル記憶媒体

Also Published As

Publication number Publication date
US20170329877A1 (en) 2017-11-16
US10394989B2 (en) 2019-08-27
JP2017204279A (ja) 2017-11-16
EP3244326A1 (de) 2017-11-15
EP3244326B1 (de) 2021-07-07
CN107357948A (zh) 2017-11-17
CN107357948B (zh) 2023-04-07

Similar Documents

Publication Publication Date Title
JP6910198B2 (ja) Ｆｐｇａネットリストを作成する方法
JP6448195B2 (ja) ランタイムにｆｐｇａの信号値にランダムにアクセスするための方法、データ処理装置、コンピュータプログラム、ディジタル記憶媒体及びｆｐｇａビルドの実施方法
US8775986B1 (en) Software debugging of synthesized hardware
US12393756B2 (en) Methods and apparatus for profile-guided optimization of integrated circuits
JP6436916B2 (ja) ランタイムにｆｐｇａの信号値を変更するための方法、当該方法を実施するためのデータ処理装置、コンピュータプログラムおよびディジタル記憶媒体
JP2005092885A (ja) デジタル回路の統計的タイミング解析のためのシステムおよび方法
EP3139291A2 (en) Incremental register retiming of an integrated circuit design
US9929734B2 (en) Method for changing the configuration of a programmable logic module
US20080301598A1 (en) method for checking constraints equivalence of an integrated circuit design
US9047434B2 (en) Clustering for processing of circuit design data
US8504973B1 (en) Systems and methods for generating a test environment and test system surrounding a design of an integrated circuit
US10318687B2 (en) Implementing a constant in FPGA code
US20080300806A1 (en) Power consumption calculating method
US9600613B1 (en) Block-level code coverage in simulation of circuit designs
JP6649731B2 (ja) Ｆｐｇａからリードバックするための信号の特定
US6532584B1 (en) Circuit synthesis method
JP3472067B2 (ja) 設計支援装置
US20240256749A1 (en) Retiming sequential elements having initital states
Gong et al. Modeling dynamically reconfigurable systems for simulation-based functional verification
US11586793B2 (en) Method for producing an association list
US10789401B1 (en) Folding multiply-and-accumulate logic
US20190138310A1 (en) Method for reading out variables from an fpga
JP2012053703A (ja) 最適化ネットリスト作成プログラム、最適化ネットリスト作成装置および最適化ネットリスト作成方法
US20090326901A1 (en) Apparatus and method for estimating change amount in register transfer level structure and computer-readable recording medium
Haar Design Reconstruction for Partial Reconfigurable FPGA Systems

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20200212

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20200212

A871 Explanation of circumstances concerning accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A871

Effective date: 20200212

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20200710

A975 Report on accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A971005

Effective date: 20200728

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20200811

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20201110

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20201126

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20201222

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20210419

C60 Trial request (containing other claim documents, opposition documents)

Free format text: JAPANESE INTERMEDIATE CODE: C60

Effective date: 20210419

A911 Transfer to examiner for re-examination before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20210427

C21 Notice of transfer of a case for reconsideration by examiners before appeal proceedings

Free format text: JAPANESE INTERMEDIATE CODE: C21

Effective date: 20210510

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20210628

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20210706

R150 Certificate of patent or registration of utility model

Ref document number: 6910198

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250