CN107357948B - 用于建立fpga网表的方法 - Google Patents

用于建立fpga网表的方法 Download PDF

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Publication number
CN107357948B
CN107357948B CN201710171544.8A CN201710171544A CN107357948B CN 107357948 B CN107357948 B CN 107357948B CN 201710171544 A CN201710171544 A CN 201710171544A CN 107357948 B CN107357948 B CN 107357948B
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fpga
signal
source code
shadow
shadow register
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CN107357948A (zh
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H·卡尔特
D·卢贝雷
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Desbeth Co ltd
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Desbeth Co ltd
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G06F30/343—Logical level
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/331—Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)
  • Stored Programmes (AREA)
CN201710171544.8A 2016-05-10 2017-03-22 用于建立fpga网表的方法 Active CN107357948B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP16168899.9 2016-05-10
EP16168899.9A EP3244326B1 (de) 2016-05-10 2016-05-10 Verfahren zum erstellen einer fpga-netzliste

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CN107357948A CN107357948A (zh) 2017-11-17
CN107357948B true CN107357948B (zh) 2023-04-07

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US (1) US10394989B2 (enExample)
EP (1) EP3244326B1 (enExample)
JP (1) JP6910198B2 (enExample)
CN (1) CN107357948B (enExample)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10902132B2 (en) * 2017-08-25 2021-01-26 Graf Research Corporation Private verification for FPGA bitstreams
EP3647801A1 (de) 2018-10-30 2020-05-06 dSPACE digital signal processing and control engineering GmbH Verfahren zur überprüfung eines fpga-programms
CN109739705A (zh) * 2018-12-29 2019-05-10 西安智多晶微电子有限公司 一种fpga片上实时调试系统及方法
US11216277B2 (en) * 2019-09-26 2022-01-04 Arm Limited Apparatus and method of capturing a register state
DE102021133835A1 (de) * 2021-12-20 2023-06-22 Dspace Gmbh Verfahren und Anordnung zur partiellen Neuprogrammierung einer programmierbaren Gatteranordnung
DE102023100161A1 (de) 2023-01-04 2024-07-04 Dspace Gmbh Überwachungsschaltung für eine programmierbare gatteranordnung, anordnung mit überwachungsschaltung, prozessor und gatteranordnung sowie verfahren zum betrieb einer solchen anordnung

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CN101933098A (zh) * 2007-09-18 2010-12-29 明导公司 使用线性反馈移位寄存器在存储器内建自测试环境中的故障诊断

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US5764079A (en) * 1996-03-11 1998-06-09 Altera Corporation Sample and load scheme for observability of internal nodes in a PLD
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GB2381910B (en) * 2000-05-11 2005-03-02 Quickturn Design Systems Inc Emulation circuit with a hold time algorithm logic analyzer and shadow memory
US7213216B2 (en) * 2002-08-09 2007-05-01 Synplicity, Inc. Method and system for debugging using replicated logic and trigger logic
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US9262303B2 (en) * 2008-12-05 2016-02-16 Altera Corporation Automated semiconductor design flaw detection system
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EP2765528B1 (de) 2013-02-11 2018-11-14 dSPACE digital signal processing and control engineering GmbH Wahlfreier Zugriff auf Signalwerte eines FPGA zur Laufzeit
WO2014122320A2 (de) * 2013-02-11 2014-08-14 Dspace Digital Signal Processing And Control Engineering Gmbh Verändern eines signalwerts eines fpga zur laufzeit

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Publication number Priority date Publication date Assignee Title
CN101933098A (zh) * 2007-09-18 2010-12-29 明导公司 使用线性反馈移位寄存器在存储器内建自测试环境中的故障诊断

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
Delay-Bounded Routing for Shadow Registers;Eddie Hung，et al;《FPGA "15: Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays》;20150222;Pages 56–65 *
Securing netlist-level FPGA design through exploiting process variation and degradation;Jason Xin Zheng，et al;《FPGA "12: Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays》;20120224;Pages 129–138 *
基于GK803的SoC设计与验证平台实现;匡春雨;《中国优秀硕士学位论文全文数据库 信息科技》;20140815;第1-72页 *

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Publication number Publication date
US20170329877A1 (en) 2017-11-16
US10394989B2 (en) 2019-08-27
JP2017204279A (ja) 2017-11-16
EP3244326B1 (de) 2021-07-07
EP3244326A1 (de) 2017-11-15
JP6910198B2 (ja) 2021-07-28
CN107357948A (zh) 2017-11-17

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