JP6908012B2 - Semiconductor module - Google Patents

Semiconductor module Download PDF

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JP6908012B2
JP6908012B2 JP2018186698A JP2018186698A JP6908012B2 JP 6908012 B2 JP6908012 B2 JP 6908012B2 JP 2018186698 A JP2018186698 A JP 2018186698A JP 2018186698 A JP2018186698 A JP 2018186698A JP 6908012 B2 JP6908012 B2 JP 6908012B2
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overlapping portion
island
semiconductor element
lower arm
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JP2020058126A (en
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鈴木　啓介
鈴木　　啓介
高志 増澤
高志 増澤
浩志 瀧
浩志 瀧
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Denso Corp
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    • H—ELECTRICITY
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    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
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Description

本発明は、一対の半導体素子と、該半導体素子を搭載した積層基板とを有する半導体モジュールに関する。 The present invention relates to a semiconductor module having a pair of semiconductor elements and a laminated substrate on which the semiconductor elements are mounted.

従来から、上アーム半導体素子と下アーム半導体素子との一対の半導体素子と、該半導体素子を搭載した積層基板とを有する半導体モジュールが知られている（図１９参照）。この半導体モジュールは、直流電源に電気接続される。そして、上記半導体素子をスイッチング動作させることにより、直流電源から供給される直流電力を交流電力に変換するよう構成されている。 Conventionally, a semiconductor module having a pair of semiconductor elements of an upper arm semiconductor element and a lower arm semiconductor element and a laminated substrate on which the semiconductor elements are mounted has been known (see FIG. 19). This semiconductor module is electrically connected to a DC power supply. Then, by switching the semiconductor element, the DC power supplied from the DC power supply is converted into AC power.

上記積層基板は、絶縁材料からなる絶縁基板と、該絶縁基板の、半導体素子側の主面に形成された素子側金属層と、反対側の主面に形成された反対側金属層とを備える。上記素子側金属層をエッチングして、複数のアイランドを形成してある。これらのアイランドに半導体素子が搭載される。 The laminated substrate includes an insulating substrate made of an insulating material, an element-side metal layer formed on the main surface of the insulating substrate on the semiconductor element side, and an opposite-side metal layer formed on the opposite main surface. .. A plurality of islands are formed by etching the element-side metal layer. Semiconductor elements are mounted on these islands.

また、上記積層基板では、反対側金属層によって、一つの大型のアイランドを形成してある（図１８参照）。半導体素子をスイッチング動作させると、半導体素子や素子側金属層に、周波数の高い交流電流が流れる。これに伴って、反対側金属層に渦電流が発生する。この渦電流の周囲に発生した磁束によって、上記交流電流の周囲に発生した磁束が相殺されるため、インダクタンスを低減することができる。そのため、半導体素子に大きなサージが加わることを抑制できる。 Further, in the laminated substrate, one large island is formed by the metal layer on the opposite side (see FIG. 18). When the semiconductor element is switched, a high-frequency alternating current flows through the semiconductor element and the metal layer on the element side. Along with this, an eddy current is generated in the metal layer on the opposite side. Since the magnetic flux generated around the eddy current cancels out the magnetic flux generated around the alternating current, the inductance can be reduced. Therefore, it is possible to suppress the application of a large surge to the semiconductor element.

しかしながら、上記半導体モジュールは、積層基板が反りやすいという課題がある。すなわち、上記半導体モジュールでは、反対側金属層によって一つの大型のアイランドを形成してあるため、素子側金属層と反対側金属層との、アイランドの形状が大きく異なる。そのため、温度が上昇したときに、２枚の金属層の、熱膨張によって生じる延び量（以下、熱膨張量とも記す）が大きく異なり、積層基板が反りやすくなる。その結果、半導体素子と素子側金属層との接合部等へ応力が集中し、半導体モジュールの寿命が低下する可能性が考えられる。 However, the above-mentioned semiconductor module has a problem that the laminated substrate is easily warped. That is, in the semiconductor module, since one large island is formed by the metal layer on the opposite side, the shape of the island is significantly different between the metal layer on the element side and the metal layer on the opposite side. Therefore, when the temperature rises, the amount of elongation (hereinafter, also referred to as the amount of thermal expansion) generated by the thermal expansion of the two metal layers is significantly different, and the laminated substrate tends to warp. As a result, stress may be concentrated on the joint between the semiconductor element and the metal layer on the element side, and the life of the semiconductor module may be shortened.

この課題を解決するため、素子側金属層および反対側金属層の、厚さとアイランド形状を等しくすることが検討されている（下記特許文献１参照）。例えば、反対側金属層をエッチングして、素子側金属層と同じパターンにする（図２０参照）。このようにすれば、２枚の金属層の熱膨張量が等しくなり、積層基板の反りを抑制できると考えられる。 In order to solve this problem, it has been studied to make the thickness and the island shape of the element-side metal layer and the opposite-side metal layer equal (see Patent Document 1 below). For example, the metal layer on the opposite side is etched to have the same pattern as the metal layer on the element side (see FIG. 20). By doing so, it is considered that the amount of thermal expansion of the two metal layers becomes equal and the warp of the laminated substrate can be suppressed.

特許第５９２８４８５号公報Japanese Patent No. 5928485

しかしながら、素子側金属層と反対側金属層とを同じパターンにすると、反対側金属層が細かく分割される。上述したように、半導体素子をスイッチング動作したときに、素子側金属層に交流電流が流れ、この交流電流の周囲に発生した磁束を打ち消す渦電流が反対側金属層に誘起されるが、反対側金属層を分割すると、渦電流が流れる経路が制限され（図２０参照）、渦電流が、交流電流の経路に沿って流れにくくなる。したがって、渦電流による磁束の打ち消し効果が低下する。その結果、寄生インダクタンスが大きくなり、半導体素子に加わるサージ電圧が増加する。 However, if the element-side metal layer and the opposite-side metal layer have the same pattern, the opposite-side metal layer is finely divided. As described above, when the semiconductor element is switched, an alternating current flows through the metal layer on the element side, and an eddy current that cancels the magnetic flux generated around the alternating current is induced in the metal layer on the opposite side, but on the opposite side. When the metal layer is divided, the path through which the eddy current flows is restricted (see FIG. 20), and the eddy current becomes difficult to flow along the path of the alternating current. Therefore, the effect of canceling the magnetic flux due to the eddy current is reduced. As a result, the parasitic inductance increases and the surge voltage applied to the semiconductor element increases.

本発明は、かかる課題に鑑みてなされたものであり、積層基板の反りを抑制でき、かつインダクタンスを低減できる半導体モジュールを提供しようとするものである。 The present invention has been made in view of such a problem, and an object of the present invention is to provide a semiconductor module capable of suppressing warpage of a laminated substrate and reducing inductance.

本発明の一態様は、互いに直列に電気接続された、上アーム半導体素子（２U）と下アーム半導体素子（２L）との、少なくとも一対の半導体素子（２）と、
上記上アーム半導体素子に電気接続した正極端子（３P）と、上記下アーム半導体素子に電気接続した負極端子（３N）との、一対の直流端子（３）と、
絶縁材料からなる絶縁基板（４）と、該絶縁基板の上記半導体素子側の主面（Ｓ1）に形成された素子側金属層（５０）と、上記絶縁基板の、上記素子側金属層を設けた側とは反対側の主面（Ｓ2）に形成された反対側金属層（６０）と、を有する積層基板（１０）とを備え、
上記素子側金属層によって複数のアイランド（５）が形成され、該複数のアイランドのうち少なくとも一部の該アイランドは、上記半導体素子が搭載され、該半導体素子を流れる電流の経路をなしており、
上記反対側金属層は、上記絶縁基板の厚さ方向（Ｚ）から見たときに、個々の上記アイランドと重なり合う複数の重複部（６）と、該複数の重複部のうち少なくとも２個の該重複部を連結する連結部（６１）とを備え、
上記半導体素子のスイッチング動作に伴って、交流電流が、上記一対の直流端子の間に、上記一対の半導体素子および上記アイランドを介して流れたとき、渦電流が、上記複数の重複部と上記連結部とを含む経路に流れるよう構成されている、半導体モジュール（１）にある。 One aspect of the present invention comprises at least a pair of semiconductor elements (2), an upper arm semiconductor element (2 U ) and a lower arm semiconductor element (2 L), electrically connected in series with each other.
A pair of DC terminals (3) consisting of a positive electrode terminal (3 P ) electrically connected to the upper arm semiconductor element and a negative electrode terminal (3 N ) electrically connected to the lower arm semiconductor element.
An insulating substrate (4) made of an insulating material, an element-side metal layer (50) formed on the main surface (S 1 ) of the insulating substrate on the semiconductor element side, and an element-side metal layer of the insulating substrate. A laminated substrate (10) having a metal layer (60) on the opposite side formed on a main surface (S 2 ) opposite to the provided side and a laminated substrate (10) having the metal layer (60) on the opposite side is provided.
A plurality of islands (5) are formed by the element-side metal layer, and at least a part of the islands is mounted with the semiconductor element and forms a path of a current flowing through the semiconductor element.
The metal layer on the opposite side has a plurality of overlapping portions (6) that overlap with the individual islands when viewed from the thickness direction (Z) of the insulating substrate, and at least two of the plurality of overlapping portions. It is provided with a connecting portion (61) for connecting the overlapping portions.
When an alternating current flows between the pair of DC terminals through the pair of semiconductor elements and the islands due to the switching operation of the semiconductor elements, the eddy current is connected to the plurality of overlapping portions. It is in the semiconductor module (1), which is configured to flow in a path including a part.

上記半導体モジュールでは、積層基板の上記反対側金属層によって、上記重複部と、上記連結部とを形成してある。そのため、積層基板の反りを抑制しつつ、インダクタンスを低減できる。
すなわち、上記重複部は、上記厚さ方向から見たときに、素子側金属層によって形成されたアイランドと重なり合うよう構成されている。そのため、素子側金属層と反対側金属層のパターンを近似させることができる。したがって、これらの金属層の熱膨張量が略等しくなり、積層基板の反りを抑制できる。 In the semiconductor module, the overlapping portion and the connecting portion are formed by the metal layer on the opposite side of the laminated substrate. Therefore, the inductance can be reduced while suppressing the warp of the laminated substrate.
That is, the overlapping portion is configured to overlap the island formed by the element-side metal layer when viewed from the thickness direction. Therefore, the pattern of the metal layer on the element side and the metal layer on the opposite side can be approximated. Therefore, the amounts of thermal expansion of these metal layers are substantially equal, and the warpage of the laminated substrate can be suppressed.

また、上記半導体モジュールでは、上記連結部を形成してあるため、上記交流電流が流れたときに、渦電流を、連結部を介して、複数の重複部の間に流すことができる。そのため、渦電流の経路が制限されにくくなり、渦電流を、交流電流の経路に沿って流しやすくなる。したがって、交流電流の磁束を、渦電流の磁束によって効果的に打ち消すことができ、インダクタンスを低減することが可能になる。そのため、半導体素子に大きなサージが加わることを抑制できる。 Further, in the semiconductor module, since the connecting portion is formed, when the alternating current flows, the eddy current can flow between the plurality of overlapping portions via the connecting portion. Therefore, the path of the eddy current is less likely to be restricted, and the eddy current can easily flow along the path of the alternating current. Therefore, the magnetic flux of the alternating current can be effectively canceled by the magnetic flux of the eddy current, and the inductance can be reduced. Therefore, it is possible to suppress the application of a large surge to the semiconductor element.

以上のごとく、上記態様によれば、積層基板の反りを抑制でき、インダクタンスを低減できる半導体モジュールを提供することができる。
なお、特許請求の範囲及び課題を解決する手段に記載した括弧内の符号は、後述する実施形態に記載の具体的手段との対応関係を示すものであり、本発明の技術的範囲を限定するものではない。 As described above, according to the above aspect, it is possible to provide a semiconductor module capable of suppressing the warp of the laminated substrate and reducing the inductance.
The reference numerals in parentheses described in the scope of claims and the means for solving the problem indicate the correspondence with the specific means described in the embodiments described later, and limit the technical scope of the present invention. It's not a thing.

実施形態１における、半導体モジュールの斜視図。The perspective view of the semiconductor module in Embodiment 1. 実施形態１における、半導体モジュールの平面図であって、図３のII矢視図。FIG. 2 is a plan view of the semiconductor module according to the first embodiment, and is a view taken along the line II of FIG. 図２のIII-III断面図。FIG. 2 is a sectional view taken along line III-III of FIG. 実施形態１における、ケースを取り除いた半導体モジュールの平面図。The plan view of the semiconductor module which removed the case in Embodiment 1. FIG. 図４の裏面図。Back view of FIG. 実施形態１における、半導体モジュールの回路図。The circuit diagram of the semiconductor module in Embodiment 1. 実施形態２における、半導体モジュールの裏面図。The back view of the semiconductor module in Embodiment 2. 実施形態３における、半導体モジュールの裏面図。The back view of the semiconductor module in Embodiment 3. 実施形態４における、半導体モジュールの裏面図。The back view of the semiconductor module in Embodiment 4. シミュレーション例１における、サンプルＡの平面図。The plan view of the sample A in the simulation example 1. シミュレーション例１における、サンプルＡの裏面図。The back view of the sample A in the simulation example 1. シミュレーション例１における、サンプルＢの裏面図。The back view of the sample B in the simulation example 1. シミュレーション例１における、サンプルＣの裏面図。The back view of the sample C in the simulation example 1. 図１３の要部拡大図。An enlarged view of a main part of FIG. シミュレーション例１における、反り量の計算結果。Calculation result of the amount of warpage in simulation example 1. シミュレーション例１における、インダクタンスの計算結果。Calculation result of inductance in simulation example 1. シミュレーション例１における、半導体モジュールの回路図。The circuit diagram of the semiconductor module in the simulation example 1. 比較形態１における、半導体モジュールの裏面図であって、図１９のXVIII矢視図。It is a back view of the semiconductor module in the comparative form 1, and is the XVIII arrow view of FIG. 比較形態１における、半導体モジュールの断面図。The cross-sectional view of the semiconductor module in the comparative form 1. FIG. 比較形態２における、半導体モジュールの裏面図。The back view of the semiconductor module in the comparative form 2.

（実施形態１）
上記半導体モジュールに係る実施形態について、図１〜図６を参照して説明する。図１〜図３に示すごとく、本形態の半導体モジュール１は、一対の半導体素子２と、一対の直流端子３と、積層基板１０とを備える。半導体素子２には、上アーム側に配された上アーム半導体素子２U（図６参照）と、下アーム側に配された下アーム半導体素子２Lとがある。これら一対の半導体素子２U，２Lは、互いに直列に接続されている。 (Embodiment 1)
An embodiment relating to the semiconductor module will be described with reference to FIGS. 1 to 6. As shown in FIGS. 1 to 3, the semiconductor module 1 of this embodiment includes a pair of semiconductor elements 2, a pair of DC terminals 3, and a laminated substrate 10. The semiconductor element 2 includes an upper arm semiconductor element 2 U (see FIG. 6) arranged on the upper arm side and a lower arm semiconductor element 2 L arranged on the lower arm side. These pair of semiconductor elements 2 U and 2 L are connected in series with each other.

図１、図２に示すごとく、直流端子３には、上アーム半導体素子２Uに電気接続した正極端子３Pと、下アーム半導体素子２Lに電気接続した負極端子３Nとがある。 As shown in FIGS. 1 and 2, the DC terminal 3 includes a positive electrode terminal 3 P electrically connected to the upper arm semiconductor element 2 U and a negative electrode terminal 3 N electrically connected to the lower arm semiconductor element 2 L.

図３に示すごとく、積層基板１０は、絶縁材料からなる絶縁基板４と、素子側金属層５０と、反対側金属層６０とを備える。素子側金属層５０は、絶縁基板４の、半導体素子２側の主面Ｓ1に形成されている。また、反対側金属層６０は、絶縁基板４の、素子側金属層５０を設けた側とは反対側の主面Ｓ2に形成されている。 As shown in FIG. 3, the laminated substrate 10 includes an insulating substrate 4 made of an insulating material, a metal layer 50 on the element side, and a metal layer 60 on the opposite side. Element-side metal layer 50, the insulating substrate 4, is formed on the main surface S 1 of the semiconductor element 2 side. Further, the side opposite the metal layer 60, the insulating substrate 4, is formed on the main surface S 2 on the opposite side to the side provided with the element-side metal layer 50.

図２、図４に示すごとく、素子側金属層５０によって複数のアイランド５が形成されている。複数のアイランド５のうち一部のアイランド５（５U，５L）に、半導体素子２が搭載されている。このアイランド５U，５Lは、半導体素子２に流れる電流の経路をなしている。 As shown in FIGS. 2 and 4, a plurality of islands 5 are formed by the element-side metal layer 50. The semiconductor element 2 is mounted on some of the islands 5 (5 U , 5 L) among the plurality of islands 5. The islands 5 U and 5 L form a path for a current flowing through the semiconductor element 2.

図５に示すごとく、反対側金属層６０は、複数の重複部６と、連結部６１とを備える。重複部６は、絶縁基板４の厚さ方向（Ｚ方向）から見たときに、個々のアイランド５（図４参照）と重なり合う。重複部の周縁部６９は、アイランド５の周縁部５９と一致している。連結部６１は、複数の重複部６を連結している。 As shown in FIG. 5, the opposite metal layer 60 includes a plurality of overlapping portions 6 and a connecting portion 61. The overlapping portion 6 overlaps with the individual islands 5 (see FIG. 4) when viewed from the thickness direction (Z direction) of the insulating substrate 4. The peripheral edge portion 69 of the overlapping portion coincides with the peripheral edge portion 59 of the island 5. The connecting portion 61 connects a plurality of overlapping portions 6.

図２、図４に示すごとく、半導体素子２のスイッチング動作に伴って、交流電流Ｉが、一対の直流端子３の間に、一対の半導体素子２およびアイランド５を介して流れたとき、図５に示すごとく、渦電流ｉが、複数の重複部６と連結部６１とを含む経路に流れるよう構成されている。 As shown in FIGS. 2 and 4, when an alternating current I flows between the pair of DC terminals 3 via the pair of semiconductor elements 2 and the island 5 due to the switching operation of the semiconductor element 2, FIG. 5 As shown in the above, the eddy current i is configured to flow in a path including the plurality of overlapping portions 6 and the connecting portion 61.

本形態の半導体モジュール１は、電気自動車やハイブリッド車等の車両に搭載するための、車載用半導体モジュールである。本形態では、３個の半導体モジュール１を用いて、インバータ回路１９（図１７参照）を構成してある。個々の半導体素子２をスイッチング動作させることにより、直流電源から供給される直流電力を交流電力に変換している。これにより、三相交流モータを駆動し、上記車両を走行させている。 The semiconductor module 1 of this embodiment is an in-vehicle semiconductor module for mounting on a vehicle such as an electric vehicle or a hybrid vehicle. In this embodiment, the inverter circuit 19 (see FIG. 17) is configured by using three semiconductor modules 1. By switching the individual semiconductor elements 2, the DC power supplied from the DC power supply is converted into AC power. As a result, the three-phase AC motor is driven to drive the vehicle.

図１に示すごとく、本形態の半導体モジュール１は、フレーム７を備える。このフレーム７内に、半導体素子２等が配されている。フレーム７の内部には、シリコン樹脂等からなる封止部材１２（図３参照）を充填してある。 As shown in FIG. 1, the semiconductor module 1 of this embodiment includes a frame 7. A semiconductor element 2 and the like are arranged in the frame 7. The inside of the frame 7 is filled with a sealing member 12 (see FIG. 3) made of silicon resin or the like.

また、図１、図２、図４に示すごとく、アイランド５には、上アーム搭載アイランド５Uと、下アーム搭載アイランド５Lと、中継アイランド５Hと、フレームアイランド５Fとがある。上アーム搭載アイランド５Uに上アーム半導体素子２Uを搭載してあり、下アーム搭載アイランド５Lに下アーム半導体素子２Lを搭載してある。本形態では、はんだ層１８（図３参照）を用いて、半導体素子２をアイランド５（５U，５L）に接続してある。 Further, as shown in FIGS. 1, 2 and 4, the island 5 includes an upper arm mounted island 5 U , a lower arm mounted island 5 L , a relay island 5 H, and a frame island 5 F. An upper arm semiconductor element 2 U is mounted on the upper arm mounted island 5 U , and a lower arm semiconductor element 2 L is mounted on the lower arm mounted island 5 L. In this embodiment, the semiconductor element 2 is connected to the island 5 (5 U , 5 L ) by using the solder layer 18 (see FIG. 3).

中継アイランド５Hには、半導体素子２が搭載されていない。中継アイランド５Hは、導電部材８（８B）を介して、下アーム半導体素子２Lに電気接続されている。また、中継アイランド５Hは、ボンディングワイヤ１１を介して、負極端子３Nに電気接続されている。 The semiconductor element 2 is not mounted on the relay island 5 H. The relay island 5 H is electrically connected to the lower arm semiconductor element 2 L via the conductive member 8 (8 B). Further, the relay island 5 H is electrically connected to the negative electrode terminal 3 N via the bonding wire 11.

フレームアイランド５Fは、上アーム搭載アイランド５Uと、下アーム搭載アイランド５Lと、中継アイランド５Hとを取り囲んでいる。フレームアイランド５Fは、Ｚ方向から見たときに、フレーム７と重なる。フレームアイランド５Fは、フレーム７を積層基板１０に接着するために形成されている。 The frame island 5 F surrounds the upper arm mounted island 5 U , the lower arm mounted island 5 L, and the relay island 5 H. The frame island 5 F overlaps with the frame 7 when viewed from the Z direction. The frame island 5 F is formed to bond the frame 7 to the laminated substrate 10.

図１、図２に示すごとく、本形態の半導体モジュール１は、上記直流端子３P，３Nの他に、交流電力を出力する交流端子３９を備える。直流端子３及び交流端子３９は、ボンディングワイヤ１１を介して、半導体素子２に電気接続されている。 As shown in FIGS. 1 and 2, the semiconductor module 1 of this embodiment includes an AC terminal 39 that outputs AC power in addition to the DC terminals 3 P and 3 N. The DC terminal 3 and the AC terminal 39 are electrically connected to the semiconductor element 2 via the bonding wire 11.

また、フレーム７内には、上記導電部材８（８A，８B）が配されている。第１導電部材８Aは、上アーム半導体素子２U（ＭＯＳＦＥＴ）のソース電極と、下アーム搭載アイランド５Lとを電気接続している。また、第２導電部材８Bは、下アーム半導体素子２Lのソース電極と中継アイランド５Hとを電気接続している。 Further, the conductive members 8 (8 A , 8 B ) are arranged in the frame 7. The first conductive member 8 A electrically connects the source electrode of the upper arm semiconductor element 2 U (MOSFET) and the lower arm mounting island 5 L. Further, the second conductive member 8 B electrically connects the source electrode of the lower arm semiconductor element 2 L and the relay island 5 H.

正極端子３Pは、ボンディングワイヤ１１を介して、上アーム搭載アイランド５Uに電気接続している。また、負極端子３Nは、ボンディングワイヤ１１を介して、中継アイランド５Hに電気接続している。本形態では、負極端子３Nを下アーム半導体素子２Lに直接、接続せず、中継アイランド５Hを介して、下アーム半導体素子２Lに電気接続している。これにより、下アーム半導体素子２Lから発生した熱が、負極端子３Nに直接、伝わらないようにしている。 The positive electrode terminal 3 P is electrically connected to the upper arm mounting island 5 U via the bonding wire 11. Further, the negative electrode terminal 3 N is electrically connected to the relay island 5 H via the bonding wire 11. In this embodiment, direct negative terminal 3 N to the lower arm semiconductor element 2 L, not connected, via the relay Island 5 H, is electrically connected to the lower arm semiconductor element 2 L. As a result, the heat generated from the lower arm semiconductor element 2 L is prevented from being directly transferred to the negative electrode terminal 3 N.

半導体素子２をスイッチング動作させると、半導体素子２やアイランド５U，５Lにオン電流が流れる。このオン電流に、周波数が例えば数ｋＨｚ以上の上記交流電流Ｉが、ノイズ成分として重畳する。交流電流Ｉは、２つの直流端子３P，３Nの間を、半導体素子２、導電部材８、アイランド５（５U，５L，５H）等を通って流れる。 When the semiconductor element 2 is switched, an on-current flows through the semiconductor element 2 and the islands 5 U and 5 L. The alternating current I having a frequency of, for example, several kHz or higher is superimposed on this on-current as a noise component. The alternating current I flows between the two direct current terminals 3 P and 3 N through the semiconductor element 2, the conductive member 8, the island 5 (5 U , 5 L , 5 H ) and the like.

交流電流Ｉは、インダクタンスが最小になる経路を流れやすい。図４に示す電流経路は、交流電流Ｉ同士が接近しており、磁界が互いに打ち消されるため、インダクタンスが小さい。したがって、交流電流Ｉは、図４に示す経路を流れやすい。 The alternating current I tends to flow in the path where the inductance is minimized. In the current path shown in FIG. 4, the alternating currents I are close to each other and the magnetic fields cancel each other out, so that the inductance is small. Therefore, the alternating current I tends to flow in the path shown in FIG.

上述したように本形態では、図５に示すごとく、直流端子３P，３N間に交流電流Ｉが流れたとき、複数の重複部６間に、連結部６１を介して渦電流ｉが流れるようにしている。この渦電流ｉの周囲に発生した磁束によって、交流電流Ｉの周囲に発生した磁束を打ち消すことができる。そのため、一対の直流端子３P，３N間のインダクタンスを低減でき、半導体素子２に高いサージが加わることを抑制できる。 As described above, in the present embodiment, as shown in FIG. 5, when an alternating current I flows between the DC terminals 3 P and 3 N , an eddy current i flows between the plurality of overlapping portions 6 via the connecting portion 61. I am trying to do it. The magnetic flux generated around the eddy current i can cancel the magnetic flux generated around the alternating current I. Therefore, the inductance between the pair of DC terminals 3 P and 3 N can be reduced, and it is possible to suppress the application of a high surge to the semiconductor element 2.

図５に示すごとく、重複部６には、上アーム重複部６Uと、下アーム重複部６Lと、中継重複部６Hと、フレーム重複部６Fとがある。上アーム重複部６Uは、Ｚ方向から見たときに、上アーム搭載アイランド５U（図４参照）と重なる位置に形成されている。同様に、下アーム重複部６Lは、下アーム搭載アイランド５Lと重なり、中継重複部６Hは、中継アイランド５Hと重なる位置に形成されている。また、フレーム重複部６Fは、フレームアイランド５Fと重なる位置に形成されている。 As shown in FIG. 5, the overlapping portion 6 includes an upper arm overlapping portion 6 U , a lower arm overlapping portion 6 L , a relay overlapping portion 6 H, and a frame overlapping portion 6 F. The upper arm overlapping portion 6 U is formed at a position overlapping the upper arm mounting island 5 U (see FIG. 4) when viewed from the Z direction. Similarly, the lower arm overlapping portion 6 L overlaps with the lower arm mounting island 5 L, and the relay overlapping portion 6 H is formed at a position overlapping with the relay island 5 H. Further, the frame overlapping portion 6 F is formed at a position overlapping the frame island 5 F.

図５に示すごとく、本形態では、４個の連結部６１を形成してある。第１連結部６１Aは、上アーム重複部６Uと下アーム重複部６Lとを連結している。第２連結部６１Bは、下アーム重複部６Lと中継重複部６Hとを連結している。第３連結部６１Cは、中継重複部６Hとフレーム重複部６Fとを連結している。また、第４連結部６１Dは、フレーム重複部６Fと上アーム重複部６Uとを連結している。これらの連結部６１A〜６１Dは、Ｚ方向から見たときに、交流電流Ｉの経路から外れた位置に形成されている。 As shown in FIG. 5, in this embodiment, four connecting portions 61 are formed. The first connecting portion 61 A connects the upper arm overlapping portion 6 U and the lower arm overlapping portion 6 L. The second connecting portion 61 B connects the lower arm overlapping portion 6 L and the relay overlapping portion 6 H. The third connecting portion 61 C connects the relay overlapping portion 6 H and the frame overlapping portion 6 F. Further, the fourth connecting portion 61 D connects the frame overlapping portion 6 F and the upper arm overlapping portion 6 U. These connecting portions 61 A to 61 D are formed at positions deviated from the path of the alternating current I when viewed from the Z direction.

反対側金属層６０は、図示しない冷却器に接触している。半導体素子２をスイッチング動作させると発熱するため、この冷却器を用いて、半導体素子２を冷却している。また、冷却器と反対側金属層６０との間には、ヒートシンクが介在していない。ヒートシンクを設けると、ヒートシンクの熱抵抗によって熱が冷却器に伝わりにくくなる。そのため本形態では、ヒートシンクを設けず、反対側金属層６０を冷却器に直接、接触させている。なお、反対側金属層６０を直接、冷却水に接触させても良い。 The opposite metal layer 60 is in contact with a cooler (not shown). Since heat is generated when the semiconductor element 2 is switched, the semiconductor element 2 is cooled by using this cooler. Further, no heat sink is interposed between the cooler and the metal layer 60 on the opposite side. When a heat sink is provided, heat is less likely to be transferred to the cooler due to the thermal resistance of the heat sink. Therefore, in this embodiment, the heat sink is not provided, and the metal layer 60 on the opposite side is in direct contact with the cooler. The metal layer 60 on the opposite side may be brought into direct contact with the cooling water.

本形態の作用効果について説明する。図５に示すごとく、本形態では、反対側金属層６０によって、重複部６と連結部６１とを形成してある。そのため、積層基板１０の反りを抑制しつつ、インダクタンスを低減できる。
すなわち、重複部６は、Ｚ方向から見たときに、素子側金属層５０によって形成されたアイランド５と重なり合うよう構成されている。そのため、素子側金属層５０と反対側金属層６０のパターンを近似させることができる。したがって、これらの金属層５０，６０の熱膨張量が略等しくなり、積層基板１０の反りを抑制できる。 The action and effect of this embodiment will be described. As shown in FIG. 5, in this embodiment, the overlapping portion 6 and the connecting portion 61 are formed by the metal layer 60 on the opposite side. Therefore, the inductance can be reduced while suppressing the warp of the laminated substrate 10.
That is, the overlapping portion 6 is configured to overlap the island 5 formed by the element-side metal layer 50 when viewed from the Z direction. Therefore, the patterns of the element-side metal layer 50 and the opposite-side metal layer 60 can be approximated. Therefore, the amounts of thermal expansion of these metal layers 50 and 60 are substantially equal, and the warpage of the laminated substrate 10 can be suppressed.

また、本形態では、連結部６１を形成してあるため、上記交流電流Ｉが流れたときに、渦電流ｉを、連結部６１を介して、複数の重複部６の間に流すことができる。そのため、渦電流ｉの経路が制限されにくくなり、渦電流ｉを、交流電流Ｉの経路に沿って流しやすくなる。したがって、交流電流Ｉの磁束を、渦電流ｉの磁束によって効果的に打ち消すことができ、インダクタンスを低減することが可能になる。そのため、半導体素子２に大きなサージが加わることを抑制できる。 Further, in the present embodiment, since the connecting portion 61 is formed, when the alternating current I flows, the eddy current i can flow between the plurality of overlapping portions 6 via the connecting portion 61. .. Therefore, the path of the eddy current i is less likely to be restricted, and the eddy current i can easily flow along the path of the alternating current I. Therefore, the magnetic flux of the alternating current I can be effectively canceled by the magnetic flux of the eddy current i, and the inductance can be reduced. Therefore, it is possible to suppress the application of a large surge to the semiconductor element 2.

従来の半導体モジュール１は、図１８、図１９に示すごとく、反対側金属層６０によって１つの大型のアイランドを形成していた。そのため、素子側金属層５０と反対側金属層６０の面積差が大きく、熱膨張量の差が大きかった。したがって、半導体素子２が発熱して温度が上昇したときに、積層基板１０が反りやすかった。 In the conventional semiconductor module 1, as shown in FIGS. 18 and 19, one large island is formed by the metal layer 60 on the opposite side. Therefore, the area difference between the element-side metal layer 50 and the opposite-side metal layer 60 was large, and the difference in the amount of thermal expansion was large. Therefore, when the semiconductor element 2 generates heat and the temperature rises, the laminated substrate 10 tends to warp.

この問題を解決するため、図２０に示すごとく、反対側金属層６０を素子側金属層５０と同じパターンにすると、熱膨張量の差を低減でき、積層基板１０の反りを抑制できるものの、個々の重複部６が分断されてしまうため、渦電流ｉの経路が制限され、渦電流ｉが、交流電流Ｉに沿って流れにくくなる。そのため、磁束の打ち消し効果が低減し、インダクタンスが大きくなりやすい。 In order to solve this problem, if the metal layer 60 on the opposite side has the same pattern as the metal layer 50 on the element side as shown in FIG. 20, the difference in the amount of thermal expansion can be reduced and the warpage of the laminated substrate 10 can be suppressed. Since the overlapping portion 6 of the above is divided, the path of the eddy current i is restricted, and the eddy current i becomes difficult to flow along the alternating current I. Therefore, the effect of canceling the magnetic flux is reduced, and the inductance tends to increase.

これに対して、図５に示すごとく、本形態のように、重複部６と連結部６１とを形成すれば、素子側金属層５０と反対側金属層６０との、熱膨張量の差を低減でき、積層基板１０の反りを低減できると共に、渦電流ｉが、連結部６１を介して複数の重複部６間に流れるため、渦電流ｉの経路が制限されにくい。そのため、渦電流ｉが、交流電流Ｉの経路に沿って流れやすくなり、交流電流Ｉの磁束を、渦電流ｉの磁束によって効果的に打ち消すことができる。そのため、インダクタンスを低減でき、半導体素子２に大きなサージが加わることを抑制できる。 On the other hand, as shown in FIG. 5, if the overlapping portion 6 and the connecting portion 61 are formed as in the present embodiment, the difference in the amount of thermal expansion between the element side metal layer 50 and the opposite side metal layer 60 can be obtained. The warpage of the laminated substrate 10 can be reduced, and the eddy current i flows between the plurality of overlapping portions 6 via the connecting portion 61, so that the path of the eddy current i is not easily restricted. Therefore, the eddy current i tends to flow along the path of the alternating current I, and the magnetic flux of the alternating current I can be effectively canceled by the magnetic flux of the eddy current i. Therefore, the inductance can be reduced, and it is possible to suppress the application of a large surge to the semiconductor element 2.

また、本形態の半導体モジュール１は、図５に示すごとく、上アーム重複部６Uと、下アーム重複部６Lと、中継重複部６Hと、フレーム重複部６Fとを備える。そして、連結部６１を用いて、上アーム重複部６Uと下アーム重複部６Lとの間と、下アーム重複部６Lと中継重複部６Hとの間と、中継重複部６Hとフレーム重複部６Fとの間と、フレーム重複部６Fと上アーム重複部６Uとの間とを連結している。
このようにすると、渦電流ｉを、交流電流Ｉに沿って、長い距離にわたって流すことができる。そのため、交流電流Ｉから発生した磁束を、渦電流ｉの磁束によって効果的に打ち消すことができ、インダクタンスを効果的に低減することができる。 Further, as shown in FIG. 5, the semiconductor module 1 of the present embodiment includes an upper arm overlapping portion 6 U , a lower arm overlapping portion 6 L , a relay overlapping portion 6 H, and a frame overlapping portion 6 F. Then, using the connecting portion 61, between the upper arm overlapping portion 6 U and the lower arm overlapping portion 6 L , between the lower arm overlapping portion 6 L and the relay overlapping portion 6 H , and the relay overlapping portion 6 H. The frame overlapping portion 6 F and the frame overlapping portion 6 F and the upper arm overlapping portion 6 U are connected to each other.
In this way, the eddy current i can flow along the alternating current I over a long distance. Therefore, the magnetic flux generated from the alternating current I can be effectively canceled by the magnetic flux of the eddy current i, and the inductance can be effectively reduced.

以上のごとく、本形態によれば、積層基板の反りを抑制でき、インダクタンスを低減できる半導体モジュールを提供することができる。 As described above, according to this embodiment, it is possible to provide a semiconductor module capable of suppressing warpage of a laminated substrate and reducing inductance.

なお、本形態では、図４に示すごとく、４個のアイランド５を形成したが、本発明はこれに限るものではない。すなわち、上アーム搭載アイランド５Uと下アーム搭載アイランド５Lとの、２個のアイランド５のみ形成してもよい。また、４個以上のアイランド５を形成してもよい。 In the present embodiment, as shown in FIG. 4, four islands 5 are formed, but the present invention is not limited to this. That is, only two islands 5, an upper arm-mounted island 5 U and a lower arm-mounted island 5 L , may be formed. Further, four or more islands 5 may be formed.

また、本形態では、図１に示すごとく、半導体モジュール１内に一対の半導体素子２（２U，２L）を封止したが、本発明はこれに限るものではない。すなわち、後述するシミュレーション結果のように、３対の半導体素子２を１個の半導体モジュール１に封止してもよい。また、２対でもよく、４対以上の半導体素子を１個の半導体モジュール１に封止してもよい。 Further, in the present embodiment, as shown in FIG. 1, a pair of semiconductor elements 2 (2 U , 2 L ) are sealed in the semiconductor module 1, but the present invention is not limited to this. That is, as shown in the simulation results described later, the three pairs of semiconductor elements 2 may be sealed in one semiconductor module 1. Further, two pairs may be used, or four or more pairs of semiconductor elements may be sealed in one semiconductor module 1.

また、本形態では、１個の上アーム半導体素子２Uと１個の下アーム半導体素子２Lとを互いに直列に接続したが、本発明はこれに限るものではない。すなわち、２個以上の上アーム半導体素子２Uを互いに並列接続して上アーム半導体素子群を構成すると共に、２個以上の下アーム半導体素子２Lを互いに並列接続して下アーム半導体素子群を構成し、これら２つの半導体素子群を互いに直列に接続してもよい。 Further, in the present embodiment, one upper arm semiconductor element 2 U and one lower arm semiconductor element 2 L are connected in series with each other, but the present invention is not limited to this. That is, two or more upper arm semiconductor elements 2 U are connected in parallel to each other to form an upper arm semiconductor element group, and two or more lower arm semiconductor elements 2 L are connected in parallel to each other to form a lower arm semiconductor element group. These two semiconductor element groups may be configured and connected in series with each other.

以下の実施形態においては、図面に用いた符号のうち、実施形態１において用いた符号と同一のものは、特に示さない限り、実施形態１と同様の構成要素等を表す。 In the following embodiments, among the codes used in the drawings, the same codes as those used in the first embodiment represent the same components and the like as those in the first embodiment unless otherwise specified.

（実施形態２）
本形態は、反対側金属層６０の形状を変更した例である。図７に示すごとく、本形態の反対側金属層６０は、実施形態１と同様に、複数の重複部６と、複数の連結部６１（６１A，６１B，６１E）とを備える。第１連結部６１Aによって、上アーム重複部６Uと下アーム重複部６Lとを連結してある。また、第２連結部６１Bによって、下アーム重複部６Lと中継重複部６Hとを連結してある。さらに、別の連結部６１Eによって、中継重複部６Hと上アーム重複部６Uと連結している。本形態では、実施形態１と異なり、中継重複部６Hとフレーム重複部６Fとの間、及びフレーム重複部６Fと上アーム重複部６Uとの間は、連結していない。 (Embodiment 2)
This embodiment is an example in which the shape of the metal layer 60 on the opposite side is changed. As shown in FIG. 7, the metal layer 60 on the opposite side of the present embodiment includes a plurality of overlapping portions 6 and a plurality of connecting portions 61 (61 A , 61 B , 61 E ) as in the first embodiment. The upper arm overlapping portion 6 U and the lower arm overlapping portion 6 L are connected by the first connecting portion 61 A. Further, the lower arm overlapping portion 6 L and the relay overlapping portion 6 H are connected by the second connecting portion 61 B. Further, another connecting portion 61 E connects the relay overlapping portion 6 H and the upper arm overlapping portion 6 U. In the present embodiment, unlike the first embodiment, the relay overlapping portion 6 H and the frame overlapping portion 6 F and the frame overlapping portion 6 F and the upper arm overlapping portion 6 U are not connected.

本形態の作用効果について説明する。上記構成にすると、実施形態１と比べて、連結部６１の数を少なくすることができる。そのため、素子側金属層５０と反対側金属層６０のパターンを、より近似させることができ、積層基板１０の反りをより効果的に抑制できる。また、上記構成を採用した場合も、渦電流ｉを、交流電流Ｉに沿って、比較的長い距離にわたって流すことができる。そのため、交流電流Ｉの磁束を、渦電流ｉの磁束によって効果的に打ち消すことができ、インダクタンスを効果的に低減できる。
その他、実施形態１と同様の構成および作用効果を備える。 The action and effect of this embodiment will be described. With the above configuration, the number of connecting portions 61 can be reduced as compared with the first embodiment. Therefore, the patterns of the element-side metal layer 50 and the opposite-side metal layer 60 can be more approximated, and the warp of the laminated substrate 10 can be suppressed more effectively. Further, even when the above configuration is adopted, the eddy current i can be passed along the alternating current I over a relatively long distance. Therefore, the magnetic flux of the alternating current I can be effectively canceled by the magnetic flux of the eddy current i, and the inductance can be effectively reduced.
In addition, it has the same configuration and action as in the first embodiment.

（実施形態３）
本形態は、反対側金属層６０の形状を変更した例である。図８に示すごとく、本形態の半導体モジュール１は、実施形態１と同様に、４個の連結部６１（６１A〜６１D）を備える。これらの連結部６１によって、上アーム重複部６Uと下アーム重複部６Lとの間と、下アーム重複部６Lと中継重複部６Hとの間と、中継重複部６Hとフレーム重複部６Fとの間と、フレーム重複部６Fと上アーム重複部６Uとの間を連結している。また、本形態では、１個の連結部６１（第１連結部６１A）を、Ｚ方向から見たときに、交流電流Ｉと重なる位置に形成してある。 (Embodiment 3)
This embodiment is an example in which the shape of the metal layer 60 on the opposite side is changed. As shown in FIG. 8, the semiconductor module 1 of the present embodiment includes four connecting portions 61 (61 A to 61 D ) as in the first embodiment. By these connecting portions 61, the upper arm overlapping portion 6 U and the lower arm overlapping portion 6 L , the lower arm overlapping portion 6 L and the relay overlapping portion 6 H , and the relay overlapping portion 6 H and the frame overlap. and between the parts 6 F, it is connected between the frame overlapping unit 6 F and upper arm overlapping section 6 U. Further, in the present embodiment, one connecting portion 61 (first connecting portion 61 A ) is formed at a position where it overlaps with the alternating current I when viewed from the Z direction.

本形態の作用効果について説明する。上述したように、本形態では、複数の連結部６１のうち、１個の連結部６１（第１連結部６１A）を、Ｚ方向から見たときに、交流電流Ｉと重なる位置に形成してある。
このようにすると、渦電流ｉを、交流電流Ｉに沿って、より長い距離にわたって流すことができる。そのため、渦電流ｉによる磁束の打ち消し効果をより高めることができ、インダクタンスをより低減できる。
その他、実施形態１と同様の構成および作用効果を備える。 The action and effect of this embodiment will be described. As described above, in the present embodiment, one of the plurality of connecting portions 61 (first connecting portion 61 A ) is formed at a position overlapping the alternating current I when viewed from the Z direction. There is.
In this way, the eddy current i can flow along the alternating current I over a longer distance. Therefore, the effect of canceling the magnetic flux due to the eddy current i can be further enhanced, and the inductance can be further reduced.
In addition, it has the same configuration and action as in the first embodiment.

なお、本形態では、複数の連結部６１のうち、１個の連結部６１（第１連結部６１A）を、Ｚ方向から見たときに交流電流Ｉと重なる位置に形成したが、本発明はこれに限るものではなく、２個以上の連結部６１を、交流電流Ｉと重なる位置に形成してもよい。
また、本形態の第１連結部６１Aは、Ｚ方向から見たときに、その全ての部位が交流電流Ｉと重なるよう構成されているが、本発明はこれに限るものではなく、第１連結部６１Aの一部のみが交流電流Ｉと重なるよう構成してもよい。
このように、複数の連結部６１のうち、少なくとも１個の連結部６１を、その少なくとも一部が、Ｚ方向から見たときに交流電流Ｉと重なるよう構成することができる。 In this embodiment, one of the plurality of connecting portions 61 (first connecting portion 61 A ) is formed at a position where it overlaps with the alternating current I when viewed from the Z direction. Is not limited to this, and two or more connecting portions 61 may be formed at positions where they overlap with the alternating current I.
Further, the first connecting portion 61 A of the present embodiment is configured so that all the portions thereof overlap with the alternating current I when viewed from the Z direction, but the present invention is not limited to this, and the first Only a part of the connecting portion 61 A may be configured to overlap the alternating current I.
In this way, at least one of the plurality of connecting portions 61 can be configured so that at least a part thereof overlaps with the alternating current I when viewed from the Z direction.

また、本形態では４個の連結部６１を設けたが、本発明はこれに限るものではない。すなわち、実施形態２のように、３個の連結部６１を設け、これら３個の連結部６１のうち、少なくとも１個の連結部６１を、Ｚ方向から見たときに交流電流Ｉと重なるよう構成してもよい。 Further, in the present embodiment, four connecting portions 61 are provided, but the present invention is not limited to this. That is, as in the second embodiment, the three connecting portions 61 are provided, and at least one of the three connecting portions 61 is overlapped with the alternating current I when viewed from the Z direction. It may be configured.

（実施形態４）
本形態は、反対側金属層６０の形状を変更した例である。図９に示すごとく、本形態の半導体モジュール１は、実施形態１と同様に、４個の連結部６１（６１A〜６１D）を備える。これらの連結部６１によって、上アーム重複部６Uと下アーム重複部６Lとの間と、下アーム重複部６Lと中継重複部６Hとの間と、中継重複部６Hとフレーム重複部６Fとの間と、フレーム重複部６Fと上アーム重複部６Uとの間を連結している。また、本形態では、全ての連結部６１A〜６１Dを、Ｚ方向から見たときに、交流電流Ｉと重なる位置に形成してある。
個々の連結部６１は、Ｚ方向から見たときに、その全ての部位が、交流電流Ｉと重なるよう構成されている。なお、Ｚ方向から見たときに、個々の連結部６１の、一部のみが交流電流Ｉと重なるよう構成してもよい。 (Embodiment 4)
This embodiment is an example in which the shape of the metal layer 60 on the opposite side is changed. As shown in FIG. 9, the semiconductor module 1 of the present embodiment includes four connecting portions 61 (61 A to 61 D ) as in the first embodiment. By these connecting portions 61, the upper arm overlapping portion 6 U and the lower arm overlapping portion 6 L , the lower arm overlapping portion 6 L and the relay overlapping portion 6 H , and the relay overlapping portion 6 H and the frame overlap. and between the parts 6 F, it is connected between the frame overlapping unit 6 F and upper arm overlapping section 6 U. Further, in the present embodiment, all the connecting portions 61 A to 61 D are formed at positions where they overlap with the alternating current I when viewed from the Z direction.
The individual connecting portions 61 are configured so that all the portions thereof overlap with the alternating current I when viewed from the Z direction. When viewed from the Z direction, only a part of the individual connecting portions 61 may overlap with the alternating current I.

本形態の作用効果について説明する。上述したように、本形態では、全ての連結部６１A〜６１Dを、Ｚ方向から見たときに、交流電流Ｉと重なる位置に形成してある。
そのため、渦電流ｉを、交流電流Ｉに沿って、より長い距離にわたって流すことができる。したがって、渦電流ｉによる磁束の打ち消し効果をより高めることができ、インダクタンスをより効果的に低減できる。
その他、実施形態１と同様の構成および作用効果を備える。 The action and effect of this embodiment will be described. As described above, in the present embodiment, all the connecting portions 61 A to 61 D are formed at positions where they overlap with the alternating current I when viewed from the Z direction.
Therefore, the eddy current i can flow along the alternating current I over a longer distance. Therefore, the effect of canceling the magnetic flux due to the eddy current i can be further enhanced, and the inductance can be reduced more effectively.
In addition, it has the same configuration and action as in the first embodiment.

（シミュレーション例）
本発明の効果を確認するためのシミュレーションを行った。まず、シミュレータ上で、半導体モジュール１の３個のサンプル（サンプルＡ、サンプルＢ、サンプルＣ）を作成した。サンプルＡは、図１０に示すごとく、３個の上アーム半導体素子２Uと、３個の下アーム半導体素子２Lとを備える。これらの半導体素子２によって、インバータ回路１９（図１７参照）を形成してある。また、サンプルＡは、１本の正極端子３Pと、２本の負極端子３Nとを備える。さらに、サンプルＡは、アイランド５として、上アーム半導体素子２Uを搭載した上アーム搭載アイランド５Uと、下アーム半導体素子２Lを搭載した下アーム搭載アイランド５Lと、中継アイランド５Hと、フレームアイランド５Fとを備える。中継アイランド５Hは、導電部材８Bを介して、下アーム半導体素子２Lのソース電極に電気接続している。下アーム搭載アイランド５Lに、交流端子３９が接続している。また、中継アイランド５Hと上アーム搭載アイランド５Uとの間には、これらを絶縁する素子側溝部５８が形成されている。サンプルＡの反対側金属層６０（図示しない）は、図１１に示すごとく、所謂ベタパターンになっている。 (Simulation example)
A simulation was performed to confirm the effect of the present invention. First, three samples (sample A, sample B, and sample C) of the semiconductor module 1 were prepared on the simulator. As shown in FIG. 10, the sample A includes three upper arm semiconductor elements 2 U and three lower arm semiconductor elements 2 L. The inverter circuit 19 (see FIG. 17) is formed by these semiconductor elements 2. Further, the sample A includes one positive electrode terminal 3 P and two negative electrode terminals 3 N. Further, as the island 5, the sample A includes an upper arm-mounted island 5 U equipped with an upper arm semiconductor element 2 U , a lower arm-mounted island 5 L equipped with a lower arm semiconductor element 2 L , and a relay island 5 H. and a frame island 5 F. The relay island 5 H is electrically connected to the source electrode of the lower arm semiconductor element 2 L via the conductive member 8 B. The AC terminal 39 is connected to the lower arm mounted island 5 L. Further, an element side groove 58 for insulating the relay island 5 H and the upper arm mounting island 5 U is formed. The metal layer 60 (not shown) on the opposite side of the sample A has a so-called solid pattern as shown in FIG.

図１０に示すごとく、半導体素子２をスイッチング動作させると、交流電流Ｉが、正極端子３Pと負極端子３Nとの間を流れる。交流電流Ｉは、一対の半導体素子２U，２Lと、導電部材８と、アイランド５（５U，５L，５H）を通過する。交流電流Ｉが流れると、図１１に示すごとく、反対側金属層６０に渦電流ｉが発生する。サンプルＡでは、反対側金属層６０をベタパターンにしてあるため、渦電流ｉの経路が制限を受けにくい。したがって、渦電流ｉは、交流電流Ｉの経路に沿って流れる。 As shown in FIG. 10, when the semiconductor element 2 is switched, an alternating current I flows between the positive electrode terminal 3 P and the negative electrode terminal 3 N. The alternating current I passes through a pair of semiconductor elements 2 U , 2 L , a conductive member 8, and an island 5 (5 U , 5 L , 5 H). When the alternating current I flows, an eddy current i is generated in the metal layer 60 on the opposite side as shown in FIG. In sample A, since the metal layer 60 on the opposite side has a solid pattern, the path of the eddy current i is not easily restricted. Therefore, the eddy current i flows along the path of the alternating current I.

次に、サンプルＢの説明を行う。サンプルＢの、半導体素子２側の構成は、サンプルＡ（図１０参照）と同一である。サンプルＢの反対側金属層６０は、図１２に示すごとく、素子側金属層５０のパターンと同一にしてある。より詳しくは、素子側金属層５０は、上アーム重複部６Uと、下アーム重複部６Lと、中継重複部６Hと、フレーム重複部６Fとを備える。これらの重複部６は、連結部６１によって連結されていない。そのため、サンプルＢでは、渦電流ｉが、複数の重複部６の間を流れず、渦電流ｉの経路が制限を受けやすい。したがって、渦電流ｉは、交流電流Ｉに沿って流れにくい。 Next, sample B will be described. The configuration of the sample B on the semiconductor element 2 side is the same as that of the sample A (see FIG. 10). As shown in FIG. 12, the metal layer 60 on the opposite side of the sample B has the same pattern as the metal layer 50 on the element side. More specifically, the element-side metal layer 50 includes an upper arm overlapping portion 6 U , a lower arm overlapping portion 6 L , a relay overlapping portion 6 H, and a frame overlapping portion 6 F. These overlapping portions 6 are not connected by the connecting portion 61. Therefore, in sample B, the eddy current i does not flow between the plurality of overlapping portions 6, and the path of the eddy current i is likely to be restricted. Therefore, the eddy current i does not easily flow along the alternating current I.

次に、サンプルＣの説明を行う。サンプルＣの、半導体素子２側の構成は、サンプルＡ（図１０参照）と同一である。図１３に示すごとく、サンプルＣでは、反対側金属層６０に、複数の重複部６と、連結部６１とを形成してある。この連結部６１により、上アーム重複部６Uと下アーム重複部６Lとの間、複数の下アーム重複部６L同士、下アーム重複部６Lと中継重複部６Hの間を連結している。また、中継重複部６Hと上アーム重複部６Uとの間には、反対側溝部６８が形成されている。図１３、図１４に示すごとく、反対側溝部６８の先端６８Pにも、連結部６１が形成されている。この連結部６１により、上アーム重複部６Uと中継重複部６Hとを連結している。サンプルＣでは、このように複数の連結部６１を形成することにより、複数の重複部６の間に渦電流ｉが流れるようにしてある。 Next, sample C will be described. The configuration of the sample C on the semiconductor element 2 side is the same as that of the sample A (see FIG. 10). As shown in FIG. 13, in the sample C, a plurality of overlapping portions 6 and connecting portions 61 are formed on the opposite metal layer 60. The connecting portion 61 connects the upper arm overlapping portion 6 U and the lower arm overlapping portion 6 L , the plurality of lower arm overlapping portions 6 L , and the lower arm overlapping portion 6 L and the relay overlapping portion 6 H. ing. Further, a groove portion 68 on the opposite side is formed between the relay overlapping portion 6 H and the upper arm overlapping portion 6 U. As shown in FIGS. 13 and 14, a connecting portion 61 is also formed at the tip 68 P of the opposite side groove portion 68. The connecting portion 61 connects the upper arm overlapping portion 6 U and the relay overlapping portion 6 H. In sample C, by forming the plurality of connecting portions 61 in this way, the eddy current i flows between the plurality of overlapping portions 6.

上記３個のサンプルについてシミュレーションを行い、反り量とインダクタンスを算出した。まず、上記３個のサンプルを−４０℃から１５０℃に温度変化させ、積層基板１０の反り量を算出した。その結果を図１５に示す。このグラフでは、サンプルＡ（すなわち、反対側金属層６０をベタパターンにしたサンプル）の反り量を１としたときの、サンプルＢ、Ｃの反り量を比率にして表している。図１５から、反対側金属層６０をベタパターンにすると反り量が大きいことが分かる。また、サンプルＢ、Ｃは、反り量が少ないことが分かる。これは、素子側金属層５０と反対側金属層６０との、熱膨張量が略等しいためだと考えられる。 Simulations were performed on the above three samples, and the amount of warpage and inductance were calculated. First, the temperature of the above three samples was changed from −40 ° C. to 150 ° C., and the amount of warpage of the laminated substrate 10 was calculated. The result is shown in FIG. In this graph, when the amount of warpage of sample A (that is, the sample in which the metal layer 60 on the opposite side is a solid pattern) is 1, the amount of warpage of samples B and C is represented as a ratio. From FIG. 15, it can be seen that the amount of warpage is large when the metal layer 60 on the opposite side has a solid pattern. Further, it can be seen that the samples B and C have a small amount of warpage. It is considered that this is because the amount of thermal expansion of the element-side metal layer 50 and the opposite-side metal layer 60 are substantially equal.

次に、インダクタンスのシミュレーション結果を図１６に示す。このグラフでは、サンプルＡのインダクタンスを１としたときの、サンプルＢ、Ｃのインダクタンスを比率にして表している。図１６から、連結部６１を形成しないサンプルＢは、インダクタンスが高いことが分かる。また、連結部６１を形成したサンプルＣは、インダクタンスを低減でき、サンプルＡと略同じ値になることが分かる。これは、サンプルＣでは連結部６１を形成したため、渦電流ｉを、交流電流Ｉの経路に沿って流しやすくなり、交流電流Ｉの磁束を効果的に打ち消すことができるからだと考えられる。 Next, the simulation result of the inductance is shown in FIG. In this graph, when the inductance of the sample A is 1, the inductances of the samples B and C are represented as a ratio. From FIG. 16, it can be seen that the sample B, which does not form the connecting portion 61, has a high inductance. Further, it can be seen that the sample C in which the connecting portion 61 is formed can reduce the inductance and has substantially the same value as the sample A. It is considered that this is because the connecting portion 61 is formed in the sample C, so that the eddy current i can easily flow along the path of the alternating current I, and the magnetic flux of the alternating current I can be effectively canceled.

本発明は上記各実施形態に限定されるものではなく、その要旨を逸脱しない範囲において種々の実施形態に適用することが可能である。 The present invention is not limited to each of the above embodiments, and can be applied to various embodiments without departing from the gist thereof.

１ 半導体モジュール
２ 半導体素子
３ 直流端子
４ 絶縁基板
５０ 素子側金属層
５ アイランド
６０ 反対側金属層
６ 重複部
６１ 連結部 1 Semiconductor module 2 Semiconductor element 3 DC terminal 4 Insulation substrate 50 Element side metal layer 5 Island 60 Opposite side metal layer 6 Overlapping part 61 Connecting part

Claims (4)

互いに直列に電気接続された、上アーム半導体素子（２U）と下アーム半導体素子（２L）との、少なくとも一対の半導体素子（２）と、
上記上アーム半導体素子に電気接続した正極端子（３P）と、上記下アーム半導体素子に電気接続した負極端子（３N）との、一対の直流端子（３）と、
絶縁材料からなる絶縁基板（４）と、該絶縁基板の上記半導体素子側の主面（Ｓ1）に形成された素子側金属層（５０）と、上記絶縁基板の、上記素子側金属層を設けた側とは反対側の主面（Ｓ2）に形成された反対側金属層（６０）と、を有する積層基板（１０）とを備え、
上記素子側金属層によって複数のアイランド（５）が形成され、該複数のアイランドのうち少なくとも一部の該アイランドは、上記半導体素子が搭載され、該半導体素子を流れる電流の経路をなしており、
上記反対側金属層は、上記絶縁基板の厚さ方向（Ｚ）から見たときに、個々の上記アイランドと重なり合う複数の重複部（６）と、該複数の重複部のうち少なくとも２個の該重複部を連結する連結部（６１）とを備え、
上記半導体素子のスイッチング動作に伴って、交流電流が、上記一対の直流端子の間に、上記一対の半導体素子および上記アイランドを介して流れたとき、渦電流が、上記複数の重複部と上記連結部とを含む経路に流れるよう構成されている、半導体モジュール（１）。 At least a pair of semiconductor elements (2), an upper arm semiconductor element (2 U ) and a lower arm semiconductor element (2 L), electrically connected in series with each other.
A pair of DC terminals (3) consisting of a positive electrode terminal (3 P ) electrically connected to the upper arm semiconductor element and a negative electrode terminal (3 N ) electrically connected to the lower arm semiconductor element.
An insulating substrate (4) made of an insulating material, an element-side metal layer (50) formed on the main surface (S 1 ) of the insulating substrate on the semiconductor element side, and an element-side metal layer of the insulating substrate. A laminated substrate (10) having a metal layer (60) on the opposite side formed on a main surface (S 2 ) opposite to the provided side and a laminated substrate (10) having the metal layer (60) on the opposite side is provided.
A plurality of islands (5) are formed by the element-side metal layer, and at least a part of the islands is mounted with the semiconductor element and forms a path of a current flowing through the semiconductor element.
The metal layer on the opposite side has a plurality of overlapping portions (6) that overlap with the individual islands when viewed from the thickness direction (Z) of the insulating substrate, and at least two of the plurality of overlapping portions. It is provided with a connecting portion (61) for connecting the overlapping portions.
When an alternating current flows between the pair of DC terminals through the pair of semiconductor elements and the islands due to the switching operation of the semiconductor elements, the eddy current is connected to the plurality of overlapping portions. A semiconductor module (1) configured to flow in a path including a part. 複数の上記連結部を備え、上記アイランドとして、上記上アーム半導体素子を搭載した上アーム搭載アイランド（５U）と、上記下アーム半導体素子を搭載した下アーム搭載アイランド（５L）と、上記半導体素子が搭載されず導電部材（８）を介して上記半導体素子に電気接続した中継アイランド（５H）とを備え、上記重複部として、上記厚さ方向から見たときに上記上アーム搭載アイランドと重なる上アーム重複部（６U）と、上記下アーム搭載アイランドと重なる下アーム重複部（６L）と、上記中継アイランドと重なる中継重複部（６H）とを備え、個々の上記連結部によって、上記上アーム重複部と上記下アーム重複部との間と、該下アーム重複部と上記中継重複部との間と、該中継重複部と上記上アーム重複部との間を、それぞれ連結してある、請求項１に記載の半導体モジュール。 An upper arm-mounted island (5 U ) equipped with the upper arm semiconductor element, a lower arm-mounted island (5 L ) equipped with the lower arm semiconductor element, and the semiconductor It is provided with a relay island (5 H ) in which the element is not mounted and is electrically connected to the semiconductor element via the conductive member (8), and as the overlapping portion, the island on which the upper arm is mounted when viewed from the thickness direction. An overlapping upper arm overlapping portion (6 U ), a lower arm overlapping portion (6 L ) overlapping the lower arm mounting island, and a relay overlapping portion (6 H ) overlapping the relay island are provided, and are provided by the individual connecting portions. , The upper arm overlapping portion and the lower arm overlapping portion, the lower arm overlapping portion and the relay overlapping portion, and the relay overlapping portion and the upper arm overlapping portion are connected, respectively. The semiconductor module according to claim 1. 複数の上記連結部を備え、上記アイランドとして、上記上アーム半導体素子を搭載した上アーム搭載アイランドと、上記下アーム半導体素子を搭載した下アーム搭載アイランドと、上記半導体素子が搭載されず導電部材を介して上記半導体素子に電気接続した中継アイランドと、上記上アーム搭載アイランドと上記下アーム搭載アイランドと上記中継アイランドとを取り囲むフレームアイランド（５F）とを備え、上記重複部として、上記厚さ方向から見たときに上記上アーム搭載アイランドと重なる上アーム重複部と、上記下アーム搭載アイランドと重なる下アーム重複部と、上記中継アイランドと重なる中継重複部と、上記フレームアイランドと重なるフレーム重複部（６F）とを備え、個々の上記連結部によって、上記上アーム重複部と上記下アーム重複部との間と、該下アーム重複部と上記中継重複部との間と、該中継重複部と上記フレーム重複部との間と、該フレーム重複部と上記上アーム重複部との間とを、それぞれ連結してある、請求項１に記載の半導体モジュール。 As the islands having the plurality of connecting portions, the upper arm mounting island on which the upper arm semiconductor element is mounted, the lower arm mounting island on which the lower arm semiconductor element is mounted, and the conductive member on which the semiconductor element is not mounted are provided. A relay island electrically connected to the semiconductor element via the semiconductor element, a frame island (5 F ) surrounding the upper arm mounting island, the lower arm mounting island, and the relay island are provided, and as the overlapping portion, the thickness direction is provided. When viewed from above, the upper arm overlapping portion that overlaps the upper arm mounting island, the lower arm overlapping portion that overlaps the lower arm mounting island, the relay overlapping portion that overlaps the relay island, and the frame overlapping portion that overlaps the frame island ( 6 F ), and by the individual connecting portions, between the upper arm overlapping portion and the lower arm overlapping portion, between the lower arm overlapping portion and the relay overlapping portion, and the relay overlapping portion. The semiconductor module according to claim 1, wherein the frame overlapping portion and the frame overlapping portion and the upper arm overlapping portion are connected to each other. 上記複数の連結部のうち少なくとも一個の該連結部は、その少なくとも一部が、上記厚さ方向から見たときに、上記交流電流の経路と重なるよう構成されている、請求項２又は３に記載の半導体モジュール。 According to claim 2 or 3, at least one of the plurality of connecting portions is configured such that at least a part thereof overlaps with the path of the alternating current when viewed from the thickness direction. The semiconductor module described.
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