JP6903195B1 - Delayed lock loop device and how it works - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a delay lock loop device and an operation method thereof. A delay lock loop device includes a delay line, a copy circuit, a phase detector and a delay controller. The delay line delays the input clock according to the delay code and provides a delay clock. The copy circuit generates a feedback clock based on the delay clock. The phase detector compares the input clock and the feedback clock to generate a delay control signal. Based on the control clock, the delay controller generates a delay code at the first time point according to the delay control signal, delays the copy delay time length, and provides the delay code to the delay line at the second time point. The delay line adjusts the input clock at the second time point. The period of the control clock is adjusted to be larger than the copy delay time length. [Selection diagram] Fig. 1

Description

The present invention relates to a delayed lock loop device and a method of operating the delayed lock loop device, and more particularly to a method of operating the delayed lock loop device and the delayed lock loop device applicable to an arbitrary input clock cycle.

Generally, a delay-locked loop (DLL) is set to adjust the received input clock to a desired delay clock within a preset cycle. However, when the input clock has a relatively small period, the DLL frequently causes an overshift, and further causes a situation in which the delay clock has insufficient or excessive delay. If the input clock has a relatively large period, the DLL can improve the overshift, but the input clock received by the DLL cannot be adjusted to the desired delay clock within the preset period.

Therefore, designing a delay lock loop device applicable to any input clock period is one of the challenges for those skilled in the art to study.

The present invention provides a delay lock loop device and a method of operating a delay lock loop device applicable to any input clock cycle.

The delay lock loop device of the present invention includes a delay line, a copy circuit, a phase detector and a delay controller. The delay line is configured to provide a delay clock by receiving the input clock and delaying the input clock in response to a multi-bit delay code. The copy circuit is coupled to the delay line. The copy circuit is configured to receive the delay clock and generate a feedback clock based on the delay clock. The phase detector is coupled to the copy circuit. The phase detector is configured to receive the input clock and the feedback clock and compare the input clock with the feedback clock to generate a delay control signal. The delay controller is coupled to the phase detector and the delay line. The delay controller generates a delay code at the first time point according to the delay control signal based on the control clock, delays the copy delay time length, provides the delay code to the delay line at the second time point, and makes the delay line. It is configured to adjust the timing of the input clock at the second time point. The period of the control clock is adjusted to be larger than the copy delay time length.

The method of operation of the present invention applies to delayed lock loop devices. The operation method includes a step of receiving an input clock and delaying the input clock in response to a multi-bit delay code to provide a delay clock, a step of generating a feedback clock based on the delay clock, and an input clock. A step of comparing the feedback clocks to generate a delay control signal, and a delay code is generated at the first time point according to the delay control signal based on the control clock, the copy delay time length is delayed, and the delay code is generated at the second time point. The control clock cycle is adjusted to be greater than the copy delay time length, including the step of adjusting the timing of the input clock at the second time point.

Based on the above, the period of the control clock is adjusted to be greater than the copy delay time length, and the delay lock loop device and operating method provide a delay code based on the control clock and enter the delay code after the copy delay time length. Adjust the phase of the clock. As described above, the delay lock loop device and the operation method of the present invention can be applied to any input clock period.

It is explanatory drawing of the delay lock loop device by 1st Embodiment of this invention. It is a signal timing diagram applied to the input clock which has the minimum period by embodiment of this invention. It is a signal timing diagram applied to the input clock which has the maximum period by embodiment of this invention. It is a signal timing diagram applied to the slow skew according to the embodiment of this invention. It is a signal timing diagram applied to the fast skew according to the embodiment of this invention. It is explanatory drawing of the delay lock loop device device by 2nd Embodiment of this invention. It is explanatory drawing of the delay lock loop device device according to 3rd Embodiment of this invention. It is a flow chart of the operation method by embodiment of this invention.

In order to make the above-mentioned features and advantages of the present invention easy to understand, embodiments will be given, and the details will be described below together with the drawings.

Although some examples of the present invention will be described in detail with reference to the drawings, the member codes cited in the following description are regarded as the same or similar members when the same member code appears in different drawings. These examples are only a part of the present invention and do not disclose all possible embodiments of the present invention. More precisely, these examples are merely examples of devices within the claims of the present invention.

With reference to FIG. 1, FIG. 1 is an explanatory diagram of a delay lock loop device device according to the first embodiment of the present invention. The delay lock loop device 100 includes a delay line 110, a replica circuit 120, a phase detector 130 and a delay controller 140. The delay line 110 receives the input clock I_CLK and delays the input clock I_CLK in response to the delay code DCD of a plurality of bits to provide the delay clock D_CLK. The copy circuit 120 is coupled to the delay line 110. The copy circuit 120 receives the delay clock D_CLK from the delay line 110 and generates the feedback clock FB_CLK based on the delay clock D_CLK. The phase detector 130 is coupled to the copy circuit 120. The phase detector 130 receives the input clock I_CLK and the feedback clock FB_CLK, compares the input clock I_CLK with the feedback clock FB_CLK, and generates a delay control signal DCS.

The delay controller 140 is coupled to the phase detector 130 and the delay line 110. The delay controller 140 generates a delay code DCD at the first time point according to the delay control signal DCS based on the control clock CTRL_CLK. In the present embodiment, the delay control signal DCS includes delay commands UP and DN. The delay controller 140 increases the value of the delay code DCD according to the delay command UP. The delay line 110 increases the delay of the input clock I_CLK based on the increased delay code DCD. On the other hand, the delay controller 140 reduces the delay code DCD according to the delay command DN. The delay line 110 reduces the delay of the input clock I_CLK based on the reduced number of delay code DCD. When the delay controller 140 generates the delay code DCD at the first time point, it delays the copy delay time length RDT and provides the delay code DCD to the delay line 110 at the second time point. Therefore, the delay line 110 adjusts the timing of the input clock I_CLK at the second time point. In the present embodiment, the period of the control clock CTRL_CLK is adjusted to be larger than the copy delay time length RDT and smaller than the time length obtained by adding the period of the input clock I_CLK to the copy delay time length RDT. Next, after the second time point, the delay controller 140 provides another delay code DCD based on the control clock CTRL_CLK.

It should be mentioned that the period of the control clock CTRL_CLK is adjusted to be larger than the copy delay time length RDT. That is, the delay lock loop device 100 adjusts the cycle of the control clock CTRL_CLK after the copy delay time length RDT, and the cycle of the control clock CTRL_CLK becomes slightly larger than the copy delay time length RDT. The delay controller 140 can generate another delay code DCD after the feedback clock FB_CLK is provided (ie, within the time interval of at least one input clock I_CLK cycle). For example, the period of the control clock CTRL_CLK is adjusted to be larger than the copy delay time length RDT and smaller than the time length obtained by adding the period of the single input clock I_CLK to the copy delay time length RDT. Further, as another example, the period of the control clock CTRL_CLK is adjusted to be larger than the copy delay time length RDT and smaller than the time length obtained by adding the periods of the two input clocks I_CLK to the copy delay time length RDT. .. Therefore, the delay controller 140 can generate another delay code DCD after the feedback clock FB_CLK is provided (ie, within the time interval of one or two input clocks I_CLK cycles). Therefore, when the input clock I_CLK has a relatively small period, the delay lock loop device 100 does not have an overshift situation. Further, when the input clock I_CLK has a relatively large cycle, the delay lock loop device 100 has a cycle of the control clock CTRL_CLK adjusted according to the copy delay time length RDT. Therefore, the length of time until the input clock I_CLK of the delay lock loop device 100 is adjusted to the desired delay clock D_CLK is not extended. In this way, the delay lock loop device 100 can be applied to an arbitrary input clock I_CLK cycle, and the input clock I_CLK received within the specified preset cycle can be adjusted to a desired delay clock D_CLK. ..

For example, with reference to FIGS. 1 and 2A at the same time, FIG. 2A is a signal timing diagram applied to an input clock having a minimum period according to an embodiment of the present invention. The signal timing diagram of this embodiment is applied to the delay lock loop device 100. The delay controller 140 increases the value of the delay code DCD according to the delay command UP, and increases the delay of the input clock I_CLK. On the other hand, the delay controller 140 reduces the numerical value of the delay code DCD according to the delay command DN, and reduces the delay of the input clock I_CLK. In the present embodiment, the delay controller 140 generates a delay code DCD at the first time point t1 according to the delay control signal DCS based on the control clock CTRL_CLK. In this embodiment, the delay controller 140 generates a delay code DCD associated with the delay control signal DCS based on the rising edge of the control clock CTRL_CLK. In some embodiments, the delay controller 140 generates a delay code DCD associated with the delay control signal DCS based on the falling edge of the control clock CTRL_CLK. The delay line 110 adjusts the timing of the input clock I_CLK at the second time point t2. The second time point t2 has a copy delay time length RDT delay with respect to the first time point t1. In the present embodiment, the period of the control clock CTRL_CLK is adjusted to be larger than the copy delay time length RDT. Therefore, the delay controller 140 generates another delay code DCD at the third time point t3 after the second time point t2 based on the control clock CTRL_CLK. The time length between the third time point t3 and the first time point t1 is substantially equal to the period of the control clock CTRL_CLK.

In the present embodiment, the period of the control clock CTRL_CLK is determined by the copy delay time length RDT. Therefore, after the feedback clock FB_CLK is provided, the delay controller 140 has a single input clock I_CLK cycle or a single feedback clock FB_CLK cycle (the input clock I_CLK cycle is substantially the feedback clock FB_CLK cycle). Another delay code DCD can be generated within the time interval (equal to). Therefore, when the input clock I_CLK has the minimum period, the delay lock loop device 100 does not have an overshift situation.

As an example, reference to FIGS. 1, 2A, and 2B at the same time, FIG. 2B is a signal timing diagram applied to an input clock having a maximum period according to an embodiment of the present invention. The signal timing diagram of FIG. 2B also applies to the delay lock loop device 100. In the present embodiment, the copy delay time length RDT of FIG. 2A is the same as the copy delay time length RDT of FIG. 2B. Therefore, in the present embodiment, the period of the control clock CTRL_CLK shown in FIG. 2B may be equal to the period of the control clock CTRL_CLK shown in FIG. 2A. That is, when the input clock I_CLK has a maximum period, the delay lock loop device 100 adjusts the period of the control clock CTRL_CLK according to the copy delay time length RDT. Therefore, the length of time until the input clock I_CLK of the delay lock loop device 100 is adjusted to the desired delay clock D_CLK is not extended.

With reference to FIGS. 1, 3A and 3B at the same time, FIG. 3A is a signal timing diagram applied to slow skew according to the embodiment of the present invention. FIG. 3B is a signal timing diagram applied to the fast skew according to the embodiment of the present invention. The signal timing diagram of FIG. 3A and the signal timing diagram of FIG. 3B are also applied to the delay lock loop device 100. In this embodiment, the copy delay time length RDT is adjusted according to the transistor skew generated by the delay lock loop device 100 process. Transistor skew is thus determined to the threshold voltage of the transistor. For example, based on the process of the delay locked loop device 100, when a transistor is relatively large threshold voltage of the delay locked loop device 100, it means the situation with a slow skew delay locked loop device 100 (slow skew) , The delay lock loop device 100 will have a relatively large delay. As shown in FIG. 3A, the copy delay time length RDT is increased by slow skew. By increasing the copy delay time length RDT by slow skew, the cycle of the control clock CTRL_CLK is also increased.

In another example, when the transistor of the delay locked loop device 100 has a relatively small threshold voltage, which means that the delay locked loop device 100 has a status of first skew (fast skew), a delay locked loop The device 100 will have a relatively small delay. As shown in FIG. 3B, the copy delay time length RDT is reduced by the fast skew. By reducing the copy delay time length RDT by the fast skew, the cycle of the control clock CTRL_CLK is also reduced.

With reference to FIG. 4, FIG. 4 is an explanatory diagram of a delay lock loop device according to a second embodiment of the present invention. The difference from the first embodiment is that the delay lock loop device 200 further includes an oscillator 150. In this embodiment, the oscillator 150 is coupled to the delay controller 140. Oscillator 150 provides the control clock CTRL_CLK. In this embodiment, the oscillator 150 receives the enable signal ES. Oscillator 150 is enabled according to the enable signal ES to provide the control clock CTRL_CLK.

With reference to FIG. 5, FIG. 5 is an explanatory diagram of a delay lock loop device according to the third embodiment of the present invention. The difference from the second embodiment is that the delay lock loop device 300 further includes an enable signal generator 160. In this embodiment, the enable signal generator 160 is coupled to the oscillator 150. The enable signal generator 160 provides the enable signal ES. In this embodiment, the enable signal generator 160 is further coupled to a delay line 110, a copy circuit 120, a phase detector 130 and a delay controller 140. The enable signal generator 160 also enables the delay line 110, the copy circuit 120, the phase detector 130, and the delay controller 140 by the enable signal ES.

Referring to FIGS. 1 and 6 at the same time, FIG. 6 is a flow chart of an operation method according to an embodiment of the present invention. In step S110, the delay line 110 receives the input clock I_CLK and delays the input clock I_CLK in response to the multi-bit delay code DCD to provide the delay clock D_CLK. In step S120, the copy circuit 120 generates the feedback clock FB_CLK based on the delay clock D_CLK. In step S130, the phase detector 130 compares the input clock I_CLK with the feedback clock FB_CLK to generate a delay control signal DCS. In step S140, based on the control clock, the delay controller 140 generates a delay code DCD at the first time point according to the delay control signal DCS, delays the copy delay time length, and provides the delay code DCD at the second time point. To do. Moreover, the delay line 110 adjusts the timing of the input clock I_CLK at the second time point. Details of the implementation of steps S110 to S140 of this embodiment will not be repeated here because sufficient teaching can be obtained in at least a plurality of embodiments of FIGS. 1 to 3B.

In summary, the period of the control clock of the present invention is larger than the copy delay time length, and the delay lock loop device and operation method provide a delay code based on the control clock and input the delay code after the copy delay time length. The phase of the clock can be adjusted. As described above, the delay lock loop device and the operation method of the present invention can be applied to any input clock cycle, and the input clock received within the specified preset period is adjusted to a desired delay clock. Can be done.

Although the present invention has disclosed examples as described above, it is not intended to limit the present invention, and those skilled in the art can make some modifications and modifications without departing from the spirit of the present invention. Therefore, the scope of protection of the present invention is based on the scope of claims described later.

The present invention relates to a delayed lock loop device and a method of operating the same. Delayed lock loop devices and operating methods can be applied to any input clock cycle.

100, 200, 300 Delay lock loop device 110 Delay line 120 Copy circuit 130 Phase detector 140 Delay controller 150 Oscillator 160 Enable signal generator D_CLK Delay clock DCD Delay code DCS Delay control signal DN, UP Delay command ES enable signal FB_CLK Feedback Clock I_CLK Input clock RDT Copy delay time length S110 to S140 Step t1 1st time point t2 2nd time point t3 3rd time point

Claims (13)

A delay line configured to receive the input clock and delay the input clock in response to a multi-bit delay code to provide a delay clock.
A copy circuit coupled to the delay line, having a copy delay time length, receiving the delay clock, and being configured to generate a feedback clock based on the delay clock.
A phase detector coupled to the copy circuit, receiving the input clock and the feedback clock, and comparing the input clock with the feedback clock to generate a delay control signal.
Coupled with the phase detector and the delay line, the delay code is generated at the first time point according to the delay control signal based on the control clock, and the copy delay time length causes the first time point to be the second time. delaying the point, the delay controller wherein said providing a delay code to the delay line at the second time point, adjusting the timing of the input clock by the second time point in the delay line,
Including
Period of the control clock, said copy delay time much larger than the length smaller than the length of time period was added for at least one of said input clock to said copy delay time length, the delay locked loop device. The delay controller provides another delay code at the third time point after the second time point, and the length of time between the third time point and the first time point is the control clock. delay locked loop device according to claim 1 substantially equal to the period of. Said copy delay time length is adjusted in accordance with the transistor skew generated by the delay locked loop device process, the transistor skew, delay locked loop according to claim 1 or 2 in the threshold voltage of the transistor thus determined devices. The delay lock loop device according to claim 3, wherein the copy delay time length is increased according to the slow skew of the transistor skew, and the copy delay time length is decreased according to the fast skew of the transistor skew. The delay lock loop device according to any one of claims 1 to 4, further comprising an oscillator coupled to the delay controller and configured to provide the control clock. The delay lock loop device according to claim 5, wherein the oscillator is enabled according to an enable signal to provide the control clock. Coupled to said oscillator, a delay locked loop device according to claim 6, further comprising a configured enable signal generator to provide the enable signal. The enable signal generator is further coupled to the delay line, the copy circuit, the phase detector and the delay controller, and the delay line, the copy circuit, the phase detector and the delay control are controlled by the enable signal. The delay lock loop device according to claim 7, wherein the device is enabled. A step of providing a delay clock by receiving an input clock and delaying the input clock in response to a multi-bit delay code.
A step of generating a feedback clock based on the delay clock,
A step of comparing the input clock with the feedback clock to generate a delay control signal,
Generating the delay code first hour point according to said delay control signal based on the control clock, and the first time point by copying the delay time length delaying the second time point, the delay code the second time point And the step of adjusting the timing of the input clock at the second time point,
Including
The period of the control clock, the much larger than the copy delay time length, said copy delay time length smaller than the length of time plus the period of at least one of the input clock, a method of operating a delay locked loop device. The third time point after the second time point further comprises providing another delay code.
The operation method according to claim 9, wherein the time length between the third time point and the first time point is substantially equal to the cycle of the control clock. The copy delay time length adjusted according transistor skew generated by the delay locked loop device process, the transistor skew the operation method according to claim 9 or claim 10 in thresholds voltage of the transistor thus determined .. The operation method according to claim 11, wherein the copy delay time length is increased according to the slow skew of the transistor skew, and the copy delay time length is decreased according to the fast skew of the transistor skew. The operation method according to claim 9, further comprising a step of providing the control clock according to an enable signal.

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