JP2004328459A - Clock recovery circuit and semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a clock recovery circuit and a semiconductor integrated circuit for reducing malfunctions in phase control. <P>SOLUTION: The clock recovery circuit comprises a phase comparison circuit 3, capable of executing phase comparison between an input clock signal and a comparison subject clock signal to which an internal clock signal is fed back, a counter 24 for counting the phase comparison result in the phase comparison circuit, a decoder circuit 20 for decoding the counted value from the counter, and a control circuit 4 capable of controlling the generation of the internal clock signal, based on the decoding result from the decoder. The clock recovery circuit is set so that it does not produce jitters, when the phase of an output clock signal changes temporarily, by establishing a blind zone where a decoding output is not updated, when an output code of the counter enters into a range established beforehand. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a clock recovery circuit and a semiconductor integrated circuit incorporating the same.
[0002]
[Prior art]
As an example of a semiconductor integrated circuit that operates synchronously with a clock signal, a clock synchronous SRAM (static random access memory) is known. In such a semiconductor integrated circuit, a clock recovery circuit is used to synchronize the timing of fetching write data with a clock signal. As an example of the clock recovery circuit, a DLL (Delay Locked Loop) circuit that generates an internal clock signal based on an input clock signal is used.
[0003]
As such a DLL circuit, for example, a DLL circuit having an accumulation register for respectively holding a plurality of phase comparison results in a phase comparison circuit, and adjusting a delay time using the plurality of phase comparison results Is known (for example, see Patent Document 1). At this time, the phase adjustment is not performed for each phase comparison, but is performed once for a plurality of phase comparison results. Thereby, an extra adjustment operation is omitted. The phase comparison circuit outputs three types of determination results: a lead signal, a delay signal, and a coincidence signal. In the majority circuit, based on the above three types of determination results, the activation state of the delay increase signal, the activation state of the delay decrease signal, and when it is determined that the phases match, both the delay increase signal and the delay decrease signal are determined. It has three states that are inactive.
[0004]
[Patent Document 1]
JP 2001-290555 A (FIG. 2, paragraphs 26 and 40)
[0005]
[Problems to be solved by the invention]
When trying to remove jitter due to power supply or signal noise, there is a trade-off between phase tracking and jitter removal. That is, if the priority is given to the phase tracking, the jitter removal capability is reduced, and if the jitter removal is given priority, the phase tracking is deteriorated. In addition, the optimum design values of the phase follow-up property and the jitter removal ability differ depending on the used frequency and the mounting situation. In order to make an optimal decision, it is necessary to provide a wide range of sampling decision methods. On the other hand, in the above-described conventional method, majority decision is taken for a plurality of phase comparison results. No consideration is given to providing a range of methods.
[0006]
For example, assuming that the up signal is output four times and the down signal is output five times as a result of the phase comparison in the phase comparison circuit, according to the majority decision technique, the number of down signals is larger than the number of up signals. Therefore, the delay control is performed so as to reduce the amount of delay in the variable delay circuit. However, under the above conditions, there is a similar probability that the up signal is output five times and the down signal is output four times. In this case, the delay control is performed so as to increase the delay amount in the variable delay circuit. This is the cause of the jitter, which causes a malfunction of the phase control.
[0007]
An object of the present invention is to provide a technique for reducing malfunction of phase control.
[0008]
[Means for Solving the Problems]
The outline of a representative invention among the inventions disclosed in the present application will be briefly described as follows.
[0009]
That is, a phase comparison circuit capable of performing a phase comparison between an input clock signal and a comparison target clock signal to which an internal clock signal is fed back, a counter for counting a phase comparison result in the phase comparison circuit, And a control circuit capable of controlling the generation of the internal clock signal based on the decoding result from the decoder, wherein the output code of the counter is set in advance in the decoder circuit. A dead zone in which the decoded output is not updated when it falls within the specified range is set.
[0010]
According to the above means, since the dead band is set in the decoder circuit, the phase control is not performed when the code output from the counter enters the dead band. For this reason, when the phase of the output clock signal is temporarily changed due to power supply noise or the like, phase control is not performed due to the dead zone, and jitter does not occur. At this time, by setting the decoding logic of the decoder circuit in advance in relation to the output code of the counter, the dead zone can be easily set.
[0011]
A second phase comparison circuit capable of performing a phase comparison between the input clock signal and a comparison target clock signal to which the internal clock signal is fed back; counting the input clock signal; and setting a flag based on the count result. A flag counter to be formed and a selector capable of selectively transmitting an output signal of the decoder and an output signal of the second phase comparison circuit to the control circuit according to a state of the flag can be provided. Thereby, during the period from when the flag changes from the high level to the low level by the flag counter, the dead zone is set when the output signal of the coarse phase comparator is selectively transmitted to the delay control circuit by the selector. Since the phase control is performed without being performed, the convergence of the phase control can be accelerated and the lock-in time can be shortened accordingly.
[0012]
At this time, the selector transmits the output signal of the second phase comparison circuit to the control circuit based on the flag in the first state before the count value of the flag counter reaches a predetermined value, and The output signal of the second phase comparison circuit may be transmitted to the control circuit based on the flag in the second state in which the count value has reached a predetermined value. A second phase comparison circuit capable of performing a phase comparison between the input clock signal and a comparison target clock signal to which the internal clock signal is fed back; a second phase comparison circuit to which the input clock signal and the internal clock signal are fed back; A phase difference detection circuit capable of detecting a phase difference from a clock signal; and selectively controlling an output signal of the decoder circuit and an output signal of the second phase comparison circuit based on a detection result of the phase detection circuit. By providing a selector that can be transmitted to the circuit, when the phase difference between the clock signal and the comparison target clock signal is large, the amount of phase transition is increased, and the phase difference between the clock signal and the comparison target clock signal is increased to some extent. If the number becomes too small, the phase transition amount is reduced to speed up the convergence of the phase control and shorten the lock-in time. Door can be.
[0013]
Further, in order to make the width of the dead zone variable by the mode signal, the decoder circuit includes a plurality of decoders having different dead zone widths and a selection circuit capable of selecting the plurality of decoders according to the mode signal. Good. The mode signal can be, for example, a signal output from a fuse circuit whose logic can be set by blowing the fuse, a signal supplied from outside the chip, or a signal output from a JTAG circuit for circuit diagnosis. When the mode signal is a signal output from the fuse circuit, the dead zone can be set to an appropriate width for each chip based on a wafer inspection result. If the mode signal is a signal given from outside the chip, or a signal output from a JTAG (Joint Test Action Group: an internal control scanning method based on IEEE) circuit, the signal is mounted even after the chip is cut out. The dead zone can be set to an appropriate width according to the system. Further, when the system is mounted on a system in which the clock frequency is lowered by the low power consumption mode signal, the dead zone can be set to an appropriate width according to the logic of the low power consumption mode signal.
[0014]
For application to a DLL circuit, a variable delay circuit capable of delaying the input clock signal under the control of the control circuit can be provided. In this case, the variable delay circuit can delay the input clock signal. A plurality of unit delay stages may be provided, and the control circuit may include a timing control circuit for causing a delay time control timing of the unit delay stage to follow a delay time of the unit delay stage. The timing control circuit may include a plurality of second unit delay stages arranged corresponding to the plurality of unit delay stages in the variable delay circuit.
[0015]
The variable delay circuit includes a fine adjustment delay circuit for finely adjusting the delay amount of the input clock signal, and a coarse adjustment delay circuit for delaying the output signal of the fine adjustment delay circuit; A fine adjustment control circuit for controlling the operation of the fine adjustment delay circuit, a coarse adjustment control circuit for controlling the operation of the coarse adjustment delay circuit, and the fine adjustment delay circuit for carrying the carry signal output from the fine adjustment control circuit. And a latch circuit for transmitting the signal to the coarse adjustment control circuit in synchronization with the output signal of the circuit.
[0016]
The coarse delay circuit includes a plurality of third unit delay stages capable of delaying the output signal of the fine delay circuit, and the coarse control circuit sets a delay time control timing of the third unit delay stage. It can be configured to include a second timing control circuit for following the delay time in the third unit delay stage.
[0017]
The second timing control circuit may include a plurality of fourth unit delay stages arranged corresponding to the plurality of third unit delay stages in the coarse delay circuit, and the output of the fine delay circuit By delaying the signal by the fourth unit delay stage, a timing signal for causing the delay time control timing of the third unit delay stage to follow the delay time of the third unit delay stage can be obtained.
[0018]
The coarse delay circuit includes a plurality of first inverters connected in series to each other, a plurality of second inverters arranged corresponding to the first inverters, and a plurality of the plurality of second inverters that can be connected to each other in series. A plurality of second switches arranged between the first switch, the first inverter, and the corresponding second inverter, and capable of transmitting an output signal of the first inverter to the corresponding second inverter. And the third unit delay stage can be formed by including the first inverter and the corresponding second inverter.
[0019]
In the layout of the coarse delay circuit and the second timing control circuit in the coarse control circuit, the arrangement wiring pitch can be equal to each other, and the signal propagation directions can be equal to each other.
[0020]
A semiconductor integrated circuit can be configured to include the clock recovery circuit having the above configuration and data holding means for capturing data in synchronization with the internal clock signal obtained thereby.
[0021]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 shows a main part of an SRAM which is an example of a semiconductor integrated circuit according to the present invention.
[0022]
Although not particularly limited, the SRAM 10 takes in an input buffer 7 for taking in write data DATA to a memory cell array (not shown) into a chip, and takes in data DATAINT taken in via the input buffer in synchronization with an internal clock signal CLKINT. Input register 8, a clock input buffer 1 for taking in an external clock signal CLK into the chip, and an internal clock signal CLKINT by delaying a clock signal CLKR taken in via the clock input buffer 1. And a clock distribution buffer 5 for transmitting a clock signal output from the DLL circuit 9 to a clock input terminal of the data input register 8, and a known semiconductor integrated circuit manufacturing technique. By It is formed on a semiconductor substrate such as a single crystal silicon substrate. The output data WDATA of the data input register 8 is written to a memory cell array via a write circuit (not shown).
[0023]
Here, the data input register 8 is an example of a data holding unit.
[0024]
The DLL circuit 9 is not particularly limited, but is equivalent to the variable delay circuit 2 that delays the input clock signal CLKR based on the control signal CNT [n: 0] from the delay control circuit 4 and the clock distribution buffer 5. A dummy circuit 6 having a delay time for delaying the output clock signal CLKD of the variable delay circuit 2, and comparing the phase of the output clock signal CLKF of the dummy circuit 6 with the output clock signal CLKR of the clock input buffer 1. A phase comparison circuit 3 for performing the operation; a counter 24 for counting the output signals UP and DN of the phase comparison circuit 3; a decoder circuit 20 for decoding the output code CODE [k: 0] of the counter 24; Clock delay time in the variable delay circuit 2 based on the decode outputs UP0 and DN0 of the decoder circuit 20 And a controllable delay control circuit 4.
[0025]
The phase comparison circuit 3 compares the phases of the clock signal CLKF and the clock signal CLKR in each successive cycle, and determines the logic of the up signal UP and the down signal DN according to the result of the phase comparison. Although not particularly limited, in the phase comparison circuit 3, when the clock signal CLKF is later than the clock signal CLKR, the up signal UP is at a low (L) level and the down signal DN is at a high (H) level. On the other hand, when the clock signal CLKF is earlier than the clock signal CLKR, the up signal UP is at a high level and the down signal DN is at a low level. Further, when the phases of the clock signal CLKF and the clock signal CLKR match, both the up signal UP and the down signal DN are set to low level.
[0026]
The counter 24 counts up (increment) when the amplifier signal UP is at a high level, and counts down (decrement) when the down signal is at a high level. Then, the count result is output by the code CODE [k: 0] every successive cycle.
[0027]
FIG. 2 shows a truth table of the decoder circuit 20.
[0028]
The decoder circuit 20 decodes the code CODE [k: 0] output from the counter 24 and determines the logic of the up control signal UP0 and the down control signal DN0. Although not particularly limited, if the code CODE [k: 0] output from the counter 24 does not fall between the preset threshold a and the threshold b, the up control signal UP0 and the down control signal DN0 Are both low level. When the code CODE [k: 0] output from the counter 24 is equal to or larger than the threshold value b, the up control signal UP0 is set to the high level, and the code CODE [k: 0] output from the counter 24 is set to the threshold value a. In the following cases, the down control signal DN0 is set to the high level.
[0029]
More specifically, decoding is performed as shown in FIG. 2 in relation to the output code of the counter 24 that counts the output signals UP and DN of the phase comparison circuit 3.
[0030]
For example, if the number of times that UP goes high (H) is equal to or greater than the number of times that DN goes high (H) plus 5, the output code of the counter 24 is c (b) to c (m). The number of times that UP becomes high (H) level is larger than the value obtained by subtracting 5 from the number of times that DN becomes high (H) level, and 5 is added to the number of times that DN becomes high (H) level. If it is smaller than the value, the output code of the counter 24 is c (a + 1) to c (b-1), and the number of times UP goes high (H) level is 5 times the number of times DN goes high (H) level. Is less than or equal to the value obtained by subtracting c, the output codes of the counter 24 are c (1) to c (a). When the output codes of the counter 24 are c (b) to c (m), the up control signal UP0 is at a high (H) level and the down control signal DL0 is at a low (L) level. In this case, assuming that the current delay amount of the variable delay circuit 2 is td, the next update value is td + Δtd. When the output code of the counter 24 is c (a + 1) to c (b-1) (when it is a dead zone), both the up control signal UP0 and the down control signal DL0 are set to low (L) level. In this case, the delay amount of the variable delay circuit 2 is not updated. When the output codes of the counter 24 are c (1) to c (a), the up control signal UP0 is at a low (L) level and the down control signal DL0 is at a high (H) level. In this case, the next update value of the variable delay circuit 2 is set to td−Δtd.
[0031]
The delay control circuit 4 maintains the current delay time of the variable delay circuit 2 when both the up control signal UP0 and the down control signal DN0 are set to the low level by the decoding circuit 20. In other words, even though the up signal UP or the down signal DN is set to the high level by the phase comparison circuit 3, the code CODE [k: 0] output from the counter 24 is larger than the threshold value a. , The delay time in the variable delay circuit 2 is not updated. In this sense, a band in which the code CODE [k: 0] output from the counter 24 is larger than the threshold a and smaller than the threshold b is referred to as a “dead zone”. The thresholds a and b that determine the width of the dead zone are set to optimal values in consideration of the delay time of the input buffer circuit, noise included in the power supply voltage, and the like when designing the SRAM 10.
[0032]
Further, when the up control signal UP0 is set to the high level by the decoding circuit 20, the delay control circuit 4 updates the delay time in the variable delay circuit 2 from td by Δtd to td + Δtd. . When the down control signal DN0 is set to the high level, the delay control circuit 4 updates the delay time in the variable delay circuit 2 from td by Δtd to td−Δtd.
[0033]
When the phase difference between the output clock signal CLKF of the dummy circuit 6 and the output clock signal CLKR of the clock input buffer 1 is small, both the up control signal UP0 and the down control signal DN0 are set to low level by the decoding circuit 20. Even if the timing of the output clock signal CLKF of the dummy circuit 6 temporarily fluctuates due to noise or the like, such fluctuation does not affect the control of the delay time in the variable delay circuit 2 due to the presence of the dead zone. .
[0034]
FIG. 3 shows that the noise distribution is assumed to be a normal distribution, and the determination value probability in the phase comparison circuit 3 when the phase of the output clock signal CLKF of the dummy circuit 6 is earlier than the phase of the output clock signal CLKR of the clock input buffer 1. Properties are indicated. In FIG. 3, the vertical axis represents the phase difference between the clock signal CLKF and the clock signal CLKR, and the horizontal axis represents the probability.
[0035]
The probability that the up signal UP will be at the high level is indicated by the area S1, the probability that the down signal DN will be at the high level is indicated by the area S3, and the probability that both the up signal UP and the down signal DN are the low level is the area S2. Indicated by In the determination value probability characteristic of FIG. 3, the clock signal CLKF is earlier than the phase of the clock signal CLKR, and the difference between the areas S1 and S3 is large. In such a case, the up control signal UP0 is set to the high level.
[0036]
FIG. 4 shows a phase comparison circuit 3 in a case where the noise distribution is assumed to be a normal distribution, and the phase of the output clock signal CLKF of the dummy circuit 6 and the phase of the output clock signal CLKR of the clock input buffer 1 substantially match. A decision value probability characteristic is shown. Since the difference between the areas S1 and S3 is small, both the up control signal UP0 and the down control signal DN0 are determined to be low level due to the presence of the dead zone.
[0037]
FIG. 5 shows a more specific configuration example of the DLL circuit 9.
[0038]
The DLL circuit 9 shown in FIG. 5 is greatly different from that shown in FIG. 1 in that a counter clock generation circuit 2 for generating a counter clock based on an output clock signal CLKR of a clock input buffer 1 and a clock input buffer A divide-by-16 circuit 23 for dividing the output clock signal CLKR of 1 by 16, a reset signal generation circuit 26 for generating a reset signal of the counter 24 based on the output clock CLK16 of the divide-by-16 circuit 23; In addition, registers 22A and 22B for taking in the output signals UP1 and DN1 of the decoder circuit 20 based on the output clock CLK16 of the 16 frequency dividing circuit 23 are provided.
[0039]
The delay control circuit 4 controls the operation of the variable delay circuit 2 based on the up control signal UP1 output from the register 22A and the down control signal DN1 output from the register 22A.
[0040]
The counter 24 includes an up signal input terminal up for receiving an up signal UP, a down signal input terminal dn for receiving a down signal DN, a clock input terminal ck for receiving a clock signal for a count operation, and a reset signal RS. Has an input terminal rst.
[0041]
The decoder circuit 20 decodes the count output CODE [k: 0] of the counter 24 and decodes the count output CODE [k: 0] of the counter 24 to obtain the up control signal UP0. And a decoding unit 20B for obtaining the down control signal DN0. The truth table of the decoder circuit 20 is as shown in FIG. The decoding unit 20A sets the up control signal UP0 to high level only when the number of times UP goes high is equal to or more than the value obtained by adding 5 to the number of times DN goes high, otherwise the up control signal UP UP0 is set to low level. Also, the decoding unit 20B sets the down control signal DN0 to high level only when the number of times that UP goes high is less than or equal to a value obtained by subtracting 5 from the number of times that DN goes high, The control signal DN0 is set to low level.
[0042]
The reset signal of the counter 24 is generated based on the output clock signal CLK16 of the 16-frequency divider 23, and the writing of the output signals UP0 and DN0 of the decoder circuit 20 to the registers 22A and 22B is controlled. The delay control by the delay control circuit 4 is performed once every 16 cycles of CLKR.
[0043]
FIG. 6 shows the operation timing of the main part in the DLL circuit 9 shown in FIG. 5, and FIG. 7 shows the output code CODE [k: 0] from the counter 24 and the corresponding decoder circuit 20 of the decoder circuit 20. The relationship with output signals UP0 and DN0 is shown.
[0044]
In the above configuration, the counter 24 sets the counter value to the initial value c (8) by the reset signal RS. When the counter 24 captures the high level of the up signal UP output from the phase comparison circuit 3 with the counter clock signal CLKS from the counter clock generation circuit 25 as a trigger, it changes the count value from c (k) to c (k + 1). Increment. When the counter 24 captures the high level of the down signal DN output from the phase comparison circuit 3 using the counter clock signal CLKS from the counter clock generation circuit 25 as a trigger, the counter 24 changes the count value from C (k) to c (k). Decrement to -1). The counter clock signal CLKS is continuously generated by the clock generation circuit 25 for eight cycles, and after the counting operation of the eighth cycle is completed, the counter clock signal CLKS is transmitted to the registers 22A and 22B in synchronization with the frequency-divided-by-16 clock signal CLK and transmitted to the decode circuit 20. Output values UP1 and UP2 are captured.
[0045]
FIG. 8 shows an example of a decoder output with respect to the number of appearances of the determination value in the phase comparison circuit 3. As shown in FIG. 8, when the number of times the up signal UP goes high and the number of times the down signal DN goes high are close (in the example shown in FIG. 8, when the difference is 4 or less), Due to the dead zone, both outputs UP0 and DN0 of the decoder circuit 20 are set to low level.
[0046]
FIG. 23 shows a circuit to be compared with DLL circuit 9 shown in FIG. 5, and FIG. 24 shows operation timings of main parts in DLL circuit 90 shown in FIG.
[0047]
In the DLL circuit 90 shown in FIG. 23, since the output signals UP and DN of the comparison circuit 3 are transmitted to the delay control circuit 4 at the subsequent stage, no dead zone is set. Therefore, the delay control circuit 4 directly controls the delay time of the variable delay circuit 2 according to the up signal UP and the down signal DN, as shown in FIG. In FIG. 24, tDR is the delay time of the clock input buffer 1 and the data input buffer 7, tVDL is the delay time of the variable delay circuit, tBF is the delay time of the clock distribution buffer and the dummy circuit, and CNT (k) is the delay control circuit. Is the code value of
[0048]
FIG. 9 shows an example of phase transition in DLL circuit 90 shown in FIG.
[0049]
Since no dead zone is set in the DLL circuit 90, as shown in FIG. 9, even after the phase is once matched, the setting of the variable resistance circuit always fluctuates due to the influence of noise. On the other hand, in the DLL circuit 9 shown in FIG. 5, as shown in an example of phase transition in FIG. 10, the period T2 becomes longer than T1 due to the fact that sampling is performed a plurality of times. Although the lock-in time becomes longer, the setting of the variable delay circuit 2 is not updated once the phases match because the dead zone is set, so that errors due to noise are eliminated.
[0050]
FIG. 11 shows a configuration example of the phase comparison circuit 3.
[0051]
A first logic circuit 31 for asserting a down signal DN by comparing a phase between an output clock signal CLKF of the dummy circuit 6 and an output clock signal CLKR of the clock input buffer 1; and an output clock signal CLKF of the dummy circuit 6 A second logic circuit 32 for asserting the up signal UP by comparing the phase with the output clock signal CLKR of the clock input buffer 1. The first control logic circuit 31 includes NAND gates 301 to 305, 308, 309, and 312, inverters 306, 310, 311 and 313, and a MOS transistor 307. The MOS transistor 307 is arranged between the output terminal of the NAND gate 302 that takes in the output clock signal CLKF of the dummy circuit 6 and the low potential power supply VSS, and functions as a capacitive load of the NAND gate 302. The NAND gate 301 is a dummy circuit. The second control logic circuit 32 includes NAND gates 321 to 325, 328, 329, 332, inverters 326, 330, 331, 333, and a MOS transistor 327. The MOS transistor 327 is arranged between the output terminal of the NAND gate 323 that captures the output clock signal CLKR of the clock input buffer 1 and the low potential power supply VSS, and functions as a capacitive load for the NAND gate 323. The NAND gate 321 is a dummy circuit. When the phase of the clock signal CLKF is later than the phase of the clock signal CLKR, the second logic circuit 32 asserts the up signal UP to a high level. At this time, since the output signal of the inverter 330 is at a low level, the output signal of the NAND gate 312 is at a high level, and accordingly, the down signal DN is at a low level. When the phase of the clock signal CLKF is earlier than that of the clock signal CLKR, the down signal DN is asserted to a high level by the second logic circuit 32. At this time, since the output signal of the inverter 311 is at a low level, the output signal of the NAND gate 312 is at a high level, and accordingly, the up signal UP is at a low level. Reset signal RESET is transmitted to NAND gates 302, 304, 308 via inverter 306, and transmitted to NAND gates 322, 324, 328 via inverter 326. When the reset signal RESET is set to the high level, the first logic circuit 31 and the second logic circuit 32 are initialized.
[0052]
As described above, in the configuration shown in FIG. 5, the period T2 is longer than T1, and the lock-in time is longer, and the dead zone is set, because the counter 24 performs sampling a plurality of times. Thus, once the phases are matched, the setting of the variable delay circuit 2 is not updated, so that an error due to noise is eliminated.
[0053]
According to the above example, the following effects can be obtained.
[0054]
(1) Since the dead band is set in the decoder circuit 20, the code CODE [k output from the counter 24 is output even though the up signal UP or the down signal DN is set to the high level by the phase comparison circuit 3. : 0] is larger than the threshold value a and smaller than the threshold value b, the delay time in the variable delay circuit 2 is not updated. By setting the dead zone in this manner, even if the phase of the output clock signal of the dummy circuit 6 is temporarily changed due to power supply noise or the like, jitter does not occur. Here, a technique of taking a majority decision of the phase comparison result and controlling the variable delay circuit based on the majority decision result is known, but it is better to set a dead zone as in the above example for noise resistance. . For example, assuming that the up signal is output four times and the down signal is output five times as a result of the phase comparison in the phase comparison circuit, the number of down signals is smaller than the number of up signals according to the majority decision technique. Because of the large number, the delay control is performed so as to reduce the delay amount in the variable delay circuit, and the delay amount in the variable delay circuit is increased when it is assumed that the up signal is output five times and the down signal is output four times. The delay control is performed as described above, and this causes jitter. On the other hand, according to the above example, when the number of up signals is close to the number of down signals, the dead amount of the variable delay circuit is not updated due to the dead zone, so that no jitter occurs. Thereby, it is possible to reduce the malfunction of the phase control.
[0055]
(2) The threshold values a and b for determining the width of the dead zone can be set to optimal values in consideration of the delay time of the input buffer circuit, noise included in the power supply voltage, and the like when designing the SRAM 10. Specifically, the width of the dead zone is set by presetting the decoding logic of the decoder circuit 20 in relation to the result of the phase comparison in the phase comparison circuit 3 and the result counted by the counter 24. There is a trade-off between the phase tracking performance of the DLL circuit 9 and the jitter elimination ability, and the optimal design of this relationship depends on the frequency used and the mounting situation. By setting the dead zone, the judgment of the phase comparison result can be given a wide range. Therefore, by appropriately changing the use frequency of the SRAM 10 and the mounting state, the phase followability of the DLL circuit 9 can be improved. The relationship with the jitter elimination ability can be optimized.
[0056]
(3) Since the phase of the clock signal CKINT can be accurately matched by optimizing the relationship between the phase following property and the jitter removing ability of the DLL circuit 9, the SRAM 10 is formed by the DLL circuit 9. Since the setup and hold margin at the time of taking in the write data DATAINT in synchronization with the clock signal CLKINT are improved, the reliability of the data written in the memory cell can be improved.
[0057]
Next, another configuration example of each unit in the DLL circuit 9 will be described.
[0058]
The counter 24 can be configured to output a gray code. FIG. 12 shows the relationship between the gray code CODE [k: 0] output from the counter 24 and the corresponding output signals UP0 and DN0 of the decoder circuit 20. In this example, the code generated by the counter 24 is a 5-bit gray code. By using a gray code, the number of bits that fluctuate from an adjacent code can be minimized, so that noise called “glitch” hardly occurs in the output of the counter 24.
[0059]
FIG. 13 shows another configuration example of the decoder circuit 20. FIG. 14 shows a truth table of the decoder circuit 20 shown in FIG.
[0060]
The decoder circuit 20 shown in FIG. 13 includes decoding units 20A-1, 20A-2, 20B-1, and 20B-2 for decoding the code CODE [k: 0] output from the counter 24, and a mode signal MODE. A selector circuit 201 for selectively outputting the output signals of the decoding units 20A-1 and 20A-2 to the outside based on the output signal of the decoding units 20B-1 and 20B-2 based on a mode signal MODE And a selector circuit 201 for externally outputting the signal. The width of the dead zone can be changed by selecting a decoder in the selector circuits 201 and 202. For example, as shown in FIG. 14, when the mode signal MODE is set to the high (H) level, the output signal of the decoding unit 20A-1 is selected by the selector circuit 201, and the output signal of the decoding unit 20B-1 is selected by the selector circuit 202. When the output signal is selected, the code CODE [k: 0] sets a dead band in a relatively wide range from c (12) to c (4), whereas the mode signal MODE is When the output signal of the decoding unit 20A-2 is selected by the selector circuit 201 by the low (L) level and the output signal of the decoding unit 20B-2 is selected by the selector circuit 202, the code CODE [ k: 0] is c (10) to c (6), and the dead zone is set in a relatively narrow range. The mode signal can be, for example, a signal output from a fuse circuit whose logic can be set by blowing the fuse, a signal supplied from outside the chip, or a signal output from a JTAG circuit for circuit diagnosis. When the mode signal is a signal output from the fuse circuit, the dead zone can be set to an appropriate width for each chip based on a wafer inspection result. If the mode signal is a signal given from outside the chip, or a signal output from a JTAG (Joint Test Action Group: an internal control scanning method based on IEEE) circuit, the signal is mounted even after the chip is cut out. The dead zone can be set to an appropriate width according to the system. Further, when the system is mounted on a system in which the clock frequency is lowered by the low power consumption mode signal, the dead zone can be set to an appropriate width according to the logic of the low power consumption mode signal.
[0061]
FIG. 15 shows another configuration example of the DLL circuit 9. The DLL circuit 9 shown in FIG. 15 is greatly different from that shown in FIG. 5 in that a coarse phase comparison circuit 30, a flag counter 34, selectors 35A and 35B, and two frequency dividing circuits 33A and 33B are provided. It is.
[0062]
The divide-by-2 circuit 33A divides the frequency of the clock signal CLKR input via the clock input buffer 1 by 2, and the divide-by-2 circuit 33B divides the frequency of the clock signal CLKF output from the dummy circuit 6 by 2. Output clock signals CLKRR and CLKFF of the divide-by-2 circuits 33A and 33B are input to the phase comparison circuit 3. The phase comparison circuit 3 compares the phases of the input clock signals CLKRR and CLKFF. The counter clock generation circuit 25 generates a counter clock signal CLKS based on the output clock signal CLKRR of the divide-by-2 circuit 33A. The divide-by-16 circuit 23 generates the clock signal CLK16 by dividing the output clock signal CLKRR of the divide-by-2 circuit 33A by 16. The coarse adjustment phase comparison circuit 30 compares the phases of the clock signals CLKRR and CLKFF. The flag counter 34 is reset when the reset signal is set to the high level, and thereafter switches the flag signal FLG from the previous high level to the low level after a lapse of a predetermined time from the reset by counting the clock signal CLKR. Has functions. This flag signal FLG is transmitted to selectors 35A and 35B. In the selectors 35A and 35B, the output signals UP1 and DN1 of the registers 22A and 22B and the output signals UPC and DNC of the coarse phase comparator 30 are selectively selected according to the logic of the flag signal FLG. To communicate.
[0063]
FIG. 16 shows the operation timing of the main part in DLL circuit 9 shown in FIG.
[0064]
During the period from when the flag counter 34 is reset by the reset signal RESET to when the flag FLG transitions from the high level to the low level by the flag counter 34, the output signals UPC, DNC of the coarse adjustment phase comparison circuit 30 by the selectors 35A, 35B. Is selectively transmitted to the delay control circuit 4, and delay control is performed based on the signal. In this delay control, since no dead zone is set, the delay control cycle is set to T1, which is shorter than T2 in the configuration shown in FIG. Therefore, the phase difference between the clock signals CLK and CLKR becomes smaller in a short time. After the flag FLG is changed from the high level to the low level by the flag counter 34, the output signals UP1 and DN1 of the registers 22A and 22B are selectively transmitted to the delay control circuit 4 by the selectors 35A and 35B. Delay control is performed. In this delay control, since a dead zone is set as in the case of the configuration shown in FIG. 5, delay control with excellent noise resistance is performed.
[0065]
During the period from the reset of the flag counter 34 by the reset signal RESET to the transition of the flag FLG from the high level to the low level by the flag counter 34, the output signals of the coarse adjustment phase comparison circuit 30 by the selectors 35A and 35B. Since the UPC and DNC are selectively transmitted to the delay control circuit 4 and the delay control is performed based thereon, the delay control cycle becomes shorter as compared with the configuration shown in FIG. Lock-in time can be reduced.
[0066]
FIG. 17 shows another configuration example of the DLL circuit 9.
[0067]
The DLL circuit 9 shown in FIG. 17 is significantly different from that shown in FIG. 15 in that 16 frequency divider circuits 23A and 23B are provided at the subsequent stage of the frequency divider circuits 2A and 33B, and the 16 frequency divider circuits 23A and 23B The difference lies in that the output clock signals CLKRC and CLKFC are supplied to the coarse adjustment phase comparison circuit 30 and that the output signal FLG of the flag counter 34 is supplied to the delay control circuit 4.
[0068]
FIG. 18 shows the operation timing of the main part in DLL circuit 9 shown in FIG. When the output signal FLG from the flag counter 34 is at a high level, the delay control circuit 4 sets the phase transition between the clock signals CLKF and CLKR at intervals of 4Δt, and when the output signal FLG from the flag counter 34 is at a low level. Assumes that the phase transition between the clock signals CLKF and CLKR is in increments of Δt. Further, in the coarse adjustment phase comparison circuit 30, since the coarse adjustment phase comparison is performed based on the output signals of the 16 frequency dividing circuits 23A and 23B, the output signals UPC and DNC of the coarse adjustment phase comparison circuit 30 are provided. The delay control cycle in the delay control based on is defined as T2. As described above, by making the phase transition largely change at intervals of 4Δt until the flag FLG becomes low level, and making the phase transition at intervals of Δt after the flag FLG becomes high level, the lock-in can be more improved than in FIG. Time can be reduced.
[0069]
FIG. 19 shows another configuration example of the DLL circuit 9.
[0070]
The DLL circuit 9 shown in FIG. 19 is significantly different from that shown in FIG. 17 in that the phase difference between the output clock signal CLKRR of the divide-by-2 circuit 33A and the output clock signal CLKFF of the divide-by-2 circuit 33B is detected. In that a phase difference detection circuit 40 is provided. In the configuration shown in FIG. 17, the clock signal CLKR is counted by the flag counter 34, and the logic of the flag signal FLG is determined based on the count result. However, according to the configuration shown in FIG. The logic of the flag signal FLG is determined based on the result of the phase difference detection at 40. That is, when the phase difference between the clock signals CLKRR and CLKFF exceeds a predetermined value, the flag signal FLG is set to a high level, and when the phase difference between the clock signals CLKRR and CLKFF becomes smaller than the predetermined value, , The flag signal FLG is set to the low level. Accordingly, when the phase difference between the clock signals CLKRR and CLKFF is large, the amount of phase transition is increased, and when the phase difference between the clock signals CLKRR and CLKFF is reduced to some extent, the amount of phase transition is reduced. Therefore, the same effect as that shown in FIG. 17 can be obtained.
[0071]
In the above example, the dead zone is digitally provided by setting the decoding logic in the decoder circuit 20. However, in addition to the setting of the dead zone in the decoder circuit 20, the dead band is set in the phase comparison circuit 3. Is also good.
[0072]
FIG. 20 shows a simulation result of the phase error with respect to the dead band width of the phase comparison circuit 3. As is clear from FIG. 20, when the minimum step width of the variable delay circuit 2 is Δt, the phase error is minimized when the dead band width in the phase comparison circuit 3 is near Δt. Further, when the dead band width in the coarse adjustment phase comparison circuit 30 is set to around 2Δt, the phase error is minimized. When the phase comparison circuit 3 and the coarse phase comparison circuit 30 are configured as shown in FIG. 11, the dead band width in the phase comparison circuit 3 and the coarse phase comparison circuit 30 is determined by the gate capacitance of the MOS transistors 307 and 327. Therefore, by adjusting the gate capacitance value, the dead band width can be set to an optimum value.
[0073]
In the example illustrated in FIG. 2, in the control of the variable delay circuit 2, a case where the variable delay circuit 2 is updated to td + Δtd, a case where the variable delay circuit 2 is not updated due to the dead zone, and a case where the variable delay circuit 2 is updated to td−Δtd are described. Not something. For example, as shown in FIG. 21, it is possible to set the relationship between the output code of the counter 24 and the output of the decoder circuit 20. That is, in the example shown in FIG. 21, in the control of the variable delay circuit 2, the variable delay circuit 2 is updated to td + 2Δtd, td + Δtd, not updated due to the dead zone, and updated to td−Δtd. And a case of updating to td−2Δtd may be set. Compared to the case shown in FIG. 2, a case of updating to td + 2Δtd and a case of updating to td−2Δtd are added, and when the phase difference is relatively large, the amount of one phase transition is increased. Therefore, the following performance of the DLL circuit 9 can be improved.
[0074]
FIG. 22 shows another configuration example of the DLL circuit 9.
[0075]
In the configuration shown in FIG. 22, variable delay circuits 2A and 2B are connected in series, and an output signal of DLL circuit 9 is taken out from the series connection node. According to such output signal extraction, a clock signal CLKINT having a phase difference of 180 degrees with respect to the input clock signal CLK can be obtained, and data can be fetched in synchronization with such a clock signal CLKINT. Is The variable delay circuits 2A and 2B are each equal to the variable delay circuit 2.
[0076]
Next, the variable delay circuit 2 and the delay control circuit 4 will be described in detail.
[0077]
FIG. 25 shows a configuration example applicable as the variable delay circuit 2 and the delay control circuit 4.
[0078]
The variable delay circuit 2 includes a fine delay circuit 210 for finely adjusting the delay amount of the clock signal input from the input terminal in, and a delay amount of the output clock signal of the fine delay circuit 210 provided at a stage subsequent thereto. And a coarse adjustment delay circuit 220 for performing the coarse adjustment. The fine delay circuit 210 and the coarse delay circuit 220 each include a plurality of unit delay stages. The delay control circuit 4 includes a fine adjustment control circuit 410 for performing the delay amount control in the fine adjustment delay circuit 210 and a coarse adjustment control circuit 420 for performing the delay amount control in the coarse adjustment delay circuit 220. Including. The variable delay circuit 2 is controlled by a control signal CNT [n: 0] from the delay control circuit 4. The control timing of the control signal CNT [n: 0] is fixed.
[0079]
26 and 27 show the operation timing of the main part in the configuration shown in FIG. The operation timing shown in FIG. 26 is when the delay time (τD_max) of the variable delay circuit is shorter than the cycle time (tc), and the operation timing shown in FIG. 27 is when the delay time (τD_max) of the variable delay circuit is shorter than the cycle time. This is the case where the time is longer than the time (tc). As shown in FIG. 26, when the delay time (τD_max) of the variable delay circuit is shorter than the cycle time (tc), the delay control is performed after the delay is determined, so that no delay control error occurs. However, when the delay time (τD_max) of the variable delay circuit is longer than the cycle time (tc), if the control timing of the control signal CNT [n: 0] is fixed, as shown in FIG. The delay control is performed before the determination, and a delay control error occurs. The inventor of the present application has found that a pulse-like noise called a glitch occurs in the output signal of the variable delay circuit 2 due to the delay control error.
[0080]
Therefore, by making the control timing of the control signal CNT [n: 0] for controlling the delay time of the variable delay circuit 2 follow the delay time of the variable delay circuit 2, the delay time (τD_max) of the variable delay circuit becomes longer than the cycle time. Even if the time is longer than (tc), a delay control error is prevented from occurring. Hereinafter, specific examples thereof will be described in detail.
[0081]
FIG. 28 shows a specific configuration example of the variable delay circuit 2 that suppresses the occurrence of the delay control error.
[0082]
The main body delay circuit 211 has a function of delaying a clock signal input from the input terminal in and outputting the delayed signal from the output terminal cfout, and includes a plurality of unit delay stages 211-0 to 211-n connected in series. Delay control circuit 4 includes a dummy delay circuit 221 and a delay control unit 400. The dummy delay circuit 221 includes a plurality of unit delay stages 221-0 to 221-n arranged corresponding to the plurality of unit delay stages 211-0 to 211-n in the main body delay circuit 211. The plurality of unit delay stages 221-0 to 221-n are connected in series with each other and have a function of sequentially delaying the output signal of the delay circuit 231. The delay circuit 231 delays the clock signal input from the input terminal in by a predetermined time and outputs the clock signal to the dummy delay circuit 221 in order to secure a setup margin in the dummy delay circuit 221. The output signals std0 to stdn of the plurality of unit delay stages 221-0 to 221-n are transmitted to the delay control circuit 4. The delay control circuit 4 adjusts the control timing of the control signal CNT [n: 0] based on the output signals std0 to stdn of the plurality of unit delay stages 221-0 to 221-n by the delay time of the main body delay circuit 211. To follow. This ensures a timing margin for the control signal CNT [n: 0]. Here, the dummy delay circuit 221 is an example of the timing control circuit in the present invention.
[0083]
FIG. 29 shows operation timings of main parts in the configuration shown in FIG. This operation timing is when the delay time (τD_max) of the variable delay circuit is longer than the cycle time (tc). FIG. 28 representatively shows control timings of control signals CNT0, CNT2, and CNTn from delay control circuit 4. The settable range of the control signal [CNTn: 0] is equal to the value obtained by subtracting the setup time and the hold time from one cycle time. The control timing of the variable delay circuit 2 is set within this settable range.
[0084]
As described above, even when the delay time (τD_max) of the variable delay circuit is longer than the cycle time (tc), the delay control can be performed after the delay is determined, and a delay control mistake can be prevented. Since this can be prevented, the cycle of the delay control can be increased.
[0085]
FIG. 30 shows another configuration example of the variable delay circuit 2 and the delay control circuit 4.
[0086]
In the configuration shown in FIG. 30, the variable delay circuit 2 includes a fine adjustment delay circuit 210 and a coarse adjustment delay circuit 220, and the delay control circuit 4 includes a fine adjustment control circuit 410, a latch circuit 232, and a dummy delay circuit. A circuit 221 and a coarse adjustment control circuit 420 are included. In this circuit, first, the fine adjustment delay circuit 210 finely adjusts the phase of the input clock signal under the control of the fine adjustment control circuit 410. If the adjustment is not sufficient, the fine adjustment control circuit 410 generates the carry signal carry. Asserted. Thus, under the control of the delay control circuit 4, the coarse adjustment delay by the coarse adjustment delay circuit 220 is performed.
[0087]
The latch circuit 232 forms the trigger signal trig by capturing the carry signal carry from the fine adjustment control circuit 410 in synchronization with the output signal fout of the fine adjustment delay circuit 210. This trigger signal trig is supplied to the dummy delay circuit 221. The dummy delay circuit 221 includes unit delay stages 221-0 to 221-n corresponding to the unit delay stages 220-0 to 220-n in the coarse delay circuit 22. The unit delay stages 221-0 to 221-n , The control signals std0 to stdn are generated by delaying the trigger signal. Since the coarse delay control is performed according to the timing of the control signals std0 to stdn, the control by the control signal CNT [n: 0] is performed following the signal delay in the coarse delay circuit 220. Therefore, as in the case shown in FIG. 28, a timing margin of control signal CNT [n: 0] is secured.
[0088]
As shown in FIG. 31, fine adjustment control circuit 410 generates a carry signal carry in response to carry or carry of fine adjustment delay circuit 210. That is, when the timing of coarse adjustment and fine adjustment (k → K + 1) and the control signal CNT [n: 0] are synchronized with the output of the fine adjustment delay circuit, the timing changes from “49” to “50”. In the case of a synchronization error with the output fout of the fine adjustment delay circuit, "49" changes to "40" and "50", or "49" changes to "59" and "50", and once "40" or "59" changes. Will be output. However, the timing of each of the control signals CNT [n: 0] is made to follow the delay time of the coarse delay circuit 220 by the output signals std0 to stdn of the dummy delay circuit 221 based on the carry signal carry, so that control is performed. The timing of the signal CNT [n: 0] is synchronized with the output signal fout of the fine adjustment delay circuit 210, and a carry error (or a carry error) can be prevented.
[0089]
FIG. 43 shows a detailed configuration example of a main part in FIG. FIG. 50 shows a detailed layout of a main part in FIG.
[0090]
The unit delay stage 220-0 is formed by combining inverters IV1, IV2, IV3, IV4, IV5 and transfer switches TM1, TM2. Inverters IV3 and IV4 are used as dummy loads. The operation of the transfer switches TM1 and TM2 is controlled by a control signal CNT0 from the coarse adjustment control circuit 420. When the control signal CNT0 is at a low level, the transfer switch TM1 is turned off and the transfer switch TM2 is turned on. At this time, the clock signal transmitted from fine delay circuit 210 is transmitted to unit delay stage 220-1 via inverter IV1, and the clock signal transmitted from unit delay circuit 220-1 is transmitted via inverter IV2 and transfer switch TM2. Output to the subsequent circuit. When the control signal CNT0 is at a high level, the transfer switch TM1 is turned on and the transfer switch TM2 is turned off. At this time, since the clock signal transmitted from the fine adjustment delay circuit 210 is output to the subsequent circuit via the inverter IV1 and the transfer switch TM1, only the unit delay stage 220-1 is involved in the signal delay of the clock signal. .
[0091]
The unit delay stage 220-1 includes inverters IV6, IV7, IV8, IV9 and transfer switches TM3, TM4. The unit delay stage 220-1 is not provided with an equivalent to the inverter IV3 in the unit delay stage 220-0. Inverters IV3 and IV4 are used as dummy loads. The operation of the transfer switches TM3 and TM4 is controlled by a control signal CNT1 from the coarse adjustment control circuit 420. When the control signal CNT1 is at a low level, the transfer switch TM3 is turned off and the transfer switch TM4 is turned on. At this time, the clock signal transmitted from unit delay stage 220-0 is transmitted to unit delay stage 220-2 via inverter IV6, and the clock signal transmitted from unit delay circuit 220-2 is transmitted to inverter IV7 and transfer switch TM4. To the unit delay stage 220-0. When the control signal CNT1 is at a high level, the transfer switch TM3 is turned on and the transfer switch TM4 is turned off. At this time, since the clock signal transmitted from unit delay stage 220-0 is transmitted to unit delay stage 220-0 via inverter IV6 and transfer switch TM3, only unit delay stages 220-1 and 220-1 output signals. Be involved in delays.
[0092]
The configurations of the unit delay stages 220-2 and 220-n are the same as those of the unit delay stages 220-0 and 220-1, respectively, and a detailed description thereof will be omitted.
[0093]
The dummy delay circuit 221 is configured corresponding to the coarse delay circuit 220. For example, the unit delay stage 221-0 corresponds to the unit delay stage 220-0 in the coarse delay circuit 220, and is formed by combining inverters IV1D, IV2D, IV3D, IV4D, IV5D, and transfer switches TM1D, TM2D. . The unit delay stage 221-1 includes inverters IV6D, IV7D, IVD8, IVD9 and transfer switches TM3D, TM4D. The control signal trigger1 is supplied from the inverter IV3D in the unit delay stage 221-0 to the coarse adjustment control circuit 420. Similarly, the control signal trigger2 is supplied to the coarse adjustment control circuit 420 from the inverter corresponding to the inverter IV3D in the unit delay stage 221-2.
[0094]
The coarse adjustment control circuit 420 includes registers 422-0 to 422-n arranged corresponding to the unit delay stages 220-0 to 220-n in the coarse adjustment delay circuit 220, and a counter 421. The registers 422-0 and 422-1 take in the output signals rgin0 and rgin1 of the counter 421 in synchronization with the trigger control signal trgn from the dummy delay circuit 221-0. As a result, the control signals CNT0 and CNT1 are updated. Similarly, the registers 422-2 and 422-n take in the output signals rgin2 and rginn of the counter 421 in synchronization with the trigger control signal trigger2 from the dummy delay circuit 221-2. Thereby, the control signals CNT2 and CNTn are updated.
[0095]
The inverter included in the coarse delay circuit 220 and the dummy delay circuit 221 includes a p-channel MOS transistor and an n-channel MOS transistor connected in series. The p-channel MOS transistor is formed in a P-well region (P_well), and the n-channel MOS transistor is formed in an N-well region (N_well) (see FIG. 50).
[0096]
FIG. 44 shows a configuration example of the counter 421 in the coarse adjustment control circuit 420.
[0097]
As shown in FIG. 44, the counter 421 includes count units 421-0 to 421-n arranged corresponding to the registers 422-0 to 422-n. The counting units 421-0 to 421-n have the same configuration. For example, the count unit 421 is configured by combining eight 2-input NAND gates 441 to 448 and an inverter 449. Each time the control signals UP0 and / UP0 (/ means signal inversion) are input, an up-count is performed, and each time DN and / DN are input, a down-count is performed.
[0098]
FIG. 32 shows a configuration example of the coarse adjustment delay circuit 220.
[0099]
As shown in FIG. 32, the coarse delay circuit 220 includes a plurality of inverters INV and switches SW1 to SW8 for switching signal paths. The switches SW1 to SW8 are transfer switches each formed by connecting a p-channel MOS transistor and an n-channel MOS transistor in parallel, and their operation is controlled by a control signal CNT [n: 0] from the coarse adjustment control circuit 420. . Each of the unit delay stages 211-0 to 211-n basically includes two inverters and two switches corresponding thereto. By switching on and off the switches SW1 to SW8, as shown in FIG. 33, states 1 to 5 having different delay amounts from each other are formed. In FIG. 33, “*” indicates that ON / OFF is optional. Therefore, if the switch state of the "*" portion is set as shown in FIG. 39, the switch SW is switched when the input and output polarities of the B-side switch are opposite. As shown in FIG. 40, an undesired waveform (glitch) occurs in the output signal cfout. As a countermeasure to prevent this glitch, the control of the delay stage is changed as shown in FIG. That is, all the A-side switches are initially set to ON and all the B-side switches are set to OFF, and the A-side switches are sequentially held OFF and the B-side switches are sequentially held ON each time the delay amount is changed. Let it do. In this case, as shown in FIG. 42, the delay time difference Δtd between the input and output of the B-side switch corresponds to one unit delay. This time difference is small, and no glitch occurs at any timing. The configuration shown in FIG. 32 is a so-called folded delay stage configuration, and can reduce the number of wirings as compared with a multiplex system in which outputs are selectively extracted from each node of a plurality of inverters connected in series. This is effective in reducing the area occupied by the chip in the circuit.
[0100]
FIG. 34 shows another configuration example of the coarse delay circuit 220.
[0101]
The unit delay stages 220-0 to 220-n include two inverters connected in series. By performing path selection using a switch provided on the output side of the unit delay stage, the unit delay stage involved in signal delay is determined. That is, a switch is arranged in each of the columns A, B, C, and n, and one switch is turned on in each of the columns A, B, C, and n to determine the delay time. You. The switches in the rows A, B, C, and n are controlled in operation by a control signal CNT [n: 0] from the coarse adjustment control circuit 420.
[0102]
FIG. 35 shows a configuration example of the fine adjustment delay circuit 210.
[0103]
Although not particularly limited, the fine adjustment delay circuit 210 includes coarse adjustment replicas 51 to 54, differential circuits 55 to 57, and inverters 59, 59.
[0104]
Coarse-adjustment replicas 51 to 54 are arranged in order to use a delay obtained by dividing a unit delay stage in the coarse-adjustment delay circuit 220 with high precision as a unit of fine adjustment. A clock signal is input to the coarse adjustment replicas 51 and 53 from an input terminal in. Clock signals from the input terminal in are input to the coarse-adjustment replicas 52 and 54 via inverters 58 and 59, respectively. The output signals of the coarse replicas 51 and 52 are differentially amplified by a differential circuit 55 at the subsequent stage, and the output signals of the coarse replicas 53 and 54 are differentially amplified by a differential circuit 56 at the subsequent stage. Then, the output signal fout1 of the coarse adjustment replica 55 and the output signal fout2 of the coarse adjustment replica 56 are differentially amplified by the differential circuit 57 at the subsequent stage, and then output. The delay amount in the coarse adjustment replicas 51 to 54 is adjusted by control signals Ckt1 to ckt4 from the fine adjustment control circuit 410.
[0105]
FIG. 36 shows an example of the configuration of the coarse replicas 51 and 52.
[0106]
As shown in FIG. 36, the coarse replica 51 includes, but is not limited to, shape dummies a3 and a4, unit delay stages a1 and a2, and an output unit 380.
[0107]
The unit delay stage a1 includes inverters 361, 362, 363 for signal delay and transfer switches 364, 365 for signal path selection. The transfer switches 364 and 365 are each formed by connecting a p-channel MOS transistor and an n-channel MOS transistor in parallel, and are complementarily turned on by a control signal CKCNT1 from the fine adjustment control circuit 410. For example, when the control signal CKCNT1 is at a high level, the transfer switch 364 is turned on, and the output signal of the inverter 361 is transmitted to the shape dummy a3 via the transfer switch 364. At this time, the transfer switch 365 is turned off. When the control signal CKCNT1 is at a low level, the transfer switch 365 is turned on, and the output signal of the inverter 363 is transmitted to the shape dummy a3 via the transfer switch 365. At this time, the transfer gate 364 is turned off.
[0108]
The unit delay stage a2 includes inverters 371, 372, and 373 for signal delay and transfer switches 374 and 375 for signal path selection, and is configured similarly to the unit delay stage a1. However, when the high-potential-side power supply Vdd is supplied, the transfer switch 374 is fixed to the conductive state, and the transfer switch 375 is fixed to the non-conductive state. As a result, the output signal of the inverter 371 is transmitted to the unit delay stage a1 via the transfer switch 374.
[0109]
The shape dummy a4 includes inverters 381, 382, 383 for signal delay and transfer switches 384, 385 for signal path selection, and has the same configuration as the unit delay stage a2. When the high-potential-side power supply Vdd is supplied, the transfer switch 384 is fixed in a conductive state, and the transfer switch 385 is fixed in a non-conductive state. As a result, the output signal of the inverter 381 is transmitted to the unit delay stage a2 via the transfer switch 384.
[0110]
The shape dummy a3 includes inverters 391, 392, 393 for signal delay, and transfer switches 394, 395 for signal path selection, and is configured similarly to the unit delay stage a1. However, when the low-potential-side power supply AVss is supplied, the transfer switch 394 is fixed to a non-conductive state, and the transfer switch 395 is fixed to a conductive state. As a result, the output signal of inverter 391 is transmitted to unit delay stage a1, and the output signal of inverter 394 is transmitted to output section 380 via transfer switch 395. The output unit 380 includes p-channel MOS transistors 366 and 367 and an n-channel MOS transistor 368 connected in series. The source electrode of p-channel type MOS transistor 366 is coupled to high potential side power supply Vdd, and the source electrode of n-channel type MOS transistor 368 is coupled to low potential side power supply Vss. A predetermined bias voltage VP is supplied to the gate electrode of the p-channel MOS transistor 366. The output signal of the shape dummy a3 is output to the subsequent circuit via the MOS transistors 367 and 368.
[0111]
Although not particularly limited, the coarse replica 52 includes shape dummies b3 and b4, unit delay stages b1 and b2, and an output unit 390. Since the shape dummies b3 and b4 and the unit delay stages b1 and b2 are configured in the same manner as the coarse replica 51, detailed description thereof will be omitted. The output section 390 in the coarse replica 52 includes a p-channel MOS transistor 376 and n-channel MOS transistors 377 and 378 connected in series. The source electrode of p-channel MOS transistor 376 is coupled to high potential power supply Vdd, and the source electrode of n-channel MOS transistor 378 is coupled to low potential power supply Vss. The output signal of the shape dummy b3 is output to the subsequent circuit via the MOS transistors 376 and 277.
[0112]
FIG. 37 shows operation waveforms of main parts of the fine adjustment delay circuit 210.
[0113]
The operation of the fine adjustment delay circuit 210 is divided into steps 1 to 3.
[0114]
First, in steps 1 and 2, when the control signal CKCNT2 is changed from the high level to the low level by the fine adjustment control circuit 410, the unit delay stage in the coarse adjustment replica is switched from b1 to b2, and ckb1 is delayed by Δt. However, the output signal fout of the differential circuit 55 is delayed by 0.5 × Δt due to the reference voltage ckt1 (the rising angle is assumed to be 45 degrees).
[0115]
In steps 2 and 3, when the control signal CKCNT1 transitions from the high level to the low level by the fine control circuit 410, the unit delay in the coarse replica is switched from a1 to a2, and ckt is delayed by Δt. However, the output fout1 of the differential circuit 55 is delayed by 0.5 × Δt due to the reference potential ckb1 (assuming the rising angle is 45 degrees).
[0116]
Thus, the output signal fout of the differential circuit 55 divides the unit delay in the coarse adjustment circuit 220 into two. Therefore, in the configuration shown in FIG. 35, the signal is divided into four by the differential circuit 57 that takes in the divided fout1 and the divided fout2. By using the coarse adjustment replica, a fine adjustment unit delay can be compensated for a temperature change and a variation in MOS transistor characteristics with high accuracy.
[0117]
FIG. 38 shows another configuration example of the fine adjustment delay circuit 210.
[0118]
The fine adjustment delay circuit 210 shown in FIG. 38 is also a coarse adjustment replica, and shows an example in which a coarse adjustment unit is divided into four. Since the coarse-adjustment unit delay path is constituted by the inverter and the transfer switch (see FIG. 32), the coarse-adjustment replica shown in FIG. 38 also includes the inverter and the transfer switch correspondingly. That is, it includes inverters 401 to 406 and 415 to 418, and transfer switches 411 to 414. Inverters 415 to 418 are provided for controlling the operation of the transfer switches 411 to 414. The size (gate length or gate width) of the MOS transistor in each of the transfer switches 411 to 414 is adjusted for the delay time of each path. The inverters 402, 403, 404, and 405 are used for delay adjustment, and the size of the MOS transistor that forms the inverter is made equal to the size of the MOS transistor that forms the inverter 401.
[0119]
When CKCNT1 is set to the high level by the fine adjustment control circuit 410, the transfer switch 411 is turned on, and the output signal of the inverter 401 is output via the transfer switch 411 and the inverter 406. When the CKCNT2 is set to the high level by the fine adjustment control circuit 410, the transfer switch 412 is turned on, and the output signal of the inverter 401 is output via the transfer switch 412 and the inverter 406. When the CKCNT3 is set to the high level by the fine adjustment control circuit 410, the transfer switch 413 is turned on, and the output signal of the inverter 401 is output via the inverters 402 and 403, the transfer switch 413, and the inverter 406. When the CKCNT4 is set to the high level by the fine adjustment control circuit 410, the transfer switch 414 is turned on, and the output signal of the inverter 401 is output via the inverters 404 and 405, the transfer switch 414, and the inverter 406.
[0120]
FIG. 45 shows a layout example of the circuit shown in FIG.
[0121]
The dummy delay circuit 221 has the same arrangement pitch of devices as the coarse delay circuit 220 and the same arrangement direction, that is, the same signal propagation direction. Further, a power supply line for supplying a high-potential-side power supply Vdd and a low-potential-side power supply Vss is formed as a power supply for operating the circuit. In particular, the form of the high-potential-side power supply Vdd and the low-potential-side power supply Vss is made uniform between the coarse delay 220 and the dummy delay circuit 221 to reduce delay control errors. The periodicity of the layout of the dummy delay circuit 221 matches the periodicity of the layout of the coarse delay circuit 220. One unit of the coarse adjustment control circuit 420 is larger than one unit of the coarse adjustment delay circuit 220. In such a case, the unit circuits of the coarse adjustment control circuit 420 are laid out in the chip X direction and the Y direction, and the layout periodicity of the coarse adjustment delay circuit 220 is matched.
[0122]
The dummy delay circuit 221 does not need to be laid out exactly the same as the coarse delay circuit 220. For example, as shown in FIG. 47, the periodicity of the layout when the registers 422-0 to 422-n are laid out between the unit delay stages 221-0 to 221-n in the dummy delay circuit 221 is roughly adjusted. 220 may be made to coincide with the periodicity of the layout.
[0123]
FIG. 48 shows another configuration example of the variable delay circuit 2, and FIG. 49 shows the operation timing of the main part in that case.
[0124]
In order to delay the phase of the output fout of the DLL circuit 9 by 0.5 cycle (180 degrees) with respect to the input clock signal CLK, the fine delay circuit 210 and the coarse delay circuit 220 are provided with the replica fine delay stage 481 and the replica coarse control. The delay stages 482 may be connected in series, and the output signal cfout of the replica coarse adjustment delay stage 482 may be fed back and supplied to the frequency dividing circuit 33B. FIG. 46 shows a layout example including a replica fine adjustment delay stage 481 and a replica coarse adjustment delay stage 482.
[0125]
Although the invention made by the present inventors has been specifically described above, the present invention is not limited thereto, and it goes without saying that various modifications can be made without departing from the gist of the invention.
[0126]
For example, in the above example, the case where the present invention is applied to a DLL circuit as an example of the clock recovery time has been described. However, the present invention is not limited to this, and can be applied to a PLL. That is, in a general PLL circuit, a phase comparison between an input clock signal and a fed-back clock signal is performed, and an oscillation frequency control of a voltage controlled oscillator is performed according to the phase comparison result. The input voltage level of the voltage controlled oscillator can be controlled based on the output signal of the decoder circuit 20. Also in such a configuration, the same operation and effect as in the case of the DLL circuit 9 can be obtained with respect to the phase control of the clock signal.
[0127]
In the above description, the case where the invention made by the present inventor is applied to the SRAM, which is the application field as the background, has been mainly described. However, the present invention is not limited to this, and the DRAM (dynamic type, random, Access memory) and other semiconductor integrated circuits.
[0128]
The present invention can be applied on condition that at least a clock signal is handled.
[0129]
【The invention's effect】
The effects obtained by the representative inventions among the inventions disclosed in the present application will be briefly described as follows.
[0130]
That is, the accuracy of the phase control can be improved by reducing the jitter by setting an appropriate dead zone in the decoder circuit.
[0131]
Further, even when the delay time of the variable delay circuit is longer than the cycle time, the delay control can be performed after the delay is determined, so that a delay control error can be prevented, thereby improving the accuracy of the phase control.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration example of a DLL circuit included in an SRAM which is an example of a semiconductor integrated circuit according to the present invention.
FIG. 2 is an operation explanatory view of a main part in FIG. 1;
FIG. 3 is a diagram illustrating a determination value probability characteristic in a phase comparison circuit when a noise distribution is assumed to be a normal distribution.
FIG. 4 is a diagram illustrating a determination value probability characteristic in a phase comparison circuit when a noise distribution is assumed to be a normal distribution.
FIG. 5 is a block diagram illustrating another configuration example of a DLL circuit included in the SRAM.
FIG. 6 is an operation timing chart of a main part in FIG. 5;
FIG. 7 is an explanatory diagram showing a relationship between an output code from a counter included in the DLL circuit and an output signal of a corresponding decoder circuit.
FIG. 8 is an explanatory diagram of a decoder output with respect to the number of appearances of a determination value in a phase comparison circuit included in the DLL.
9 is a characteristic diagram of phase transition in a circuit to be compared with the DLL circuit shown in FIG. 5;
FIG. 10 is a characteristic diagram of a phase transition in the DLL circuit shown in FIG. 5;
FIG. 11 is a circuit diagram illustrating a configuration example of a phase comparison circuit included in the DLL circuit.
FIG. 12 is an explanatory diagram showing a relationship between an output code of a counter circuit included in the DLL circuit and an output signal of a corresponding decoder circuit.
FIG. 13 is a block diagram illustrating another configuration example of the decoder circuit included in the DLL circuit.
14 is an operation explanatory diagram of the decoder circuit shown in FIG.
FIG. 15 is a block diagram showing another configuration example of the DLL circuit.
16 is an operation timing chart of a main part in the DLL circuit shown in FIG. 15;
FIG. 17 is a block diagram showing another configuration example of the DLL times.
18 is an operation timing of a main part in the DLL circuit shown in FIG. 17;
FIG. 19 is a block diagram showing another configuration example of the DLL circuit.
FIG. 20 is a characteristic diagram showing a simulation result of a phase error with respect to a dead band width of a phase comparison circuit included in the DLL circuit.
FIG. 21 is a diagram illustrating the relationship between the output code of a counter and the output of a decoder circuit in the DLL circuit.
FIG. 22 is a block diagram showing another configuration example of the DLL circuit.
FIG. 23 is a block diagram illustrating a configuration example of a circuit to be compared with the DLL circuit illustrated in FIG. 5;
24 is an operation timing chart of a main part in the DLL circuit shown in FIG. 23;
FIG. 25 is a block diagram illustrating a configuration example of a variable delay circuit and a delay control circuit in the DLL circuit.
26 is an operation timing chart of a main part in the configuration shown in FIG. 25;
27 is an operation timing chart of a main part in the configuration shown in FIG. 25;
FIG. 28 is a block diagram illustrating a configuration example of a variable delay circuit in the DLL circuit.
FIG. 29 is an operation timing chart of a main part in the configuration shown in FIG. 28;
FIG. 30 is a block diagram illustrating another configuration example of the variable delay circuit and the delay control circuit.
FIG. 31 is an explanatory diagram of operation timings of main parts in the configuration shown in FIG. 30;
FIG. 32 is a circuit diagram illustrating a configuration example of a coarse delay circuit included in the variable delay circuit.
FIG. 33 is an operation explanatory diagram of a main part in the circuit configuration shown in FIG. 32;
FIG. 34 is a circuit diagram illustrating another configuration example of the coarse delay circuit.
FIG. 35 is a circuit diagram showing a configuration example of the fine delay circuit shown in FIG. 30;
36 is a circuit diagram showing a configuration example of the coarse-tuning replica shown in FIG. 35;
FIG. 37 is an operation explanatory diagram of a main part in the fine adjustment delay circuit.
FIG. 38 is a circuit diagram showing another configuration example of the fine adjustment delay circuit.
FIG. 39 is an operation explanatory view of the circuit shown in FIG. 32;
FIG. 40 is an operation timing chart of a main part in the circuit shown in FIG. 32;
FIG. 41 is another operation explanatory diagram of the circuit shown in FIG. 32;
FIG. 42 is another operation timing chart of a main part in the circuit shown in FIG. 32;
FIG. 43 is a detailed configuration example circuit diagram of a main part in FIG. 30;
44 is a circuit diagram showing a configuration example of a main part in FIG. 43.
FIG. 45 is an explanatory diagram of a layout of a main part in the circuit shown in FIG. 43;
FIG. 46 is an explanatory diagram of a layout of a main part when the configuration shown in FIG. 48 is adopted;
FIG. 47 is another layout explanatory diagram of a main part in the circuit shown in FIG. 43;
FIG. 48 is a circuit diagram showing another configuration example of the DLL circuit.
FIG. 49 is an operation timing chart of a main part in FIG. 48.
FIG. 50 is a detailed layout explanatory view of a main part in FIG. 43;
[Explanation of symbols]
1 clock input buffer
2 Variable delay circuit
3 Phase comparison circuit
4 Delay control circuit
5 Clock distribution buffer
6 Dummy circuit
7 Input buffer
8 Data input register
9 DLL circuit

Claims (21)

A clock recovery circuit that generates an internal clock signal based on an input clock signal,
A phase comparison circuit capable of performing a phase comparison between the input clock signal and a comparison target clock signal to which the internal clock signal is fed back;
A counter for counting a phase comparison result in the phase comparison circuit,
A decoder circuit for decoding the count value of the counter,
A control circuit capable of controlling generation of the internal clock signal based on a decoding result from the decoder,
A clock recovery circuit, wherein the decoder circuit has a dead zone in which a decoded output is not updated when an output code of the counter falls within a preset range. 2. The clock recovery circuit according to claim 1, wherein the dead zone is set by presetting a decoding logic of the decoder circuit in relation to an output code of the counter. A second phase comparison circuit capable of performing a phase comparison between the input clock signal and a comparison target clock signal to which the internal clock signal is fed back;
A flag counter that counts the input clock signal and forms a flag based on the count result;
2. The clock recovery circuit according to claim 1, further comprising: a selector capable of selectively transmitting an output signal of the decoder and an output signal of the second phase comparison circuit to the control circuit according to a state of the flag. The selector transmits an output signal of the second phase comparison circuit to the control circuit based on the flag in the first state before the count value of the flag counter reaches a predetermined value, and outputs the count value of the flag counter. 4. The clock recovery circuit according to claim 3, wherein an output signal of the second phase comparison circuit is transmitted to the control circuit based on the flag in a second state in which a predetermined value has been reached. A second phase comparison circuit capable of performing a phase comparison between the input clock signal and a comparison target clock signal to which the internal clock signal is fed back;
A phase difference detection circuit that can detect a phase difference between the input clock signal and the comparison target clock signal to which the internal clock signal is fed back;
Based on the detection result of the phase detection circuit,
2. The clock recovery circuit according to claim 1, further comprising: a selector capable of selectively transmitting an output signal of said decoder circuit and an output signal of said second phase comparison circuit to said control circuit. The clock according to any one of claims 1 to 5, wherein the decoder circuit includes a plurality of decoders each having a different dead zone width, and a selection circuit capable of selecting the plurality of decoders according to a mode signal. Reproduction circuit. 7. The clock recovery circuit according to claim 1, further comprising a variable delay circuit capable of delaying the input clock signal under the control of the control circuit. The variable delay circuit includes a plurality of unit delay stages capable of delaying the input clock signal,
8. The clock recovery circuit according to claim 7, wherein said control circuit includes a timing control circuit for causing a delay time control timing of said unit delay stage to follow a delay time of said unit delay stage. The timing control circuit includes a plurality of second unit delay stages arranged corresponding to the plurality of unit delay stages in the variable delay circuit, and delays the input clock signal by the second unit delay stage. 9. The clock recovery circuit according to claim 8, wherein a timing signal for causing the delay time control timing of the unit delay stage to follow the delay time of the unit delay stage is obtained. The variable delay circuit, a fine adjustment delay circuit for fine adjustment of the delay amount of the input clock signal,
A coarse delay circuit for delaying the output signal of the fine delay circuit,
The control circuit, a fine adjustment control circuit for controlling the operation of the fine adjustment delay circuit,
A coarse adjustment control circuit for controlling the operation of the coarse adjustment delay circuit,
A latch circuit for transmitting the carry signal output from the fine adjustment control circuit to the coarse adjustment control circuit in synchronization with the output signal of the fine adjustment delay circuit,
The coarse delay circuit includes a plurality of third unit delay stages capable of delaying an output signal of the fine delay circuit,
8. The clock recovery circuit according to claim 7, wherein said coarse adjustment control circuit includes a second timing control circuit for causing a delay time control timing of said third unit delay stage to follow a delay time of said third unit delay stage. The second timing control circuit includes a plurality of fourth unit delay stages arranged corresponding to the plurality of third unit delay stages in the coarse delay circuit, and outputs the output signal of the fine delay circuit to the fourth delay unit. 11. The clock recovery circuit according to claim 10, wherein the timing signal for causing the delay time control timing of the third unit delay stage to follow the delay time of the third unit delay stage is obtained by delaying by the four unit delay stages. The coarse delay circuit includes a plurality of first inverters connected in series to each other;
A plurality of second inverters arranged corresponding to the first inverter;
A plurality of first switches capable of serially connecting the plurality of second inverters to each other;
A plurality of second switches disposed between the first inverter and the corresponding second inverter and capable of transmitting an output signal of the first inverter to the corresponding second inverter; 12. The clock recovery circuit according to claim 10, wherein the third unit delay stage includes a first inverter and a corresponding second inverter. 13. The coarse adjustment delay circuit and the second timing control circuit in the coarse adjustment control circuit have a same arrangement wiring pitch and a same signal propagation direction. A clock recovery circuit as described. A clock recovery circuit according to claim 1,
A semiconductor integrated circuit in which a data holder for taking in data in synchronization with an internal clock signal obtained by the clock recovery circuit is formed on one semiconductor substrate. A variable delay circuit that generates an internal clock signal by delaying an input clock signal,
A phase comparison circuit capable of performing a phase comparison between the input clock signal and a comparison target clock signal to which the internal clock signal is fed back;
A control circuit capable of controlling the operation of the variable delay circuit based on the phase comparison result in the phase comparison circuit,
The variable delay circuit includes a plurality of unit delay stages capable of delaying the input clock signal,
A clock recovery circuit, wherein the control circuit includes a timing control circuit for causing a delay time control timing of the unit delay stage to follow a delay time of the unit delay stage. The timing control circuit includes a plurality of second unit delay stages arranged corresponding to the plurality of unit delay stages in the variable delay circuit, and delays the input clock signal by the second unit delay stage. 16. The clock recovery circuit according to claim 15, wherein a timing signal for causing the delay time control timing of the unit delay stage to follow the delay time of the unit delay stage is obtained. The variable delay circuit, a fine adjustment delay circuit for fine adjustment of the delay amount of the input clock signal,
A coarse delay circuit for delaying the output signal of the fine delay circuit,
The control circuit, a fine adjustment control circuit for controlling the operation of the fine adjustment delay circuit,
A coarse adjustment control circuit for controlling the operation of the coarse adjustment delay circuit,
A latch circuit for transmitting the carry signal output from the fine adjustment control circuit to the coarse adjustment control circuit in synchronization with the output signal of the fine adjustment delay circuit,
The coarse delay circuit includes a plurality of third unit delay stages capable of delaying an output signal of the fine delay circuit,
16. The clock recovery circuit according to claim 15, wherein the coarse adjustment control circuit includes a second timing control circuit for causing a delay time control timing of the third unit delay stage to follow a delay time of the third unit delay stage. The second timing control circuit includes a plurality of fourth unit delay stages arranged corresponding to the plurality of third unit delay stages in the coarse delay circuit, and outputs the output signal of the fine delay circuit to the fourth delay unit. 18. The clock recovery circuit according to claim 17, wherein the timing signal for causing the delay time control timing of the third unit delay stage to follow the delay time of the third unit delay stage is obtained by delaying the delay time by the four unit delay stages. The coarse delay circuit includes a plurality of first inverters connected in series to each other;
A plurality of second inverters arranged corresponding to the first inverter;
A plurality of first switches capable of serially connecting the plurality of second inverters to each other;
A plurality of second switches disposed between the first inverter and the corresponding second inverter and capable of transmitting an output signal of the first inverter to the corresponding second inverter; 19. The clock recovery circuit according to claim 17, wherein the third unit delay stage includes a first inverter and a corresponding second inverter. 20. The coarse adjustment delay circuit and the second timing control circuit in the coarse adjustment control circuit, wherein arrangement and wiring pitches are equal to each other, and signal propagation directions are equal to each other. A clock recovery circuit as described. A clock recovery circuit according to any one of claims 15 to 20,
A semiconductor integrated circuit in which data holding means for taking in data in synchronization with an internal clock signal obtained by the clock recovery circuit is formed on one semiconductor substrate.

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