JP2012094205A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent an output timing of read data and an external clock signal from not being synchronized with each other due to inability of a resume trigger signal to be generated.SOLUTION: A reset signal RESET for causing a DLL circuit 100 to initially boot and a resume trigger signal RESTART for causing the DLL circuit 100 to resume controlling a delay amount with respect to an internal clock signal ICLK of an internal clock signal LCLK are input to the DLL circuit 100. The DLL circuit 100 resumes controlling the delay amount in response to the reset signal RESET or the resume trigger signal RESTART having been activated. The DLL circuit 100 continues controlling the delay amount even after the DLL circuit 100 has been locked before the resume trigger signal RESTART is activated after the reset signal RESET has been activated, and stops controlling the delay amount in response to a lock of the DLL circuit 100 after the resume trigger signal RESTART has been activated.

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device that generates a clock signal using a DLL (Delay-Locked Loop) circuit.

  In recent years, semiconductor devices that operate in synchronization with a clock have been widely used. For example, a DDR (Double Data Rate) type synchronous memory used as a main memory of a personal computer or the like. In such a semiconductor device, since it is necessary to accurately synchronize the output timing of read data with an external clock signal, a DLL circuit for generating an internal clock signal synchronized with the external clock signal is used. Patent Document 1 discloses an example of such a DLL circuit.

  The DLL circuit generally has a counter circuit whose count value is updated based on the phase difference between the external clock signal and the internal clock signal and the duty ratio of the internal clock signal, and a delay that generates the internal clock signal by delaying the external clock signal. And the delay amount of the delay line is determined by the count value of the counter circuit. The count value update operation, that is, the delay amount control operation is performed after the DLL circuit is locked, that is, after the phase difference and the duty ratio each reach a predetermined value (generally, the phase difference is zero and the duty ratio is 50%). Is also continued to follow the external clock signal. For this reason, the DLL circuit continues to consume predetermined power even after locking.

JP 2009-278528 A

  In recent years, a technique has been devised in which the control operation of the delay amount of the delay line is stopped when the DLL circuit is locked, while the control operation is restarted as necessary. According to this, while the power consumption of the DLL circuit can be reduced, the delay amount control operation is restarted when necessary, so that the output timing of the read data and the external clock signal are out of synchronization by stopping the delay amount control operation. Can also be prevented.

  In the above technique, the delay amount control operation is restarted by a restart trigger signal. This is a signal that is automatically generated in response to a refresh command, counter output, oscillator output, etc. in the semiconductor device, and is different from a reset signal for initially starting the DLL circuit. By using the restart trigger signal, for example, it is possible to restart the delay amount control operation at the start timing of the refresh operation, or to periodically restart the delay amount control operation.

  However, using such a restart trigger signal has a risk that the delay amount control operation cannot be restarted. That is, there is no problem as long as the restart trigger signal can be generated, but the restart trigger signal may not be generated depending on the operating environment (power supply voltage, temperature, etc.) of the semiconductor device. In such a case, after the DLL circuit is locked once after the initial startup and the delay amount control operation is stopped, the delay amount control operation is not resumed at least until the operation environment is changed. There is a possibility that the duty ratio is greatly deviated from the predetermined value, and the output timing of the read data is not synchronized with the external clock signal.

  Of course, there is a possibility that the reset signal cannot be generated. In such a case, since the DLL circuit does not operate at all, the read data output timing and the external clock signal are not synchronized. Therefore, the event of out of synchronization does not occur.

  Although it is a kind of failure that the restart trigger signal cannot be generated, it cannot always be detected by a test in a manufacturing process in which conditions such as a power supply voltage and temperature are constant, and may be found only after being mounted on an actual machine. Therefore, there is a demand for a measure for preventing the read data output timing from being out of synchronization with the external clock signal because the restart trigger signal cannot be generated.

  A semiconductor device according to the present invention includes a DLL circuit that generates a second clock signal obtained by delaying a first clock signal, and the DLL circuit includes a reset signal that initially activates the DLL circuit. And a restart trigger signal for causing the DLL circuit to resume control of the delay amount of the second clock signal with respect to the first clock signal, and the DLL circuit is activated by the reset signal or the restart trigger signal. Control of the delay amount in response to activation of the delay circuit, and after the reset signal is activated and before the restart trigger signal is activated, the delay amount is controlled even after the DLL circuit is locked. The delay amount control is stopped according to the lock of the DLL circuit after the restart trigger signal is activated.

  A semiconductor device according to another aspect of the present invention has a function of generating a second clock signal obtained by delaying a first clock signal, and the phase of the first clock signal and the second clock signal The semiconductor device includes a DLL circuit that controls a delay amount of the second clock signal with respect to the first clock signal so that the phase of the reference clock signal generated based on the first clock signal matches the phase of the reference clock signal. The first and second DLL update signals are sequentially input in this order, and the DLL circuit receives the first DLL update signal and starts controlling the delay amount, and then the first clock signal. Even after the phase of the reference clock signal substantially coincides with the phase of the reference clock signal, control of the delay amount is continued, and after receiving the second DLL update signal, the phase of the first clock signal and the reference And the phase of the clock signal, characterized in that the stop control of substantially matched the amount of delay in response to the.

  According to the present invention, since the control of the delay amount started in response to the activation of the reset signal (first DLL update signal) is not stopped even after the DLL circuit is locked, the restart trigger signal (second The DLL circuit lock state can be maintained even if the DLL update signal) is not activated indefinitely. Therefore, it is possible to prevent the output data output timing from being out of synchronization with the external clock signal due to the inability to generate the restart trigger signal.

1 is a block diagram showing an overall configuration of a semiconductor device according to a preferred embodiment of the present invention. It is a figure which shows the circuit structure of the DLL circuit by preferable embodiment of this invention. 4 is a timing chart of various signals used in a DLL circuit according to a preferred embodiment of the present invention.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a block diagram showing the overall configuration of a semiconductor device 10 according to a preferred embodiment of the present invention.

  The semiconductor device 10 according to the present embodiment is a DDR SDRAM (Synchronous Dynamic Random Access Memory), and includes clock terminals 11a and 11b, command terminals 12a to 12e, an address terminal 13, and a data input / output terminal 14 as external terminals. Yes. In addition, although a power supply terminal, a data strobe terminal, and the like are also provided, these are not shown.

  The clock terminals 11 a and 11 b are terminals to which external clock signals CK and / CK are respectively supplied. The supplied external clock signals CK and / CK are supplied to the clock input circuit 21. In this specification, a signal having “/” at the head of a signal name means an inverted signal of the corresponding signal or a low active signal. Therefore, the external clock signals CK and / CK are complementary signals. The clock input circuit 21 generates a single-phase internal clock signal ICLK based on the external clock signals CK and / CK, and supplies this to the DLL circuit 100.

  The DLL circuit 100 is a clock generation circuit that receives the internal clock signal ICLK and generates an internal clock signal LCLK that is phase-controlled and duty-controlled with respect to the external clock signals CK and / CK. The generated internal clock signal LCLK is supplied to the data input / output circuit 70. As shown in FIG. 1, the DLL circuit 100 includes a delay line 110, a delay amount control circuit 120, a restart trigger signal generation circuit 130, and an activation circuit 140. Details of the DLL circuit 100 will be described later.

  The command terminals 12a to 12e are terminals to which a row address strobe signal / RAS, a column address strobe signal / CAS, a write enable signal / WE, a chip select signal / CS, and an on-die termination signal ODT are supplied, respectively. These command signals CMD are supplied to the command input circuit 31. These command signals CMD supplied to the command input circuit 31 are supplied to the command decoder 32. The command decoder 32 is a circuit that generates various internal commands ICMD by holding, decoding, and counting command signals. The generated internal command ICMD is supplied to the row control circuit 51, the column control circuit 52, the mode register 53, the data input / output circuit 70, the DLL circuit 100, and the like.

  The address terminal 13 is a terminal to which an address signal ADD is supplied. The supplied address signal ADD is supplied to the address input circuit 41. The output of the address input circuit 41 is supplied to the address latch circuit 42. Of the address signal ADD latched by the address latch circuit 42, the row address is supplied to the row control circuit 51, and the column address is supplied to the column control circuit 52. If the entry is made in the mode register set, the address signal ADD is supplied to the mode register 53, whereby the contents of the mode register 53 are updated.

  The row-related control circuit 51 is a circuit that supplies a row address supplied from the address latch circuit 42 to the row decoder 61. The row-related control circuit 51 includes a refresh counter 51a. The count value of the refresh counter 51a indicates a row address (refresh address) to be refreshed, and is supplied to the row decoder 61 as a row address at the timing when a refresh signal which is a kind of internal command ICMD is activated.

  The row decoder 61 is a circuit that selects any word line WL included in the memory cell array 60. In the memory cell array 60, a plurality of word lines WL and a plurality of bit lines BL intersect, and memory cells MC are arranged at the intersections (in FIG. 1, one word line WL, one line Only the bit line BL and one memory cell MC are shown). In order to hold the data stored in the memory cell MC, a refresh operation (re-update of the information in the memory cell) is required, and the refresh target address is designated by the refresh address input from the row control circuit 51. Is done. The bit line BL is connected to a corresponding sense amplifier SA in the sense circuit 63.

  The output of the column control circuit 52 is supplied to the column decoder 62. The column decoder 62 is a circuit that selects one of the sense amplifiers SA included in the sense circuit 63. The sense amplifier SA selected by the column decoder 62 is connected to the data amplifier 64 via the main I / O line MIO. The data amplifier 64 further amplifies the read data amplified by the sense amplifier SA during the read operation, and supplies it to the data input / output circuit 70 via the read / write bus RWBS. On the other hand, during the write operation, the write data supplied from the data input / output circuit 70 via the read / write bus RWBS is amplified and supplied to the sense amplifier SA.

  The data input / output terminal 14 is a terminal for outputting read data DQ and inputting write data DQ, and is connected to the data input / output circuit 70. The data input / output circuit 70 includes an output buffer 71, and read data DQ is output from the output buffer 71 in synchronization with the internal clock signal LCLK during a read operation. Although only one data input / output terminal 14 is shown in FIG. 1, the number of data input / output terminals 14 is not necessarily one, and a plurality of data input / output terminals 14 may be provided.

  The above is the overall configuration of the semiconductor device 10 according to the present embodiment. Next, the DLL circuit 100 will be described in detail.

  FIG. 2 is a diagram illustrating a circuit configuration of the DLL circuit 100. As described above, the DLL circuit 100 has a function of generating the internal clock signal LCLK (second clock signal) based on the internal clock signal ICLK (first clock signal). Internal clock signal LCLK is a signal obtained by delaying internal clock signal ICLK by a given delay amount, and the cycle thereof is the same as the cycle of internal clock signal ICLK.

  The delay line 110 is a delay circuit that generates an internal clock signal LCLK for output by delaying the internal clock signal ICLK. The delay amount is for the purpose of controlling the phase and duty of the internal clock signal LCLK. It is adjusted by the delay amount control circuit 120. Although not particularly limited, the delay line 110 includes a coarse delay line that delays the internal clock signal ICLK with a relatively coarse adjustment pitch, and a fine delay that delays the internal clock signal ICLK with a relatively fine adjustment pitch. It preferably includes a line.

  The delay amount control circuit 120 receives the internal clock signals ICLK and LCLK, and based on these, the output timing of the read data DQ is synchronized with the internal clock signal ICLK, and the duty ratio of the internal clock signal LCLK is a predetermined value (usually 50%) is a circuit that controls the delay amount of the delay line 110. As shown in FIG. 2, the delay amount control circuit 120 includes a buffer 121, a replica circuit 122, a phase / duty determination circuit 123, a control circuit 124, a frequency dividing circuit 125, a counter circuit 126, a delay circuit 127, and update stop / restart. A circuit 128 is included. Hereinafter, each of these circuits will be described.

  The buffer 121 has substantially the same circuit configuration as the output buffer 71 shown in FIG. The replica circuit 122 has substantially the same circuit configuration as other circuits from the DLL circuit 100 to the data input / output terminal 14. Therefore, a replica circuit of a circuit from the DLL circuit 100 to the data input / output terminal 14 is realized by the buffer 121 and the replica circuit 122. Note that although the buffer 121 and the replica circuit 122 include transistors, the sizes thereof do not have to be the same as the sizes of the corresponding transistors. That is, as long as the impedance is substantially the same, a shrink transistor may be used for the buffer 121 and the replica circuit 122.

  The internal clock signal LCLK is input to the buffer 121, and the output of the buffer 121 (the internal clock signal LCLK that has passed through the buffer 121) is input to the replica circuit 122. The replica circuit 122 generates a feedback clock signal fbCLK (reference clock signal) in synchronization with the input internal clock signal LCLK and outputs it to the phase / duty determination circuit 123. Since the buffer 121 and the replica circuit 122 are replica circuits of the circuit from the DLL circuit 100 to the data input / output terminal 14, the phase and duty of the feedback clock signal fbCLK are the output signal of the data input / output terminal 14 ( It exactly matches the phase and duty of the read data DQ).

  The phase / duty determination circuit 123, the control circuit 124, and the counter circuit 126 cooperate to at least one of the phase difference between the feedback clock signal fbCLK and the internal clock signal ICLK, and the duty ratio of the feedback clock signal fbCLK. Based on this, the count value COUNT is updated. Each will be described in detail below.

  First, the phase / duty determination circuit 123 detects the phase difference between the internal clock signal ICLK and the feedback clock signal fbCLK, and determines whether the phase of the feedback clock signal fbCLK is advanced or delayed with respect to the internal clock signal ICLK. At the same time, the duty ratio of the feedback clock signal fbCLK is also detected, and it is determined whether the detected duty ratio is larger or smaller than a predetermined value. The determination is performed every cycle of the internal clock signal ICLK, and the result is supplied to the control circuit 124 as the determination signal PD.

  The control circuit 124 updates the up / down signal U / D based on the determination signal PD. This update is performed in synchronization with the sampling clock signal SYNCLK. Here, the sampling clock signal SYNCLK is a signal generated by the frequency dividing circuit 125. The frequency dividing circuit 125 has a function of generating a sampling clock signal SYNCLK having a lower frequency by dividing the internal clock signal ICLK. Although not particularly limited, the frequency dividing number is preferably set to 16 or 32. Therefore, for example, when the frequency dividing circuit 125 divides the internal clock signal ICLK by 16, the sampling clock signal SYNCLK is activated every 16 cycles of the internal clock signal ICLK. In this case, the update period of the up / down signal U / D is 16 clock cycles. The up / down signal U / D generated by the control circuit 124 is supplied to the counter circuit 126.

  The counter circuit 126 has a function of counting up or counting down based on the up / down signal U / D. This count-up or count-down is performed in synchronization with the delayed sampling clock signal SYNCLKD obtained by passing the sampling clock signal SYNCLK through the delay circuit 127 described above. The count value COUNT of the counter circuit 126 is supplied to the delay line 110, whereby the delay amount of the delay line 110 is determined.

  The update stop / restart circuit 128 has a function of determining whether or not the DLL circuit 100 is locked based on the count value COUNT. If it is determined that the DLL circuit 100 is locked, the delay amount control circuit 120 Stop controlling the amount of delay. Specifically, the operation of the buffer 121 and the frequency dividing circuit 125 is stopped by activating the stop instruction signal STP. Thereby, the delay amount control operation by the delay amount control circuit 120 is stopped. The update stop / restart circuit 128 performs a process of activating the stop instruction signal STP only when a start signal SS (described later) input from the start circuit 140 is in an inactive state.

  The operation for determining whether or not the lock is applied will be described. When the DLL circuit 100 is locked, the phase of the feedback clock signal fbCLK and the phase of the internal clock signal ICLK substantially coincide with each other, and the duty ratio of the feedback clock signal fbCLK substantially coincides with a predetermined target value. Will do. “Substantially match” means to include a case where it fluctuates across a value when it is completely matched. In this case, the count value COUNT goes back and forth between two adjacent values. The update stop / restart circuit 128 is configured to be able to detect a change pattern of the count value COUNT, and when detecting a change pattern that goes back and forth between two values as described above, the DLL circuit 100 Is determined to be locked.

  The update stop / restart circuit 128 also has a function of inactivating the stop instruction signal STP in response to the activation signal SS being activated. When the stop instruction signal STP is deactivated, the buffer 121 and the frequency dividing circuit 125 start operating, and the delay amount control circuit 120 starts controlling the delay amount.

  The circuits in the delay amount control circuit 120 have been described above.

  Next, the restart trigger signal generation circuit 130 is a circuit that generates a restart trigger signal RESTART indicating that the delay amount control circuit 120 restarts control of the delay amount. The restart trigger signal RESTART may be a signal that is activated in response to the activation of the refresh signal REFB (the same signal as the refresh signal input to the row control circuit 51 described above), an oscillator output, or some count The signal may be activated based on the count value of the circuit. When the restart trigger signal RESTART is generated based on the output of the oscillator, the restart trigger signal RESTART is activated periodically (with a constant cycle).

  The activation circuit 140 activates the activation signal SS in response to the activation of the above-described restart trigger signal RESTART or the reset signal RESET which is a kind of the internal command ICMD, and the restart trigger signal RESTART is deactivated. This is a circuit that deactivates the activation signal SS accordingly. The reset signal RESET is a signal input from the outside for initial activation of the DLL circuit 100 and is normally activated when the semiconductor device 10 is powered on. The activation circuit 140 does not deactivate the activation signal SS in response to the deactivation of the reset signal RESET.

  Specifically, the activation circuit 140 includes a flip-flop 141 and an OR circuit 142 as shown in FIG. The flip-flop 141 is configured to have each input of D, S (Set), and CLK and Q output. A low is always input to the D input, a reset signal RESET is input to the S input, and a restart trigger signal RESTART is input to the CLK input. The OR circuit 142 receives the restart trigger signal RESTART and the Q output of the flip-flop 141, and the output of the OR circuit 142 becomes the above-described start signal SS.

  Due to the operation of the activation circuit 140, the DLL circuit 100 starts to control the delay amount in response to the activation of the reset signal RESET or the restart trigger signal RESTART. In addition, after the reset signal RESET is activated and before the restart trigger signal RESTART is activated, control of the delay amount is continued even after the DLL circuit 100 is locked, and after the restart trigger signal RESTART is activated. The control of the delay amount is stopped according to the lock of the DLL circuit 100. Hereinafter, the operation of the DLL circuit 100 will be described in detail with reference to the timing chart of each signal.

  FIG. 3 is a timing chart of the reset signal RESET, the restart trigger signal RESTART, the signal output from the Q output of the flip-flop 141, the start signal SS, and the stop instruction signal STP. In the figure, each signal is a high active signal. As shown in the figure, the period during which the delay amount control by the delay amount control circuit 120 is performed coincides with the period in which the stop instruction signal STP is in an inactive state.

  As shown in FIG. 3, both the reset signal RESET and the restart trigger signal RESTART are pulse signals. The reset signal RESET is activated only once when the DLL circuit 100 is initially activated, and the restart trigger signal RESTART is activated as many times as necessary after the initial activation. The specific activation timing of the restart trigger signal RESTART is determined by the restart trigger signal generation circuit 130 as described above.

_First , when the reset signal RESET (first DLL update signal) is activated at time T1, the Q output of the flip-flop 141 and the activation signal SS are sequentially activated. Therefore, the stop instruction signal STP is deactivated, and the delay amount control by the delay amount control circuit 120 is started. Even if the reset signal RESET is deactivated at time T ₂ , the Q output of the flip-flop 141 is maintained in an activated state, so that the activation signal SS is not deactivated and the delay by the delay amount control circuit 120. Quantity control continues.

Next, when the restart trigger signal RESTART (second DLL update signal) is activated at time _{T 3,} Q output of the flip-flop 141 is deactivated. This is because the row input to the D input is output to the Q output, but this causes the Q output, which is one input of the OR circuit 142, to be deactivated. However, on the other hand, the restart trigger signal RESTART, which is the other input of the OR circuit 142, is activated, and as a result, the start signal SS, which is the output of the OR circuit 142, maintains the active state as shown in FIG. . Therefore, the delay amount control by the delay amount control circuit 120 is continued. In other words, control of the delay amount by the delay amount control circuit 120 is started again at the timing when the restart trigger signal RESTART (second DLL update signal) is activated. Thereafter, the Q output of the flip-flop 141 is maintained in an inactive state regardless of the state of the restart trigger signal RESTART.

Thereafter, at time _{T 4} restart trigger signal RESTART (second DLL update signal) when deactivated, the start signal SS at that timing is deactivated. Therefore, the stop instruction signal STP is activated at the next timing (time T ₅ ) when the DLL circuit 100 is locked, and the delay amount control operation by the delay amount control circuit 120 is stopped.

Then, when at time _{T 6} the next restart trigger signal RESTART (third DLL update signal) is activated, the operation of the OR circuit 142, the start signal SS is the same pulsed and resumption trigger signal RESTART Activated. Thus, when the activation signal SS is temporarily activated, the stop instruction signal STP is deactivated, and the delay amount control circuit 120 starts controlling the delay amount. When the DLL circuit 100 at time T ₇ to reach the locked state, stop instruction signal STP is activated, the control of the delay amount is stopped. Thereafter, the same processing is repeated each time the restart trigger signal RESTART is activated.

  Thus, in the DLL circuit 100, the activation signal SS is not deactivated even when the reset signal RESET is deactivated. In other words, since the activation signal SS is not deactivated in response to the deactivation of the reset signal RESET, the DLL circuit 100 is locked until the restart trigger signal RESTART is activated. The control of the delay amount is continued later. Therefore, even if the restart trigger signal RESTART is not generated at all, the locked state of the DLL circuit 100 is maintained.

  As described above, according to the semiconductor device 10 according to the present embodiment, even after the reset signal RESET is activated, the locked state of the DLL circuit 100 can be maintained even if the restart trigger signal RESTART is not activated indefinitely. Therefore, it is prevented that the output timing of the read data is out of synchronization with the external clock signal because the restart trigger signal RESTART cannot be generated.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

  For example, in the above-described embodiment, an example in which the present invention is applied to a DLL circuit that controls both phase and duty has been described. However, the present invention can also be applied to a DLL circuit that controls only one of them. .

  In the above embodiment, the example in which the present invention is applied to the SDRAM has been described. However, the present invention is not limited to a memory device or a logic device as long as it is a semiconductor device that outputs read data synchronized with an external clock signal. Widely applicable.

DESCRIPTION OF SYMBOLS 10 Semiconductor device 11a, 11b Clock terminal 12a-12e Command terminal 13 Address terminal 14 Data input / output terminal 21 Clock input circuit 31 Command input circuit 32 Command decoder 41 Address input circuit 42 Address latch circuit 51 Row system control circuit 51a Refresh counter 52 Column System control circuit 53 Mode register 60 Memory cell array 61 Row decoder 62 Column decoder 63 Sense circuit 64 Data amplifier 70 Data input / output circuit 71 Output buffer 100 DLL circuit 110 Delay line 120 Delay amount control circuit 121 Buffer 122 Replica circuit 123 Phase / duty determination Circuit 124 Control circuit 125 Frequency divider circuit 126 Counter circuit 127 Delay circuit 128 Update stop / restart circuit 130 Restart trigger signal generation circuit 1 1 flip flop 132 OR circuit 140 starting circuit CK, / CK external clock signal COUNT count fbCLK feedback clock signal (a reference clock signal)
ICLK Internal clock signal (first clock signal)
LCLK Internal clock signal (second clock signal)
RESET Reset signal RESTART Restart trigger signal SS Start signal STP Stop instruction signal

Claims (8)

A semiconductor device including a DLL circuit that generates a second clock signal obtained by delaying a first clock signal,
The DLL circuit receives a reset signal for initial activation of the DLL circuit and a restart trigger signal for causing the DLL circuit to resume control of the delay amount of the second clock signal with respect to the first clock signal.
The DLL circuit
In response to the activation of the reset signal or the restart trigger signal, the control of the delay amount is started,
After the reset signal is activated and before the restart trigger signal is activated, control of the delay amount is continued even after the DLL circuit is locked,
After the restart trigger signal is activated, the control of the delay amount is stopped according to the lock of the DLL circuit. The semiconductor device according to claim 1, wherein the restart trigger signal is activated a plurality of times after the reset signal is activated. The semiconductor device according to claim 1, wherein the reset signal is activated when the semiconductor device is powered on. The DLL circuit
A delay line for delaying the first clock signal by the delay amount to generate the second clock signal;
An activation circuit that activates an activation signal in response to activation of the reset signal or the restart trigger signal;
Control of the delay amount is started in response to the activation of the activation signal, while the delay amount is not controlled when the activation signal is inactive and the DLL circuit is locked. A delay amount control circuit, and
The activation circuit deactivates the activation signal in response to the deactivation of the restart trigger signal, while deactivating the activation signal in response to the deactivation of the reset signal. The semiconductor device according to claim 1, wherein the semiconductor device is not performed. The delay amount control circuit is based on at least one of a phase difference between a reference clock signal generated based on the second clock signal and the first clock signal, and a duty ratio of the reference clock signal. The semiconductor device according to claim 4, wherein a count value update operation is performed, and it is determined whether or not the DLL circuit is locked based on the count value. A function of generating a second clock signal obtained by delaying the first clock signal, the phase of the first clock signal and the phase of the reference clock signal generated based on the second clock signal; A semiconductor device including a DLL circuit that controls a delay amount of the second clock signal with respect to the first clock signal so that
First and second DLL update signals are sequentially input to the DLL circuit in this order,
The DLL circuit receives the first DLL update signal and starts controlling the delay amount, and then after the phase of the first clock signal and the phase of the reference clock signal substantially coincide with each other, After continuing the control of the delay amount and receiving the second DLL update signal, the delay amount is controlled according to the fact that the phase of the first clock signal substantially matches the phase of the reference clock signal. A semiconductor device characterized in that control is stopped. A third DLL update signal is input to the DLL circuit following the second DLL update signal,
The DLL circuit receives the third DLL update signal and starts controlling the delay amount, and in response to the phase of the first clock signal substantially matching the phase of the reference clock signal The semiconductor device according to claim 6, wherein control of the delay amount is stopped. The semiconductor device according to claim 6, wherein the first DLL update signal is input to the DLL circuit when the semiconductor device is powered on.

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