JP6902947B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP6902947B2
JP6902947B2 JP2017136328A JP2017136328A JP6902947B2 JP 6902947 B2 JP6902947 B2 JP 6902947B2 JP 2017136328 A JP2017136328 A JP 2017136328A JP 2017136328 A JP2017136328 A JP 2017136328A JP 6902947 B2 JP6902947 B2 JP 6902947B2
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threshold value
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JP2018036253A (en
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友生 挽地
友生 挽地
稔 有山
稔 有山
功造 飯島
功造 飯島
聖史 志賀
聖史 志賀
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Ablic Inc
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Priority to US15/685,508 priority patent/US10110213B2/en
Priority to CN201710735785.0A priority patent/CN107786189B/en
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections

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Description

本発明は、半導体装置に関し、特に高駆動能が高い出力ドライバを備えた出力端子をテスト端子と兼用する技術に関する。 The present invention relates to a semiconductor device, and more particularly to a technique in which an output terminal provided with an output driver having a high drive capability is also used as a test terminal.

端子数の制限から専用のテスト端子を設けることの出来ない半導体装置において、量産検査のためのテストモードへ投入するためのテスト端子を出力端子と兼用する回路が搭載されている。 In a semiconductor device in which a dedicated test terminal cannot be provided due to the limitation of the number of terminals, a circuit is mounted which also serves as an output terminal as a test terminal for inputting to a test mode for mass production inspection.

例えば特許文献１には、出力端子から強制的に電圧を入力することによって発生する、通常動作では起こりえない状態を検出して、テストモードへ移行する技術が開示されている。 For example, Patent Document 1 discloses a technique of detecting a state that cannot occur in normal operation, which is generated by forcibly inputting a voltage from an output terminal, and shifting to a test mode.

特開２００９−３１２２５号公報Japanese Unexamined Patent Publication No. 2009-31225

しかしながら、特許文献１の技術は、電流駆動能力の低い検査装置と、出力端子に電流駆動能力が高い出力ドライバを備えた半導体装置の組み合わせは想定していなかった。 However, the technique of Patent Document 1 does not assume a combination of an inspection device having a low current driving ability and a semiconductor device having an output driver having a high current driving ability at an output terminal.

本発明は、電流駆動能力の低い検査装置であってもテストが可能な、テスト端子と兼用した出力端子に電流駆動能力が高い出力ドライバを備えた半導体装置を提供することを目的としている。 An object of the present invention is to provide a semiconductor device having an output driver having a high current driving ability at an output terminal that also serves as a test terminal, which can test even an inspection device having a low current driving ability.

本発明の半導体装置は、半導体装置の出力端子に接続され夫々閾値の異なる複数の電圧判定回路と、複数の電圧判定回路から入力される信号に応じて２値の符号化信号を出力する符号化回路と、入力される符号化信号と内部回路の信号に応じて内部回路にモード信号を出力するモード切替回路と、を備えたことを特徴とする。 The semiconductor device of the present invention is encoded by connecting to the output terminals of the semiconductor device and outputting a plurality of voltage determination circuits having different thresholds and a binary coded signal according to signals input from the plurality of voltage determination circuits. It is characterized by including a circuit and a mode switching circuit that outputs a mode signal to the internal circuit according to an input coded signal and a signal of the internal circuit.

本発明の半導体装置によれば、複数の電圧判定回路と符号化回路を備えたので、電流駆動能力の低い検査装置であっても、電流駆動能力が高い出力ドライバを備えた出力端子を外部から駆動して、テストモードに切替えることが可能となる。 According to the semiconductor device of the present invention, since a plurality of voltage determination circuits and coding circuits are provided, an output terminal equipped with an output driver having a high current drive capability can be externally provided even for an inspection device having a low current drive capability. It is possible to drive and switch to the test mode.

第１の実施形態の半導体装置のブロック図である。It is a block diagram of the semiconductor device of 1st Embodiment. 第２の実施形態の半導体装置のブロック図である。It is a block diagram of the semiconductor device of 2nd Embodiment. 第３の実施形態の半導体装置のブロック図である。It is a block diagram of the semiconductor device of 3rd Embodiment.

以下、本発明の半導体装置について図面を参照して説明する。 Hereinafter, the semiconductor device of the present invention will be described with reference to the drawings.

＜第１の実施形態＞
図１は、第１の実施形態の半導体装置１００のブロック図である。
第１の実施形態の半導体装置１００は、電圧判定回路１０ａ、１０ｂ、１０ｃと、出力ドライバ２０と、符号化回路３０と、モード切替回路４０、内部回路５０とで構成される。 <First Embodiment>
FIG. 1 is a block diagram of the semiconductor device 100 of the first embodiment.
The semiconductor device 100 of the first embodiment includes voltage determination circuits 10a, 10b, and 10c, an output driver 20, a coding circuit 30, a mode switching circuit 40, and an internal circuit 50.

出力ドライバ２０は、入力が内部回路５０の出力に接続され、出力が半導体装置１００の出力端子ＯＵＴに接続される。出力端子ＯＵＴは、電圧判定回路１０ａ、１０ｂ、１０ｃの入力に接続される。電圧判定回路１０ａ、１０ｂ、１０ｃは、出力がそれぞれ符号化回路３０の入力に接続される。符号化回路３０は、出力がモード切替回路４０の第一入力に接続される。モード切替回路４０は、第二入力が内部回路５０の出力に接続され、出力が内部回路５０の入力に接続される。 In the output driver 20, the input is connected to the output of the internal circuit 50, and the output is connected to the output terminal OUT of the semiconductor device 100. The output terminal OUT is connected to the input of the voltage determination circuits 10a, 10b, and 10c. The outputs of the voltage determination circuits 10a, 10b, and 10c are connected to the inputs of the coding circuit 30, respectively. The output of the coding circuit 30 is connected to the first input of the mode switching circuit 40. In the mode switching circuit 40, the second input is connected to the output of the internal circuit 50, and the output is connected to the input of the internal circuit 50.

電圧判定回路１０ａは、閾値Ｖｔ１を有し、出力信号Ｖ１０ａを出力する。電圧判定回路１０ａの出力信号Ｖ１０ａは、出力端子ＯＵＴの電位ＶＯＵＴが閾値Ｖｔ１以上の時にＨレベルになり、出力端子ＯＵＴの電位ＶＯＵＴが閾値Ｖｔ１未満の時にＬレベルになる。 The voltage determination circuit 10a has a threshold value Vt1 and outputs an output signal V10a. The output signal V10a of the voltage determination circuit 10a becomes H level when the potential VOUT of the output terminal OUT is equal to or higher than the threshold value Vt1, and becomes L level when the potential VOUT of the output terminal OUT is less than the threshold value Vt1.

電圧判定回路１０ｂは、閾値Ｖｔ２を有し、出力信号Ｖ１０ｂを出力する。電圧判定回路１０ｂの出力信号Ｖ１０ｂは、出力端子ＯＵＴの電位ＶＯＵＴが閾値Ｖｔ２以上の時にＨレベルになり、出力端子ＯＵＴの電位ＶＯＵＴが閾値Ｖｔ２未満の時にＬレベルになる。 The voltage determination circuit 10b has a threshold value Vt2 and outputs an output signal V10b. The output signal V10b of the voltage determination circuit 10b becomes H level when the potential VOUT of the output terminal OUT is equal to or higher than the threshold value Vt2, and becomes L level when the potential VOUT of the output terminal OUT is less than the threshold value Vt2.

電圧判定回路１０ｃは、閾値Ｖｔ３を有し、出力信号Ｖ１０ｃを出力する。電圧判定回路１０ｃの出力信号Ｖ１０ｃは、出力端子ＯＵＴの電位ＶＯＵＴが閾値Ｖｔ３以上の時にＨレベルになり、出力端子ＯＵＴの電位ＶＯＵＴが閾値Ｖｔ３未満の時にＬレベルになる。 The voltage determination circuit 10c has a threshold value Vt3 and outputs an output signal V10c. The output signal V10c of the voltage determination circuit 10c becomes H level when the potential VOUT of the output terminal OUT is equal to or higher than the threshold value Vt3, and becomes L level when the potential VOUT of the output terminal OUT is less than the threshold value Vt3.

ここで、閾値Ｖｔ１〜Ｖｔ３は、Ｖｔ１＜Ｖｔ２＜Ｖｔ３の関係を満たしている。 Here, the threshold values Vt1 to Vt3 satisfy the relationship of Vt1 <Vt2 <Vt3.

符号化回路３０は、２値論理回路であり、電圧判定回路１０ａ〜１０ｃの出力信号が入力され、その出力信号に応じて２値信号を出力する。ここで、例えば、電圧判定回路１０ａの出力信号がＬレベル、１０ｂの出力信号がＬレベル、１０ｃの出力信号がＬレベルのとき、ＬＬＬと記載する。符号化回路３０が出力する２値信号は、電圧判定回路１０ａ〜１０ｃの出力信号が、ＬＬＬの時はＬレベル、ＨＬＬの時はＨレベル、ＨＨＬの時はＬレベル、ＨＨＨの時はＨレベル、である。 The coding circuit 30 is a binary logic circuit, and the output signals of the voltage determination circuits 10a to 10c are input, and the binary signals are output according to the output signals. Here, for example, when the output signal of the voltage determination circuit 10a is L level, the output signal of 10b is L level, and the output signal of 10c is L level, it is described as LLL. The binary signal output by the coding circuit 30 is the L level when the voltage determination circuits 10a to 10c are LLL, the H level when it is HLL, the L level when it is HHL, and the H level when it is HHH. ,.

モード切替回路４０は、内部回路５０の出力電位と符号化回路３０の２値信号を入力して、これらの信号が同じ電位であるとき、テストモードに切替えるモード信号を内部回路５０に出力する。 The mode switching circuit 40 inputs the output potential of the internal circuit 50 and the binary signal of the coding circuit 30, and when these signals have the same potential, outputs a mode signal for switching to the test mode to the internal circuit 50.

内部回路５０は、モード切替回路４０から入力されるモード信号に応じて、通常モードであれば、例えば、物理量の大小の判定結果を出力し、テストモードであれば所定のテスト動作を実行する。 The internal circuit 50 outputs, for example, a determination result of a large or small physical quantity in the normal mode according to the mode signal input from the mode switching circuit 40, and executes a predetermined test operation in the test mode.

出力ドライバ２０は、ＰＭＯＳトランジスタとＮＭＯＳトランジスタで構成されたＣＭＯＳ出力ドライバである。ここでは、出力ドライバ２０は、高い電流駆動能力を有する。 The output driver 20 is a CMOS output driver composed of a NMOS transistor and an NMOS transistor. Here, the output driver 20 has a high current drive capability.

次に、第１の実施形態の半導体装置１００の動作について説明する。 Next, the operation of the semiconductor device 100 of the first embodiment will be described.

先ず、内部回路５０がＬレベルの信号を出力している時に、出力端子ＯＵＴの電位ＶＯＵＴを強制的にＬレベルにして、内部回路５０をテストモードにする動作について説明する。 First, when the internal circuit 50 is outputting an L level signal, the operation of forcibly setting the potential VOUT of the output terminal OUT to the L level and putting the internal circuit 50 into the test mode will be described.

内部回路５０がＬレベルの信号を出力している時は、出力ドライバ２０はＰＭＯＳトランジスタがオンして、出力端子ＯＵＴの電位ＶＯＵＴはＨレベルになっている。 When the internal circuit 50 outputs an L level signal, the epitaxial transistor of the output driver 20 is turned on, and the potential VOUT of the output terminal OUT is set to H level.

ここで、出力端子ＯＵＴに電流駆動能力の低い検査装置でソース駆動電流が供給されると、出力ドライバ２０のＰＭＯＳトランジスタのオン抵抗と検査装置の電流駆動能力の関係で出力端子ＯＵＴの電位ＶＯＵＴはＬレベルにすることが出来ない。そして、電位ＶＯＵＴは、閾値Ｖｔ２以上、閾値Ｖｔ３未満になる。 Here, when the source drive current is supplied to the output terminal OUT by an inspection device having a low current drive capability, the potential VOUT of the output terminal OUT changes due to the relationship between the on-resistance of the epitaxial transistor of the output driver 20 and the current drive capability of the inspection device. It cannot be L level. Then, the potential VOUT becomes equal to or more than the threshold value Vt2 and less than the threshold value Vt3.

電圧判定回路１０ａは、出力端子ＯＵＴの電位ＶＯＵＴが閾値Ｖｔ１以上なのでＨレベルの出力信号Ｖ１０ａを出力する。電圧判定回路１０ｂは、出力端子ＯＵＴの電位ＶＯＵＴが閾値Ｖｔ２以上なのでＨレベルの出力信号Ｖ１０ｂを出力する。電圧判定回路１０ｃは、出力端子ＯＵＴの電位ＶＯＵＴが閾値Ｖｔ３未満なのでＬレベルの出力信号Ｖ１０ｃを出力する。即ち、符号化回路３０は、電圧判定回路１０ａ〜１０ｃからＨＨＬの信号が入力される。 Since the potential VOUT of the output terminal OUT is equal to or higher than the threshold value Vt1, the voltage determination circuit 10a outputs the H level output signal V10a. Since the potential VOUT of the output terminal OUT is equal to or higher than the threshold value Vt2, the voltage determination circuit 10b outputs the H level output signal V10b. Since the potential VOUT of the output terminal OUT is less than the threshold value Vt3, the voltage determination circuit 10c outputs the L level output signal V10c. That is, the coding circuit 30 receives an HHL signal from the voltage determination circuits 10a to 10c.

符号化回路３０は、電圧判定回路１０ａ〜１０ｃからＨＨＬの信号が入力されると、Ｌレベルの信号を出力する。即ち、符号化回路３０は、電位ＶＯＵＴが閾値Ｖｔ１未満になった時と同様にＬレベルの信号を出力する。 When the HHL signal is input from the voltage determination circuits 10a to 10c, the coding circuit 30 outputs an L level signal. That is, the coding circuit 30 outputs an L level signal in the same manner as when the potential VOUT becomes less than the threshold value Vt1.

モード切替回路４０は、内部回路５０がＬレベルの信号を出力している時に、符号化回路３０からＬレベルの信号を受けると、出力端子ＯＵＴの電位ＶＯＵＴが強制的にＬレベルにされたと認識して、内部回路５０をテストモードにするモード信号を出力する。 When the mode switching circuit 40 receives the L level signal from the coding circuit 30 while the internal circuit 50 is outputting the L level signal, the mode switching circuit 40 recognizes that the potential VOUT of the output terminal OUT is forcibly set to the L level. Then, a mode signal for setting the internal circuit 50 to the test mode is output.

次に、内部回路５０がＨレベルの信号を出力している時に、出力端子ＯＵＴの電位ＶＯＵＴを強制的にＨレベルにして、内部回路５０をテストモードにする動作について説明する。 Next, when the internal circuit 50 is outputting an H level signal, the operation of forcibly setting the potential VOUT of the output terminal OUT to the H level and putting the internal circuit 50 into the test mode will be described.

内部回路５０がＨレベルの信号を出力している時は、出力ドライバ２０はＮＭＯＳトランジスタがオンして、出力端子ＯＵＴの電位ＶＯＵＴはＬレベルになっている。
ここで、出力端子ＯＵＴに電流駆動能力の低い検査装置でシンク駆動電流が供給されると、出力ドライバ２０のＮＭＯＳトランジスタのオン抵抗と検査装置の電流駆動能力の関係で出力端子ＯＵＴの電位ＶＯＵＴはＨレベルにすることが出来ない。そして、電位ＶＯＵＴは、閾値Ｖｔ１以上、閾値Ｖｔ２未満になる。 When the internal circuit 50 outputs an H level signal, the NMOS transistor of the output driver 20 is turned on, and the potential VOUT of the output terminal OUT is at the L level.
Here, when a sink drive current is supplied to the output terminal OUT by an inspection device having a low current drive capability, the potential VOUT of the output terminal OUT changes due to the relationship between the on-resistance of the NMOS transistor of the output driver 20 and the current drive capability of the inspection device. It cannot be set to H level. Then, the potential VOUT becomes equal to or more than the threshold value Vt1 and less than the threshold value Vt2.

電圧判定回路１０ａは、出力端子ＯＵＴの電位ＶＯＵＴが閾値Ｖｔ１以上なのでＨレベルの出力信号Ｖ１０ａを出力する。電圧判定回路１０ｂは、出力端子ＯＵＴの電位ＶＯＵＴが閾値Ｖｔ２未満なのでＬレベルの出力信号Ｖ１０ｂを出力する。電圧判定回路１０ｃは、出力端子ＯＵＴの電位ＶＯＵＴが閾値Ｖｔ３未満なのでＬレベルの出力信号Ｖ１０ｃを出力する。即ち、符号化回路３０は、電圧判定回路１０ａ〜１０ｃからＨＬＬの信号が入力される。 Since the potential VOUT of the output terminal OUT is equal to or higher than the threshold value Vt1, the voltage determination circuit 10a outputs the H level output signal V10a. Since the potential VOUT of the output terminal OUT is less than the threshold value Vt2, the voltage determination circuit 10b outputs the L level output signal V10b. Since the potential VOUT of the output terminal OUT is less than the threshold value Vt3, the voltage determination circuit 10c outputs the L level output signal V10c. That is, the coding circuit 30 receives an HLL signal from the voltage determination circuits 10a to 10c.

符号化回路３０は、電圧判定回路１０ａ〜１０ｃからＨＬＬの信号が入力されると、Ｈレベルの信号を出力する。即ち、符号化回路３０は、電位ＶＯＵＴが閾値Ｖｔ３以上になった時と同様にＨレベルの信号を出力する。 When the HLL signal is input from the voltage determination circuits 10a to 10c, the coding circuit 30 outputs an H level signal. That is, the coding circuit 30 outputs an H level signal in the same manner as when the potential VOUT becomes the threshold value Vt3 or more.

モード切替回路４０は、内部回路５０がＨレベルの信号を出力している時に、符号化回路３０からＨレベルの信号を受けると、出力端子ＯＵＴの電位ＶＯＵＴが強制的にＨレベルにされたと認識して、内部回路５０をテストモードにするモード信号を出力する。 When the mode switching circuit 40 receives the H level signal from the coding circuit 30 while the internal circuit 50 is outputting the H level signal, the mode switching circuit 40 recognizes that the potential VOUT of the output terminal OUT is forcibly set to the H level. Then, a mode signal for setting the internal circuit 50 to the test mode is output.

以上説明したように、高い電流駆動能力の出力ドライバ２０を備えた第１の実施形態の半導体装置１００は、電圧判定回路１０ａ〜１０ｃと符号化回路３０を備えたので、電流駆動能力の低い検査装置であっても、内部回路５０をテストモードにすることが可能である。 As described above, the semiconductor device 100 of the first embodiment provided with the output driver 20 having a high current driving ability includes the voltage determination circuits 10a to 10c and the coding circuit 30, so that the inspection has a low current driving ability. Even in the device, the internal circuit 50 can be put into the test mode.

＜第２の実施形態＞
図２は、第２の実施形態の半導体装置２００のブロック図である。第２の実施形態の半導体装置２００は、図１の半導体装置１００に追加して低域通過フィルタ６０を備えた。その他の構成については、図１の半導体装置１００と同一であるため、同一の構成要素には同一の符号を付し、説明は省略する。 <Second embodiment>
FIG. 2 is a block diagram of the semiconductor device 200 of the second embodiment. The semiconductor device 200 of the second embodiment includes a low-pass filter 60 in addition to the semiconductor device 100 of FIG. Since the other configurations are the same as those of the semiconductor device 100 of FIG. 1, the same components are designated by the same reference numerals, and the description thereof will be omitted.

低域通過フィルタ６０は、出力端子ＯＵＴと電圧判定回路１０ａ〜１０ｃの間に接続される。低域通過フィルタ６０は、出力端子ＯＵＴにパルス状のノイズが重畳した場合に、電圧判定回路１０ａ〜１０ｃに入力される出力端子ＯＵＴの電位ＶＯＵＴにそのノイズによる電位の変動を受けないようにする機能を有する。 The low-pass filter 60 is connected between the output terminal OUT and the voltage determination circuits 10a to 10c. When the pulse-shaped noise is superimposed on the output terminal OUT, the low-pass filter 60 prevents the potential VOUT of the output terminal OUT input to the voltage determination circuits 10a to 10c from being affected by the potential fluctuation due to the noise. Has a function.

内部回路５０がＨレベルの信号を出力している時は、出力ドライバ２０はＮＭＯＳトランジスタがオンして、出力端子ＯＵＴの電位ＶＯＵＴはＬレベルになっている。ここで、出力端子ＯＵＴにパルス状のＨレベルのノイズが重畳した場合、出力ドライバ２０のＮＭＯＳトランジスタのオン抵抗との関係で出力端子ＯＵＴの電位ＶＯＵＴはパルス状に閾値Ｖｔ１以上、閾値Ｖｔ２未満になる。 When the internal circuit 50 outputs an H level signal, the NMOS transistor of the output driver 20 is turned on, and the potential VOUT of the output terminal OUT is at the L level. Here, when pulse-shaped H-level noise is superimposed on the output terminal OUT, the potential VOUT of the output terminal OUT is pulsed to a threshold value Vt1 or more and less than a threshold value Vt2 in relation to the on-resistance of the NMOS transistor of the output driver 20. Become.

低域通過フィルタ６０は、入力される電位ＶＯＵＴがパルス状に変動しても、一定の時定数に従って応答するため、その出力電位は閾値Ｖｔ１を超ることがない。 Even if the input potential VOUT fluctuates in a pulse shape, the low-pass filter 60 responds according to a constant time constant, so that the output potential does not exceed the threshold value Vt1.

第１の実施形態の半導体装置１００は、電流駆動能力の低い検査装置に対応するために、電圧判定回路１０ａの低い閾値Ｖｔ１によって出力端子ＯＵＴの強制Ｈレベル入力を検出するようにしたので、出力端子ＯＵＴに印加されるノイズの影響を受ける可能性がある。本実施形態の半導体装置２００は、出力端子ＯＵＴと電圧判定回路１０ａ〜１０ｃの間に低域通過フィルタ６０を設けることによって、外部から出力端子ＯＵＴに印加されるノイズの影響を排除することが可能である。 The semiconductor device 100 of the first embodiment detects the forced H level input of the output terminal OUT by the low threshold value Vt1 of the voltage determination circuit 10a in order to correspond to the inspection device having a low current drive capability. It may be affected by the noise applied to the terminal OUT. The semiconductor device 200 of the present embodiment can eliminate the influence of noise applied to the output terminal OUT from the outside by providing the low-pass filter 60 between the output terminal OUT and the voltage determination circuits 10a to 10c. Is.

以上説明したように、第２の実施形態の半導体装置２００によれば、第１の実施形態の半導体装置１００と同様の効果を有し、更に、出力端子ＯＵＴに印加されるノイズの影響を排除することが可能なので、より信頼性の高い半導体装置を提供することが出来る。 As described above, the semiconductor device 200 of the second embodiment has the same effect as the semiconductor device 100 of the first embodiment, and further eliminates the influence of noise applied to the output terminal OUT. Therefore, it is possible to provide a more reliable semiconductor device.

＜第３の実施形態＞
図３は、第３の実施形態の半導体装置３００のブロック図である。第３の実施形態の半導体装置３００は、図１の半導体装置１００に追加してさらに電圧判定回路１０ｄ、１０ｅと、符号化回路３１を備えた。その他の構成については、図１の半導体装置１００と同一であるため、同一の構成要素には同一の符号を付し、説明は省略する。 <Third embodiment>
FIG. 3 is a block diagram of the semiconductor device 300 of the third embodiment. The semiconductor device 300 of the third embodiment further includes voltage determination circuits 10d and 10e and a coding circuit 31 in addition to the semiconductor device 100 of FIG. Since the other configurations are the same as those of the semiconductor device 100 of FIG. 1, the same components are designated by the same reference numerals, and the description thereof will be omitted.

電圧判定回路１０ｄは、閾値Ｖｔ４を有し、出力信号Ｖ１０ｄを出力する。電圧判定回路１０ｄの出力信号Ｖ１０ｄは、出力端子ＯＵＴの電位ＶＯＵＴが閾値Ｖｔ４以上の時にＨレベルになり、出力端子ＯＵＴの電位ＶＯＵＴが閾値Ｖｔ４未満の時にＬレベルになる。 The voltage determination circuit 10d has a threshold value Vt4 and outputs an output signal V10d. The output signal V10d of the voltage determination circuit 10d becomes H level when the potential VOUT of the output terminal OUT is equal to or higher than the threshold value Vt4, and becomes L level when the potential VOUT of the output terminal OUT is less than the threshold value Vt4.

電圧判定回路１０ｅは、閾値Ｖｔ５を有し、出力信号Ｖ１０ｅを出力する。電圧判定回路１０ｅの出力信号Ｖ１０ｅは、出力端子ＯＵＴの電位ＶＯＵＴが閾値Ｖｔ５以上の時にＨレベルになり、出力端子ＯＵＴの電位ＶＯＵＴが閾値Ｖｔ５未満の時にＬレベルになる。 The voltage determination circuit 10e has a threshold value Vt5 and outputs an output signal V10e. The output signal V10e of the voltage determination circuit 10e becomes H level when the potential VOUT of the output terminal OUT is equal to or higher than the threshold value Vt5, and becomes L level when the potential VOUT of the output terminal OUT is less than the threshold value Vt5.

ここで、閾値Ｖｔ１〜Ｖｔ５は、Ｖｔ１＜Ｖｔ２＜Ｖｔ３＜Ｖｔ４＜Ｖｔ５の関係を満たしている。 Here, the threshold values Vt1 to Vt5 satisfy the relationship of Vt1 <Vt2 <Vt3 <Vt4 <Vt5.

符号化回路３１は、２値論理回路であり、電圧判定回路１０ａ〜１０ｅの出力信号が入力され、その出力信号に応じて２値信号を出力する。ここで、２値信号は、電圧判定回路１０ａ〜１０ｅの出力信号が、ＬＬＬＬＬの時はＬレベル、ＨＬＬＬＬの時はＨレベル、ＨＨＬＬＬの時はＬレベル、ＨＨＨＬＬの時はＨレベル、ＨＨＨＨＬの時はＬレベル、ＨＨＨＨＨの時はＨレベル、である。 The coding circuit 31 is a binary logic circuit, and the output signals of the voltage determination circuits 10a to 10e are input, and the binary signals are output according to the output signals. Here, the binary signal is the L level when the voltage determination circuit 10a to 10e is LLLLL, the H level when it is HLLLL, the L level when it is HHLLL, the H level when it is HHHLL, and when it is HHHHL. Is the L level, and when it is HHHHH, it is the H level.

次に、第３の実施形態の半導体装置３００の動作について説明する。 Next, the operation of the semiconductor device 300 of the third embodiment will be described.

先ず、内部回路５０がＬレベルの信号を出力している時に、出力端子ＯＵＴの電位ＶＯＵＴを強制的にＬレベルにして、内部回路５０をテストモードにする動作について説明する。 First, when the internal circuit 50 is outputting an L level signal, the operation of forcibly setting the potential VOUT of the output terminal OUT to the L level and putting the internal circuit 50 into the test mode will be described.

内部回路５０がＬレベルの信号を出力している時は、出力ドライバ２０はＰＭＯＳトランジスタがオンして、出力端子ＯＵＴの電位ＶＯＵＴはＨレベルになっている。 When the internal circuit 50 outputs an L level signal, the epitaxial transistor of the output driver 20 is turned on, and the potential VOUT of the output terminal OUT is set to H level.

出力端子ＯＵＴに電流駆動能力の低い検査装置でソース駆動電流が供給されると、電位ＶＯＵＴは閾値Ｖｔ４以上、閾値Ｖｔ５未満になる。符号化回路３１は、電圧判定回路１０ａ〜１０ｅからＨＨＨＨＬの信号が入力されると、Ｌレベルの信号を出力する。 When the source drive current is supplied to the output terminal OUT by an inspection device having a low current drive capability, the potential VOUT becomes the threshold value Vt4 or more and less than the threshold value Vt5. When the HHHHL signal is input from the voltage determination circuits 10a to 10e, the coding circuit 31 outputs an L level signal.

また、出力端子ＯＵＴの電位ＶＯＵＴが閾値Ｖｔ３以上、閾値Ｖｔ４未満になると、符号化回路３１は、電圧判定回路１０ａ〜１０ｅからＨＨＨＬＬの信号が入力されるので、Ｈレベルの信号を出力する。 Further, when the potential VOUT of the output terminal OUT becomes equal to or more than the threshold value Vt3 and less than the threshold value Vt4, the coding circuit 31 outputs the H level signal because the HHHLL signal is input from the voltage determination circuits 10a to 10e.

従って、閾値Ｖｔ４と閾値Ｖｔ５を近い値に設定すると、内部回路５０をテストモードにするためには、出力端子ＯＵＴの電位ＶＯＵＴを正確に閾値Ｖｔ４以上、閾値Ｖｔ５未満にする必要がある。即ち、符号化回路３１は、外部から出力端子ＯＵＴに印加されるノイズの影響を受け難くなる、と言う効果がある。 Therefore, when the threshold value Vt4 and the threshold value Vt5 are set to close values, the potential VOUT of the output terminal OUT must be accurately set to the threshold value Vt4 or more and less than the threshold value Vt5 in order to put the internal circuit 50 into the test mode. That is, the coding circuit 31 has an effect of being less susceptible to the influence of noise applied to the output terminal OUT from the outside.

更に、符号化回路３１は、電圧判定回路１０ａ〜１０ｅから入力される信号を適切な周期でサンプリングして、２値信号を出力するように構成すれば、よりノイズの影響を受け難くなる。 Further, if the coding circuit 31 is configured to sample the signals input from the voltage determination circuits 10a to 10e at an appropriate cycle and output a binary signal, the coding circuit 31 is less susceptible to noise.

第１の実施形態の半導体装置１００は、電流駆動能力の低い検査装置に対応するために、電圧判定回路１０ａの低い閾値Ｖｔ１によって出力端子ＯＵＴの強制Ｈレベル入力を検出するようにしたので、出力端子ＯＵＴに印加されるノイズの影響を受ける可能性がある。本実施形態の半導体装置３００は、電圧判定回路１０ｄ、１０ｅを更に設けることによって、外部から出力端子ＯＵＴに印加されるノイズの影響を排除することが可能である。 The semiconductor device 100 of the first embodiment detects the forced H level input of the output terminal OUT by the low threshold value Vt1 of the voltage determination circuit 10a in order to correspond to the inspection device having a low current drive capability. It may be affected by the noise applied to the terminal OUT. The semiconductor device 300 of the present embodiment can eliminate the influence of noise applied to the output terminal OUT from the outside by further providing the voltage determination circuits 10d and 10e.

以上説明したように、第３の実施形態の半導体装置３００によれば、第１の実施形態の半導体装置１００と同様の効果を有し、更に、出力端子ＯＵＴに印加されるノイズの影響を排除することが可能なので、より信頼性の高い半導体装置を提供することが出来る。 As described above, the semiconductor device 300 of the third embodiment has the same effect as the semiconductor device 100 of the first embodiment, and further eliminates the influence of noise applied to the output terminal OUT. Therefore, it is possible to provide a more reliable semiconductor device.

以上、本発明の実施形態について説明したが、本発明は上記実施形態に限定されず、本発明の趣旨を逸脱しない範囲において種々の変更や組合せが可能である。例えば、第三の実施形態の半導体装置に低域通過フィルタを設けても良い。また、出力ドライバにはＣＭＯＳドライバを用いた例を示したが、どのような回路の出力ドライバであっても適用が可能である。また、複数の出力端子に適用して、複数ビットからなるパラレル形式のテストモード信号をモード切替回路に供給する構成としてもよい。 Although the embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various modifications and combinations can be made without departing from the spirit of the present invention. For example, the semiconductor device of the third embodiment may be provided with a low-pass filter. Further, although an example in which a CMOS driver is used as the output driver is shown, any circuit output driver can be applied. Further, it may be applied to a plurality of output terminals to supply a parallel type test mode signal composed of a plurality of bits to the mode switching circuit.

１０ａ〜１０ｅ 電圧判定回路
２０ 出力ドライバ
３０、３１ 符号化回路
４０ モード切替回路
５０ 内部回路
６０ 低域通過フィルタ 10a to 10e Voltage judgment circuit 20 Output driver 30, 31 Coding circuit 40 Mode switching circuit 50 Internal circuit 60 Low-pass filter

Claims (6)

内部回路から入力された信号を半導体装置の出力端子に出力する出力ドライバと、
前記半導体装置の出力端子に入力端子が接続され、第１の閾値を有する第１の電圧判定回路と、
前記半導体装置の出力端子に入力端子が接続され、前記第１の閾値よりも高い第２の閾値を有する第２の電圧判定回路と、
前記半導体装置の出力端子に入力端子が接続され、前記第２の閾値よりも高い第３の閾値を有する第３の電圧判定回路と、
前記第１〜３の電圧判定回路の出力端子が入力端子に接続され、前記第１〜３の電圧判定回路の出力信号に応じて２値の符号化信号を出力する符号化回路と、
前記符号化回路の出力端子が入力端子に接続され、入力される前記符号化信号と前記内部回路の前記信号に応じて、前記内部回路にモード信号を出力するモード切替回路と、を備えた、
ことを特徴とする半導体装置。 An output driver that outputs the signal input from the internal circuit to the output terminal of the semiconductor device,
An input terminal is connected to an output terminal of the semiconductor device, and a first voltage determination circuit having a first threshold value and a first voltage determination circuit
A second voltage determination circuit in which an input terminal is connected to an output terminal of the semiconductor device and has a second threshold value higher than the first threshold value.
A third voltage determination circuit in which an input terminal is connected to an output terminal of the semiconductor device and has a third threshold value higher than the second threshold value.
A coding circuit in which the output terminals of the first to third voltage judgment circuits are connected to input terminals and output a binary coded signal according to the output signals of the first to third voltage judgment circuits.
An output terminal of the coding circuit is connected to an input terminal, and a mode switching circuit for outputting a mode signal to the internal circuit according to the coded signal to be input and the signal of the internal circuit is provided.
A semiconductor device characterized by this. 前記符号化回路は、
前記出力端子の電位が前記第１の閾値よりも低い場合に第１の論理信号を出力し、
前記出力端子の電位が前記第１の閾値以上、かつ、前記第２の閾値よりも低い場合に第２の論理信号を出力し、
前記出力端子の電位が前記第２の閾値以上、かつ、前記第３の閾値よりも低い場合に前記第１の論理信号を出力し、
前記出力端子の電位が前記第３の閾値以上の場合に前記第２の論理信号を出力する、
ことを特徴とする請求項１に記載の半導体装置。 The coding circuit
When the potential of the output terminal is lower than the first threshold value, the first logic signal is output.
When the potential of the output terminal is equal to or higher than the first threshold value and lower than the second threshold value, a second logic signal is output.
When the potential of the output terminal is equal to or higher than the second threshold value and lower than the third threshold value, the first logic signal is output.
When the potential of the output terminal is equal to or higher than the third threshold value, the second logic signal is output.
The semiconductor device according to claim 1. 前記半導体装置の出力端子と前記第１〜３の電圧判定回路の入力端子の間に低域通過フィルタを設けた、
ことを特徴とする請求項１または２に記載の半導体装置。 A low-pass filter is provided between the output terminal of the semiconductor device and the input terminal of the first to third voltage determination circuits.
The semiconductor device according to claim 1 or 2. 内部回路から入力された信号を半導体装置の出力端子に出力する出力ドライバと、
前記半導体装置の出力端子に入力端子が接続され、第１の閾値を有する第１の電圧判定回路と、
前記半導体装置の出力端子に入力端子が接続され、前記第１の閾値よりも高い第２の閾値を有する第２の電圧判定回路と、
前記半導体装置の出力端子に入力端子が接続され、前記第２の閾値よりも高い第３の閾値を有する第３の電圧判定回路と、
前記半導体装置の出力端子に入力端子が接続され、前記第３の閾値よりも高い第４の閾値を有する第４の電圧判定回路と、
前記半導体装置の出力端子に入力端子が接続され、前記第４の閾値よりも高い第５の閾値を有する第５の電圧判定回路と、
前記第１〜５の電圧判定回路の出力端子が入力端子に接続され、前記第１〜５の電圧判定回路の出力信号に応じて２値の符号化信号を出力する符号化回路と、
前記符号化回路の出力端子が入力端子に接続され、入力される前記符号化信号と前記内部回路の前記信号に応じて、前記内部回路にモード信号を出力するモード切替回路と、を備えた、
ことを特徴とする半導体装置。 An output driver that outputs the signal input from the internal circuit to the output terminal of the semiconductor device,
An input terminal is connected to an output terminal of the semiconductor device, and a first voltage determination circuit having a first threshold value and a first voltage determination circuit
A second voltage determination circuit in which an input terminal is connected to an output terminal of the semiconductor device and has a second threshold value higher than the first threshold value.
A third voltage determination circuit in which an input terminal is connected to an output terminal of the semiconductor device and has a third threshold value higher than the second threshold value.
A fourth voltage determination circuit in which an input terminal is connected to an output terminal of the semiconductor device and has a fourth threshold value higher than the third threshold value.
A fifth voltage determination circuit in which an input terminal is connected to an output terminal of the semiconductor device and has a fifth threshold value higher than the fourth threshold value.
A coding circuit in which the output terminals of the first to fifth voltage judgment circuits are connected to input terminals and output a binary coded signal according to the output signals of the first to fifth voltage judgment circuits.
An output terminal of the coding circuit is connected to an input terminal, and a mode switching circuit for outputting a mode signal to the internal circuit according to the coded signal to be input and the signal of the internal circuit is provided.
A semiconductor device characterized by this. 前記符号化回路は、
前記出力端子の電位が前記第１の閾値よりも低い場合に第１の論理信号を出力し、
前記出力端子の電位が前記第１の閾値以上、かつ、前記第２の閾値よりも低い場合に第２の論理信号を出力し、
前記出力端子の電位が前記第２の閾値以上、かつ、前記第３の閾値よりも低い場合に前記第１の論理信号を出力し、
前記出力端子の電位が前記第３の閾値以上、かつ、前記第４の閾値よりも低い場合に前記第２の論理信号を出力し、
前記出力端子の電位が前記第４の閾値以上、かつ、前記第５の閾値よりも低い場合に前記第１の論理信号を出力し、
前記出力端子の電位が前記第５の閾値以上の場合に前記第２の論理信号を出力する、
ことを特徴とする請求項４に記載の半導体装置。 The coding circuit
When the potential of the output terminal is lower than the first threshold value, the first logic signal is output.
When the potential of the output terminal is equal to or higher than the first threshold value and lower than the second threshold value, a second logic signal is output.
When the potential of the output terminal is equal to or higher than the second threshold value and lower than the third threshold value, the first logic signal is output.
When the potential of the output terminal is equal to or higher than the third threshold value and lower than the fourth threshold value, the second logic signal is output.
When the potential of the output terminal is equal to or higher than the fourth threshold value and lower than the fifth threshold value, the first logic signal is output.
When the potential of the output terminal is equal to or higher than the fifth threshold value, the second logic signal is output.
The semiconductor device according to claim 4. 前記半導体装置の出力端子と前記第１〜５の電圧判定回路の入力端子の間に低域通過フィルタを設けた、
ことを特徴とする請求項４または５に記載の半導体装置。
A low-pass filter is provided between the output terminal of the semiconductor device and the input terminal of the first to fifth voltage determination circuits.
The semiconductor device according to claim 4 or 5.
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