JP6901509B2 - Impedance reduction device, power supply device, power supply, impedance reduction method and impedance reduction processing program - Google Patents

Description

The present invention relates to a method of suppressing the influence of an output abnormality from a power source.

In the case of a power supply having redundancy by connecting a plurality of power supply modules in parallel, an orling element is generally inserted into an output unit from each power supply module from the viewpoint of preventing backflow of current (Patent Document 1). reference).

FIG. 1 is a conceptual diagram showing a configuration of a power supply 100, which is a general example of a power supply having a redundant configuration.

The power supply 100 shown in FIG. 1 has a redundant configuration by two power supply modules connected in parallel. The power supply 100 is, for example, a power supply for a server.

As shown in FIG. 1, the power supply 100 includes power supply modules 101a and 101b.

To each of the power modules 101a and 101b (each power module) voltage _{V in} a common input voltage is input. It is assumed that each power supply module outputs a voltage V _out , which is the same output voltage, to the load 201. In the power supply 100, even if the output from one of the power supply modules 101a and 101b is stopped, if the output from the other is maintained, _{the supply of the voltage V out} to the load 201 is continued.

FIG. 2 is a conceptual diagram showing the configuration of the power supply module 101, which is an example of each power supply module shown in FIG.

The power supply module 101 includes a voltage control unit 103, a voltage adjustment unit 106, a voltage detection unit 111, an oring element 120, a capacitor 126, a FET control unit 131, and a current detection unit 146. Here, FET is an abbreviation for Field Effect Transistor.

The oring element 120 includes a diode 121 and an FET 116.

_{The voltage detection unit 111 detects the voltage V m} , which is the output voltage from the voltage adjustment unit 106, and sends a signal S2 representing the voltage V _m to the voltage control unit 103.

The voltage control unit 103 sequentially sends the signal S1 which is a control signal for bringing the _{voltage V m} represented by the signal S2 closer to the voltage Vs1 which is a set value for the voltage V _{m to the voltage adjusting unit 106.} As the signal S1, a well-known control signal generally used to bring the output value close to the set value can be used.

The voltage control unit 103 also determines whether the _{voltage V m} represented by the signal S2 sent from the voltage detection unit 111 exceeds the threshold value V _{t 1.} Threshold _{V t} 1, if the voltage _{V m} exceeds the threshold value _{V t} 1, stop the supply to the load 201 of the voltage _{V out} is the power supply module 101 is the output voltage as the abnormal voltage _{V m} is too high resulting This is a threshold value for a predetermined voltage V _m. The reason for stopping the supply of the voltage V _{out to} the load 201 is to suppress damage to the load 201 as much as possible when an abnormality occurs in which the output voltage is too high.

When the voltage control unit 103 determines that the voltage V _m exceeds the threshold value V _t 1, the voltage control unit 103 causes the voltage adjustment unit 106 to stop the output of the signal S1 sent to the voltage adjustment unit 106.

The voltage adjusting unit 106 is, for example, a DC-DC converter or an AC-DC converter. Here, DC is an abbreviation for Direct Current. AC is an abbreviation for Alternating Current.

If the voltage adjustment unit 106 is a DC-DC converter, the voltage _{V in} is the input voltage is a DC voltage. If the voltage adjustment unit 106 is a AC-DC converter, the voltage _{V in} is an AC voltage. _{The voltage V m,} which is the output voltage from the voltage adjusting unit 106, is a DC voltage.

Voltage adjustment unit 106 includes, for example, a variable resistor for changing the voltage V _m which is the output voltage. In that case, the voltage adjusting unit 106 adjusts the value of the voltage V _m by changing the resistance value of the variable resistor according to the signal S1.

The voltage adjusting unit 106 also includes, for example, a switch for stopping the output. In that case, if the signal S1 sent from the voltage control unit 103 indicates to stop the output, the voltage adjusting unit 106 turns off the switch and stops the output.

The current detection unit 146 detects the current value I _out of the output current from the oring element 120. The current detection unit 146 sends a signal S7, which is a signal representing the _{current value I out, to the FET control unit 131.}

FET controller 131, it is determined whether the current value _{I out} expressed by the signal S7 is sent from the current detection unit 146 exceeds the threshold value _{I th.} FET controller 131, when it is determined that the current value _{I out} exceeds the threshold _{I th,} the signal S4 to be sent to the gate of the FET 116, the source - level which conduction between the drain (hereinafter, "on-level" ). FET controller 131, when it is determined that the current value _{I out} is below the threshold value _{I th,} the signal S4 to be sent to the gate of the FET 116, the source - level to insulate the drain (hereinafter, referred to as "off level" .). This operation is a general control performed on an oring element including an FET in the power supply module.

The FET 116 conducts the source and the drain while the signal S4 sent from the FET control unit 131 is on-level. The FET 116 insulates the source and drain while the signal S4 is off-level.

The diode 121 may be a body diode included in the oring element 120 attached to the FET 116.

The capacitor 126 is inserted for removing noise contained in the output from the voltage adjusting unit 106 and for smoothing the output.

JP-A-2015-192301

FIG. 3 is an image diagram showing a time change _{of the voltage V out} , which is the output voltage from the power supply module 101, when an abnormality in which the voltage V _{m rises occurs in the power supply module 101 shown in FIG.} In FIG. 3, it is assumed that the _{voltage V out} starts to rise as a result of an abnormality in _{which the voltage V m rises at time t1.}

The voltage V _out is a value obtained by subtracting the voltage drop in the current path from the output terminal of the voltage adjusting unit 106 to the output terminal of the power supply module 101 from the voltage V _m. If the voltage drop is negligible, the voltage V _out is equal to the voltage V _m. Since the on / off of the FET 116 by the FET control unit 131 is for the purpose of reducing the voltage drop and the accompanying power consumption and heat generation, the voltage drop can usually be ignored.

The voltage control unit 103 determines that the voltage V _m exceeds the threshold value V _t 1 (the threshold value for the voltage V _m corresponding to the voltage V _t 2 in FIG. 3) at time t2, and sends a signal to the voltage adjustment unit 106. Set S1 to the content to stop the output. The voltage adjusting unit 106 receives the content of the signal S1 and stops the output. As a result, the voltage V _out decreases after reaching the _{voltage V t} 2 at time t2.

At time t2, the voltage V _out reaches the voltage V _{t 2.} The voltage V _t 2 is generally set to be about 110% to 130% (typically 120%) of the set value Vs 2 which is _{the set value (rated voltage) for the voltage V out.}

At time t2, the capacitor 126 shown in FIG. 2 stores an electric charge corresponding to the _{voltage V t 2.} Therefore, even after time t2, the current is supplied from the capacitor 126 to the load 201 through the diode 121. The current gradually decreases and approaches zero, but in the period of time t1 and time t3, the voltage V _out exceeds the set value Vs2 which is the rated voltage.

Then, depending on the configuration provided in the load 201, although _{it is permissible for the voltage V out} to reach the voltage V _{t 2, the length of the period during which the voltage V out} between the time t1 and the time t3 exceeds the set value Vs2 is long. It may not be acceptable. In order to suppress a secondary abnormality caused in the load 201 due to an abnormality in which the output voltage exceeds the set value, the period during which the output voltage exceeds the set value should be as short as possible.

An object of the present invention is to provide an impedance reducing device or the like capable of further reducing the probability of occurrence of a secondary abnormality occurring in a load due to an abnormality in which the output voltage from the voltage adjusting unit rises.

The impedance reduction device of the present invention has a determination unit that determines whether or not the output voltage from the voltage adjustment unit that adjusts the input voltage and outputs exceeds the threshold value, and the determination result related to the determination is that the value of the output voltage is the above. It is provided with an impedance reducing unit that reduces the impedance between the subsequent stage of the voltage adjusting unit and the ground when the threshold value is exceeded.

The impedance reducing device or the like of the present invention can further reduce the probability of occurrence of a secondary abnormality occurring in a load due to an abnormality in which the output voltage from the voltage adjusting unit rises.

It is a conceptual diagram which shows the general configuration example of the power supply which has a redundant structure. It is a conceptual diagram which shows the structural example of each power supply module shown in FIG. It is an image diagram which shows the time change of the output voltage in the power supply module shown in FIG. It is a conceptual diagram which shows the structural example of the power supply module of this embodiment. It is a conceptual diagram which shows the processing flow example of the processing to perform when the voltage control part of this embodiment occurs an abnormality that the output rises. It is an image diagram (No. 1) which shows the time change of the output voltage when an abnormality occurs in the power supply module of this embodiment. It is an image diagram (No. 2) which shows the time change of the output voltage when an abnormality occurs in the power supply module of this embodiment. It is a block diagram which shows the minimum structure of the impedance reduction apparatus of embodiment.

The configuration of the power supply of the present embodiment is the power supply 100 shown in FIG. 1, but the configuration of each power supply module included in each power supply 100 of the present embodiment is different from that shown in FIG.

FIG. 4 is a conceptual diagram showing the configuration of the power supply module 101, which is an example of the power supply module of the present embodiment.

The description of the power supply module 101 shown in FIG. 4 is the same as the description of the power supply module 101 shown in FIG. 2 except for the following description. Hereinafter, the parts of the power supply module 101 shown in FIG. 4 that are different from the power supply module 101 shown in FIG. 2 will be described. If the following explanation differs from the explanation in the background technology section, the following explanation will take precedence.

The power supply module 101 shown in FIG. 4 includes an FET control unit 141 and an FET 136 in addition to the configuration provided in the power supply module 101 shown in FIG.

When the voltage control unit 103 determines that the voltage V _m exceeds the threshold value V _t 1, the voltage control unit 103 performs the following two operations.

One of the operations is to make the signal S1 sent to the voltage adjusting unit 106 stop the output of the voltage adjusting unit 106.

The second operation is to make the signal S3 sent to the FET control unit 131 instruct the insulation between the source and the drain of the FET 116.

When the voltage control unit 103 also determines that the voltage V _m exceeds the threshold value V _t 1, the voltage control unit 103 sends a signal S5 to be sent to the FET control unit 141 to the FET control unit 141 to the gate of the FET 136. The content is to switch S6 from off-level to on-level. Here, it is premised that the FET control unit 141 turns off the signal S6 sent to the gate of the FET 136 when the signal S5 does not have the above contents.

When the signal S3 sent from the voltage control unit 103 causes the signal S4 to be turned off, the FET control unit 131 sets the signal S4 to the off level regardless of the _{current value I out represented by the signal S7.} To do.

When the signal S5 sent from the voltage control unit 103 has the above contents, the FET control unit 141 switches the signal S6 sent to the gate of the FET 136 from the off level to the on level.

The FET 136 insulates the source and the drain while the signal S6 sent from the FET control unit 141 to the gate is off-level. The FET 136 also conducts the source-drain while the signal S6 is on-level.

Figure 5 is performed by the voltage control unit 103 depicted in FIG. 4 is a conceptual diagram showing a processing flow example of a process in the case where the abnormality in which the voltage V _m increases occurred.

The voltage control unit 103 starts the process shown in FIG. 5, for example, by inputting start information from the outside.

Then, as the process of S101, the voltage control unit 103 determines whether the _{voltage V m,} which is the output voltage from the voltage adjustment unit 106, exceeds the threshold value V _{t 1.} Here, the threshold value V _{t 1} is the threshold for voltage V _m predetermined purport assumed that the abnormality is the voltage V _m increases when the voltage V _m exceeds the threshold value V _{t 1} occurs.

When the determination result by the processing of S101 is yes, the voltage control unit 103 performs the processing of S102 to S104.

On the other hand, when the determination result by the processing of S101 is no, the voltage control unit 103 performs the processing of S101 again.

When the voltage control unit 103 performs the process of S102, the signal S1 sent to the voltage adjustment unit 106 is set to stop the output as the process. The voltage adjusting unit 106 receives the content of the signal S1 and stops the output.

When the voltage control unit 103 performs the process of S103, the signal S3 sent to the FET control unit 131 is set to the content of turning off the signal S4 as the process. The FET control unit 131 receives the content of the signal S3 and turns the signal S4 off-level. The FET control unit 131 maintains the off level when the signal S4 is already off level.

When the voltage control unit 103 performs the process of S104, the signal S5 sent to the FET control unit 141 is set to turn on the signal S6 as the process. The FET control unit 141 receives the content of the signal S5 and turns the signal S6 on-level. Here, the FET control unit 141 is premised on turning the signal S6 off-level if the signal S5 does not mean to turn the signal S6 on-level.

When the processing of S102 to S104 is completed, the voltage control unit 103 ends the processing shown in FIG.

The voltage control unit 103 includes, for example, a processor and a computer, and executes the process shown in FIG. 5 by the operation of the processor and the computer. When the computer executes the process shown in FIG. 5, the computer may execute the process shown in FIG. 5 by a program held by a storage unit (not shown).

FIG. 6 is an image diagram showing a time change _{of the voltage V out} , which is an output voltage, when an abnormality occurs _{in which the voltage V m} becomes high in the power supply module 101 shown in FIG.
In FIG. 6, it is assumed that the _{voltage V out} starts to rise as a result of an abnormality in _{which the voltage V m} rises at time t1 as in the case shown in FIG.

The voltage V _out is a value obtained by subtracting the voltage drop in the current path from the output terminal of the voltage adjusting unit 106 to the output terminal of the power supply module 101 from the voltage V _m. If the voltage drop is negligible, the voltage V _out is equal to the voltage V _m. Since the on / off of the FET 116 by the FET control unit 131 is for the purpose of reducing the voltage drop and the accompanying power consumption and heat generation, the voltage drop can usually be ignored.

The voltage control unit 103 determines that the voltage V _m exceeds the threshold value V _t 1 (the threshold value for the voltage V _{m corresponding to the voltage V t} 2 in FIG. 6) at time t2, as in the case shown in FIG. Then, the signal S1 sent to the voltage adjusting unit 106 is set to stop the output. The voltage adjusting unit 106 receives the content of the signal S1 and stops the output.

The voltage control unit 103 also sets the signal S3 to be sent to the FET control unit 131 at time t2 so that the signal S4 is turned off. The FET control unit 131 receives the content of the signal S3 and turns the signal S4 off-level. Then, the FET 116 insulates between the source and the drain.

The voltage control unit 103 also sets the signal S5 to be sent to the FET control unit 141 at time t2 so that the signal S6 is turned on. The FET control unit 141 receives the content of the signal S5 and turns the signal S6 on-level. Then, the FET 136 conducts the source and the drain.

At time t2, the capacitor 126 stores an electric charge corresponding to the _{voltage V t 2.}

At time t2, the source and drain of the FET 116 are isolated. Therefore, the current path in the oring element 120 becomes the diode 121. The forward resistance of the diode 121 is greater than the source-drain resistance of the FET 116 in the on state. Therefore, the forward resistance of the diode 121 limits the current flowing through the oring element 120 due to the electric charge.

Then, after the time t2, the electric charge rapidly flows to the ground via the FET 136 which is conducted between the source and the drain. Therefore, the voltage V _out drops rapidly after time t2 as compared with the _{voltage V out shown in FIG.}

Even when it is assumed that the signal S3 does not exist in FIG. 4, the electric charge flows to the ground via the FET 136 which is conducted between the source and the drain after the time t2. Therefore, the voltage V _out drops rapidly after time t2 as compared with the _{voltage V out shown in FIG.} When the signal S3 shown in FIG. 4 is present, the _{rate of decrease of the voltage V out} after the time t2 can be further improved as compared with the case where the signal S3 is not present.

In the case shown in FIG. 6, the _{period in which the voltage V out} exceeds the set value Vs2 is the period between the time t1 and the time t4. The time t3 shown in FIG. 6 is the same as that shown in FIG. In the power supply module 101 shown in FIG. 2, the _{period during which the voltage V out} exceeds the set value Vs2 is between time t1 and time t3. In FIG. 6, the _{period during which the voltage V out} exceeds the set value Vs2 is shorter than that period. As described above, the power supply module 101 shown in FIG. 4 can shorten the period in which _{the voltage V out exceeds the set value Vs2.}

FIG. 7 is an image diagram showing a time change of the voltage V _{out when the upper limit of the voltage V out} is further lowered to the voltage V _{t 3.} In the case shown in FIG. 7, the period in which the voltage V _out exceeds the set value voltage Vs is between the time t1 and the time t5, which is shorter than the case shown in FIG.

Even when the capacitor 126 does not exist in the power supply module 101 shown in FIG. 4, there is a parasitic capacitance in the subsequent stage of the portion of the power supply module 101 where the output is stopped in the voltage adjusting unit 106. Therefore, it can be assumed that the output voltage of the power supply module is maintained in a state of exceeding the set value due to the electric charge stored in the parasitic capacitance. Even in such a case, the power supply module of the present embodiment can shorten the period in which the output voltage exceeds the set value.

Further, when the output voltage of the power supply module exceeds the set value, it can be assumed that the output stop circuit in the voltage adjusting unit 106 shown in FIG. 4 and the detection portion of the signal S3 in the FET control unit 131 are out of order. .. Even in such a case, the power supply module of the present embodiment can shorten the period in which the output voltage exceeds the set value.

The FET 136 shown in FIG. 4 may be another switching element.

Further, the position where the terminal not connected to the ground of the FET 136 is connected is arbitrary as long as it is after the portion where the output of the voltage adjusting unit 106 can be stopped. The position may be inside the voltage adjusting unit 106 or the current detecting unit 146.

Further, the voltage detection unit 111 may be located after the oring element 120 and detect the value of the _{voltage V out.} In that case, in the above description regarding the voltage detection unit 111, the voltage V _m is read as the voltage V _out.
[effect]
In the power supply module of the present embodiment, when an abnormality in which the output rises occurs, the rear stage of the voltage adjusting unit is grounded. As a result, the output voltage is rapidly attenuated as compared with the case without the ground. Therefore, the power supply module can shorten the period in which the output exceeds the set value. Therefore, the power supply module can further reduce the probability of occurrence of a secondary abnormality caused by the abnormality in the load.

Although the technology is not directly related to the power supply device of the embodiment, the following technology can be assumed as a technology that is expected to have the same effect as the effect obtained by the power supply device. However, each of the following technologies has the problems described below.

One such technique is to provide a clamp circuit using a Zener diode inside the power supply module so that the voltage does not exceed a predetermined voltage. However, Zener diodes generally have large variations in their voltage accuracy. Therefore, this method cannot be said to be effective when the allowable output voltage range is narrow. On the other hand, the power supply module of the embodiment can be applied even when the allowable output voltage range is narrow.

It is also conceivable to mount a power supply circuit that stabilizes the load so that the overvoltage is not output even if the subsequent stage of the voltage adjustment unit becomes overvoltage. However, this method requires a predetermined mounting area. Therefore, this method cannot be adopted when such a mounting area cannot be secured. On the other hand, the FET (corresponding to FET 136 shown in FIG. 4) and the FET control unit (corresponding to the FET control unit 141 shown in FIG. 4) included in the power supply module of the embodiment can be mounted in a narrow area as compared with the mounting area. Therefore, the power supply module of the embodiment can solve the above-mentioned problems.

In the above description, when an abnormality occurs in which the output voltage from the voltage adjusting unit rises, the case where the subsequent stage of the voltage adjusting unit is directly grounded by the FET has been described. However, the latter stage may be grounded via an object having a predetermined impedance such as a resistor. The power supply module of the embodiment may include an impedance reducing device that reduces the impedance between the latter stage and the ground when an abnormality occurs in which the output voltage from the voltage adjusting unit rises. The ground does not necessarily have to be the ground of the earth, and is a non-insulator having a size that can be used for so-called grounding of electrical equipment. The non-insulator may be, for example, the main body of the spacecraft when used in the spacecraft.

FIG. 8 is a block diagram showing the configuration of the impedance reduction device 101x, which is the minimum configuration of the impedance reduction device of the embodiment.

The impedance reduction device 101x includes a determination unit 103x and an impedance reduction unit 141x.

The determination unit 103x determines whether or not the output voltage from the voltage adjustment unit that adjusts the input voltage and outputs exceeds the threshold value.

The impedance reducing unit 141x reduces the impedance between the rear stage of the voltage adjusting unit and the ground when the determination result related to the determination indicates that the value of the output voltage exceeds the threshold value.

The impedance reducing device 101x reduces the impedance between the rear stage of the voltage adjusting unit and the ground when an abnormality occurs in which the output voltage from the voltage adjusting unit exceeds the threshold value. Due to the reduction of the impedance, the electric charge existing in the subsequent stage quickly flows to the ground, so that the voltage level in the latter stage is rapidly reduced.

Therefore, the impedance reduction device 101x shortens the period in which the voltage level in the subsequent stage exceeds the set value. In order to suppress a secondary abnormality caused by the abnormality in the load connected to the subsequent stage, it is preferable that the period is as short as possible.

Therefore, the impedance reducing device 101x can further reduce the probability of occurrence of a secondary abnormality occurring in the load due to an abnormality in which the output voltage from the voltage adjusting unit rises.

Therefore, the impedance reducing device 101x exhibits the effects described in the section of [Effects of the Invention] by the above configuration.

Here, the impedance reduction device 101x is, for example, a combination of the voltage control unit 103 shown in FIG. 4, the FET control unit 141, and the FET 136.

Further, the determination unit 103x is, for example, the voltage control unit 103 shown in FIG.

Further, the impedance reduction unit 141x is, for example, a combination of the FET control unit 141 and the FET 136 shown in FIG.

Further, the voltage adjusting unit is, for example, the voltage adjusting unit 106 shown in FIG.

The output voltage is, for example, the voltage V _{m shown} in FIG.

Further, the threshold value is, for example, the threshold value V _t 1 represented in the process of S101 in FIG.

Further, the latter stage is, for example, a subsequent stage of the voltage adjusting unit 106 shown in FIG.

The ground does not necessarily have to be the ground of the earth, and is a non-insulator having a size that can be used for so-called grounding of electrical equipment.

Although each embodiment of the present invention has been described above, the present invention is not limited to the above-described embodiment, and further modifications, substitutions, and adjustments can be made without departing from the basic technical idea of the present invention. Can be added. For example, the composition of the elements shown in each drawing is an example for facilitating the understanding of the present invention, and is not limited to the composition shown in these drawings.

Further, a part or all of the above-described embodiment may be described as in the following appendix, but is not limited to the following.
(Appendix 1)
A determination unit that adjusts the input voltage and determines whether the output voltage from the output voltage adjustment unit exceeds the threshold value, and
When the determination result related to the determination indicates that the value of the output voltage exceeds the threshold value, the impedance reduction unit that reduces the impedance between the rear stage of the voltage adjustment unit and the ground, and the impedance reduction unit.
An impedance reduction device.
(Appendix 2)
The impedance reducing unit is described in Appendix 1, wherein when the determination result indicates that the value of the output voltage exceeds the threshold value, the latter stage is grounded directly or via an object having a finite impedance. Impedance reduction device.
(Appendix 3)
The impedance reducing device according to Appendix 1, wherein the thing having impedance is a thing having resistance.
(Appendix 4)
The impedance reduction unit includes a switch installed between the rear stage and the ground, and the reduction makes the switch conduct with the rear stage and the ground directly or through an object having a second impedance. The impedance reduction device according to any one of Supplementary note 1 to Supplementary note 3, which is performed according to the above.
(Appendix 5)
The impedance reduction device according to Appendix 4, further comprising a switch control unit that switches between conduction and insulation between two terminals in the switch.
(Appendix 6)
The impedance reduction device according to Appendix 4 or 5, wherein the switch comprises a field effect transistor.
(Appendix 7)
A stop unit for stopping the output of the output voltage is further provided, and the stop unit performs the stop when the determination result indicates that the value of the output voltage exceeds the threshold value. The impedance reducing device according to any one of.
(Appendix 8)
In the latter stage, a diode and a second field effect transistor connected in parallel are connected in series, and the second is when the determination result indicates that the value of the output voltage exceeds the threshold value. The impedance reducing device according to any one of Supplementary note 1 to Supplementary note 7, wherein the field effect transistor insulates between the source and the drain.
(Appendix 9)
The impedance reduction device according to Appendix 8, wherein the element in which the diode and the second field effect transistor are connected in parallel is an oring element.
(Appendix 10)
Between the source and drain of the second field effect transistor, depending on whether or not the current detection unit that detects the current level in the subsequent stage and the current level and the determination result indicate that the value of the output voltage exceeds the threshold value. The impedance reduction device according to Appendix 8 or Appendix 9, further comprising a second switch control unit that switches between insulation and continuity.
(Appendix 11)
The impedance reducing device according to Appendix 10, wherein the second switch control unit conducts conduction between the source and drain of the second field effect transistor when the current level exceeds a predetermined current threshold value.
(Appendix 12)
A power supply device including the impedance reducing device according to any one of Supplementary Note 1 to Supplementary Note 11 and the voltage adjusting unit.
(Appendix 13)
A power supply in which a plurality of power supply devices described in Appendix 12 are connected in parallel.
(Appendix 14)
The process of adjusting the input voltage and determining whether the output voltage from the output voltage adjustment unit exceeds the threshold value, and
An impedance reduction processing device that executes a process of reducing the impedance between the subsequent stage of the voltage adjusting unit and the ground when the determination result related to the determination indicates that the value of the output voltage exceeds the threshold value. ..
(Appendix 15)
Adjusts the input voltage, determines whether the output voltage from the output voltage adjustment unit exceeds the threshold value, and determines whether or not it exceeds the threshold value.
When the determination result according to the determination indicates that the value of the output voltage exceeds the threshold value, the impedance between the rear stage of the voltage adjusting unit and the ground is reduced.
Impedance reduction method.
(Appendix 16)
The process of adjusting the input voltage and determining whether the output voltage from the output voltage adjustment unit exceeds the threshold value, and
Impedance reduction that causes a computer to perform a process of reducing the impedance between the subsequent stage of the voltage adjusting unit and the ground when the determination result related to the determination indicates that the value of the output voltage exceeds the threshold value. Processing program.

100 Power supply 101, 101a, 101b Power supply module 101x Impedance reduction device 103 Voltage control unit 103x Judgment unit 106 Voltage adjustment unit 111 Voltage detection unit 116, 136 FET
120 Oring element 121 Diode 131, 141 FET control unit 141x Impedance reduction unit 146 Current detection unit 201 Load

Claims (10)

A determination unit that adjusts the input voltage and determines whether the output voltage from the output voltage adjustment unit exceeds the threshold value, and
When the determination result related to the determination indicates that the value of the output voltage exceeds the threshold value, the impedance reduction unit that short-circuits between the rear stage of the voltage adjustment unit and the ground
An impedance reduction device. The impedance reduction device according to claim 1 , wherein the impedance reduction unit directly grounds the latter stage when the determination result indicates that the value of the output voltage exceeds the threshold value. Claim 1 or claim 2 in which the impedance reducing unit includes a switch installed between the rear stage and the ground, and the short circuit is performed by causing the switch to directly conduct with the rear stage and the ground. Impedance reduction device described in. The impedance reducing device according to claim 3, further comprising a switch control unit that switches between conduction and insulation between two terminals in the switch. Claims 1 to 1, further comprising a stop unit for stopping the output of the output voltage, wherein the stop unit performs the stop when the determination result indicates that the value of the output voltage exceeds the threshold value. The impedance reduction device according to any one of item 4. In the latter stage, a diode and a second field effect transistor connected in parallel are connected in series, and the second is when the determination result indicates that the value of the output voltage exceeds the threshold value. The impedance reducing device according to any one of claims 1 to 5, wherein the field effect transistor insulates between the source and the drain. A power supply device including the impedance reducing device according to any one of claims 1 to 6 and the voltage adjusting unit. A power supply in which a plurality of power supply devices according to claim 7 are connected in parallel. Adjusts the input voltage, determines whether the output voltage from the output voltage adjustment unit exceeds the threshold value, and determines whether or not it exceeds the threshold value.
When the determination result according to the determination indicates that the value of the output voltage exceeds the threshold value, the impedance between the rear stage of the voltage adjusting unit and the ground is short-circuited .
Impedance reduction method. The process of adjusting the input voltage and determining whether the output voltage from the output voltage adjustment unit exceeds the threshold value, and
Impedance reduction that causes the computer to perform a process of short-circuiting the impedance between the subsequent stage of the voltage adjusting unit and the ground when the determination result related to the determination indicates that the value of the output voltage exceeds the threshold value. Processing program.

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