JP2009273243A - Power supply unit, and image processor, power supply control method, program and storage medium therewith - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power supply unit can prevent misoperation of a device, and an image processor, a power supply method, a program and a storage medium therewith. <P>SOLUTION: Misoperation of the device can be prevented by on-off controlling discharge circuit means based on detection information of residual charges. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a power supply control apparatus that supplies a power supply voltage to a plurality of devices, an image processing apparatus using the same, a power supply control method, a program, and a storage medium.

In recent years, apparatuses having a plurality of devices have been developed along with diversification of electronic devices. For this reason, a power supply apparatus that supplies a power supply voltage to a plurality of devices has been developed.
FIG. 15 is a block diagram of a power supply control device related to the present invention.

  The power supply control device shown in FIG. 15 includes a DC-DC converter 1 (53), a DC-DC converter 2 (54), a DC-DC converter 3 (55), and a DC-DC converter (53) that operate at a power supply voltage + 5VE. Generated by the devices 59a to 59c that operate with the generated output voltage Vout1, the devices 60a to 60c that operate with the output voltage Vout2 generated by the DC-DC converter 2 (54), and the DC-DC converter 3 (55) It comprises devices 61a to 61c that operate with the output voltage Vout3.

The power supply control device shown in FIG. 15 has the discharge timing shown in FIG.
In the power supply control device shown in FIG. 15, when the main power is turned on (P1), the DC-DC converter 1 (53), the DC-DC converter 2 (54), and the DC-DC converter 3 (55) are turned on sequentially. (P2 to P4) When the main power is turned off (P2), DC-DC converter 1 (53), DC-DC converter 2 (54), and DC-DC converter 3 (55) are turned off at the same time (P6) However, since there are residual charges, the waveforms of the output voltages Vout1 to Vout3 have different discharge periods (P7).
For this reason, when the main power is turned on again, the manual describes a restriction such as waiting for 1 second or more after the main power is turned off and then turning on the main power. As a result of this restriction, when the main power supply of the power control device is turned on again (P8), the DC-DC converter 1 (53), the DC-DC converter 2 (54), and the DC-DC converter 3 (55) are sequentially turned on. (P9-P11).

FIG. 17 is a block diagram of another power supply control device related to the present invention.
The power supply control device shown in the figure is obtained by providing a discharge reset IC 14, a discharge circuit 1 (15), a discharge circuit 2 (16), and a discharge circuit 3 (17) in the power supply control device shown in FIG. .

The power supply control device shown in FIG. 17 has the discharge timing shown in FIG.
In the power supply control device shown in FIG. 17, when the main power supply is turned on (P1), the DC-DC converter 1 (53), the DC-DC converter 2 (54), and the DC-DC converter 3 (55) are sequentially turned on. (P2 to P4), when the main power is turned off (P2), the DC-DC converter 1 (53), the DC-DC converter 2 (54), and the DC-DC converter 3 (55) are turned off at the same time ( P6), the discharge time for the residual charge is the longest discharge time required for discharging the residual charge when the main power supply of the power supply control device is turned off (maximum time required for discharging the residual charge: P9 in FIG. 18). Is set as a set value (see FIG. 17). Regardless of the presence or absence of residual charges, the discharge circuits 15 to 17 work at the maximum discharge time value, and the startup speed is slow.
In addition, as described above, the discharge circuits 15 to 17 have the maximum discharge time value (the maximum time required for the residual charge to be discharged) for various voltages, so that the operating environment state before turning off the main power supply, etc. Depending on the case, when the residual charges of various voltages are discharged earlier than the maximum discharge time value (P9), useless discharge time is generated, and the start-up speed becomes slow (P10 to P13).

A technique related to this type of power supply control device is disclosed in Patent Document 1.
The invention described in this Patent Document 1 states that “a plurality of power supply voltages generating means each for generating a power supply voltage and a plurality of power supply voltages generated by each of the power supply voltage generating means while monitoring a plurality of power supply voltages. A power supply apparatus comprising: a start-up control that performs a start-up operation in the order of: A time measuring means for measuring the time from the time until the one power supply voltage that is performing the falling operation out of a plurality of power supply voltages becomes lower than a predetermined voltage during the falling operation. When the time measured by the means exceeds a predetermined time, it is controlled to perform the next power supply voltage falling operation ".

That is, the invention described in Patent Document 1 is characterized in that the next output voltage is controlled while monitoring the output of the previous stage in the startup sequence of the power supply sequence.
According to the invention described in Patent Document 1, a plurality of power supply voltages can be surely dropped in a predetermined order, and a plurality of power supply voltages can be reduced during the shutdown control for dropping the plurality of power supply voltages in a predetermined order. Even when the start-up is requested, the power supply voltages can be raised in a predetermined order after the power supply voltages are lowered in a predetermined order.
JP 2006-311748 A

By the way, the invention described in Patent Document 1 is provided with a discharge circuit to discharge for a certain period (regardless of the presence or absence of residual charge).
However, although the discharge circuit is provided in the invention described in Patent Document 1, the discharge time is set to the maximum time (fixed) required for the residual charge to be discharged. Will work. For this reason, a device connected to the power supply device may malfunction.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a power supply control apparatus that can prevent device malfunction, an image processing apparatus using the same, a power supply control method, a program, and a storage medium.

  In order to solve the above-described problem, the invention described in claim 1 includes a voltage generation unit that generates a plurality of supply voltages corresponding to different devices based on an input power source, a residual charge detection unit that detects residual charges, Discharge circuit means for discharging electric charge, and control means for controlling on / off of the discharge circuit means based on information from the residual charge detection means.

  According to a second aspect of the present invention, in the first aspect of the present invention, the control unit turns on the residual charge detection unit and turns on the discharge circuit unit within a voltage generation period defined by each device. It is characterized by.

  According to a third aspect of the present invention, in the first aspect of the present invention, the control unit determines a discharge time of a discharge circuit unit for discharging the residual charge based on information from the residual charge detection unit. It is characterized by controlling.

  According to a fourth aspect of the present invention, in the first aspect of the present invention, the control unit performs the total residual charge detection within a period in which the residual charge is first detected based on information from the residual charge detection unit. And the discharge circuit means is turned on.

  According to a fifth aspect of the present invention, in the first aspect of the invention, the control unit controls the detection and discharge of the residual charge within a period defined by each device.

  According to a sixth aspect of the present invention, in the first aspect of the present invention, the control means performs on / off control of the discharge circuit means based on information in a storage means storing residual charge information. It is characterized by.

  A seventh aspect of the invention is an image processing apparatus including the power supply control device according to any one of the first to sixth aspects.

  The invention according to claim 8 generates a plurality of supply voltages corresponding to different devices based on an input power supply, detects a residual charge when the input power supply is turned off, and based on the information on the residual charge The residual charge is discharged.

  A ninth aspect of the invention is characterized in that, in the eighth aspect of the invention, the residual charge is detected and the residual charge is discharged within a voltage generation period defined by each device.

  According to a tenth aspect of the present invention, in the eighth aspect of the invention, a discharge time of the residual charge is controlled based on the information on the residual charge.

  According to an eleventh aspect of the invention, in the eighth aspect of the invention, based on the residual charge information, the total residual charge is detected within a period in which the residual charge is first detected, and the residual charge is discharged. It is characterized by doing.

  A twelfth aspect of the invention is characterized in that in the invention of the eighth aspect, the detection and discharge of the residual charge are controlled within a period defined by each device.

  According to a thirteenth aspect of the present invention, in the eighth aspect of the invention, the residual charge is discharged based on the residual charge information stored in the storage means.

  According to a fourteenth aspect of the present invention, in the computer, the voltage generating means generates a plurality of supply voltages corresponding to different devices based on the input power supply, the residual charge detecting means detects the residual charge, the discharge circuit means Is characterized in that a procedure for discharging the residual charge and a procedure for controlling the on / off by the discharge circuit means based on information from the residual charge detection means are executed.

  The invention according to claim 15 is a storage medium storing the program according to claim 14.

  According to the present invention, malfunction of the device can be prevented by controlling on / off of the discharge circuit means on the basis of information on detection of residual charge.

An embodiment of a power supply control device according to the present invention includes a voltage generation unit that generates a plurality of supply voltages corresponding to different devices based on an input power supply, a residual charge detection unit that detects residual charge, and a residual charge. Discharge circuit means for discharging and control means for controlling on / off of the discharge circuit means based on information from the residual charge detection means.
Examples of the device include an image reading device, a printer, and an HDD (Hard Disc Drive) in a multifunction machine. As the residual charge, for example, the residual charge of an electrolytic capacitor used in a smoothing circuit of a power source built in each device can be cited.
As the discharge circuit means, for example, the source is grounded and the drain is connected to one terminal of an electrolytic capacitor used for the smoothing circuit of the power supply circuit of the device through a resistor, and a control signal for discharge is applied to the gate. An input FET (field effect transistor) can be mentioned.

  According to the above configuration, malfunction of the device can be prevented by controlling on / off of the discharge circuit means based on the detection information of the residual charge.

  In another embodiment of the power supply control device according to the present invention, in addition to the above configuration, the control means turns on the residual charge detection means and turns on the discharge circuit means within the voltage generation period defined by each device. It is characterized by doing.

  According to the above configuration, the residual charge can be detected (measured) within each voltage generation period of the power supply sequence (power supply voltage supply order) defined by each device, and the residual charge can be discharged within that period. Since the discharge period (time) is not newly added to the power supply sequence, the startup speed of the apparatus can be increased.

  In another embodiment of the power supply control device according to the present invention, in addition to the above configuration, the control means controls the discharge time of the discharge circuit means for discharging the residual charge based on information from the residual charge detection means. It is characterized by doing.

  According to the above configuration, the discharge time of the discharge circuit means for discharging the residual charge can be controlled based on the result of feedback of the residual charge detection (measurement) information. Setting the time value to zero can increase the startup speed. In addition, when there is residual charge, the residual charge detection (measurement) information is fed back, so the maximum discharge time value can be set to an optimum value (value corresponding to the residual charge time), and the startup speed can be increased. can do.

  In another embodiment of the power supply control device according to the present invention, in addition to the above-described configuration, the control unit performs total residual charge detection within a period in which the residual charge is first detected based on information from the residual charge detection unit. And the discharge circuit means is turned on.

  According to the above configuration, the residual charge of all the various voltages can be detected within the period of the power supply sequence defined by each device, and the discharge circuit means having the residual charge can be turned on based on the detection result. , Power sequence control can be facilitated.

  Another embodiment of the power supply control device according to the present invention is characterized in that, in addition to the above configuration, the control means controls the detection and discharge of the residual charges within a period defined by each device.

  According to the above configuration, since the residual charge detection (measurement) and the discharge of the residual charge can be controlled based on the time within each voltage generation period of the power supply sequence, the power supply sequence can be controlled without delay, and the startup speed Will not be affected.

  In another embodiment of the power supply control device according to the present invention, in addition to the above configuration, the control means performs on / off control of the discharge circuit means based on the information of the storage means storing the residual charge information. It is characterized by.

  According to the above configuration, since it is possible to perform the on-control of the discharge circuit means based on the information of the storage means storing the residual charge information, it is possible to eliminate the time required for detecting the residual charge, and to increase the residual charge. Charge discharge processing and other processing can be performed.

  An image processing apparatus according to the present invention is an image processing apparatus including any one of the power supply control devices described above.

  An embodiment of a power supply control method according to the present invention generates a plurality of supply voltages corresponding to different devices based on an input power supply, detects a residual charge when the input power supply is turned off, and detects residual charge information Based on the above, the residual charge is discharged.

  According to the above configuration, malfunction of the device can be prevented by controlling on / off of the discharge circuit means based on the detection information of the residual charge.

  Another embodiment of the power supply control method according to the present invention is characterized in that, in addition to the above configuration, the residual charge is detected and the residual charge is discharged within a voltage generation period defined by each device.

  According to the above configuration, the residual charge can be detected (measured) within each voltage generation period of the power supply sequence defined by each device, and the residual charge can be discharged within that period. Time) is not newly added, the startup speed of the apparatus can be increased.

  Another embodiment of the power supply control method according to the present invention is characterized in that, in addition to the above configuration, the discharge time of the residual charge is controlled based on the residual charge information.

  According to the above configuration, the discharge time of the discharge circuit means for discharging the residual charge can be controlled based on the result of feedback of the residual charge detection (measurement) information. Setting the time value to zero can increase the startup speed. In addition, when there is residual charge, the residual charge detection (measurement) information is fed back, so the maximum discharge time value can be set to an optimum value (value corresponding to the residual charge time), and the startup speed can be increased. can do.

  In another embodiment of the power supply control method according to the present invention, in addition to the above configuration, based on the residual charge information, the total residual charge is detected within the period when the residual charge is first detected, and the residual charge is discharged. It is characterized by doing.

  According to the above configuration, the residual charge of all the various voltages can be detected within the period of the power supply sequence defined by each device, and the discharge circuit means having the residual charge can be turned on based on the detection result. , Power sequence control can be facilitated.

  Another embodiment of the power supply control method according to the present invention is characterized in that, in addition to the above configuration, the detection and discharge of residual charges are controlled within a period defined by each device.

  According to the above configuration, since the residual charge detection (measurement) and the discharge of the residual charge can be controlled based on the time within each voltage generation period of the power supply sequence, the power supply sequence can be controlled without delay, and the startup speed Will not be affected.

  Another embodiment of the power supply control method according to the present invention is characterized in that, in addition to the above configuration, the residual charge is discharged based on the residual charge information stored in the storage means.

  According to the above configuration, since it is possible to perform the on-control of the discharge circuit means based on the information of the storage means storing the residual charge information, it is possible to eliminate the time required for detecting the residual charge, and to increase the residual charge. Charge discharge processing and other processing can be performed.

<Program and storage medium>
The power control apparatus or image processing apparatus of the present invention described above is realized by a program that causes a computer to execute processing. Examples of the computer include general-purpose computers such as personal computers and workstations, but the present invention is not limited to this.

  One embodiment of the program according to the present invention is a procedure for causing a computer to generate a plurality of supply voltages corresponding to different devices based on an input power source, a procedure for a residual charge detection means to detect a residual charge, The discharge circuit means discharges the residual charge, and the discharge circuit means executes a procedure for controlling on / off based on information from the residual charge detection means.

  According to the above configuration, malfunction of the device can be prevented by controlling on / off of the discharge circuit means based on the detection information of the residual charge.

With the above configuration, the power supply control device or the image processing device of the present invention can be realized anywhere as long as there is a computer environment in which the program can be executed.
Such a program may be stored in a computer-readable storage medium.

  Here, examples of the storage medium include computer-readable storage media such as a CD-ROM (Compact Disc Read Only Memory), a flexible disk (FD), a CD-R (CD Recordable), and a DVD (Digital Versatile Disk). Semiconductor memories such as HDD, flash memory, RAM (Random Access Memory), ROM (Read Only Memory), and FeRAM (ferroelectric memory).

  The above-described embodiment shows an example of a preferred embodiment of the present invention, and the present invention is not limited thereto, and various modifications can be made without departing from the scope of the invention. is there.

FIG. 1 shows an example of a configuration diagram of hardware (H / W) of a power supply control device according to the present invention.
The DC-DC converter 1 (53), DC-DC converter 2 (54), and DC-DC converter 3 (55) are connected to the devices 59a to 59c on the board based on the input power input from the outside. This is a regulator for generating a supply voltage. The DC-DC converter 1 (53) to the DC-DC converter 3 (55) can be controlled to be turned on / off by an external trigger input to the EN terminal.

Also, the PWG terminals of DC-DC converter 1 (53) to DC-DC converter 3 (55) are the specified values for the output voltage of DC-DC converter 1 (53) to DC-DC converter 3 (55). Enabled by reaching
The discharge circuit 1 (56), the discharge circuit 2 (57), and the discharge circuit 3 (58) are charges that are temporarily left as residual charges with no supply voltage consumed when the main power of the device is turned off. It is a discharge circuit for discharging (for example, the electric charge of the electrolytic capacitor of a smoothing circuit). The discharge circuits 1 (56) to 3 (58) are constituted by FETs (Field Effect Transistors) or the like.

  The 1-chip CPU (Central Processing Unit) is connected via the 5VE system, which is the same system as the input voltage of DC-DC converter 1 (53) to DC-DC converter 3 (55). AD (Analog Digital) AD1 (52a), AD2 (52b), and AD2 (52b) to detect the presence or absence of residual charge) (different from the voltage generated by DC converter 1 (53) to DC-DC converter 3 (55)) AD3 (52c) is built-in, and the presence or absence of residual charge is detected by setting (changeable) a reference value (threshold value) indicating whether or not residual charge exists in an internal register.

Also, the terminals EN1 to 3 are terminals for controlling on / off of the discharge circuits 56 to 58 by controlling the terminals EN1 to 3 when the main power of the apparatus is turned off / on and it is detected that there is a residual charge. It is.
The memory 51 is a memory for storing residual charge presence / absence information of the supply voltage when the main power is off / on.

The outline of the power supply sequence in this H / W structure is demonstrated along the timing chart of FIG.
FIG. 2 is an example of a timing chart when there is no residual charge in the power supply control device according to the present invention.
After the main power supply of the power supply control unit is turned on (P1 to P4), it is turned off (P5, P6) and then turned on again (P7). Unit: Power supply unit). By supplying 5VE, Vout1 is generated by the DC-DC converter 1 (53) (P8).
At the same time as the voltage Vout1 is generated, power is supplied to the one-chip CPU 52, and the charge of Vout1 is detected. When the output voltage of Vout1 reaches 70% or more of the design value, the EN pin of DC-DC converter 2 (54) is enabled and the output voltage of DC-DC converter 2 (54) is generated (P9) .
Furthermore, when the output voltage of Vout2 reaches 70% or more of the design value, the EN pin of DC-DC converter 3 (55) is enabled and the output voltage of DC-DC converter 3 (55) is generated ( P9).

FIG. 7 is a flowchart showing an embodiment of the power control method according to the present invention.
This will be described below with reference to the power supply control device shown in FIG. 1 and the flowchart shown in FIG.

When the main power supply of the power supply control device shown in FIG. 1 is turned on, 5VE is supplied. The one-chip CPU 52 writes a reference value (threshold value) in a register in the one-chip CPU 52 for determining whether there is a residual charge. The one-chip CPU 52 is an AD converter (AD1 (52a) to AD3 (52C)) built in the one-chip CPU 52. The level of the voltage supplied to each device 59a to 59c, 60a to 60c, 61a to 61c (residual) The presence or absence of charge) is detected (FIG. 7: S1), and the presence or absence of residual charge is determined, that is, compared with a reference value (threshold) (FIG. 7: S2).
The one-chip CPU 52 turns on the discharge circuits 56 to 57 (FIG. 7: S3) when there is residual charge (FIG. 7: S2 / Yes), and further remains when there is no residual charge (FIG. 7: S2 / No). The presence or absence of charge is determined (FIG. 7: S4).
The one-chip CPU 52 stands by when there is a residual charge (FIG. 7: S4 / Yes), and turns off the discharge circuits 56 to 57 when there is no residual charge (FIG. 7: S5).

  That is, the power supply control device includes a discharge circuit 56 for discharging residual charges based on the result of comparing the level of the voltage supplied to each device 59a to 59c, 60a to 60c, 61a to 61c with a reference value. Performs on / off control of ~ 57. The one-chip CPU 52 performs control while detecting the residual charge during the period when the discharge circuits 56 to 57 are on.

FIG. 3 is an example of a timing chart of residual charge detection for the next voltage generation in the power supply control device according to the present invention. FIG. 8 is a flowchart showing another embodiment of the power control method according to the present invention.
The following description will be made along the power supply control device shown in FIG. 1, the timing chart shown in FIG. 3, and the flowchart shown in FIG.

  The main power supply of the power supply control device shown in FIG. 1 is once turned on (FIG. 3: P1 to P4) and then turned off (FIG. 3: P5, P6), and when it is turned on again (FIG. 3: P7), the output voltage Vout2 A case where a residual charge waveform is recognized in the waveform of FIG. 3, that is, a case where there is a residual charge (FIG. 3: P9) will be described.

  When the main power supply of the power control device is turned on again (FIG. 3: P7), 5VE is supplied. The one-chip CPU 52 has a register for determining the presence or absence of residual charge, and the one-chip CPU 52 writes a reference value (threshold value) for the presence or absence of residual charge in the register. The one-chip CPU 52 sets a reference value for each of the output voltages Vout1, Vout2, and Vout3.

The one-chip CPU 52 also stores the set values of the power supply sequence times (design values) of the output voltages Vout1, Vout2, and Vout3 generated by the DC-DC converter 1 (53) to the DC-DC converter 3 (55). Write in.
When the above settings including the H / W initial settings are completed, the 1-chip CPU 52 sets the voltage level of Vout1 (with or without residual charge) with the AD1 converter 52a built in the 1-chip CPU 52 until the time Vout1 is output. It detects (FIG. 8: S11) and compares with a reference value (threshold) (FIG. 8: S11).
When there is a residual charge (FIG. 3: P9, FIG. 8: S12 / Yes), the one-chip CPU 52 turns on the discharge circuits 56 to 57 (FIG. 8: S13), and when there is no residual charge (FIG. 8: S12 / No) performs residual charge detection of the next voltage (FIG. 8: S14).

Here, the one-chip CPU 52 does not enable the discharge circuit 1 (56) when the output voltage Vout1 is lower than the reference value (threshold value) as a result of comparing the output voltage Vout1 with the reference value (EN1 terminal of the one-chip CPU 52). Is disabled.)
When the output time of Vout1, which is the design value, elapses from the supply of 5VE, the output voltage Vout1 is generated (FIG. 3: P8). To supplement here, when detecting the voltage level of the output voltage Vout1 after initialization of the 1-chip CPU 52 after 5VE supply, the output time of the output voltage Vout1 from the 5VE supply is short, and after the output of the output voltage Vout1 When the voltage level of the output voltage Vout1 is detected, the time from the 5VE output to the output voltage Vout1 (design value) is stored in the memory 51, so the 5VE output level is erroneously detected as having residual charge. Never do.

  After the output voltage Vout1 is output, the 1-chip CPU 52 uses the time until the output voltage Vout2 is output, and the AD2 converter (52b) built in the 1-chip CPU 52 uses the voltage level of the output voltage Vout2 (residual The presence or absence of charge) is detected and compared with a reference value (threshold value). As a result of the comparison, the output voltage Vout2 is higher than the reference value (threshold value) (FIG. 3: P9). Therefore, the discharge circuit 2 (57) is enabled (FIG. 3: P10), and the residual charge of the output voltage Vout2 is discharged. (Enable the EN2 pin of 1-chip CPU52).

FIG. 9 is a flowchart showing another embodiment of the power control method according to the present invention.
This will be described below with reference to the flowcharts shown in FIGS.

  When the main power supply is once turned on and then turned off (Fig. 3: P1 to P6), and when it is turned on again (Fig. 3: P7), a residual charge is observed in the waveform of the output voltage Vout2, that is, the residual charge. The case where there is (FIG. 3: P9) will be described as an example.

  When the main power supply of the power supply control device is turned on (FIG. 3: P7), 5VE is supplied. The one-chip CPU 52 has a register for determining the presence / absence of residual charge, and the one-chip CPU 52 writes a reference value (threshold) for the presence / absence of residual charge in the register. The reference value is set for each of the output voltages Vout1, Vout2, and Vout3. The one-chip CPU 52 also stores the power supply sequence time (design values) of the output voltages Vout1, Vout2, and Vout3 generated by the DC-DC converter 1 (53) to the DC-DC converter 3 (54) in the memory 51. Write in.

When the setting including the H / W initial setting is completed, the 1-chip CPU 52 uses the AD1 converter (52a) built in the 1-chip CPU 52 to output the voltage level (residual charge) until the Vout1 is output. Presence / absence) is detected (FIG. 9: S21) and compared with a reference value (threshold) (FIG. 9: S22).
When the output voltage Vout1 is lower than the reference value (threshold value) as a result of comparing the voltage level of the output voltage Vout1 with the reference value, the one-chip CPU 52 does not enable the discharge circuit 1 (56). (The EN1 pin of the 1-chip CPU52 is disabled).
The one-chip CPU 52 generates the output voltage Vout1 when the output time of the output voltage Vout1, which is a design value, has elapsed from the supply of 5VE. After the output voltage Vout1 is output, the 1-chip CPU 52 uses the time until the output voltage Vout2 is output, and the AD2 converter (52b) built in the 1-chip CPU 52 uses the voltage level of the output voltage Vout2 (residual The presence / absence of charge) is detected and compared with a reference value (threshold value). As a result of comparison, the output voltage Vout2 is higher than the reference value (threshold value) (FIG. 3: P9). Therefore, the discharge circuit 2 (57) is enabled (EN2 terminal of the 1-chip CPU52 is enabled), and Vout2 The residual charge is discharged (FIG. 9: S23).

  While discharging the residual charge of the output voltage Vout2, the AD2 converter (52b) continues to detect the voltage level of Vout2 (presence / absence of residual charge) (FIG. 9: S24). When the residual charge of the output voltage Vout2 becomes lower than the reference value (threshold value), the discharge circuit 2 (57) is disabled (the EN2 terminal of the one-chip CPU 52 is disabled). Thereafter, when the output time of Vout2 elapses, an output voltage Vout2 is generated (FIG. 3: P12), and then the voltage level of Vout3 (presence / absence of residual charge) is detected by the AD3 converter (52c) (FIG. 9: S25).

FIG. 10 is a flowchart showing another embodiment of the power control method according to the present invention.
This will be described below with reference to the timing chart of FIG. 4 and the flowchart of FIG.
FIG. 4 is an example of a timing chart of residual charge detection of all generated voltages in the power supply control device according to the present invention.

  When the main power supply is once turned on and then turned off (P1 to P6), and when it is turned on again (P7), if residual charges are observed in the waveforms of the output voltages Vout2 and Vout3, that is, there is residual charge. A case will be described as an example.

  When the main power of the power control device is turned on (P7), 5VE is supplied. The one-chip CPU 52 has a register for determining the presence / absence of residual charge, and the one-chip CPU 52 writes a reference value (threshold) for the presence / absence of residual charge in the register. The one-chip CPU 52 sets a reference value for each of the output voltages Vout1, Vout2, and Vout3. Further, the one-chip CPU 52 also stores the set values of the power supply sequence times (design values) of the output voltages Vout1, Vout2, and Vout3 generated by the DC-DC converter 1 (53) to the DC-DC converter 3 (55). Write in. When the above settings including H / W initial settings are completed, the voltage level of the output voltage Vout1 (presence of residual charge) is detected by the AD1 converter 52a built in the one-chip CPU 52 during the time until Vout1 is output ( FIG. 10: S31) and comparison with the reference value (threshold) (FIG. 10: S32).

As a result of the comparison, if the output voltage Vout1 is lower than the reference value (threshold value), the one-chip CPU 52 does not enable the discharge circuit 1 (56). (The EN1 pin of the 1-chip CPU52 is disabled).
The output voltage Vout1 is generated when the output time of the output voltage Vout1, which is a design value, elapses from the supply of 5VE. After the output voltage Vout1 is output, the 1-chip CPU 52 uses the time until the output voltage Vout2 is output, and the AD2 converter (52b) built in the 1-chip CPU 52 uses the voltage level of the output voltage Vout2 (residual The presence / absence of charge) is detected and compared with a reference value (threshold value). When the comparison result is that the output voltage Vout2 is higher than the reference value (threshold value) and there is residual charge, the one-chip CPU 52 detects the voltage level of the output voltage Vout3 (residual charge presence or absence) (after the output voltage Vout3 in the power supply sequence) All output voltage levels with a voltage output of: are detected: FIG. 10: S33).

When the one-chip CPU 52 determines that there is residual charge in the output voltages Vout2 and 3, it enables the discharge circuits 2 and 3 (FIG. 10: S34, FIG. 4: P11, P12).
The one-chip CPU 52 continues to detect the voltage level of Vout2 and 3 (presence / absence of residual charge) with the AD2 and 3 converters while discharging the residual charge of the output voltages Vout2 and 3 (FIG. 10: S35).

The one-chip CPU 52 disables the discharge circuits 2 and 3 (the EN2 and 3 terminals of the one-chip CPU are disabled) when the residual charges of the output voltages Vout2 and 3 become lower than the reference value (threshold value) (FIG. 1). 10: S36, FIG. 4: P13).
When the discharge circuit 2 is disabled, the output voltage Vout2 is output. Since the one-chip CPU 52 performs processing on the residual charges of all output voltages after the output voltage Vout1 is output and before the output voltage Vout2 is output, the time Vout1 → Vout2 may be longer than the design value. The time extended by the processing is added to the power supply sequence time (design value) of the output voltages Vout1, Vout2, and Vout3 stored in the memory 51 (FIG. 10: S37, FIG. 4: P14, P15).

This will be described below with reference to the flowcharts shown in FIGS.
FIG. 5 is an example of a timing chart of residual charge detection within the sequence definition of the power supply control device according to the present invention. FIG. 11 is a flowchart showing another embodiment of the power control method according to the present invention.
When the main power supply is once turned on and then turned off (P1 to P6), when residual charges are observed in the waveforms of the output voltages Vout2 and Vout3, that is, there are residual charges (P9, P10) explain.

When the main power supply of the power control device is turned on, 5VE is supplied (P7).
The one-chip CPU 52 has a register for determining the presence / absence of residual charge, and the one-chip CPU 52 writes a reference value (threshold) for the presence / absence of residual charge in the register. The one-chip CPU 52 sets the reference value for each of the output voltages Vout1, Vout2, and Vout3. Further, the one-chip CPU 52 also stores the set values of the power supply sequence times (design values) of the output voltages Vout1, Vout2, and Vout3 generated by the DC-DC converter 1 (53) to the DC-DC converter 3 (55). Write in.

  When the settings including the H / W initial setting are completed, the voltage level of the output voltage Vout1 (AD1 converter 52a) built in the one-chip CPU 52 is output (P6 to P8) until the output voltage Vout1 is output. The presence or absence of residual charge is detected (FIG. 11: S41) and compared with a reference value (threshold) (FIG. 11: S42). As a result of comparison, the output voltage Vout1 of the 1-chip CPU 52 is lower than the reference value (threshold value) (FIG. 11: S42 / None), so the discharge circuit 1 (56) is not enabled (the EN1 terminal of the 1-chip CPU 52 is disabled). .

The one-chip CPU 52 determines whether or not the output time (next voltage generation time) of Vout1, which is a design value, from the supply of 5VE has come (FIG. 11: S44), and determines that it is the next voltage generation time (S44 / Yes) The output voltage Vout1 is generated (FIG. 11: S45).
After the output voltage Vout1 is output, the 1-chip CPU 52 uses the time until the output voltage Vout2 is output (time indicated by P16), and the AD2 converter (52b) built in the 1-chip CPU 52 outputs it. The voltage level of voltage Vout2 (residual charge presence / absence) is detected (FIG. 11: S46) and compared with a reference value (threshold) (FIG. 11: S47).
When the output voltage Vout2 is higher than the reference value (threshold value) as a result of the comparison (FIG. 11: S47 / Yes), the 1-chip CPU 52 enables the discharge circuit 2 (57) (enabling the EN2 terminal of the 1-chip CPU 52) The residual charge of a voltage generation source (not shown) of the output voltage Vout2 (for example, an electrolytic capacitor of a smoothing circuit) is discharged (FIG. 11: S48).
The one-chip CPU 52 determines whether or not the next voltage generation time has elapsed (FIG. 11: S49). If it is determined that it has elapsed (FIG. 11: S49 / Yes), the detection of the next voltage residual charge is terminated. (FIG. 11: S50) When it determines with not having passed (FIG. 11: S49 / No), it returns to step S46.

Next, in step S48 of FIG. 11, the one-chip CPU 52 detects the voltage level of the output voltage Vout3 (presence / absence of residual charge) with the AD3 converter (52c), but before that, the output voltage Vout2 stored in the memory 51 is detected. → Judges whether there is processing time to detect the voltage level (presence / absence of residual charge) of output voltage Vout3 with respect to power supply sequence time (design value) of output voltage Vout3 (whether it is next voltage generation time) (FIG. 11: S44).
If the one-chip CPU 52 determines that it is the next voltage generation time, that is, that there is no processing time (FIG. 11: S44 / Yes), it ends without detecting the voltage level (presence / absence of residual charge) of the output voltage Vout3 (FIG. 11). 11: S45).
When the one-chip CPU 52 determines that it is not the next voltage generation time, that is, there is a processing time (FIG. 11: S44 / No), it detects the voltage level (presence / absence of residual charge) of the output voltage Vout3 (FIG. 11: S46). Compared with the reference value (threshold value) (FIG. 11: S47).
As a result of the comparison, the output voltage Vout3 is higher than the reference value (threshold value), and thus the one-chip CPU 52 enables the discharge circuit 3 (58) (enables the EN3 terminal of the one-chip CPU 52), and the output voltage Vout3 is not shown. Residual charges are discharged (for example, an electrolytic capacitor of a smoothing circuit) (FIG. 11: S48).
Detection is performed in consideration of the power supply sequence time (design value) of the output voltages Vout1, Vout2, and Vout3 stored in the memory 51. That is, it is determined whether or not it is the next voltage generation time (FIG. 11: S49). If it is the next voltage generation time (FIG. 11: S49 / Yes), the detection of the residual charge of the next voltage is terminated (FIG. 11: S50). If it is not the next voltage generation time (FIG. 11: S49 / No), the process returns to step S46. For this reason, the time from the output voltage Vout1 to the output voltage Vout2 remains at the designed value.

This will be described below with reference to the flowcharts shown in FIGS.
FIG. 6 is an example of a timing chart of charge discharge of all generated voltages by residual charge detection in the power supply control device according to the present invention. FIG. 12 is a flowchart showing another embodiment of the power control method according to the present invention.

  A case will be described as an example where residual charges are recognized in the waveforms of the output voltages Vout2 and Vout3 when the main power supply is once turned on and then turned off and turned on again (P1 to P10).

  When the main power supply of the power control device is turned on again, 5VE is supplied (P7, P8). The one-chip CPU 52 has a register for determining the presence / absence of residual charge, and the one-chip CPU 52 writes a reference value (threshold) for the presence / absence of residual charge in the register. The one-chip CPU 52 sets a reference value for each of the output voltages Vout1, Vout2, and Vout3. Further, the one-chip CPU 52 also stores the set values of the power supply sequence times (design values) of the output voltages Vout1, Vout2, and Vout3 generated by the DC-DC converter 1 (53) to the DC-DC converter 3 (55). Write in.

  When the setting to include the H / W initial settings is completed, the voltage level of Vout1 (presence of residual charge) is detected by the AD1 converter 52a built in the one-chip CPU 52 during the time until the output voltage Vout1 is output (see figure). 12: S51) and a reference value (threshold) is compared (FIG. 11: S52).

  If the output voltage Vout1 is lower than the reference value (threshold value) as a result of comparison, the 1-chip CPU 52 does not enable the discharge circuit 1 (56) (the EN1 terminal of the 1-chip CPU 52 is disabled). ).

The output voltage Vout1 is generated when the output time of the output voltage Vout1, which is a design value, elapses from the supply of 5VE.
After the output voltage Vout1 is output, the 1-chip CPU 52 uses the time until the output voltage Vout2 is output, using the AD2 converter 52b built in the 1-chip CPU 52, and the voltage level of the output voltage Vout2 (residual charge presence / absence) ) Is detected and compared with a reference value (threshold value) (FIG. 12: S52).

When the one-chip CPU 52 determines that the output voltage Vout2 is higher than the reference value (threshold value) as a result of the comparison (P9) and there is residual charge, it stores the residual charge information in the memory 51 (FIG. 12: S53). Thereafter, the one-chip CPU 52 enables the discharge circuit 2 (57) (enables the EN2 terminal of the one-chip CPU 52) (FIG. 12: S54), and outputs an output voltage Vout2 of a voltage source (not shown) (for example, an electrolytic capacitor of a smoothing circuit). The residual charges are discharged (P10, P11). Similarly, residual charge information is also stored in the memory 51 for the output voltage Vout3 (FIG. 12: S54).
The memory 51 described here is a non-volatile memory such as NVRAM or FRAM.

The one-chip CPU 52 determines whether or not the residual charge detection for all voltages has been completed (FIG. 12: S55). If the residual charge detection for all voltages has not been completed (FIG. 12: S55 / No), the next voltage Is detected (FIG. 12: S60), and the process returns to step S52.
When the residual charge detection for all voltages is completed (FIG. 12: S55 / Yes), the one-chip CPU 52 completes the detection of the residual charge (FIG. 12: S56), and when the main power is turned on for the second and subsequent times (FIG. 12: In S57), since the residual charge for each voltage is detected based on the information stored in the memory 51 (FIG. 12: S58), the residual charge for each voltage is not detected. 2 (57) and the discharge circuit 3 (58) are enabled (FIG. 12: S59).
However, the enable timing is before the output voltages Vout2 and 3 are output (P12 to P14).

FIG. 13 is a conceptual diagram showing an embodiment of an image processing apparatus according to the present invention.
In a digital copying machine as an image processing apparatus, an image is formed by a scanner unit 101 and a laser recording unit 102, and printing on a sheet is performed, and output paper alignment, stapling, and punching holes are performed by a post-processing unit 103. The scanner unit 101 includes a transparent glass platen 104, an automatic double-sided document feeder 105 (hereinafter referred to as RADF) that feeds a document on the top surface of the document table, and reads an image of a document placed on the top surface of the document table. The scanner unit 106 is used.

  Image data read by the scanner unit 101 is output to the laser recording unit 102. The RADF 105 is a single-sided document feed path from a document tray (not shown) to a discharge tray (not shown) via a document table, and reverses the front and back surfaces of a document on which one-sided image reading has been completed by the scanner unit 106 and guides it to the document table again. It has a double-sided document feed path and can handle both single-sided and double-sided originals. The scanner unit 106 irradiates a document with a lamp and forms an image of reflected light of the document on a light receiving surface of a photoelectric conversion element with a lens, a mirror, or the like.

  The photoelectric conversion element converts the reflected light on the image surface of the document into an electrical signal and outputs the electrical signal to an image processing unit described later. The laser recording unit 102 includes a paper transport unit 107 that transports paper, a laser writing unit 108, and an electrophotographic process unit (image forming unit) 109. In the double-sided copying mode in which images are formed on both sides of a sheet, the sheet conveying unit 107 includes a sub-conveying path that reverses the front and back surfaces of the sheet that has passed through the fixing roller and guides the sheet again to the electrophotographic process unit.

  The laser writing unit 108 is a semiconductor laser that emits laser light based on the image data supplied from the image processing unit, and the light emitted from the semiconductor laser is arranged on the surface of the photosensitive drum of the electrophotographic process unit 109 through a mirror or lens. Shine. An electrostatic latent image is formed on the surface of the photosensitive drum, and the toner image is made visible by supplying toner from the developing device.

  The toner image is transferred onto the paper guided from the paper transport unit 107, and then heated and pressurized by a fixing roller, and the toner image is melted and fixed on the surface of the paper. After writing on the paper is completed in this way, a part of the output paper is aligned in the post-processing unit 103, staple and punch hole processing is performed, and the paper is discharged to the tray.

Next, the control unit of the copying machine will be described with reference to FIG.
FIG. 14 is a diagram showing an example of a control unit of the copying machine shown in FIG.
The control unit of the copying machine controls the devices constituting each unit through a CPU mounted on the board arranged for each unit by the CPU 202 mounted on the image processing board 201. In other words, the control unit of the copying machine includes an operation panel board 229 for managing an operation panel 226 provided on the upper surface of the copying machine, a machine control board 232 for managing each crisis in the copying machine, and a CCD on which photoelectric conversion elements are mounted together with peripheral components. The board 211 includes an image processing board 201 on which a CPU for performing various kinds of image processing on image data is mounted together with peripheral components.

Next, processing of image data in the copy mode in the copying machine will be described.
The image of the document fed to the document table via the RADF 105 is sequentially read by the scanner unit. Driven by the CCD control unit 213 on the CCD board 211 in the scanner unit, the output signal is subjected to gain adjustment by the analog circuit 215, and is sent from the A / D conversion unit 212 to the image processing board 201 as 8-bit image data. Sent.

  After predetermined image processing is performed in the image processing unit 204, image data for one page is stored in the page memory 206 once by the memory and network control unit 205. The image stored in the page memory 206 is then read out and stored in the server device via the network.

<Effect>
(1) Since ON / OFF of the discharge circuit means can be controlled based on the feedback result of the residual charge detection (measurement) information, the power supply sequence defined by the device can be observed.

(2) Residual charge can be detected (measured) within each voltage generation period of the power supply sequence specified by each device, and the residual charge can be discharged within the period, and the discharge period (time) is newly added to the power supply sequence. Therefore, the start-up speed of the apparatus can be increased.

(3) The discharge time of the discharge circuit means for discharging the residual charge can be controlled based on the feedback result of the residual charge detection (measurement) information. Setting it to zero can increase the startup speed (see FIG. 2). In addition, when there is residual charge, the residual charge detection (measurement) information is fed back, so the maximum discharge time value can be set to an optimal value (a value corresponding to the residual charge time), and the startup speed can be increased. can do.

(4) Since the residual charge of all the various voltages can be detected within the period of the power supply sequence specified by each device, the discharge circuit means of the voltage with the residual charge can be turned on based on the detection result. Control can be facilitated.

(5) Since residual charge detection (measurement) and residual charge discharge can be controlled based on the time within each voltage generation period of the power supply sequence, it can be controlled without delaying the power supply sequence, affecting the startup speed. Does not reach.

(6) Since the discharge circuit means can be turned on based on the information of the storage means storing the residual charge information, the time required for detection of the residual charge can be eliminated, and more residual charges can be discharged. Processing and other processing can be performed.

(7) The image processing apparatus can have the same effect as described above by including any of the power supply control devices.

It is a figure which shows an example of the block diagram of the hardware (H / W) of the power supply control apparatus which concerns on this invention. It is an example of a timing chart when there is no residual charge in the power supply control device according to the present invention. It is an example of a timing chart of residual charge detection of the next voltage generation in the power supply control device according to the present invention. It is an example of a timing chart of residual charge detection of all generated voltages in the power supply control device according to the present invention. It is an example of the timing chart of the residual charge detection within the sequence prescription | regulation of the power supply control apparatus which concerns on this invention. It is an example of the timing chart of the charge discharge of all the generation voltages by the residual charge detection in the power supply control device which concerns on this invention. It is a flowchart which shows one Example of the power supply control method which concerns on this invention. It is a flowchart which shows the other Example of the power supply control method which concerns on this invention. It is a flowchart which shows the other Example of the power supply control method which concerns on this invention. It is a flowchart which shows the other Example of the power supply control method which concerns on this invention. It is a flowchart which shows the other Example of the power supply control method which concerns on this invention. It is a flowchart which shows the other Example of the power supply control method which concerns on this invention. It is a conceptual diagram which shows one Example of the image processing apparatus which concerns on this invention. It is a figure which shows an example of the control part of the copying machine shown in FIG. It is a block diagram of the power supply control apparatus relevant to this invention. It is a discharge timing chart of the power supply control device shown in FIG. It is a block diagram of the other power supply control apparatus relevant to this invention. It is a discharge timing chart of the power supply control device shown in FIG.

Explanation of symbols

51 Memory 52 1-chip CPU
53 DC-DC Converter 1
54 DC-DC Converter 2
55 DC-DC Converter 3
56 Discharge circuit 1
57 Discharge circuit 2
58 Discharge circuit 3
59a, 59b, 59c, 60a, 60b, 60c, 61a, 61b, 61c device

Claims (15)

  Voltage generating means for generating a plurality of supply voltages corresponding to different devices based on an input power supply, residual charge detecting means for detecting residual charge, discharge circuit means for discharging the residual charge, and residual charge detection And a control means for controlling on / off of the discharge circuit means based on information from the means.   2. The power supply control apparatus according to claim 1, wherein the control means turns on the residual charge detection means and turns on the discharge circuit means within a voltage generation period defined by each device.   2. The power supply control apparatus according to claim 1, wherein the control means controls a discharge time of a discharge circuit means for discharging the residual charge based on information from the residual charge detection means.   The control means, based on information from the residual charge detection means, performs total residual charge detection within a period in which the residual charge is first detected, and turns on the discharge circuit means. The power supply control device according to 1.   The power supply control apparatus according to claim 1, wherein the control unit controls the detection and discharge of the residual charge within a period defined by each device.   2. The power supply control apparatus according to claim 1, wherein the control unit performs on / off control of the discharge circuit unit based on information in a storage unit storing residual charge information.   An image processing apparatus comprising the power supply control device according to claim 1.   Generating a plurality of supply voltages corresponding to different devices based on an input power supply, detecting a residual charge when the input power supply is turned off, and discharging the residual charge based on the information on the residual charge; Power control method.   The power supply control method according to claim 8, wherein the residual charge is detected and the residual charge is discharged within a voltage generation period defined by each device.   9. The power supply control method according to claim 8, wherein a discharge time of the residual charge is controlled based on the information on the residual charge.   9. The power supply control method according to claim 8, wherein all residual charges are detected within a period in which the residual charges are first detected based on the residual charge information, and the residual charges are discharged.   The power supply control method according to claim 8, wherein detection and discharge of the residual charge are controlled within a period defined by each device.   9. The power supply control method according to claim 8, wherein the residual charge is discharged based on information on the residual charge stored in the storage means.   In the computer, the voltage generating means generates a plurality of supply voltages corresponding to different devices based on the input power supply, the residual charge detecting means detects the residual charge, the discharge circuit means discharges the residual charge, And a program for causing the discharge circuit means to execute an on / off control procedure based on information from the residual charge detection means.   A storage medium storing the program according to claim 14.

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