JP2022113960A - Electronic apparatus - Google Patents

Abstract

To provide an electronic apparatus capable of suppressing stoppage of power supply to a storage portion while the storage portion executes internal processing without providing a power supply portion having a special function.SOLUTION: An image forming device 10 includes a storage portion 5 that executes predetermined internal processing, a power supply portion 6 that stops supplying power to the storage portion 5 in response to the input of a predetermined first signal, a signal input portion 8 that inputs the first signal to the power supply portion 6 in response to the input of a predetermined second signal when the storage portion 5 does not execute the internal processing, and does not input the first signal to the power supply portion 6 when the storage portion 5 executes the internal processing, and a control portion 7 that inputs the second signal to the signal input portion 8.SELECTED DRAWING: Figure 2

Description

The present invention relates to electronic equipment.

Flash memory and other storage units installed in electronic devices such as printers may experience problems such as corruption of the data stored inside if the power supply from the power supply is interrupted during internal processing such as writing data. may occur. On the other hand, while an electric signal indicating that internal processing is being executed is being output from the storage device, a power-off prohibition signal is input to the power source that supplies power to the storage device to stop the power-off operation by the power source. An information processing device that prohibits is known as a related technology (see, for example, Patent Document 1).

JP-A-8-95715

However, in the related art described above, it is necessary to provide the electronic device with a power supply section that can prohibit the power-off operation in response to the input of the power-off prohibition signal.

SUMMARY OF THE INVENTION An object of the present invention is to provide an electronic device capable of suppressing stoppage of power supply to a storage section while the storage section is executing internal processing without providing a power supply section having a special function.

An electronic device according to the present invention includes a storage section, a power supply section, a signal input section, and a control section. The storage unit executes predetermined internal processing. The power supply unit stops supplying power to the storage unit in response to input of a predetermined first signal. The signal input section inputs the first signal to the power supply section in response to the input of a predetermined second signal when the storage section is not executing the internal processing, and the storage section When processing is being executed, the first signal is not input to the power supply unit. The control section inputs the second signal to the signal input section.

According to the present invention, it is possible to suppress power supply stoppage to the storage unit while the storage unit is executing internal processing without providing a power supply unit having a special function.

FIG. 1 is a diagram showing the configuration of an image forming apparatus according to an embodiment of the invention. FIG. 2 is a diagram showing the configuration of the image forming apparatus according to the embodiment of the invention. FIG. 3 is a diagram showing the configuration of the signal input section of the image forming apparatus according to the embodiment of the invention. FIG. 4 is a timing chart showing digital signals input and output in the signal input section of the image forming apparatus according to the embodiment of the present invention and output voltage of the power supply section.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. It should be noted that the following embodiment is an example that embodies the present invention, and does not limit the technical scope of the present invention.

[Configuration of Image Forming Apparatus 10]
First, the configuration of an image forming apparatus 10 according to an embodiment of the present invention will be described with reference to FIGS. 1 and 2. FIG. Here, FIG. 1 is a sectional view showing the configuration of the image forming apparatus 10. As shown in FIG. 2 is a block diagram showing the configuration of the storage section 5, the power supply section 6, the control section 7, and the signal input section 8. As shown in FIG. In FIG. 2, the digital signals output from the storage section 5, the control section 7, and the signal input section 8 are indicated by arrow lines.

The image forming apparatus 10 is a multifunction device having a plurality of functions such as a scanning function for reading image data from a document, a printing function for forming an image based on the image data, a facsimile function, and a copying function. The image forming apparatus 10 is an example of the electronic device of the invention. Note that the electronic device of the present invention may be a scanner, printer, facsimile machine, copier, personal computer, notebook computer, or the like.

As shown in FIGS. 1 and 2, the image forming apparatus 10 includes an ADF (Auto Document Feeder) 1, an image reading unit 2, an image forming unit 3, a paper feeding unit 4, a storage unit 5, a power supply unit 6, a control unit 7 and a signal input unit 8 .

The ADF 1 conveys a document to be read by the scanning function. For example, the ADF 1 includes a document setting section, a plurality of transport rollers, a document presser, and a paper ejection section.

The image reading section 2 realizes the scanning function. For example, the image reading unit 2 includes a platen, a light source, a plurality of mirrors, an optical lens, and a CCD (Charge Coupled Device).

The image forming section 3 realizes the printing function. For example, the image forming section 3 forms an image on a sheet supplied from the paper feeding section 4 by electrophotography. For example, the image forming section 3 includes a photosensitive drum, a charging roller, an optical scanning device, a developing device, a transfer roller, a cleaning device, a fixing device, and a paper output tray.

The paper feeding unit 4 supplies sheets to the image forming unit 3 . For example, the paper feed unit 4 includes a paper feed cassette, a manual feed tray, a sheet transport path, and a plurality of transport rollers.

The storage unit 5 is a nonvolatile storage device. For example, the storage unit 5 is a non-volatile memory such as flash memory or EEPROM (registered trademark). Note that the storage unit 5 may be an SSD (Solid State Drive) or an HDD (Hard Disk Drive).

The storage unit 5 executes predetermined internal processing. For example, the internal processing includes program processing for writing data inside the storage unit 5 and erase processing for erasing data written inside the storage unit 5 .

The storage unit 5 inputs a predetermined third signal to the signal input unit 8 during execution of the internal processing. Here, the third signal is a logic level digital signal of either a high level or a low level.

Specifically, the storage unit 5 includes an output terminal 51 shown in FIG. 2 . A digital signal S1 (see FIG. 2) containing the third signal is output from the output terminal 51 . The output terminal 51 is connected to the signal input section 8 . That is, the digital signal S 1 output from the output terminal 51 is input to the signal input section 8 . The output terminal 51 is an example of the third terminal of the invention.

For example, the storage unit 5 inputs the high-level digital signal S1 to the signal input unit 8 when the internal processing is not being executed. The storage unit 5 also inputs the low-level digital signal S1 to the signal input unit 8 when the internal processing is being executed. In this case, the third signal is a low level digital signal S1. The third signal may be a high level digital signal S1.

The power supply unit 6 is a power supply device capable of supplying power supplied from an external power supply to the storage unit 5 . For example, the power supply unit 6 includes an AC-DC converter that converts an AC voltage of 100V supplied from the external power supply into a DC voltage of a predetermined voltage value.

The power supply unit 6 stops supplying power to the storage unit 5 in response to the input of a predetermined first signal. Here, the first signal is a digital signal of any logic level.

Specifically, the power supply unit 6 includes an input terminal 61 shown in FIG. A digital signal S2 (see FIG. 2) including the first signal is input to the input terminal 61 . The input terminal 61 is connected to the signal input section 8 . That is, the digital signal S2 input to the input terminal 61 is output from the signal input section 8. FIG. Input terminal 61 is an example of the first terminal of the present invention.

For example, the power supply unit 6 supplies power to the storage unit 5 in response to the input of the high-level digital signal S2. Also, the power supply unit 6 stops supplying power to the storage unit 5 in response to the input of the low-level digital signal S2. In this case, the first signal is a low level digital signal S2. The first signal may be a high level digital signal S2.

The control unit 7 is a control device that controls power supply to the storage unit 5 by the power supply unit 6 . For example, the control unit 7 is a CPU (Central Processing Unit). Note that the control unit 7 may be an SOC (System on a chip) or a PMIC (Power Management IC).

The control unit 7 inputs a predetermined second signal to the signal input unit 8 . Here, the second signal is a digital signal of any logic level.

Specifically, the control unit 7 has an output terminal 71 shown in FIG. A digital signal S3 (see FIG. 2) containing the second signal is output from the output terminal 71 . The output terminal 71 is connected to the signal input section 8 . That is, the digital signal S3 output from the output terminal 71 is input to the signal input section 8. FIG. The output terminal 71 is an example of the second terminal of the invention.

For example, the control unit 7 inputs the low-level digital signal S3 to the signal input unit 8 when a predetermined power supply stop timing has arrived. Further, the control unit 7 inputs a high-level digital signal S3 to the signal input unit 8 when the power supply stop timing has not arrived. In this case, the second signal is a low level digital signal S3. The second signal may be a high level digital signal S3.

For example, when the image forming apparatus 10 is powered off, the control unit 7 determines that the power supply stop timing has arrived. Note that even if the control unit 7 determines that the power supply stop timing has arrived when the operation mode of the image forming apparatus 10 shifts from the normal mode to the power saving mode in which the power consumption is reduced compared to the normal mode, good.

By the way, if the power supply from the power supply unit 6 is stopped while the internal processing is being executed, the storage unit 5 may experience problems such as corruption of the data stored therein. On the other hand, while an electric signal indicating that internal processing is being executed is being output from the storage device, a power-off prohibition signal is input to the power source that supplies power to the storage device to stop the power-off operation by the power source. An information processing device that prohibits is known as a related technology.

However, in the related art described above, it is necessary to provide the electronic device with a power supply section that can prohibit the power-off operation in response to the input of the power-off prohibition signal.

On the other hand, in the image forming apparatus 10 according to the embodiment of the present invention, as will be described below, without providing a power supply unit having a special function, the storage unit 5 performs the internal processing. It is possible to suppress power supply stoppage to the storage unit 5 .

[Configuration of Signal Input Unit 8]
Next, the configuration of the signal input section 8 will be described with reference to FIGS. 2 and 3. FIG. Here, FIG. 3 is a circuit diagram showing the configuration of the signal input section 8. As shown in FIG.

The signal input unit 8 inputs the first signal to the power supply unit 6 in response to the input of the second signal when the storage unit 5 is not executing the internal processing. Further, the signal input section 8 does not input the first signal to the power supply section 6 when the storage section 5 is executing the internal processing. That is, when the storage unit 5 is executing the internal processing, the signal input unit 8 inputs the first signal to the power supply unit 6 regardless of whether the second signal is input from the control unit 7. do not do.

Specifically, when the digital signal S1 input from the storage unit 5 is not the third signal, the signal input unit 8 outputs the first signal in response to the input of the second signal, and the storage unit 5 includes a logic circuit that does not output the first signal when the digital signal S1 input from is the third signal.

For example, the signal input section 8 includes a NOT circuit 81 and an OR circuit 82, as shown in FIG.

The NOT circuit 81 has an input section 811 connected to the output terminal 51 of the storage section 5 and an output section 812 connected to the second input section 822 of the OR circuit 82, as shown in FIG. The NOT circuit 81 inverts the logic level of the digital signal S1 output from the output terminal 51 and outputs it.

The NOT circuit 81 stops the power supply when the power supply unit 6 stops the power supply to the storage unit 5 and stops the operation, and resumes the power supply when the power supply unit 6 resumes the power supply to the storage unit 5 resumes operation. For example, the NOT circuit 81 receives power supply from the power supply unit 6 to operate. When power supply to unit 5 is restarted, power supply from power supply unit 6 is restarted. Note that the NOT circuit 81 may receive power from a power supply different from the power supply unit 6 .

As shown in FIG. 3, the OR circuit 82 has a first input section 821 connected to the output terminal 71 of the control section 7, a second input section 822 connected to the output section 812 of the NOT circuit 81, and an output section 823. is connected to the input terminal 61 of the power supply unit 6 . The OR circuit 82 outputs the low level digital signal S2, that is, the first Output a signal. The OR circuit 82 outputs a high-level digital signal when one or both of the digital signal S3 output from the output terminal 71 and the digital signal output from the output section 812 of the NOT circuit 81 are at high level. Output S2.

The OR circuit 82 receives power and operates even while power supply from the power supply unit 6 to the storage unit 5 is stopped. For example, the OR circuit 82 operates by receiving power from a power supply different from the power supply unit 6 . Note that the OR circuit 82 may operate by receiving power from the power supply unit 6 . In this case, the power supply unit 6 only needs to be able to individually control the power supply to the storage unit 5 and the NOT circuit 81 and the power supply to the OR circuit 82 .

The signal input section 8 may have a NAND circuit instead of the OR circuit 82 . In this case, the NOT circuit 81 may be connected to the output terminal 71 of the control section 7 instead of the output terminal 51 of the storage section 5 .

Next, the operation of the signal input section 8 will be described with reference to FIG.

Note that the timing t1 shown in FIG. 4 is the timing before the power supply stop timing, while the internal processing is not being executed in the storage unit 5 . Timing t2 is the timing before the power supply stop timing and at which the storage unit 5 starts executing the internal processing. Timing t3 is the timing when the internal processing is being executed in the storage unit 5 and the power supply stop timing has arrived. Timing t<b>4 is the timing after the power supply stop timing and at which the execution of the internal processing in the storage unit 5 ends.

At timing t1, since the internal processing is not being executed in the storage section 5, the output terminal 51 of the storage section 5 outputs a high-level digital signal S1. Further, at timing t1, since the power supply stop timing has not yet arrived, a high-level digital signal S3 is output from the output terminal 71 of the control section 7 . The signal input unit 8 inputs the high level digital signal S2 to the input terminal 61 of the power supply unit 6 in response to the input of the high level digital signal S1 and the high level digital signal S3. As a result, the specific voltage V<b>1 (see FIG. 4 ) is output from the power supply unit 6 to the storage unit 5 . That is, power is supplied from the power supply unit 6 to the storage unit 5 .

At the timing t2, since the storage unit 5 starts executing the internal processing, the output terminal 51 of the storage unit 5 outputs the low-level digital signal S1, that is, the third signal. Further, at timing t2, since the power supply stop timing has not yet arrived, the output terminal 71 of the control section 7 outputs a high-level digital signal S3. The signal input section 8 inputs the high-level digital signal S2 to the input terminal 61 of the power supply section 6 according to the input of the low-level digital signal S1 and the high-level digital signal S3. As a result, power supply from the power supply unit 6 to the storage unit 5 is continued.

At timing t3, since the internal processing is being executed in the storage section 5, the low-level digital signal S1, that is, the third signal, is output from the output terminal 51 of the storage section 5. FIG. Further, at timing t3, since the power supply stop timing has arrived, the low-level digital signal S3, ie, the second signal, is output from the output terminal 71 of the control section 7 . The signal input unit 8 inputs the high-level digital signal S2 to the input terminal 61 of the power supply unit 6 in response to the input of the low-level digital signal S1 and the low-level digital signal S3. As a result, power supply from the power supply unit 6 to the storage unit 5 is continued.

At timing t<b>4 , the execution of the internal processing in the storage unit 5 is completed, so that the high-level digital signal S<b>1 is output from the output terminal 51 of the storage unit 5 . Further, at timing t4, since the power supply stop timing has arrived, the low-level digital signal S3, ie, the second signal, is output from the output terminal 71 of the control section 7. FIG. The signal input unit 8 inputs the low-level digital signal S2, that is, the first signal, to the input terminal 61 of the power supply unit 6 in response to the high-level digital signal S1 and the low-level digital signal S3. As a result, power supply from the power supply unit 6 to the storage unit 5 is stopped. The voltage of the digital signal S1 output from the storage unit 5 also gradually decreases due to the stoppage of power supply from the power supply unit 6 to the storage unit 5 (see FIG. 4).

Here, since the supply of power from the power supply unit 6 to the storage unit 5 is stopped and the supply of power to the NOT circuit 81 is also stopped, even if the voltage of the digital signal S1 drops to the low level, the digital signal of the high level is output from the NOT circuit 81. is never printed. Further, since power supply to the OR circuit 82 continues even after power supply to the storage unit 5 is stopped, the control unit 7 restarts power supply to the storage unit 5 in response to arrival of a predetermined power supply restart timing. is possible. For example, the power supply restart timing is when the power of the image forming apparatus 10 is turned on, or when the operation mode of the image forming apparatus 10 shifts from the power saving mode to the normal mode.

As described above, in the image forming apparatus 10, when the storage unit 5 is not executing the internal processing, the first signal is input to the power supply unit 6 in response to the input of the second signal from the control unit 7, A signal input section 8 is provided for not inputting the first signal to the power supply section 6 when the storage section 5 is executing the internal processing. As a result, it is possible to suppress power supply stoppage to the storage unit 5 while the storage unit 5 is executing the internal processing without providing a power supply unit having a special function.

In addition, the first signal, the second signal, and the third signal need not be limited to logic level digital signals of either high level or low level. In this case, the signal input unit 8 outputs the first signal in response to the input of the second signal when the electrical signal input from the storage unit 5 is not the third signal, and When the electrical signal to be output is the third signal, any electronic circuit that does not output the first signal may be used.

Further, the control unit 7 may not input the second signal to the signal input unit 8 when the storage unit 5 is executing the internal processing. For example, the control section 7 may include an input terminal 72 (see FIG. 2) (an example of the fourth terminal of the present invention) to which the digital signal S1 is input. The control section 7 may not input the second signal to the signal input section 8 when the digital signal S1 input to the input terminal 72 is at a low level, that is, the third signal. As a result, even if the NOT circuit 81 of the signal input unit 8 malfunctions and the low-level digital signal S1 is output from the output terminal 51, the logic of the signal is not inverted. It is possible to suppress power supply stoppage to the storage unit 5 while the unit 5 is executing the internal processing.

1 ADF
2 image reading unit 3 image forming unit 4 paper feeding unit 5 storage unit 6 power supply unit 7 control unit 8 signal input unit 10 image forming apparatus 51 output terminal 61 input terminal 71 output terminal 72 input terminal 81 NOT circuit 82 OR circuit

Claims (5)

a storage unit that executes predetermined internal processing;
a power supply unit that stops supplying power to the storage unit in response to the input of a predetermined first signal;
When the storage section is not executing the internal processing, the first signal is input to the power supply section in response to the input of a predetermined second signal, and the storage section is executing the internal processing. a signal input unit that does not input the first signal to the power supply unit when the
a control unit that inputs the second signal to the signal input unit;
electronic equipment. the storage unit inputs a predetermined third signal to the signal input unit during execution of the internal processing;
wherein the first signal, the second signal, and the third signal are digital signals of any logic level,
The signal input unit outputs the first signal in response to the input of the second signal when the digital signal input from the storage unit is not the third signal, and outputs the digital signal input from the storage unit. a logic circuit that does not output the first signal when is the third signal;
The electronic device according to claim 1. The first signal, the second signal, and the third signal are low-level digital signals,
The power supply unit has a first terminal to which the first signal is input,
The control unit has a second terminal for outputting the second signal,
The storage unit has a third terminal from which the third signal is output,
The logic circuit has an input section connected to the third terminal, a NOT circuit that stops operating when power supply to the storage section is stopped, a first input section connected to the second terminal, and a first input section connected to the second terminal. an OR circuit having two inputs connected to the output of the NOT circuit and an output connected to the first terminal;
The electronic device according to claim 2. The control unit has a fourth terminal to which the third signal is input, and inputs the second signal to the signal input unit when the digital signal input to the fourth terminal is the third signal. do not do,
The electronic device according to claim 3. One or both of an image reading unit that reads image data of a document and an image forming unit that forms an image based on the image data,
The electronic device according to any one of claims 1 to 4.

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