JP2023132600A - Electronic apparatus, image formation device, and power supply control method for electronic apparatus - Google Patents

Abstract

To generate an appropriate voltage in a power supply generation unit without mediation of a program to be executed by a processor.SOLUTION: An electronic apparatus includes: a processor; a memory that stores a program to be executed by the processor and that operates in synchronization with a clock signal while receiving a clock enable signal of a valid level from the processor; a frequency detection unit that detects a frequency the clock enable signal is set to the valid level; a power supply generation unit that generates a voltage, and sets the voltage when the frequency detected by the frequency detection part is low to be lower than the voltage when the frequency is high; and a function unit that operates with the voltage generated by the power supply generation unit.SELECTED DRAWING: Figure 3

Description

The present invention relates to an electronic device, an image forming apparatus, and a power control method for an electronic device.

For example, an image forming apparatus includes a main power supply unit that operates in a normal mode that drives a print engine, and a sub power supply unit that operates in a normal mode and an energy saving mode that does not drive a print engine. Then, by operating or stopping the main power supply unit depending on the operation mode, the power supply ability to the load is switched.

In electronic devices such as the above-mentioned image forming apparatus, for example, a control program executed by a processor mounted on a control board switches between generating and stopping the generation of voltage by the main power supply unit, and changes the voltage supplied to the functional unit. The value of is changed. However, no method has been proposed for appropriately changing the value of the voltage supplied to the functional unit according to the operating state of the functional unit without intervening a control program.

In view of the above problems, an object of the present invention is to cause a power generation unit to generate an appropriate voltage without intervening a program executed by a processor.

In order to solve the above technical problem, an electronic device according to one aspect of the present invention stores a processor and a program executed by the processor, and while receiving a clock enable signal at a valid level from the processor, a clock signal is output. a memory that operates in synchronization with the clock enable signal; a frequency detection unit that detects the frequency at which the clock enable signal is set to a valid level; and a frequency detection unit that generates a voltage and detects the voltage when the frequency detected by the frequency detection unit is low. , a power generation unit that sets the voltage to be lower than the voltage when the frequency is high; and a functional unit that operates with the voltage generated by the power generation unit.

The power generation unit can generate an appropriate voltage without intervening a program executed by the processor.

1 is an overall configuration diagram showing an example of an image forming apparatus according to a first embodiment of the present invention. FIG. 2 is a state transition diagram showing an example of transition of operation modes of the image forming apparatus of FIG. 1. FIG. 2 is a circuit block diagram showing an overview of the hardware configuration of main parts of the image forming apparatus shown in FIG. 1. FIG. 4 is a circuit block diagram illustrating an example of a power generation section in FIG. 3. FIG. FIG. 4 is an explanatory diagram showing an example of the relationship between the selection signal generated by the power supply control section of FIG. 3 and the set value of the DC voltage generated by the voltage generation section. FIG. 2 is a circuit block diagram showing an overview of the hardware configuration of main parts of an image forming apparatus according to a second embodiment of the present invention. 7 is a circuit block diagram illustrating an example of a power supply control section and a power generation section of FIG. 6. FIG. 8 is an explanatory diagram showing an example of a set value for the FB voltage held in the ROM of FIG. 7. FIG.

Hereinafter, embodiments will be described using the drawings. In the following, the same symbols as the signal names are used for signal lines through which information such as signals is transmitted. Also, the same symbol as the voltage name is used for the voltage line through which the voltage is transmitted. In addition, in each drawing, the same components are given the same reference numerals, and duplicate explanations may be omitted.

<Overall configuration diagram of image forming apparatus>
FIG. 1 is an overall configuration diagram showing an example of an image forming apparatus according to an embodiment of the present invention. The image forming apparatus 100 is a multi-function printer (MFP) that includes a copy function, a FAX function, a print function, a scanner function, and the like. Image forming apparatus 100 is an example of an electronic device. The image forming apparatus 100 may have a function of storing input images, a function of distributing input images, or the like. For example, the input image is a document read by a scanner function, an image input by a FAX function, or the like.

The image forming apparatus 100 can communicate with an external device such as a PC (Personal Computer), and can also operate according to instructions received from the external device. Note that in the embodiment, the image processed by the image forming apparatus 100 may include not only image data that includes an image but also text data that does not include an image.

The image forming apparatus 100 is a so-called electrophotographic image forming apparatus. The image forming apparatus 100 forms an electrostatic latent image by selectively exposing the surface of a charged photoreceptor, attaches toner to the formed electrostatic latent image, and transfers the attached toner to a recording medium such as paper. Transfer it to and fix it.

As shown in FIG. 1, the image forming apparatus 100 includes an operation section 10, a start switch 20, a control board 51, a reading section 40, an engine control section 79, a printer section 6, and paper feed cassettes 7A and 7B. , a transport section 8 , and a power supply device 1 . Note that the control board 51, engine control section 79, printer section 6, paper feed cassettes 7A and 7B, and conveyance section 8 are provided inside the image forming apparatus 100, but the inside is not shown transparently in FIG. The current state is shown.

The operation unit 10 receives various inputs according to user operations, and displays various information on a display unit (not shown). For example, the information displayed on the operation unit 10 is information indicating the operation for which the input has been accepted, information indicating the operating status of the image forming apparatus 100, information indicating the setting state of the image forming apparatus 100, or the like.

For example, the operation unit 10 may include a liquid crystal display (LCD) having a touch panel function. Alternatively, the operation unit 10 may include an organic EL (Electro-Luminescence) display device having a touch panel function. Further, the operation unit 10 may include at least one of an operation unit such as a hardware key and a display unit such as a lamp in addition to a display device having a touch panel function.

The startup switch 20 is a switch that powers on the image forming apparatus 100 . The image forming apparatus 100 is activated when the activation switch 20 is pressed while the power is off, and is turned off when the activation switch 20 is pressed during activation. Note that turning on/off the power of the image forming apparatus 100 is not limited to the operation of the startup switch 20, and may be performed based on a startup instruction or a termination instruction from an external device.

The control board 51 is equipped with a plurality of electronic components including a controller such as a CPU (Central Processing Unit) that controls the overall operation of the image forming apparatus 100 . For example, electronic components mounted on the control board 51 control drawing processing, communication processing, input from the operation unit 10, and the like. For example, an electronic component mounted on the control board 51 controls the image forming apparatus 100 based on an operation received by the operation unit 10, and performs a copy operation or the like.

Furthermore, electronic components mounted on the control board 51 may control the image forming apparatus 100 based on instructions received from an external device such as a PC. Further, the electronic components mounted on the control board 51 cause the image forming apparatus 100 to perform predetermined operations when the activation switch 20 is detected to be pressed or when an abnormality in the image forming apparatus 100 is detected. You can also have it executed.

Note that a semiconductor chip such as an SoC (System on Chip) or an FPGA (Field-Programmable Gate Array) may be mounted on the control board 51 instead of a processor such as a CPU (Central Processing Unit). Alternatively, the control board 51 may be equipped with an SoC or an FPGA along with the CPU. By mounting the SoC or FPGA on the control board 51, the size of the control board 51 can be reduced.

The reading unit 40 includes, for example, an ADF (Auto Document Feeder) 41 and a scanner unit 42. The ADF 41 sequentially conveys the originals placed on the ADF 41 to the scanner section 42 and optically reads the originals to generate image data. The scanner unit 42 generates image data by optically reading a document placed on a transparent document table.

The engine control section 79 generates control signals for controlling the printer section 6, scanner section 42, transport section 8, etc. based on the image data generated by the reading section 40. For example, the engine control unit 79 may have the form of a circuit board on which a circuit for generating a control signal based on image data is mounted.

The printer section 6 functions as an image forming section that forms images. The printer section 6 includes a photosensitive drum 61 , a charging section 62 , a writing unit 63 , a developing section 64 , a conveying belt 65 , and a fixing section 66 . The charging unit 62 charges the outer peripheral surface of the photoreceptor drum 61. The writing unit 63 exposes the charged photoreceptor drum 61 to light based on the image data read by the reading section 40, and writes an electrostatic latent image on the photoreceptor drum 61. The developing section 64 develops the latent image written on the photoreceptor drum 61 with toner. The conveyor belt 65 conveys a recording medium on which a toner image is to be formed. The fixing unit 66 fixes the toner on the recording medium to the recording medium to form a toner image on the recording medium.

The paper feed cassettes 7A and 7B store recording media such as paper on which toner images are not formed. For example, the paper feed cassettes 7A and 7B can store recording media of different sizes. Although FIG. 1 shows an example in which two paper feed cassettes 7A and 7B are provided in the image forming apparatus 100, the number of paper feed cassettes may be one or three or more.

The transport unit 8 has various rollers and transports the recording medium stored in the paper feed cassette 7A or the paper feed cassette 7B to the printer unit 6. Note that arrow C in FIG. 1 indicates the conveyance direction of the recording medium. The power supply device 1 generates a plurality of types of DC voltages based on, for example, an AC power source such as a commercial power source, and supplies the generated DC voltages to each component of the image forming apparatus 100 .

In the image forming apparatus 100, when a user operates a function switching key or the like on the operation unit 10 and selects a document box function, a copy function, a printer function, a facsimile function, etc., each function becomes operable. The operation mode of the image forming apparatus 100 is the document box mode when the document box function is selected, and the operation mode is the copy mode when the copy function is selected. Further, the operation mode of the image forming apparatus 100 is a printer mode when a printer function is selected, and a facsimile mode when a facsimile function is selected.

An example of image forming operation when image forming apparatus 100 is set to copy mode will be described below. Note that although an example will be described below in which the printer unit 6 forms an image using a monochrome electrophotographic method, the image may be formed using a color electrophotographic method, an inkjet method, or the like. Furthermore, the image forming method is not limited to these.

In the copy mode, the image forming apparatus 100 uses the reading unit 40 to read image information of each document to be copied, and generates image data. The image forming apparatus 100 uniformly charges the outer peripheral surface of the photoreceptor drum 61 using the charging unit 62 in the dark. Next, the image forming apparatus 100 exposes the photoreceptor drum 61 to light irradiated from the writing unit 63 as indicated by the dotted arrow A in FIG. do. Arrow B in FIG. 1 indicates the rotation direction of the photoreceptor drum 61.

The image forming apparatus 100 operates the developing section 64 to visualize the electrostatic latent image using toner. As a result, a toner image is formed on the photoreceptor drum 61. Next, the image forming apparatus 100 transfers the toner image formed on the photoreceptor drum 61 to a recording medium on the conveyor belt 65. Then, the image forming apparatus 100 heats and melts the toner forming the toner image on the recording medium using a heater or the like of the fixing unit 66, thereby fixing the toner image on the recording medium. Then, the image forming apparatus 100 discharges the recording medium on which the toner image is fixed.

Note that the operation unit 10 may be controlled by the control board 51 or may be controlled by a control circuit separate from the control board 51. In that case, the control circuit of the control board 51 and the control circuit of the operation unit 10 are connected to be able to communicate with each other. The control board 51 controls the entire image forming apparatus 100 including the operation section 10.

<Example of state transition of image forming apparatus>
FIG. 2 is a state transition diagram illustrating an example of the transition of the operation mode of the image forming apparatus 100 of FIG. 1. As shown in FIG. The transition of the operation mode of the image forming apparatus 100 is controlled by, for example, a CPU mounted on the control board 51 in FIG. 1. When the image forming apparatus 100 is started by turning on the power switch, it is set to a standby mode.

When the image forming apparatus 100 receives an instruction to copy or scan from the user via the operation unit 10 during the standby mode, the image forming apparatus 100 transitions to the active mode and performs a copy operation (that is, a print operation) or a scan operation. (Figure 4(a)). After the image forming apparatus 100 completes the copying or scanning operation, it returns to the standby mode (FIG. 4(b)).

On the other hand, if the image forming apparatus 100 remains in standby mode for a predetermined period of time, the image forming apparatus 100 transitions from standby mode to energy saving mode (energy saving mode) (FIG. 4(c)). For example, when the ADF 41 is opened during the energy saving mode, the image forming apparatus 100 shifts the operation mode from the energy saving mode to the standby mode (FIG. 4(d)).

<Example of hardware configuration of image forming apparatus>
FIG. 3 is a circuit block diagram showing an overview of the hardware configuration of main parts of the image forming apparatus 100 of FIG. 1. As shown in FIG. Image forming apparatus 100 includes a control section 110, a power supply unit 120, an engine control section 79, and an operation section 10.

The control unit 110 corresponds to, for example, the control board 51 in FIG. 114 and a power generation section 115. The CPU 111 has a memory controller 111a and an internal memory 111b.

The power supply unit 120 uses an AC power source such as a commercial power source to generate a DC voltage DC24 (for example, 24V) and a DC voltage DC5 (for example, 5V). The direct current voltage DC24 is supplied to the engine mechanism including the printer section 6 and the scanner section 42, and the direct current voltage DC5 is supplied to the power generation section 115 of the control section 110.

The engine control section 79 includes a printer circuit section 79a that controls the operation of printing an image on a paper medium, etc., and a scanner circuit section 79b that controls the operation of scanning a document or the like. The CPU 111 is connected to the ROM 112, the RAM 113, the printer circuit section 79a, the scanner circuit section 79b, the operation section 10, and the like.

CPU 111 controls the overall operation of image forming apparatus 100 by executing a control program stored in RAM 113 during active mode and standby mode. Further, during the energy saving mode, the CPU 111 executes a monitoring program held in the internal memory 111b in order to detect the trigger for returning from the energy saving mode to the standby mode. CPU 111 is an example of a processor. The internal memory 111b is, for example, either a RAM or a cache installed in the CPU 111.

For example, the CPU 111 executes a print operation by controlling the printer circuit section 79a, and executes a scan operation by controlling the scanner circuit section 79b. Further, the CPU 111 controls the operation unit 10 to accept user operations, and displays the operating state of the image forming apparatus 100 and the like on a display unit (not shown) of the operation unit 10 .

The ROM 112 is, for example, a nonvolatile memory such as an embedded multi media card (eMMC) or a flash memory in which data can be electrically rewritten. The ROM 112 may store a boot program and various parameters used in the operation of the image forming apparatus 100. The RAM 113 is, for example, an SDRAM (Synchronous Dynamic Random Access Memory) that requires periodic refresh operations, and operates in synchronization with the clock signal CLK.

The RAM 113 and the CPU 111 are connected via a data signal line DQ, an address signal line AD, various command signal lines CMD, a clock signal line CLK, and a clock enable signal line CKE. For example, the command signal line CMD includes a chip select signal line, a write enable signal line, a row address strobe signal line, a column address strobe signal line, and the like. RAM 113 is an example of memory.

The RAM 113 operates while receiving a high-level clock enable signal CKE from the memory controller 111a of the CPU 111. The high level of the clock enable signal CKE is an example of a valid level. The RAM 113 performs a read operation, a write operation, or a refresh operation in response to the clock signal CLK, address signal AD, and various command signals CMD received from the memory controller 111a (ie, the CPU 111). In the following, the clock enable signal CKE is also referred to as a CKE signal.

For example, the RAM 113 stops receiving the clock signal CLK while receiving the low-level CKE signal from the memory controller 111a, thereby stopping its operation. However, when the RAM 113 receives the command signal CMD of a predetermined logic level at the falling edge of the CKE signal, it shifts to the self-refresh mode. During self-refresh mode, RAM 113 periodically performs refresh operations to retain stored data.

For example, the CPU 111 stops the operation of the engine mechanism by the engine control unit 79 during an energy saving mode to reduce power consumption. During the energy saving mode, the CPU 111 sets the CKE signal to a low level via the memory controller 111a, stops fetching the control program held in the RAM 113, and executes the monitoring program held in the internal memory 111b. RAM 113 is shifted to self-refresh mode during energy saving mode.

For example, the monitoring program is a simple program that monitors interrupts that occur in response to operations on the operating unit 10 during the energy saving mode, and does not access external devices such as the ROM 112. When the CPU 111 detects an operation of the operating unit 10 by the monitoring program, the CPU 111 changes the CKE signal from a low level to a high level via the memory controller 111a. Then, the CPU 111 starts fetching the control program held in the RAM 113, and shifts the operation mode from the energy saving mode to the standby mode.

A memory access request from the CPU 111 to the RAM 113 is held in an access queue (not shown) of the memory controller 111a. The memory access requests issued by the CPU 111 are a read access request to read a control program or data from the RAM 113 and a write access request to write data to the RAM 113.

The memory controller 111a sequentially issues memory access requests held in the access queue to the RAM 113. When memory access requests are held in the access queue, the memory controller 111a sets the CKE signal to a high level and sequentially issues the memory access requests held in the access queue to the RAM 113. If no memory access request is held in the access queue, the memory controller 111a sets the CKE signal to a low level and shifts the RAM 113 to self-refresh mode.

As described above, in this embodiment, the memory controller 111a automatically executes transition to and release from the self-refresh mode without being controlled by the CPU 111 (auto self-refresh function). In other words, the CKE signal can be automatically output by the memory controller 111a according to the operating frequency of the CPU 111 without intervening a control program executed by the CPU 111. Note that the memory controller 111a periodically issues a refresh command to the RAM 113 while setting the CKE signal to a high level. Further, the circuit that controls the output of the CKE signal may be other than the memory controller 111a.

The power supply control unit 114 includes a frequency detection unit 1140 that detects the frequency at which the memory controller 111a sets the CKE signal to a high level. The high level frequency of the CKE signal indicates the access frequency of the RAM 113 and indicates the operating frequency of the CPU 111.

When the frequency of the high level of the CKE signal is high, the frequency of operation of the CPU 111 is high, and the power consumption of the CPU 111 becomes large. Furthermore, as the frequency of access to the ROM 112 and the RAM 113 by the CPU 111 increases, the power consumption of the ROM 112 and the RAM 113 increases.

On the other hand, when the frequency of the high level of the CKE signal is low, the frequency of operation of the CPU 111 is low, and the power consumption of the CPU 111 is small. Furthermore, the power consumption of the ROM 112 and the RAM 113 is reduced because the frequency of access to the ROM 112 and the RAM 113 by the CPU 111 is reduced.

For example, the frequency at which the CKE signal is set to a high level can be indicated by the ratio of high level periods of the CKE signal in a predetermined period or the number of transition edges of the CKE signal in a predetermined period. The number of transition edges is the number of rising edges or the number of falling edges.

The power supply control unit 114 sets one of the selection signals SEL3, SEL2, SEL1, and SEL0 to a valid level (for example, high level) based on the frequency of high level of the CKE signal detected by the frequency detection unit 1140, and sets the selection signal SEL3, SEL2, SEL1, and SEL0 to a valid level (for example, high level) set to an invalid level (for example, low level). Selection signals SEL3-SEL0 are output to power generation section 115. In the following, when the selection signals SEL3 to SEL0 are explained without distinction, they will be referred to as selection signals SEL.

For example, assume that the access frequencies of the RAM 113 are Frequency A, Frequency B, Frequency C, and Frequency D in ascending order. Note that the frequency D includes a state in which the CKE signal is fixed at a low level in a predetermined period for determining the access frequency.

The frequency detection unit 1140 sets the selection signal SEL3 to a valid level when the access frequency of the RAM 113 is frequency A, and sets the selection signal SEL2 to a valid level when the access frequency of the RAM 113 is frequency B. The frequency detection unit 1140 sets the selection signal SEL1 to the valid level when the access frequency of the RAM 113 is the frequency C, and sets the selection signal SEL0 to the valid level when the access frequency of the RAM 113 is the frequency C.

When detecting the ratio of high-level periods of the CKE signal every predetermined period as a frequency, the frequency detection unit 1140 includes, for example, a DAC (Digital-to-Analog Converter), a smoothing circuit, and a comparison circuit. Good too. The DAC converts the logic level of the CKE signal into a voltage. The smoothing circuit smoothes the output voltage of the DAC and generates a voltage VCKE indicating the average voltage of the CKE signal in a predetermined period. The higher the value of the voltage VCKE, the higher the frequency of the high level of the CKE signal.

The comparison circuit sets one of the selection signals SEL3-SEL1 to a valid level by comparing the voltage VCKE with a plurality of threshold voltages. Therefore, by generating the voltage VCKE that indicates the frequency of high level of the CKE signal, it is possible to output one of the selection signals SEL3 to SEL1 to the power supply generating section 115 according to the value of the voltage VCKE.

On the other hand, when detecting the number of transition edges of the CKE signal every predetermined period as a frequency, the frequency detection section 1140 includes, for example, a counter and a comparison circuit. The counter performs a counting operation in synchronization with the rising edge or falling edge of the CLK signal, and is reset at every predetermined cycle. The larger the count value CNT generated by the counter is, the more frequently the CKE signal is at a high level. The comparison circuit sets one of the selection signals SEL3 to SEL1 to a valid level by comparing the count value CNT immediately before being reset with a plurality of threshold values. Therefore, by detecting the number of transition edges of the CKE signal every predetermined period as a frequency, it is possible to output one of the selection signals SEL3 to SEL1 to the power generation section 115 according to the count value.

The power generation unit 115 uses the DC voltage DC5 supplied from the power supply unit 120 to generate a plurality of types of DC voltages DC33, DC18, DC12, and DC105 according to the selection signals SEL3-SEL0. Then, the power supply control section 114 and the power generation section 115 execute a power supply control method for the image forming apparatus 100 (electronic device).

Below, the direct current voltages DC33, DC18, DC12, and DC105 are also simply referred to as voltages DC33, DC18, DC12, and DC105. Further, the power generation unit 115 has a function of adjusting the voltage values of the voltages DC33, DC18, DC12, and DC105, respectively, according to the selection signal SEL.

For example, the standard value of voltage DC33 is 3.3V, and the standard value of voltage DC18 is 1.8V. For example, the standard value of voltage DC12 is 1.2V, and the standard value of voltage DC105 is 1.05V. Although not particularly limited, the voltages DC33 and DC18 are, for example, power supply voltages for operating the ROM 112. The voltage DC12 is, for example, a power supply voltage for operating the RAM 113. Voltage DC105 is, for example, a power supply voltage for operating CPU111. Each of the CPU 111, ROM 112, and RAM 113 is an example of a functional unit that operates using a voltage generated by the power generation unit 115.

<Circuit block of power generation section>
FIG. 4 is a circuit block diagram showing an example of the power generation section 115 of FIG. 3. The power generation section 115 operates upon receiving the direct current voltage DC5 supplied from the power supply unit 120 and the selection signals SEL3 to SEL0 outputted from the power supply control section 114. For example, the power generation unit 115 includes four power generation units 1153, 1152, 1151, and 1150 that generate voltages DC33, DC18, DC12, and DC105, respectively.

The power generation unit 1153 includes power generation circuits G34, G33, and G32 that generate three voltages DC33 having different voltage values. For example, power generation circuits G34, G33, and G32 are DC/DC converters. The power generation circuit G34 operates when receiving the high level selection signal SEL3, and outputs a voltage DC33 of 3.4V.

The power generation circuit G33 operates when receiving the high level selection signal SEL2, and outputs a voltage DC33 of 3.3V. The power generation circuit G32 operates when receiving the high level selection signal SEL1, and outputs a voltage DC33 of 3.2V.

The power generation unit 1152 includes power generation circuits G19, G18, and G17 that generate three voltages DC18 having different voltage values. For example, power generation circuits G19, G18, and G17 are DC/DC converters. The power generation circuit G19 operates when receiving the high level selection signal SEL3, and outputs a voltage DC18 of 1.9V.

The power generation circuit G18 operates when receiving the high level selection signal SEL2, and outputs a voltage DC18 of 1.8V. The power generation circuit G17 operates when receiving the high level selection signal SEL1 and outputs a voltage DC18 of 1.7V.

The power generation unit 1151 includes power generation circuits G13, G12a, G12b, and G11 that generate three voltages DC12 having different voltage values. For example, the power generation circuits G13, G12a, G12b, and G11 are DC/DC converters. The power generation circuit G13 operates when receiving the high level selection signal SEL3, and outputs a voltage DC12 of 1.3V.

The power generation circuit G12a operates when receiving the high-level selection signal SEL2, and outputs a voltage DC12 of 1.2V. The power generation circuit G12b operates when receiving the high-level selection signal SEL1, and outputs a voltage DC12 of 1.2V. That is, the power generation unit 1151 outputs the voltage DC12 of 1.2V when receiving the selection signal SEL2 and the selection signal SEL1. The power generation circuit G11 operates when receiving the high level selection signal SEL0, and outputs a power supply voltage DC12 of 1.1V.

The power generation unit 1150 includes power generation circuits G125, G115, G105, and G10 that generate four voltages DC105 having different voltage values. For example, power generation circuits G125, G115, G105, and G10 are DC/DC converters. The power generation circuit G125 operates when receiving the high level selection signal SEL3, and outputs a voltage DC105 of 1.25V.

The power generation circuit G115 operates when receiving the high level selection signal SEL2, and outputs a voltage DC105 of 1.15V. The power generation circuit G105 operates when receiving the high level selection signal SEL1, and outputs a voltage DC105 of 1.05V. The power generation circuit G10 operates when receiving the high level selection signal SEL0, and outputs a voltage DC105 of 1.0V.

From the above, the power generation unit 115 generates the voltage DC33 of 3.4V, the voltage DC18 of 1.9V, the voltage DC12 of 1.3V, and the voltage of 1.25V during the period when it receives the high-level selection signal SEL3. DC105 is output. The power generation unit 115 generates a voltage DC33 of 3.3V, a voltage DC18 of 1.8V, a voltage DC12 of 1.2V, and a voltage DC105 of 1.15V while receiving the high-level selection signal SEL2. Output.

The power generation unit 115 generates a voltage DC33 of 3.2V, a voltage DC18 of 1.7V, a voltage DC12 of 1.2V, and a voltage DC105 of 1.05V while receiving the selection signal SEL1 at a high level. Output. While receiving the high-level selection signal SEL0, the power generation unit 115 outputs the voltage DC12 of 1.1V and the voltage DC105 of 1.0V, and stops outputting the voltage DC33 and the voltage DC18. Below, when explaining direct current voltage DC without distinction, it is also simply called voltage DC.

As described above, when the CPU 111 operates frequently, the CKE signal is at high level frequently, and the power consumption of the CPU 111 increases, the voltage DC supplied to the CPU 111 is set high. When the CPU 111 operates frequently, the ROM 112 and RAM 113 operate frequently, and the power consumption of the ROM 112 and RAM 113 increases. When the power consumption of ROM 112 and RAM 113 increases, the voltage DC supplied to ROM 112 and RAM 113 is set high. Thereby, it is possible to suppress a decrease in the voltage DC due to an increase in the power consumption of the CPU 111, ROM 112, and RAM 113.

Furthermore, when the CPU 111 operates less frequently, the CKE signal is less frequently at a high level, and the power consumption of the CPU 111 decreases, the voltage DC supplied to the CPU 111 is set low. When the CPU 111 operates less frequently, the ROM 112 and RAM 113 operate less frequently, and the power consumption of the ROM 112 and RAM 113 decreases. When the power consumption of ROM 112 and RAM 113 decreases, the voltage DC supplied to ROM 112 and RAM 113 is set low. Thereby, it is possible to suppress unnecessary voltage DC from being supplied to the CPU 111, ROM 112, and RAM 113.

Control to adjust the DC voltage DC by the power supply control unit 114 can be performed without intervening a control program executed by the CPU 111. Appropriate voltage DC (that is, electric power) can be supplied to the CPU 111, ROM 112, and RAM 113 according to the operating frequency of the CPU 111, without intervening a control program executed by the CPU 111.

FIG. 5 is an explanatory diagram showing an example of the relationship between the selection signal SEL generated by the power supply control section 114 of FIG. 3 and the set value of the DC voltage generated by the power supply generation section 115. FIG. 5 shows an example in which the frequency detection unit 1140 generates a voltage VCKE (average voltage of the CKE signal) indicating the frequency of high level of the CKE signal.

The power supply control unit 114 outputs a selection signal SEL0 when the voltage VCKE is 0V, and outputs a selection signal SEL1 when the voltage VCKE is greater than 0V and less than or equal to 0.6V. The power supply control unit 114 outputs a selection signal SEL2 when the voltage VCKE is greater than 0.6V and less than or equal to 1.2V, and outputs a selection signal SEL3 when the voltage VCKE is greater than 1.2V. 0V, 0.6V, and 1.2V are examples of threshold voltages that are compared to voltage VCKE. Then, in accordance with the selection signals SEL3-SEL0, the predetermined power generation circuits (G34, G33, etc.) shown in FIG. 4 are selected, and the values of the voltages DC33, DC18, DC12, and DC1.05 are set, respectively.

Note that when the frequency detection unit 1140 detects the number of transition edges of the CKE signal, the number of transition edges counted by the counter is used instead of the average voltage VCKE in FIG. Then, the comparator outputs one of the selection signals SEL3 to SEL1 by comparing the number of transition edges counted by the counter with three threshold values.

As described above, in this embodiment, the power generation unit 1150 changes the value of the DC voltage DC105 to be supplied to the CPU 111 according to the frequency of high level of the CKE signal outputted to the RAM 113 by the CPU 111 that executes the control program stored in the RAM 113. adjust. Thereby, the power generation unit 115 can generate an appropriate direct current voltage DC105 (i.e., electric power) to be supplied to the CPU 111 according to the operating frequency of the CPU 111 without intervening a control program executed by the CPU 111.

Further, in this embodiment, for example, one of the power generation circuits G125, G115, G105, and G10 that generates 1.25V, 1.15V, 1.05V, and 1.0V, respectively, is selected according to the selection signals SEL3-SEL0. make it work. Thereby, the value of the direct current voltage DC105 output by the power generation section 1150 can be adjusted using the selection signal SEL, which is a logic signal. Similarly, the other power generation units 1153, 1152, and 1151 can adjust the values of the DC voltages DC33, DC18, and DC12, respectively, using the selection signal SEL, which is a logic signal.

As described above, an appropriate direct current voltage DC can be supplied to the CPU 111, ROM 112, and RAM 113 according to the operating frequency. That is, it is possible to suppress excessive power from being supplied to the CPU 111, ROM 112, and RAM 113. Furthermore, it is possible to prevent the power supplied to the CPU 111, ROM 112, and RAM 113 from running out. As a result, the CPU 111, ROM 112, and RAM 113 can be operated stably, and a decrease in reliability of the image forming apparatus 100 can be suppressed.

Furthermore, detection of the frequency at which the CKE signal is set to a high level by the frequency detection unit 1140 is always performed regardless of the operation mode of the image forming apparatus 100. Therefore, for example, when the operation mode is transitioned from the energy saving mode to the standby mode to the active mode, each DC voltage DC generated by the power generation unit 115 can be increased. In other words, each DC voltage DC generated by the power generation unit 115 can be adjusted across operation modes. As a result, it is possible to achieve both optimization of power consumption and stable operation of the image forming apparatus 100.

For example, the power supply control unit 114 generates a voltage VCKE indicating the high-level frequency of the CKE signal by the frequency detection unit 1140, and outputs one of the selection signals SEL3 to SEL1 to the power supply generation unit 115 according to the value of the voltage VCKE. can do. Alternatively, the power supply control unit 114 uses the frequency detection unit 1140 to count the number of transition edges of the CKE signal as the high level frequency of the CKE signal, and outputs one of the selection signals SEL3 to SEL1 to the power generation unit 115 according to the count value. can be output to.

Further, the power generation units 1153 and 1152 generate DC voltages DC33 and DC18, respectively, to be supplied to the ROM 112 according to the frequency of high level of the CKE signal. The power generation unit 1151 generates a direct current voltage DC12 to be supplied to the RAM 113 according to the frequency of high level of the CKE signal. This allows the power generation unit 115 to generate an appropriate direct current voltage DC to be supplied to each of the ROM 112 and the RAM 113 according to the operating frequency of the CPU 111 without intervening a control program executed by the CPU 111.

Furthermore, in this embodiment, the CPU 111 is provided with a memory controller 111a that sets the CKE signal to a high level when a memory access request is held in the access queue. This allows the memory controller 111a to automatically output the CKE signal according to the operating frequency of the CPU 111 without intervening a control program executed by the CPU 111.

<Hardware configuration of main parts of image forming apparatus of second embodiment>
FIG. 6 is a circuit block diagram showing an overview of the hardware configuration of main parts of an image forming apparatus according to the second embodiment of the present invention. Elements similar to those in FIG. 3 are designated by the same reference numerals, and detailed description thereof will be omitted. The image forming apparatus 100A shown in FIG. 6 includes a power control section 124 and a power generation section 125 instead of the power control section 114 and the power generation section 115 shown in FIG. The other configuration of the image forming apparatus 100A is similar to the configuration of the image forming apparatus 100 in FIG. 3.

The power supply control unit 124 includes a frequency detection unit 1240, a ROM 1243, and four FB setting units 1244. For example, the ROM 1243 may be an electrically rewritable flash memory or the like. The frequency detection unit 1240 generates a voltage VCKE indicating the average voltage of the CKE signal in a predetermined cycle as frequency information indicating the frequency at which the CKE signal is at a high level. An example of the frequency detection unit 1240 is shown in FIG.

The ROM 1243 holds correspondence information indicating the correspondence between the voltage VCKE and the adjustment voltages FB3, FB2, FB1, and FB0 output by the four FB setting sections 1244, respectively. Below, when explaining the adjustment voltages FB3, FB2, FB1, and FB0 without distinction, they will be referred to as adjustment voltages FB. ROM1243 is an example of a holding section. An example of correspondence information indicating the correspondence between the voltage VCKE and the adjustment voltage FB held in the ROM 1243 is shown in FIG.

The four FB setting sections 1244 refer to the correspondence information indicating the correspondence between the voltage VCKE and the adjustment voltage FB held in the ROM 1243, and set the values of the adjustment voltages FB3-FB0 corresponding to the voltage VCKE received from the frequency detection section 1240. Determine each. Then, the four FB setting units 1244 generate the adjusted voltages FB3-FB0 of the determined values, for example, by stepping down the DC voltage DC5, and output the generated adjusted voltages FB3-FB0 to the power generation unit 125. .

For example, the four FB setting units 1244 change the resistance division ratio of the dividing circuit that generates the adjusted voltages FB3-FB0 from the DC voltage DC5, according to the determined values of the adjusted voltages FB3-FB0. The FB setting section 1244 is an example of an adjustment voltage generation section that generates an adjustment voltage FB according to the high-level frequency of the CKE signal.

The power generation unit 125 generates a DC voltage DC33 according to the adjusted voltage FB3, and generates a DC voltage DC18 according to the adjusted voltage FB2. Further, the power generation unit 125 generates a DC voltage DC12 according to the adjusted voltage FB1, and generates a DC voltage DC1.05 according to the adjusted voltage FB0. Then, the power control section 124 and the power generation section 125 execute a power control method for the image forming apparatus 100A (electronic device). An example of the power generation unit 125 is shown in FIG.

<Circuit blocks of power supply control section and power generation section>
FIG. 7 is a circuit block diagram showing an example of the power control section 124 and the power generation section 125 of FIG. 6. For example, the frequency detection unit 1240 includes a DAC 1241 and a smoothing circuit 1242. The DAC 1241 converts the logic level of the CKE signal into a voltage. The smoothing circuit 1242 smoothes the output voltage of the DAC 1241 and generates a voltage VCKE indicating the average voltage of the CKE signal in a predetermined period.

Note that the frequency detection unit 1240 may include a counter that counts the number of transition edges of the CKE signal every predetermined period, and a DAC that generates the voltage VCKE according to the count value counted by the counter.

Each FB setting unit 1244 generates one of the adjusted voltages FB3-FB0 based on the voltage VCKE and the correspondence information held in the ROM 1243 for each adjusted voltage FB3-FB0.

The power generation unit 125 includes four power generation circuits G33A, G18A, G12A, and G105A that generate DC voltages DC33, DC18, DC12, and DC105, respectively, according to the DC voltage DC5. For example, power generation circuits G33A, G18A, G12A, and G105A are DC/DC converters. The power generation circuit G33A can adjust the value of the DC voltage DC33 supplied to the ROM 112 in accordance with the adjustment voltage FB3 received at the voltage adjustment terminal FB (feedback terminal).

The power generation circuit G18A can adjust the value of the DC voltage DC18 supplied to the ROM 112 according to the adjustment voltage FB2 received at the voltage adjustment terminal FB. The power generation circuit G12A can adjust the value of the DC voltage DC12 supplied to the RAM 113 according to the adjustment voltage FB1 received at the voltage adjustment terminal FB. The power generation circuit G105A can adjust the value of the DC voltage DC105 supplied to the CPU 111 according to the adjustment voltage FB0 received at the voltage adjustment terminal FB.

<Correspondence information held in ROM1243>
FIG. 8 is an explanatory diagram showing an example of the set value for the FB voltage held in the ROM 1243 of FIG. The ROM 1243 holds set values VSET of the adjustment voltages FB3 to FB0 for each predetermined range of the voltage VCKE (average voltage of the CKE signal) indicating the frequency of high level of the CKE signal. The symbol OFF in FIG. 8 indicates that the corresponding setting value VSET does not exist. Note that although the correspondence information shown in FIG. 8 is shown in a table structure, it may also be shown in a numerical string or a character string.

The ROM 1243 holds set values VSET11 and VSET10 of the adjustment voltages FB1 and FB0 corresponding to when the voltage VCKE is 0V. Setting value VSET11 indicates adjustment voltage FB1 for adjusting direct current voltage DC12 to 1.1V. Set value VSET10 indicates adjustment voltage FB0 for adjusting direct current voltage DC105 to 1.0V. When the voltage VCKE is 0V, the DC voltages DC33 and DC18 are not generated, so the set value VSET for the adjustment voltages FB3 and FB2 is not held in the ROM 1243.

The ROM 1243 holds set values VSET32, VSET17, VSET12, and VSET105 of the adjustment voltages FB3 to FB0 corresponding to when the voltage VCKE is greater than 0V and less than or equal to 0.6V. Set value VSET32 indicates adjustment voltage FB3 for adjusting direct current voltage DC33 to 3.2V. A set value VSET17 indicates an adjustment voltage FB2 that adjusts the DC voltage DC18 to 1.7V. Set value VSET12 indicates adjustment voltage FB1 that adjusts direct current voltage DC12 to 1.2V. Setting value VSET105 indicates adjustment voltage FB0 for adjusting direct current voltage DC105 to 1.05V.

The ROM 1243 holds set values VSET33, VSET18, VSET12, and VSET115 of the adjustment voltages FB3 to FB0 corresponding to when the voltage VCKE is greater than 0.6V and less than or equal to 1.2V. Set value VSET33 indicates adjustment voltage FB3 for adjusting direct current voltage DC33 to 3.3V. Setting value VSET18 indicates adjustment voltage FB2 for adjusting direct current voltage DC18 to 1.8V. Set value VSET12 indicates adjustment voltage FB1 that adjusts direct current voltage DC12 to 1.2V. Setting value VSET115 indicates adjustment voltage FB0 that adjusts direct current voltage DC105 to 1.15V.

In the setting values for the adjustment voltage FB1 shown in FIG. 8, when the voltage VCKE is greater than 0V and less than or equal to 1.2V, the FB setting unit 1244 adjusts the DC voltage DC12 supplied to the RAM 113 to 1.2V based on the setting value VSET12. An adjustment voltage FB1 to be adjusted to 2V is generated. When the voltage VCKE is greater than 0V, the RAM 113 receives a high-level CKE signal with a certain frequency and performs an access operation. In this case, by setting the set value VSET to VSET12 even when the voltage VCKE is 0.6V or less, it is possible to supply a sufficient DC voltage DC12 to the RAM 113, thereby suppressing a decrease in the operating margin of the RAM 113. Can be done.

The ROM 1243 holds set values VSET34, VSET19, VSET13, and VSET125 of adjustment voltages FB3 to FB0 corresponding to when voltage VCKE is greater than 1.2V. Set value VSET34 indicates adjustment voltage FB3 for adjusting direct current voltage DC33 to 3.4V. A set value VSET19 indicates an adjustment voltage FB2 that adjusts the DC voltage DC18 to 1.9V. Set value VSET13 indicates adjustment voltage FB1 for adjusting direct current voltage DC12 to 1.3V. Set value VSET125 indicates adjustment voltage FB0 that adjusts direct current voltage DC105 to 1.25V.

By retaining correspondence information indicating the correspondence between the voltage VCKE and the adjustment voltages FB3-FB0 in the ROM 1243, each FB setting section 1244 can set the set value VSET of the adjustment voltages FB3-FB0 set for each predetermined range of the voltage VCKE. can be easily referenced. Therefore, it is possible to easily control the generation of adjustment voltages FB3-FB0 by each FB setting section 1244.

Note that, for example, if the minimum value of the DC voltage DC105 at which the CPU 111 can operate is known in advance, the set value VSET11 may be set in accordance with this minimum value. If the minimum values of each of the DC voltages DC33 and DC18 at which the ROM 1243 can operate are known in advance, each of the set values VSET32 and VSET17 may be set in accordance with each of these minimum values.

Similarly, if the minimum value of the DC voltage DC12 at which the RAM 113 can operate is known in advance, the set value VSET11 may be set in accordance with this minimum value. Here, the minimum value of the direct current voltage DC is not the minimum operating voltage set in the electrical specifications of each device, but the actual value of each device. Thereby, it is possible to set an appropriate direct current voltage DC according to the actual performance value of the device while suppressing power consumption.

As described above, in this embodiment as well, the same effects as in the above-described embodiment can be obtained. For example, an appropriate direct current voltage DC can be supplied to the CPU 111, ROM 112, and RAM 113 according to the operating frequency without intervening a control program executed by the CPU 111. As a result, the CPU 111, ROM 112, and RAM 113 can be operated stably, and a decrease in reliability of the image forming apparatus 100 can be suppressed.

Furthermore, in this embodiment, by adjusting the value of the DC voltage DC33 by the adjustment voltage FB3 supplied to the voltage adjustment terminal FB, one power generation circuit G33A generates a DC voltage according to the frequency of high level of the CKE signal. DC33 can be generated. By adjusting the value of the DC voltage DC18 with the adjustment voltage FB2 supplied to the voltage adjustment terminal FB, one power generation circuit G18A can generate the DC voltage DC18 according to the frequency of high level of the CKE signal. .

Similarly, by adjusting the value of the DC voltage DC12 with the adjustment voltage FB1 supplied to the voltage adjustment terminal FB, one power generation circuit G12A generates the DC voltage DC12 according to the frequency of high level of the CKE signal. be able to. By adjusting the value of the DC voltage DC105 with the adjustment voltage FB0 supplied to the voltage adjustment terminal FB, one power generation circuit G105A can generate the DC voltage DC105 according to the frequency of high level of the CKE signal. . As a result, the circuit scale of the power generation section 125 can be reduced compared to the circuit scale of the power generation section 115 shown in FIG. 4, and the control board 51 that implements the control section 110 can be made smaller. As a result, the cost of the image forming apparatus 100A can be reduced.

By retaining correspondence information indicating the correspondence between voltage VCKE and adjustment voltages FB3-FB0 in the ROM 1243, it is possible to easily refer to the set value VSET of adjustment voltages FB3-FB0 set for each predetermined range of voltage VCKE. can. Therefore, it is possible to easily control the generation of adjustment voltages FB3-FB0 by each FB setting section 1244.

Note that the above-described embodiments are not limited to the image forming apparatuses 100 and 100A such as multifunction peripherals, and can be applied to, for example, individual printers, scanners, facsimiles, or electronic devices such as electronic whiteboards, projectors, and drive decoders. It is.

Although the present invention has been described above based on each embodiment, the present invention is not limited to the requirements shown in the above embodiments. These points can be changed without detracting from the gist of the present invention, and can be determined appropriately depending on the application thereof.

1 Power supply device 6 Printer section 10 Operation section 20 Start switch 40 Reading section 41 ADF
42 Scanner section 51 Control board 79 Engine control section 79a Printer circuit section 79b Scanner circuit section 100, 100A Image forming apparatus 110 Control section 111 CPU
111a Memory controller 111b Internal memory 112 ROM
113 RAM
114 Power supply control section 115 Power supply generation section 120 Power supply unit 124 Power supply control section 125 Power supply generation section 1140 Frequency detection section 1150, 1151, 1152, 1153 Power supply generation section 1240 Frequency detection section 1241 DAC
1242 Smoothing circuit 1243 ROM
1244 FB Setting Department AD address signal CKE clock enable signal CLK clock signal CMD command signal CMD command signal CMD command signal CMD command signal CMD command signal CMD command signal CMD command signal CMD command signal CMD command signal CMD command signal CMD command signal CMD command signal CMD command signal CMD command signal CMD command signal CMD command signal , G115, G125 power generation circuit G11 , G12a, G12b, G12A, G13 Power generation circuit G17, G18, G18A, G19 Power generation circuit G32, G33, G33A, G34 Power generation circuit SEL (SEL1-SEL3) Selection signal VCKE Voltage VSET Setting value

Japanese Patent Application Publication No. 2012-114973

Claims (10)

a processor;
a memory that stores a program executed by the processor and operates in synchronization with a clock signal while receiving a clock enable signal at a valid level from the processor;
a frequency detection unit that detects the frequency with which the clock enable signal is set to a valid level;
a power generation unit that generates a voltage and sets the voltage when the frequency detected by the frequency detection unit is low compared to the voltage when the frequency is high;
a functional unit operated by the voltage generated by the power generation unit;
An electronic device characterized by having. The power generation section has a plurality of power generation circuits that generate the voltages that are different from each other, and operates one of the plurality of power generation circuits according to the frequency to generate the voltage supplied to the functional section. The electronic device according to claim 1, further comprising: adjusting a value of . comprising an adjusted voltage generation unit that generates an adjusted voltage according to the frequency,
The electronic device according to claim 1, wherein the power generation section adjusts the value of the voltage supplied to the functional section according to the adjusted voltage. a holding part that holds a correspondence relationship between the frequency and the adjustment voltage;
The regulated voltage generation unit determines the regulated voltage corresponding to the frequency with reference to the holding unit, and outputs the determined regulated voltage to the power supply generation unit. Electronics. The electronic device according to any one of claims 1 to 4, wherein the frequency detection unit detects an average voltage of the clock enable signal as the frequency at every predetermined period. The electronic device according to any one of claims 1 to 4, wherein the frequency detection unit detects the number of transition edges of the clock enable signal as the frequency at every predetermined period. a plurality of functional units each operating with a plurality of types of voltages having different voltage values;
a plurality of the power generation units each generating the plurality of types of voltages based on the frequency;
The electronic device according to any one of claims 1 to 6, wherein the processor is one of the plurality of functional units. The processor has a memory controller including an access queue that holds memory access requests issued to the memory,
The memory controller sets the clock enable signal to a valid level when the memory access request is held in the access queue, and sets the clock enable signal to a valid level when the memory access request is not held in the access queue. The electronic device according to any one of claims 1 to 7, characterized in that: is set to an invalid level. an image forming section that forms an image;
a processor that executes a program that controls the operation of the image forming section;
a memory that stores the program and operates in synchronization with a clock signal while receiving a clock enable signal at a valid level from the processor;
a frequency detection unit that detects the frequency with which the clock enable signal is set to a valid level;
a power generation unit that generates a voltage and sets the voltage when the frequency detected by the frequency detection unit is low compared to the voltage when the frequency is high;
a functional unit operated by the voltage generated by the power generation unit;
An image forming apparatus comprising: a processor;
a memory that stores a program executed by the processor and operates in synchronization with a clock signal while receiving a clock enable signal at a valid level from the processor; a power generation section that generates a voltage; and the power generation section. A method for controlling a power supply of an electronic device, comprising: a functional unit operated by the voltage generated by the voltage;
detecting the frequency with which the clock enable signal is set to a valid level;
A power supply control method for an electronic device, comprising: causing the power generation unit to set the voltage when the detected frequency is low to be lower than the voltage when the detected frequency is high.

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