JP6893971B2 - 非同期パイプラインのステージの動作速度の制御 - Google Patents

非同期パイプラインのステージの動作速度の制御 Download PDF

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JP6893971B2
JP6893971B2 JP2019503302A JP2019503302A JP6893971B2 JP 6893971 B2 JP6893971 B2 JP 6893971B2 JP 2019503302 A JP2019503302 A JP 2019503302A JP 2019503302 A JP2019503302 A JP 2019503302A JP 6893971 B2 JP6893971 B2 JP 6893971B2
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stage
completion status
critical path
stages
asynchronous pipeline
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JP2019521454A5 (enExample
JP2019521454A (ja
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サドウスキー グレッグ
サドウスキー グレッグ
カラマティアノス ジョン
カラマティアノス ジョン
エヌ． ダス ショーミ
エヌ． ダス ショーミ
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G06F9/3869—Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G06F9/3871—Asynchronous instruction pipeline, e.g. using handshake signals between stages
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Image Processing (AREA)
  • Power Sources (AREA)
  • Information Transfer Systems (AREA)
  • Pipeline Systems (AREA)
JP2019503302A 2016-07-21 2017-07-20 非同期パイプラインのステージの動作速度の制御 Active JP6893971B2 (ja)

Priority Applications (1)

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JP2021092900A JP7465848B2 (ja) 2016-07-21 2021-06-02 非同期パイプラインのステージの動作速度の制御

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/216,094 US10698692B2 (en) 2016-07-21 2016-07-21 Controlling the operating speed of stages of an asynchronous pipeline
US15/216,094 2016-07-21
PCT/US2017/042981 WO2018017785A2 (en) 2016-07-21 2017-07-20 Controlling the operating speed of stages of an asynchronous pipeline

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JP2019521454A JP2019521454A (ja) 2019-07-25
JP2019521454A5 JP2019521454A5 (enExample) 2020-08-27
JP6893971B2 true JP6893971B2 (ja) 2021-06-23

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JP2021092900A Active JP7465848B2 (ja) 2016-07-21 2021-06-02 非同期パイプラインのステージの動作速度の制御

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US (2) US10698692B2 (enExample)
EP (1) EP3488340B1 (enExample)
JP (2) JP6893971B2 (enExample)
KR (2) KR102266303B1 (enExample)
CN (1) CN109478141B (enExample)
WO (1) WO2018017785A2 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10503544B2 (en) * 2016-10-17 2019-12-10 Toyota Jidosha Kabushiki Kaisha Efficient mapping from task graphs to dynamic system platforms
KR102309429B1 (ko) * 2017-03-20 2021-10-07 현대자동차주식회사 차량 및 그 제어 방법
US10326452B2 (en) * 2017-09-23 2019-06-18 Eta Compute, Inc. Synchronizing a self-timed processor with an external event
US11334696B2 (en) * 2017-09-28 2022-05-17 Intel Corporation Systems and methods for dynamic voltage and frequency scaling in programmable logic devices
JP2020165713A (ja) * 2019-03-28 2020-10-08 株式会社デンソーテン 検査データ出力装置、表示システムおよび検査データ出力方法
US11467845B2 (en) * 2020-10-20 2022-10-11 Micron Technology, Inc. Asynchronous pipeline merging using long vector arbitration

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JPH04314161A (ja) * 1991-04-11 1992-11-05 Mitsubishi Electric Corp 情報処理装置
KR100239749B1 (ko) * 1997-04-11 2000-01-15 윤종용 그로스 테스트용 tft 소자 제조 방법 및 이를 형성한 액정 표시 장치 구조와 그로스 테스트 장치 및 방법
US6182233B1 (en) * 1998-11-20 2001-01-30 International Business Machines Corporation Interlocked pipelined CMOS
US6289465B1 (en) * 1999-01-11 2001-09-11 International Business Machines Corporation System and method for power optimization in parallel units
HK1053177A1 (zh) * 2000-04-25 2003-10-10 The Trustees Of Columbia University In The City Of New York 高容量异步管线处理电路和方法
US6369614B1 (en) 2000-05-25 2002-04-09 Sun Microsystems, Inc. Asynchronous completion prediction
US6590424B2 (en) * 2000-07-12 2003-07-08 The Trustees Of Columbia University In The City Of New York High-throughput asynchronous dynamic pipelines
US6502202B1 (en) 2000-10-06 2002-12-31 Elan Research Self-adjusting multi-speed pipeline
JP3884914B2 (ja) * 2001-01-30 2007-02-21 株式会社ルネサステクノロジ 半導体装置
AU2003253163A1 (en) * 2002-09-20 2004-04-08 Koninklijke Philips Electronics N.V. Adaptive data processing scheme based on delay forecast
JP4246141B2 (ja) * 2004-03-22 2009-04-02 シャープ株式会社 データ処理装置
JP2006039754A (ja) * 2004-07-23 2006-02-09 Canon Inc 画像処理装置及びその方法
JP4261453B2 (ja) * 2004-09-30 2009-04-30 京セラミタ株式会社 メモリ制御装置
US8677103B1 (en) 2004-10-20 2014-03-18 Marvell Isreal (M.I.S.L) Ltd. Asynchronous pipelined data path with data transition
WO2007089014A1 (ja) * 2006-02-03 2007-08-09 National University Corporation Kobe University デジタルｖｌｓｉ回路およびそれを組み込んだ画像処理システム
GB2459652B (en) 2008-04-28 2010-09-22 Imagination Tech Ltd Controlling instruction scheduling based on the space in a trace buffer
JP5294449B2 (ja) * 2008-07-11 2013-09-18 国立大学法人 筑波大学 ネットワークシステムおよびネットワークシステムにおける電源制御方法
JP2010141641A (ja) * 2008-12-12 2010-06-24 Ricoh Co Ltd 半導体回路、半導体回路の出力バッファ波形調整方法
JP5720243B2 (ja) 2010-12-28 2015-05-20 富士通セミコンダクター株式会社 プロセッサ検証プログラム
US9117511B2 (en) * 2013-03-08 2015-08-25 Advanced Micro Devices, Inc. Control circuits for asynchronous circuits
US20150341032A1 (en) 2014-05-23 2015-11-26 Advanced Micro Devices, Inc. Locally asynchronous logic circuit and method therefor

Also Published As

Publication number Publication date
EP3488340A4 (en) 2020-08-19
CN109478141B (zh) 2024-06-04
WO2018017785A2 (en) 2018-01-25
EP3488340B1 (en) 2023-09-06
KR20190022858A (ko) 2019-03-06
JP2021166053A (ja) 2021-10-14
JP7465848B2 (ja) 2024-04-11
US20180024837A1 (en) 2018-01-25
EP3488340A2 (en) 2019-05-29
CN109478141A (zh) 2019-03-15
US11842199B2 (en) 2023-12-12
JP2019521454A (ja) 2019-07-25
KR20210074411A (ko) 2021-06-21
US20210089324A1 (en) 2021-03-25
US10698692B2 (en) 2020-06-30
KR102266303B1 (ko) 2021-06-17
KR102663653B1 (ko) 2024-05-10
WO2018017785A3 (en) 2018-03-08

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