JP6872055B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device having a HEMT (High Electron Mobility Transistor).

Conventionally, in HEMT having a MIS (Metal Insulator Semiconductor) structure, it is known to form a gate field plate integrated with a gate electrode in order to alleviate electric field concentration on the end portion of the gate electrode. On the other hand, as another measure for alleviating the electric field concentration, it has been proposed to form a source field plate electrically connected to the source electrode on the side of the gate electrode (for example, Patent Documents 1 to 3). reference).

Japanese Unexamined Patent Publication No. 2008-124440 Japanese Unexamined Patent Publication No. 2008-131031 Special Table 2007-537593

One embodiment of the present invention provides a semiconductor device capable of reducing parasitic capacitance and relaxing electric field concentration on each end of a gate electrode and a conductive layer (source field plate).

One embodiment of the present invention comprises a group III nitride semiconductor laminated structure including a heterojunction and an insulating layer on the group III nitride semiconductor laminated structure having a gate opening reaching the group III nitride semiconductor laminated structure. , A gate insulating film covering the bottom and sides of the gate opening, a gate electrode formed on the gate insulating film in the gate opening, and arranged apart from the gate electrode so as to sandwich the gate electrode. The source electrode and drain electrode electrically connected to the group III nitride semiconductor laminated structure, respectively, and the gate electrode and the drain electrode are embedded in the insulating layer, and the gate electrode is formed by the gate insulating film. Provided is a semiconductor device including a conductive layer insulated from the above and electrically connected to the source electrode.

One embodiment of the present invention comprises a group III nitride semiconductor laminated structure including a heterojunction and an insulating layer on the group III nitride semiconductor laminated structure having a gate opening reaching the group III nitride semiconductor laminated structure. , A gate insulating film covering the bottom and sides of the gate opening, a gate electrode formed on the gate insulating film in the gate opening, and arranged apart from the gate electrode so as to sandwich the gate electrode. The side portion of the gate opening is partially formed between the source electrode and the drain electrode electrically connected to the group III nitride semiconductor laminated structure and the gate electrode and the drain electrode, respectively. Provided is a semiconductor device including a source field plate embedded in the insulating layer and insulated from the gate electrode by the gate insulating film, including a source field plate electrically connected to the source electrode.

These semiconductor devices include, for example, a step of forming a conductive layer on a group III nitride semiconductor laminated structure including a heterojunction, a step of forming an insulating layer so as to cover the conductive layer, and at least one of the conductive layers. A step of forming a gate opening by etching the insulating layer and the conductive layer from an etching region including a region facing the portion, and exposing the conductive layer to a side portion of the gate opening, and the gate. The conductive layer is formed between the step of forming the gate insulating film so as to cover the bottom and the side portion of the opening, the step of forming the gate electrode on the gate insulating film in the gate opening, and the gate electrode. One embodiment of the present invention includes a step of forming a drain electrode on the group III nitride semiconductor laminated structure so as to be sandwiched, and a step of forming a source electrode on the opposite side of the drain electrode by sandwiching the gate electrode. It can be manufactured by the method of.

According to this method, the conductive layer (source field plate) is formed by a self-alignment process during the formation of the gate opening. Thereby, the position of the end portion of the conductive layer (source field plate) on the side close to the gate electrode can be fixed to the side portion of the gate opening. Therefore, the distance between the gate electrode and the conductive layer (source field plate) can be easily controlled by the thickness of the gate insulating film. As a result, the maximum electric field strength in the semiconductor device can be designed to an intended value. Therefore, it is possible to realize a structure capable of relaxing the electric field concentration on each end of the gate electrode and the conductive layer (source field plate).

Then, in the obtained semiconductor device, a conductive layer (source field plate) electrically connected to the source electrode is arranged between the gate and the drain. As a result, it is not necessary to provide a gate field plate integrally extending laterally on the insulating layer from the gate electrode, so that the gate-drain capacitance Cgd can be reduced. As a result, the parasitic capacitance of the semiconductor device can be reduced, so that the high-speed switching operation, high-frequency operation, and the like, which are the characteristics of the nitride semiconductor device, can be satisfactorily exhibited.

One embodiment of the present invention further includes an insulating sidewall disposed between the gate insulating film and the side portion of the gate opening.
One embodiment of the present invention further includes an insulating sidewall formed on the side of the gate opening so as to be in contact with the source field plate, and the gate insulating film is formed so as to cover the sidewall. Has been done.

The configuration including these sidewalls includes, for example, a step of forming an insulating film so as to cover the bottom and side portions of the gate opening and the surface of the insulating layer prior to the formation of the gate insulating film, and the gate. One embodiment of the present invention further comprises the step of forming a sidewall on the side of the gate opening by selectively etching the bottom of the opening and the insulating film on the surface of the insulating layer. It can be obtained by the method.

According to this configuration, the distance between the gate electrode and the conductive layer can be controlled mainly by the thickness of the sidewall. Therefore, the thickness of the gate insulating film can be designed mainly according to the intended gate threshold voltage.
One embodiment of the present invention is a step of forming a base layer for insulating the conductive layer from the group III nitride semiconductor laminated structure on the group III nitride semiconductor laminated structure prior to forming the conductive layer. The step of forming the sidewall includes the step of forming a sidewall having an insulating material having an etching selectivity smaller than that of the base layer at least on the outermost surface, and after forming the sidewall, the gate opening. The step of selectively etching the base layer at the bottom of the portion to bring the bottom of the gate opening to the group III nitride semiconductor laminated structure is further included.

According to this method, when the base layer is etched, it is possible to prevent the sidewall from being etched together with the base layer and becoming thin. Therefore, even after etching the base layer, it is possible to maintain a sidewall having a thickness close to the design value.
In one embodiment of the invention, the sidewall comprises at least one material selected from the group consisting of _{SiO 2, SiN and SiON.}

In one embodiment of the present invention, the distance _LGF between the gate electrode and the conductive layer is 1 μm or less.
According to this configuration, since the conductive layer is arranged relatively close to the gate electrode, the electric field concentration on each end of the conductive layer (source field plate) can be satisfactorily relaxed.
In one embodiment of the present invention, the length L _{FP of the conductive layer and the distance L GD} between the gate electrode and the drain electrode satisfy _{L FP} <1/3 L _GD.

According to this configuration, since the area of the conductive layer (source field plate) is relatively small, it is possible to suppress an increase in the drain-source capacitance Cds due to the installation of the conductive layer.
In one embodiment of the present invention, the gate insulating film contains at least one material selected from the group consisting of Si, Al and Hf as constituent elements.
In one embodiment of the invention, the gate electrode comprises a metal electrode.

In one embodiment of the present invention, the gate electrode includes an overlapping portion formed on the gate insulating film at the periphery of the gate opening.
In one embodiment of the present invention, the group III nitride semiconductor laminated structure includes an active region including an element structure formed by sandwiching the gate electrode between the source electrode and the drain electrode, and a non-active region outside the active region. Each of the source electrode and the conductive layer includes an active region, and each includes an extension portion to the non-active region, and the extension portion of the source electrode and the extension portion of the conductive layer are connected to each other.

According to this configuration, as a structure for electrically connecting the source electrode and the conductive layer (source field plate), the conductivity is electrically connected to each of the source electrode and the conductive layer across the upper part of the gate electrode. There is no need to provide a structure in the active area. If such a conductive structure is provided in the active region, it can be a factor of increasing the parasitic capacitance of the semiconductor device. However, by connecting the source electrode and the conductive layer in the non-active region as described above, the parasitic capacitance is increased. Can be suppressed.

In one embodiment of the present invention, the group III nitride semiconductor laminated structure includes a first semiconductor layer forming the heterojunction and a second semiconductor layer on the first semiconductor layer, and the second semiconductor layer is The bottom of the gate opening selectively contains an oxide film formed by oxidation of the second semiconductor layer.
According to this configuration, the two-dimensional electron gas directly under the gate electrode can be reduced, so that a normally-off type HEMT can be realized.

In one embodiment of the present invention, the group III nitride semiconductor laminated structure includes a first semiconductor layer forming the heterojunction and a second semiconductor layer on the first semiconductor layer, and the second semiconductor layer comprises. Only the bottom of the gate opening is selectively etched.
According to this configuration, the recess structure by etching prevents the formation of a heterojunction directly under the gate electrode. As a result, when the gate bias is not applied (at the time of zero bias), the two-dimensional electron gas is not formed in the region directly under the gate bias, so that a normally-off type HEMT can be realized.

One embodiment of the present invention further includes a base layer arranged between the conductive layer and the group III nitride semiconductor laminated structure and extending to a formation region of the source electrode and the drain electrode, and further includes the source electrode and /. Alternatively, the drain electrode includes an ohmic electrode in the base layer and a pad electrode in the insulating layer formed on the ohmic electrode.
In one embodiment of the present invention, the base layer has a thickness of 5 nm to 200 nm, and the insulating layer has a thickness of 1.5 μm to 2 μm.

According to this configuration, an opening for ohmic contact can be formed by etching a relatively thin base layer, so that the surface of the group III nitride semiconductor laminated structure is less damaged when the opening is formed. It's done. As a result, the source electrode and the drain electrode can be connected to the surface of the group III nitride semiconductor laminated structure with less damage, so that good ohmic contact can be obtained.

In one embodiment of the present invention, a second embodiment is embedded in the insulating layer between the gate electrode and the source electrode, insulated from the gate electrode by the gate insulating film, and also insulated from the source electrode. Further includes a conductive layer.

FIG. 1A is a schematic plan view of a semiconductor device according to an embodiment of the present invention. FIG. 1B is a schematic plan view of a semiconductor device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view of the semiconductor device (cross-sectional view taken along line II-II of FIGS. 1A and 1B). FIG. 3 is an enlarged view of a main part of the semiconductor device (inner region of broken line III in FIG. 2). FIG. 4 is a flow chart for explaining a method for manufacturing the semiconductor device. FIG. 5A is a diagram showing a part of the manufacturing process of the semiconductor device. FIG. 5B is a diagram showing the next step of FIG. 5A. FIG. 5C is a diagram showing the next step of FIG. 5B. FIG. 5D is a diagram showing the next step of FIG. 5C. FIG. 5E is a diagram showing the next step of FIG. 5D. FIG. 5F is a diagram showing the next step of FIG. 5E. FIG. 5G is a diagram showing the next step of FIG. 5F. FIG. 5H is a diagram showing the next step of FIG. 5G. FIG. 5I is a diagram showing the next step of FIG. 5H. FIG. 5J is a diagram showing the next step of FIG. 5I. FIG. 5K is a diagram showing the next step of FIG. 5J. FIG. 5L is a diagram showing the next step of FIG. 5K. FIG. 5M is a diagram showing the next step of FIG. 5L. FIG. 5N is a diagram showing the next step of FIG. 5M. FIG. 5O is a diagram showing the next step of FIG. 5N. FIG. 6 is a model diagram of the simulation. FIG. 7 is a graph showing the relationship between _{LFP and the maximum electric field strength in the simulation model.} FIG. 8 is a graph showing the relationship between the _{L SW and the maximum electric field strength in the simulation model.} 9A-9C are diagrams showing the spread of channels in the simulation model (without SFP). 10A-10C are diagrams showing the spread of channels in the simulation model (without SFP). 11A to 11C are diagrams showing the spread of channels in the simulation model (with SFP). 12A to 12C are diagrams showing the spread of channels in the simulation model (with SFP). FIG. 13 is a diagram showing an evaluation result of parasitic capacitance. FIG. 14 is a schematic cross-sectional view of the semiconductor device according to the embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
1A and 1B are schematic plan views of the semiconductor device 1 according to the embodiment of the present invention. For clarity, the regions of the source field plate 8 and the floating plate 9 are hatched in FIG. 1A and the regions of the source electrode 5 are hatched in FIG. 1B. 1A and 1B are the same except that the hatched areas are different.

The semiconductor device 1 has a drain electrode 3, a gate electrode 4, a source electrode 5, and a plate film 6 on a base group III nitride semiconductor laminated structure 2. For example, as shown in FIGS. 1A and 1B, the drain electrode 3 (D), the gate electrode 4 (G), and the source electrode 5 (S) are periodically arranged in the order of DGSGD. As a result, the element structure 7 is formed by sandwiching the gate electrode 4 between the drain electrode 3 and the source electrode 5. The plate film 6 is arranged between the gate and the source and between the drain and the gate, respectively. The source field plate 8 as an example of the conductive layer of the present invention is arranged between the drain and the gate, and the floating plate 9 as an example of the second conductive layer of the present invention is arranged between the gate and the source.

On the surface of the group III nitride semiconductor laminated structure 2, an active region 10 including the element structure 7 and a non-active region 11 outside the active region 10 can be defined. The non-active region 11 may only be adjacent to the active region 10 as shown in FIGS. 1A and 1B, or may surround the active region 10.
The source electrode 5 includes a base portion 12 as an example of an extension portion of the present invention on the non-active region 11, and a plurality of electrode portions 13 integrally connected to the base portion 12. The source electrode 5 of this embodiment has a comb-teeth shape in which a plurality of electrode portions 13 extend in a stripe shape parallel to each other. The base portion 12 has a connection end portion 14 for the electrode portion 13 in the non-active region 11. The plurality of electrode portions 13 extend from the connection end portion 14 toward the active region 10. That is, the plurality of electrode portions 13 straddle between the active region 10 and the non-active region 11.

The space 15 between the adjacent electrode portions 13 is a region in which the drain electrode 3 is arranged. In this embodiment, two comb-shaped source electrodes 5 and drain electrodes 3 are engaged with each other by arranging linear drain electrodes 3 in each space 15. Although not shown, the drain electrode 3 has a base portion on the non-active region 11 and a plurality of electrode portions (arranged in the space 15) integrally connected to the base portion, similarly to the source electrode 5. The part to be used) and may be included.

The gate electrode 4 includes a base portion 16 on the non-active region 11 and a plurality of electrode portions 17 integrally connected to the base portion 16. The gate electrode 4 of this embodiment has a comb-teeth shape in which a plurality of electrode portions 17 extend in a stripe shape parallel to each other. The base portion 16 has a connection end portion 18 for the electrode portion 17 in the non-active region 11. The connection end 18 is located outside the connection end 14 of the source electrode 5 (relatively far from the active region 10) with reference to the boundary between the active region 10 and the non-active region 11 (element separation line 19). It is provided. The plurality of electrode portions 17 extend from the connection end portion 18 toward the active region 10. That is, the plurality of electrode portions 17 straddle between the active region 10 and the non-active region 11. Further, the base portion 16 of the gate electrode 4 includes a drawer portion 20 outside the base portion 12 of the source electrode 5. For example, the lead-out portion 20 is a region for forming a contact with the gate electrode 4.

The source field plate 8 includes a base portion 21 as an example of an extension portion of the present invention on the non-active region 11, and a plurality of electrode portions 54 integrally connected to the base portion 21. The source field plate 8 of this embodiment has an arch shape in which a pair of electrode portions 54 extend from both ends of the base portion 21. The base portion 21 has a connection end portion 22 for the electrode portion 54 in the non-active region 11. The connection end portion 22 is provided at substantially the same position as the connection end portion 14 of the source electrode 5 with reference to the element separation line 19. The pair of electrode portions 54 extend from the connection end portion 22 toward the active region 10. That is, the pair of electrode portions 54 straddle between the active region 10 and the non-active region 11.

The base portion 12 of the source electrode 5 and the base portion 21 of the source field plate 8 partially overlap in the non-active region 11. In this overlapping portion, the source electrode 5 and the source field plate 8 are connected via the source contact 23. For example, as shown in FIGS. 1A and 1B, the source contact 23 is provided at a position facing the space 15 (a position avoiding an extension portion of the electrode portion 13).

When the source contact 23 is provided in the non-active region 11 in this way, the source electrode 5 and the source field straddle the upper part of the gate electrode 4 as a structure for electrically connecting the source electrode 5 and the source field plate 8. It is not necessary to provide a conductive structure electrically connected to each of the plates 8 in the active region 10. If such a conductive structure is provided in the active region 10, it may cause an increase in the parasitic capacitance of the semiconductor device 1. However, as described above, the source electrode 5 and the source field plate 8 are connected in the non-active region 11. Therefore, the increase in parasitic capacitance can be suppressed.

The floating plate 9 includes a base portion 51 on the non-active region 11 and a plurality of electrode portions 55 integrally connected to the base portion 51. The floating plate 9 of this embodiment has an arch shape in which a pair of electrode portions 55 extend from both ends of the base portion 51. The base portion 51 has a connection end portion 52 for the electrode portion 55 in the non-active region 11. The connection end portion 52 is provided at substantially the same position as the connection end portion 14 of the source electrode 5 with reference to the element separation line 19. The pair of electrode portions 55 extend from the connection end portion 52 toward the active region 10. That is, the pair of electrode portions 55 straddle between the active region 10 and the non-active region 11.

Next, the cross-sectional structure of the semiconductor device 1 will be described with reference to FIGS. 2 and 3.
FIG. 2 is a cross-sectional view of the semiconductor device 1 (cross-sectional view taken along line II-II of FIGS. 1A and 1B). FIG. 3 is an enlarged view of a main part of the semiconductor device 1 (inner region of the broken line III in FIG. 2).
As shown in FIG. 3, the group III nitride semiconductor laminated structure 2 includes an electron traveling layer 24 as an example of the first semiconductor layer of the present invention and an example of the second semiconductor layer of the present invention on the electron traveling layer 24. The electron supply layer 25 of the above is included. The electron traveling layer 24 and the electron supply layer 25 are made of group III nitride semiconductors having different Al compositions from each other. For example, the electron traveling layer 24 may be made of a GaN layer, and its thickness may be 0.1 μm to 3 μm. For example, the electron supply layer 25 may be made of an AlN layer, and its thickness may be 1 nm to 7 nm. The electron traveling layer 24 and the electron supply layer 25 are not particularly limited as long as they have a composition capable of forming a heterojunction to generate a two-dimensional electron gas, and are each an Al _x Ga _1-x N layer (0). It may consist of ≦ x ≦ 1) and A _y Ga _1-y N layer (0 ≦ y ≦ 1).

As described above, the electron traveling layer 24 and the electron supply layer 25 are made of nitride semiconductors having different Al compositions from each other, and lattice mismatch occurs between them. Then, due to the polarization caused by this lattice mismatch, the position near the interface between the electron traveling layer 24 and the electron supply layer 25 (for example, a position at a distance of about several Å from the interface) is caused by the polarization. The dimensional electron gas 26 is spreading.

An oxide film 27 is selectively formed on the electron supply layer 25 so as to reach the electron traveling layer 24 from the surface thereof. The oxide film 27 has a film thickness substantially equal to that of the electron supply layer 25. For example, the oxide film 27 is a thermal oxide film, which is an oxide film formed without damaging the interface with the electron traveling layer 24. When the electron supply layer 25 is an AlN layer, the oxide film 27 may be made of an AlON film.

The group III nitride semiconductor laminated structure 2 may be laminated on a substrate such as a silicon substrate via a buffer layer.
The semiconductor device 1 further includes a base layer 28 and an insulating layer 29 formed on the group III nitride semiconductor laminated structure 2.
The base layer 28 is formed on the entire surface of the group III nitride semiconductor laminated structure 2 including the formation region of the drain electrode 3 and the source electrode 5. For example, the base layer 28 may be made of a SiN film, and its thickness may be 5 nm to 200 nm.

The insulating layer 29 covers the base layer 28 and includes a first layer 30 and a second layer 31 on the first layer 30. For example, the first layer 30 and the second layer 31 may both be made of a SiO ₂ film. Further, the insulating layer 29 may have a thickness of 1.5 μm to 2 μm. Individually, the first layer 30 may have a thickness of 500 nm to 1000 nm, and the second layer 31 may have a thickness of 500 nm to 1000 nm.

A gate opening 32 that reaches the group III nitride semiconductor laminated structure 2 is formed in the first layer 30 and the base layer 28. The oxide film 27 is exposed at the bottom of the gate opening 32. A gate insulating film 33 is formed so as to cover the bottom and side portions of the gate opening 32. The gate insulating film 33 is formed not only in the gate opening 32 but also between the first layer 30 and the second layer 31. For example, the gate insulating film 33 may consist of at least one material film selected from the group consisting of Si, Al, and Hf as constituent elements. More specifically, even if the gate insulating film 33 is made of at least one material film selected from the group consisting of _{SiN, SiO 2} , SiON, Al ₂ O ₃ , AlN, AlON, HfSiO, HfO _{2, and the like.} Good. Of these, an Al ₂ O ₃ film is preferable. Further, the gate insulating film 33 may have a thickness of 10 nm to 100 nm.

The gate electrode 4 is embedded in the gate opening 32. For example, the gate electrode 4 may be filled in the gate opening 32 so as not to protrude above the opening end of the gate opening 32. Alternatively, the gate electrode 4 may include an overlap portion 34 formed on the gate insulating film 33 at the periphery of the gate opening 32, as shown by the broken line in FIG. For example, the gate electrode 4 may be made of a metal electrode such as Mo or Ni, or may be made of a semiconductor electrode such as doped polysilicon. Since the metal electrode is inferior in embedding property as compared with polysilicon, the overlap portion 34 is particularly likely to be formed when the metal electrode is used.

The source field plate 8 and the floating plate 9 are arranged on the side of the gate electrode 4 so as to partially form the side portion of the gate opening 32. Specifically, the source field plate 8 and the floating plate 9 are formed on the base layer 28 with an insulating film 36 so as to be exposed below the side portion of the gate opening 32. That is, the side portion of the gate opening 32 is formed by the source field plate 8 and the floating plate 9 on the lower side and the insulating layer 29 (first layer 30) on the upper side, whereby the conductive layer / insulating layer is laminated. It has an interface.

An insulating sidewall 35 is formed on the side of the gate opening 32 so as to be in contact with the source field plate 8 and the floating plate 9. That is, the sidewall 35 is arranged between the side portion of the gate opening 32 and the gate insulating film 33. For example, the sidewall 35 may consist of at least one material film selected from the group consisting of _{SiO 2, SiN and SiON.} Of these, a SiO ₂ film is preferable. Further, the sidewall 35 may have a thickness of 10 nm to 200 nm.

The source field plate 8 and the floating plate 9 are insulated from the gate electrode 4 by the sidewall 35 and the gate insulating film 33. _{For example, the distance LGF} between the gate electrode 4 and the source field plate 8 and the floating plate 9 may be 1 μm or less, preferably 50 nm to 200 nm. The distance L _GF is defined by the total thickness of the gate insulating film 33 and the sidewall 35 in this embodiment, but in the configuration without the sidewall 35, the distance L _GF = the thickness of the gate insulating film 33. May be good. The length _{L FP} of the source field plate 8, for example, between the distance _{L GD} between the gate electrode 4 and the drain electrode _3, satisfies L FP <1 / _{3L GD.} For example, when the withstand voltage of the semiconductor device 1 is 200 V or less, the length L _FP may be 0.25 μm to 1.5 μm, and the distance L _GD may be 1 μm to 6 μm. Further, the source field plate 8 and the floating plate 9 may be made of a Mo film, and the thickness thereof may be 10 nm to 200 nm.

A source contact hole 37 and a drain contact hole 38 that reach the group III nitride semiconductor laminated structure 2 are formed in the insulating layer 29 and the base layer 28. The source contact hole 37 and the drain contact hole 38 are formed at positions laterally separated from the gate opening 32. A source electrode 5 and a drain electrode 3 are embedded in the source contact hole 37 and the drain contact hole 38, respectively. The source electrode 5 and the drain electrode 3 are electrically connected to the group III nitride semiconductor laminated structure 2 in the source contact hole 37 and the drain contact hole 38, respectively.

The source contact hole 37 and the drain contact hole 38 have ohmic contact openings 39 and 40 that are relatively larger than the portion of the insulating layer 29 in the portion of the base layer 28 (the ohmic contact opening 39 is shown in FIG. 1A, FIG. See 1B and FIG. 3, see FIG. 1A and FIG. 1B for the ohmic contact opening 40). The source electrode 5 and the drain electrode 3 have ohmic electrodes 41 and 42 in the ohmic contact openings 39 and 40, respectively, and pad electrodes 43 and 44 in the insulating layer 29. As shown in FIGS. 1A and 1B, the ends of the ohmic electrodes 41 and 42 in the depth direction of the space 15 are arranged at the same positions as each other. For example, the ends of the ohmic electrodes 42 on the drain side are selectively arranged. You may retreat to. The pad electrodes 43 and 44 are formed on the ohmic electrodes 41 and 42, and the top thereof is exposed from the surface of the insulating layer 29. For example, the ohmic electrodes 41 and 42 and the pad electrodes 43 and 44 may be made of a Ti / Al film.

Although this embodiment has a configuration that appears on the cut surface at a position different from that of FIG. 3, the insulating layer 29 may have a contact hole 46 that reaches the source field plate 8. The source contact 23 shown in FIG. 1 may be embedded in the contact hole 46 and connected to the source field plate 8.
In this semiconductor device 1, as described above, an electron supply layer 25 having a different Al composition is formed on the electron traveling layer 24 to form a heterojunction. As a result, the two-dimensional electron gas 26 is formed in the electron traveling layer 24 near the interface between the electron traveling layer 24 and the electron supply layer 25, and a HEMT using the two-dimensional electron gas 26 as a channel is formed. The gate electrode 4 faces the electron traveling layer 24 with the laminated film of the oxide film 27 and the gate insulating film 33 interposed therebetween, and the electron supply layer 25 does not exist directly under the gate electrode 4. Therefore, the two-dimensional electron gas 26 due to the polarization due to the lattice mismatch between the electron supply layer 25 and the electron traveling layer 24 is not formed immediately below the gate electrode 4. Therefore, when no bias is applied to the gate electrode 4 (at the time of zero bias), the channel due to the two-dimensional electron gas 26 is blocked directly under the gate electrode 4. In this way, a normally-off type HEMT is realized. When an appropriate on-voltage (for example, 5V) is applied to the gate electrode 4, a channel is induced in the electron traveling layer 24 immediately below the gate electrode 4, and two-dimensional electron gases 26 on both sides of the gate electrode 4 are connected. As a result, the source and drain become conductive.

At the time of use, for example, a predetermined voltage (for example, 200V to 400V) on which the drain electrode 3 side is positive is applied between the source electrode 5 and the drain electrode 3. In that state, an off voltage (0V) or an on voltage (5V) is applied to the gate electrode 4 with the source electrode 5 as a reference potential (0V).
The interface between the oxide film 27 and the electron traveling layer 24 is continuous with the interface between the electron supplying layer 25 and the electron traveling layer 24, and the state of the interface of the electron traveling layer 24 immediately below the gate electrode 4 is the electron supply layer. It is equivalent to the state of the interface between 25 and the electron traveling layer 24. Therefore, the electron mobility in the electron traveling layer 24 immediately below the gate electrode 4 is maintained in a high state. Thus, this embodiment provides a nitride semiconductor device having a normally-off HEMT structure.

Next, a method of manufacturing the semiconductor device 1 will be described with reference to FIGS. 4 and 5A to 5O.
FIG. 4 is a flow chart for explaining a manufacturing method of the semiconductor device 1. 5A to 5O are diagrams showing the manufacturing process of the semiconductor device 1 in the order of the processes.
In order to manufacture the semiconductor device 1, for example, a buffer layer (not shown) and an electron traveling layer 24 are epitaxially grown on a substrate (not shown) in order, and as shown in FIG. 5A, an electron traveling layer 24 is further formed. The electron supply layer 25 is epitaxially grown on the top. As a result, the group III nitride semiconductor laminated structure 2 is formed (step S1).

Next, as shown in FIG. 5B, the base layer 28 is formed by, for example, a CVD method (chemical vapor deposition method) so as to cover the entire surface on the electron supply layer 25 (step S2).
Next, as shown in FIG. 5C, the base layer 28 is selectively removed by, for example, dry etching (step S3). As a result, the ohmic contact opening 39 of the source contact hole 37 and the ohmic contact opening 40 of the drain contact hole 38 are formed at the same time (in FIG. 5C and thereafter, the illustration of the drain contact hole 38 and its description thereof are omitted).

Next, as shown in FIG. 5D, the ohmic electrode 41 is formed in the ohmic contact opening 39 (step S4). As shown in FIG. 5C, in forming the ohmic contact opening 39, only etching of the base layer 28, which is a thinner film than the insulating layer 29 formed in a later step, is sufficient. Therefore, damage to the surface of the group III nitride semiconductor laminated structure 2 can be reduced as compared with the case where the insulating layer 29 is etched to form an opening. As a result, the ohmic electrode 41 (source electrode 5) can be connected to the surface of the group III nitride semiconductor laminated structure 2 with less damage, so that good ohmic contact can be obtained.

Next, as shown in FIG. 5E, an insulating film 36 is formed so as to cover the entire surface on the electron supply layer 25 by, for example, a CVD method (chemical vapor deposition method), and further, a sputtering method and a vapor deposition method. A plate film 45 as an example of the conductive layer of the present invention is formed on the insulating film 36 (step S5).
Next, as shown in FIG. 5F, the plate film 45 is selectively removed by, for example, dry etching (step S6). As a result, the plate film 6 is formed between the formation region of the source electrode 5 and the formation region of the drain electrode 3. The distance between the adjacent plate films 6 is at least larger than the opening diameter of the source contact hole 37 formed in a later step, preferably larger than the opening diameter of the ohmic contact opening 39, as shown in FIG. 5F. Be enlarged. By doing so, it is possible to prevent the source electrode 5 from coming into contact with the plate film 6 even if the source contact hole 37 is laterally displaced when the source contact hole 37 is formed. That is, this prevents the source electrode 5 from being connected to the plate film 6 at a portion other than the source contact 23.

Next, as shown in FIG. 5G, the first layer 30 of the insulating layer 29 is formed by, for example, a CVD method (chemical vapor deposition method) so as to cover the entire surface on the electron supply layer 25 (step). S7). As a result, the plate film 6 is embedded in the first layer 30.
Next, as shown in FIG. 5H, the gate opening 32 is formed by etching the first layer 30 and the plate film 6 from the etching region including the region facing the plate film 6 (step S8). As a result, the plate film 6 is separated into the source field plate 8 on the drain side and the floating plate 9 on the source side in a self-aligned manner with respect to the gate opening 32. Therefore, the source field plate 8 and the floating plate 9 are exposed to the side of the gate opening 32 at this stage.

Next, as shown in FIG. 5I, an insulating film 47 is formed so as to cover the entire surface on the electron supply layer 25 by, for example, a CVD method (chemical vapor deposition method) (step S9). The step of forming the insulating film 47 includes a step of forming a lower layer film 48 in contact with the insulating layer 29 and a step of forming an upper layer film 49 forming the outermost surface of the insulating film 47, thereby forming a laminated structure of the insulating film. May include a step of forming. The laminated structure may have a two-layer structure or a three-layer or more structure. For example, the lower layer film 48 may be made of a SiO ₂ film, and the upper layer film 49 may be made of an Al ₂ O ₃ film. When both the insulating layer 29 and the lower layer film 48 are SiO ₂ films, the adhesion of the insulating film 47 (lower layer film 48) to the insulating layer 29 can be improved. Therefore, it is possible to prevent the film peeling of the sidewall 35 in a later step.

Next, as shown in FIG. 5J, for example, by etching back, the portion of the insulating film 47 on the insulating layer 29 is selectively removed, and the sidewall 35 is formed on the side portion of the gate opening 32 (the sidewall 35 is formed). Step S10). If employs an Al ₂ O ₃ film as an upper layer 49, after etching back a portion of the etched hard the Al ₂ O ₃ film would remain as protrusion 50 upward from the gate opening 32.

Next, as shown in FIG. 5K, the base layer 28 at the bottom of the gate opening 32 is selectively removed by, for example, dry etching (step S11). As a result, the electron supply layer 25 of the group III nitride semiconductor laminated structure 2 is exposed at the bottom of the gate opening 32. When the base layer 28 is a SiN film and the upper layer film 49 is an Al ₂ O ₃ film, the etching selectivity of the upper layer film 49 should be reduced with respect to the etchant for the base layer 28 (for example, CF _{4 gas, etc.).} Can be done. Therefore, when the base layer 28 is etched, the lower layer film 48 can be protected by the upper layer film 49, so that it is possible to prevent the sidewall 35 (lower layer film 48) from being etched together with the base layer 28 and becoming thinner. .. Therefore, even after etching the base layer 28, the sidewall 35 having a thickness close to the design value can be maintained.

Next, as shown in FIG. 5L, the surface portion of the sidewall 35 is selectively removed by, for example, dry etching. In this embodiment, the lower layer film 48 is left as the sidewall 35 by selectively removing the upper layer film 49 forming the outermost surface. When the upper film 49 is an Al ₂ O ₃ film, for example, BCl ₃ gas may be used as an etchant. After that, the portion exposed to the gate opening 32 of the electron supply layer 25 is selectively oxidized, so that a part of the electron supply layer 25 becomes an oxide film 27.

Next, as shown in FIG. 5M, a gate insulating film 33 is formed so as to cover the entire surface on the electron supply layer 25 by, for example, a CVD method (chemical vapor deposition method), and further, the gate insulating film 33 is formed. The gate electrode 4 is embedded inside (step S13). After the formation of the gate electrode 4, the second layer 31 is formed by, for example, a CVD method (chemical vapor deposition method) so as to cover the entire surface on the electron supply layer 25.

Next, as shown in FIG. 5N, the second layer 31, the gate insulating film 33 and the first layer 30 are selected from the etching region including the region facing the ohmic electrode 41 and the source field plate 8 by, for example, dry etching. Is removed. As a result, the source contact hole 37, the drain contact hole 38 (see FIGS. 1A, 1B and 2) and the contact hole 46 are simultaneously formed (step S14).

Next, as shown in FIG. 5O, an electrode film is formed on the insulating layer 29 by, for example, a sputtering method, a vapor deposition method, or the like so as to cover the entire surface of the electron supply layer 25, and the electrode film is patterned. A source electrode 5 (pad electrode 43), a drain electrode 3 (pad electrode 44), and a source contact 23 are formed (step S15). Through the above steps, the semiconductor device 1 shown in FIGS. 1A to 3 is obtained.

According to the above method, as shown in FIG. 5H, the source field plate 8 is formed by a self-alignment process when the gate opening 32 is formed. As a result, the source field plate 8 is exposed to the side portion of the gate opening 32, so that the end position of the source field plate 8 on the side close to the gate electrode 4 can be fixed to the side portion of the gate opening 32. .. Therefore, as shown in FIG. 3, the distance _LGF between the gate electrode 4 and the source field plate 8 can be easily controlled by the gate insulating film 33 and the sidewall 35. As a result, the maximum electric field strength in the semiconductor device 1 can be designed to an intended value. Therefore, it is possible to realize a structure capable of relaxing the electric field concentration on each end of the gate electrode 4 and the source field plate 8.

This effect can be demonstrated, for example, with reference to FIGS. 6-8. FIG. 6 is a model diagram of the simulation.
In this simulation model, the following conditions were set for the main configuration of FIG.
-Group III nitride semiconductor laminated structure 2: GaN (1.0 μm, 1 × 10 ¹⁶ cm ^-3 ) / AlGaN
・ Underlayer 28: SiN, 100 nm
-Insulating film 36: Al ₂ O ₃ , 40 nm
-Source field plate (SFP) 8: Length L _FP
Insulation layer 29: SiO ₂ , 300 nm
-Gate insulating film 33: Al ₂ O ₃ , 40 nm
・ Sidewall 35: SiO ₂ , thickness L _SW
Under such conditions, when the length L _FP of the source field plate 8 and the thickness L _SW of the sidewall 35 are changed (L _GD = 6.0 μm, V _DS = 200 V), what is the electric field strength distribution? I simulated how it changes. The results are shown in FIGS. 7 and 8.

FIG. 7 is a graph showing the relationship between _{LFP and the maximum electric field strength in the simulation model.} In FIG. 7, the _{measured value is standardized with 1 when L FP} = 0 μm (that is, without the source field plate 8). According to FIG. 7, it can be seen that the maximum electric field strength can be relaxed by installing the source field plate 8. Since this electric field relaxation effect _{saturates at L FP} > 1 μm (= 1/6 L _GD ), the length L _FP is taken into consideration in consideration of the increase in the drain-source capacitance Cds as the length L _{FP increases.} Is preferably at least about 1/3 of the _{distance LGD.}

On the other hand, FIG. 8 is a graph showing the relationship between the _{L SW and the maximum electric field strength in the simulation model.} In FIG. 8, the measured value is standardized with 1 when _{L SW = 50 nm.} According to FIG. 8, it can be seen that the maximum electric field strength does not depend on _{the thickness L SW of the sidewall 35. In other words, FIG. 8 shows that the distance LGF} between the gate electrode 4 and the source field plate 8 shown in FIG. 3 has a small effect on the maximum electric field strength regardless of whether it is small or large. Therefore, by adjusting the thickness of the gate insulating film 33 and the sidewall 35 and arranging the source field plate 8 relatively close to the gate electrode 4 (for example, 1 μm or less), the end of the source field plate 8 is reached. The electric field concentration can be satisfactorily relaxed.

Furthermore, using the model of FIG. 6, the channel spread in the group III nitride semiconductor laminated structure 2 was also verified. 9A-9C and 10A-10C are diagrams showing channel spread in a simulation model (without SFP). 11A-11C and 12A-12C are diagrams showing the spread of channels in a simulation model (with SFP).

From FIGS. 11A to 11C and FIGS. 12A to 12C, in the normally-off type GaN-HEMT using the MIS structure as in the semiconductor device 1, when the source field plate 8 is present, the carrier generated by the gate voltage is the source field plate. The result is that it does not spread directly under 8. In such a case, if the carrier of the two-dimensional electron gas 26 does not exist, for example, an oxide film region is formed directly under the source field plate 8, the oxide film region directly under the source field plate 8 The potential may be high. Therefore, if a relatively high bias is not applied to the gate electrode 4, the potential does not decrease, and there is a possibility that current does not flow between the source and drain. In this regard, in this embodiment, as shown in FIG. 5H, the source field plate 8 is formed by a self-alignment process during the formation of the gate opening 32. Therefore, the oxide film 27 is not formed directly under the source field plate 8. _{Therefore, by minimizing} the distance LGF between the gate electrode 4 and the source field plate 8, the channel can be formed at a relatively low gate voltage, so that the on-characteristics of the device can be maximized. Moreover, such a structure can be realized by a simple method of adjusting the thickness of the gate insulating film 33 and the sidewall 35. Further, according to this embodiment, since the sidewall 35 is provided, the distance _LGF between the gate electrode 4 and the source field plate 8 can be controlled mainly by the thickness of the sidewall 35. Therefore, the thickness of the gate insulating film 33 can be designed mainly according to the intended gate threshold voltage.

Then, in the semiconductor device 1, the source field plate 8 electrically connected to the source electrode 5 is arranged between the gate and the drain. As a result, it is not necessary to provide a gate field plate integrally extending laterally on the insulating layer 29 from the gate electrode 4, so that the gate-drain capacitance Cgd can be reduced. As a result, since the parasitic capacitance of the semiconductor device 1 can be reduced, the high-speed switching operation, high-frequency operation, and the like, which are the characteristics of the nitride semiconductor device, can be satisfactorily exhibited. This effect can be demonstrated, for example, with reference to FIG.

FIG. 13 is a diagram showing an evaluation result of parasitic capacitance. In FIG. 13, the solid line shows the change in each parasitic capacitance of the semiconductor device 1 including the source field plate (SFP) 8, and the broken line shows the gate field plate (GFP) instead of the source field plate 8. It shows the change of each parasitic capacitance of the semiconductor device.
According to FIG. 13, in the SFP structure, the source field plate 8 at the source potential and the two-dimensional electron gas 26 at the drain potential face each other (see FIG. 3), so that Cass (= Cds + Cgd) is generated in the low voltage region. Although it tends to be larger, it can be seen that the capacitance can be reduced as compared with the GFP structure when judged by the total parasitic capacitance including Ciss (= Cgs + Cgd) and Crss (= Cgd).

Although the embodiments of the present invention have been described above, the present invention can also be implemented in other embodiments.
For example, the semiconductor device 61 shown in FIG. 14 has a recess 53 instead of the oxide film 27 as a structure for realizing a normally-off type HEMT. The recess 53 may be formed so as to penetrate the electron supply layer 25 and reach the surface layer portion of the electron traveling layer 24, for example, by selectively etching only the bottom portion of the gate opening 32. The recess 53 prevents the formation of a heterojunction between the electron traveling layer 24 and the electron supply layer 25 immediately below the gate electrode 4. As a result, when the gate bias is not applied (at the time of zero bias), the two-dimensional electron gas 26 is not formed in the region directly under the gate bias, so that a normally-off type HEMT can be realized.

Further, the semiconductor device 1 does not have to include the sidewall 35. _{In this case, the distance LGF} between the gate electrode 4 and the source field plate 8 can be controlled based on the thickness of only the gate insulating film 33.
Further, the semiconductor device 1 does not have to include the floating plate 9 between the source and the gate. That is, the field plate (source field plate 8) may be selectively provided only in the latter of the source-gate section and the gate-drain section. In such a configuration, for example, at the time of etching shown in FIG. 5H, the etching region may be set as a region straddling the inside and outside of the end portion of the plate film 6.

In addition, various design changes can be made within the scope of the matters described in the claims.

1 Semiconductor device 2 Group III nitride semiconductor laminated structure 3 Drain electrode 4 Gate electrode 5 Source electrode 6 Plate film 7 Element structure 8 Source field plate 9 Floating plate 10 Active region 11 Non-active region 12 (Source electrode) Base 13 (Source) Electrode) Electrode 21 (Source field plate) Base 23 Source contact 24 Electron traveling layer 25 Electron supply layer 26 Two-dimensional electron gas 27 Oxide film 28 Base layer 29 Insulation layer 30 First layer 31 Second layer 32 Gate opening 33 Gate Insulation film 34 Overlap part 35 Sidewall 41 Ohmic electrode 42 Ohmic electrode 43 Pad electrode 44 Pad electrode 45 Plate film 47 Insulation film 49 Upper layer film 50 Protruding part 53 Recess 54 (Source field plate) Electrode part 61 Semiconductor device

Claims (16)

Group III nitride semiconductor laminated structure including heterojunction,
The gate electrode arranged on the group III nitride semiconductor laminated structure and
The insulating layer on the group III nitride semiconductor laminated structure and
A source electrode and a drain electrode arranged apart from the gate electrode so as to sandwich the gate electrode and electrically connected to the group III nitride semiconductor laminated structure, respectively.
A conductive layer embedded in the insulating layer between the gate electrode and the drain electrode and electrically connected to the source electrode.
An insulating region formed between the gate electrode and the conductive layer and formed in a cross section in a direction perpendicular to both side walls of the gate electrode.
A second conductive layer embedded in the insulating layer between the gate electrode and the source electrode and insulated from the source electrode is included.
The second conductive layer is a semiconductor device formed in an arch shape having a base portion and a pair of electrode portions extending from both ends of the base portion in a plan view. The semiconductor device according to claim 1 , wherein the second conductive layer is insulated from the gate electrode. The semiconductor device according to claim 1 or 2 , wherein the second conductive layer is floating. The first insulating film and the second insulating film formed under the gate electrode are included.
The semiconductor device according to any one of claims 1 to 3 , wherein the first insulating film is made of a material different from that of the second insulating film. The semiconductor device according to any one of claims 1 to 4 , wherein the conductive layer is formed in an arch shape having a base portion and a pair of electrode portions extending from both ends of the base portion in a plan view. The group III nitride semiconductor laminated structure includes an active region and a non-active region outside the active region.
The semiconductor device according to claim 5 , wherein the base portion of the conductive layer overlaps a part of the source electrode in a plan view in the non-active region. The semiconductor device according to claim 6 , wherein the source electrode and the conductive layer are electrically connected to each other via a source contact. The source electrode is formed on the insulating layer, and the source electrode is formed on the insulating layer.
The semiconductor device according to claim 7 , wherein the source contact is embedded in the insulating layer to connect the source electrode and the conductive layer. The group III nitride semiconductor laminated structure includes an active region and a non-active region outside the active region.
The semiconductor device according to any one of claims 1 to 3, wherein the pair of electrode portions of the second conductive layer are connected to the base portion in the non-active region. The semiconductor device according to claim 9 , wherein the pair of electrode portions straddle between the active region and the non-active region. The group III nitride semiconductor laminated structure includes an active region, a non-active region outside the active region, and an element separation line for separating the active region.
In a plan view, the conductive layer is connected to a first base portion, a pair of first electrode portions extending from both ends of the first base portion, and the first electrode portion to the first base portion. It has a first connection end that is a part,
In a plan view, the second conductive layer has a second base portion, a pair of second electrode portions extending from both ends of the second base portion, and the second electrode portion connected to the second base portion. Has a second connection end, which is the part to be
The semiconductor device according to any one of claims 1 to 3 , wherein the first connection end is provided at substantially the same position as the second connection end with reference to the element separation line. The semiconductor device according to any one of claims 1 to 11 , further comprising an insulating sidewall formed between the gate electrode and the conductive layer. The semiconductor device according to claim 12 , wherein the sidewall contains at least one material selected from the group consisting of _{SiO 2, SiN and SiON.} The semiconductor device according to any one of claims 1 to 13 _{, wherein the distance LGF} between the gate electrode and the conductive layer is 1 μm or less. The semiconductor device according to any one of claims 1 to 14 , wherein the length L _{FP of the conductive layer and the distance L GD} between the gate electrode and the drain electrode _{satisfy L FP} <1/3 L _GD. .. The semiconductor device according to claim 12 or 13 , comprising an insulating second sidewall formed between the gate electrode and the second conductive layer.

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