JP6834557B2 - Cross current suppression controller - Google Patents

Description

The present invention relates to a power conversion circuit in which units of multi-level inverters based on a flying capacitor (hereinafter referred to as FC) method are connected in parallel, and relates to equalization of current responsibilities of each inverter unit.

Patent Document 1 discloses an example of an FC type three-level inverter. FIG. 13 is an example of a power conversion circuit in which a plurality of these are connected in parallel. (Patent Document 1 shows a configuration of a three-phase inverter. On the other hand, FIG. 13 shows a configuration including a representative one-phase switching device and a flying capacitor. Therefore, the actual configuration of FIG. 13 is shown. In the configuration, three-phase output or single-phase output inverters are connected in parallel as in Patent Document 1.)
Table 1 shows the switching pattern of the FC type 3-level inverter. When outputting a zero voltage, the FC is made conductive by turning on the switching devices TN1 and TN3 or turning on the switching devices TN2 and TN4.

The output voltage in Table 1 is a voltage with the potential at the midpoint of the VDC as a reference point, with VDC = 2E and VfC1 = VfC2 = VfC3 = E in FIG.

As shown in FIG. 13, when a plurality of such inverter units are connected in parallel to cope with an increase in the capacity of the power conversion circuit, if there is an individual difference in the inverter units, a difference in output current occurs between the units and a cross current occurs. Current is generated and the current responsibility varies. As a result, heat generation is concentrated on a specific inverter unit and the life is shortened, and in some cases, overcurrent or overheating causes an abnormality in the switching element.

As a countermeasure, there is a method of connecting a cross flow suppression reactor Lu to each inverter unit, but new problems such as an increase in cost, weight, and loss occur. In order to solve this problem, a method of suppressing the cross flow by controlling the cross flow suppression reactor Lu as small as possible is being studied.

Patent Document 2 is a method of suppressing cross current by adjusting the gate timing (timing of an on / off signal) of a switching device. This method is characterized in that it operates so as to detect only the cross current at the apex of the carrier and make it zero. In order for this method to work properly, the following conditions are required.
(1) The frequency of the fundamental wave is sufficiently smaller than the frequency of the carrier triangle wave, and the carrier apex is substantially equal to the center of one pulse of the output voltage.
(2) During the conduction period of the switching element, the current change has a constant inclination as shown in FIG. 3 of Patent Document 2.

If the above conditions are satisfied, the cross current of the carrier apex becomes almost equal to the mean cross current of one pulse of the output current, and if the cross current of the carrier apex is set to zero, the average cross current of one pulse of the output current also becomes zero. it can.

Patent Document 2 assumes application to an inverter having a low number of levels such as 2 levels and 3 levels not equipped with FC, and further assumes a case where the frequency of the carrier triangular wave is sufficiently higher than that of the fundamental wave. Further, it is assumed that the largest factor that changes the current during the conduction period of the switching element is the voltage drop deviation of the element. The above assumed conditions can be applied without any problem because the conditions for correctly operating the method of Patent Document 2 are satisfied. Patent Document 2 discloses the circuit shown in FIG. 14 as a cross current suppression control device for a power conversion circuit.

Japanese Unexamined Patent Publication No. 2008-92651 Patent No. 5979253 Patent No. 3301761 Japanese Patent Application No. 2016-151687

If the method of Patent Document 2 is applied to the FC inverter as it is, the cross current may increase. The cause is, for example, that when the switching devices T11, T13, T21, T23, TN1 and TN3 are turned on to output zero voltage in FIG. 13, the FC of each inverter unit is connected in parallel via the cross current suppression reactor Lu, and is connected to the FC. This is because a resonance circuit is formed between the cross flow suppression inverter Lu, and the resonance current is superimposed on the cross flow current.

In addition, the condition "the current change during the conduction period of the switching element has a constant inclination", which is a necessary condition for the method of Patent Document 2 to operate correctly due to resonance, is not satisfied, and the method of Patent Document 2 malfunctions. Is also the cause.

FIG. 15 shows an example of malfunction. Here, for simplification, it is assumed that the inverter units are in parallel, the output currents Iinv1 and Iinv2 are positive, the characteristics of each switching device are the same, the switching timing is the same, and the voltage drop is also the same.

Since the output currents Iinv1 and the output currents Iinv2 are equal before the first intersection 1 of the voltage command value Vref and the carrier triangle wave, the timing adjustment is not performed at the intersection 1, and the switching devices T11 and T22 are turned off at the same timing. Therefore, the output current Iinv1 immediately after the intersection 1 and the output current Iinv2 are equal. However, the switching devices T11 and T21 are turned on, and the antiparallel diodes of the switching devices T13 and T23 are turned on to form a resonance circuit. For example, the output currents Iinv1 and Iinv2 change by drawing a curve as shown in FIG.

Since Iinv1> Iinv2 at the carrier apex 2, the method of Patent Document 2 delays the turn-on of the switching device T12 by the proportional amplifier and advances the turn-on of the switching device T22, thereby decreasing the output current Iinv1 and increasing the output current Iinv2. To urge. However, at the intersection 3 of the voltage command value Vref and the carrier triangle wave, the magnitude relationship between the output current Iinv1 and the output current Iinv2 is switched due to resonance, and as a result of the correction of the proportional amplifier, the difference between the output current Iinv1 and the output current Iinv2 (cross current). ) Will increase.

After that, the switching devices T11, T12, T21, and T22 are turned on, and the FC is disconnected. Therefore, resonance does not occur between the intersection 3 and the intersection 5. The proportional amplifier P detects the current at the carrier apex 4, delays the turn-off of the switching device T12, and accelerates the turn-off of the switching device T22, so that the cross current immediately after the intersection 5 can be completely suppressed.

However, resonance occurs again after the intersection 5. Since the output current Iinv1 and the output current Iinv2 are equal at the carrier apex 6, the timing adjustment by the proportional amplifier P is not performed in the switching at the intersection 7, but only the adjustment by the integrating amplifier I is performed.

The integrating amplifier I detects the cross current at the carrier apex 4, and makes a false judgment contrary to the assumption that the cause of the increase in the cross current is that the turn ON timing of the switching device T12 is too late and the turn ON timing of the switching device T22 is too early. Raise, advance the turn ON timing of the switching device T12 at the intersection 7, and delay the turn ON timing of the switching device T22. As a result, an increase in the output current Iinv1 and a decrease in the output current Iinv2 are promoted, and the cross current becomes even larger.

As a countermeasure, as shown in Patent Document 4, if the resonance frequency between the FC and the cross current suppression reactor is made sufficiently lower than the carrier frequency and the voltage command value is adjusted so that the switching interval is not lengthened, the cross current due to resonance is generated. The change in is small, and the method of Patent Document 2 can be applied.

However, in order to lower the resonance frequency, it is necessary to increase the capacity and reactor of the FC, which increases the weight, volume, and cost of the device. Further, when the carrier frequency is increased, the switching loss increases, which causes problems such as a decrease in efficiency and an increase in weight and cost due to an increase in the cooling mechanism.

As another measure, it is also effective to make the FC voltage of each inverter unit uniform and suppress the occurrence of resonance. For that purpose, if the capacities of the FCs are equal, the FC passing currents may be made equal, and this can be achieved by controlling the cross current to zero. However, if there is a difference in FC capacitance due to manufacturing error, aging, temperature change, etc., even if the cross current can be controlled to zero, the FC voltage will differ and resonance will occur.

Further, as shown in FIG. 16, it is also conceivable to connect the FCs of each inverter unit with a conducting wire to share the FC potential. In this case, some switching devices (T11 and T21, T14 and T24) are connected in parallel. At this time, in order to reduce the transient difference in the element passing current, the length and shape of the lead wire of each switching device must be made uniform, and the inductance parasitic on the lead wire must be made as equal as possible.

In addition, as the number of inverter levels increases, the circuit configuration becomes complicated and must be realized with a limited volume, which makes the design of the main circuit extremely difficult. Further, in order to reduce the steady difference in passing current, it is necessary to select a switching device to be connected in parallel so that the forward voltage drop Vce (sat) and the reverse voltage drop Vf are equal.

From the above, it is an issue to suppress the cross current in the cross current suppression control device of the power conversion circuit having the flying capacitor.

The present invention has been devised in view of the above-mentioned conventional problems, and one aspect thereof is a cross current suppression control device that suppresses a cross current in a power conversion circuit in which two or more inverter units are connected in parallel to a DC voltage source. The inverter unit is connected between the first to fourth switching devices sequentially connected in series, the common connection point of the first and second switching devices, and the common connection point of the third and fourth switching devices. The cross-flow current suppression control device has a flying capacitor inserted in the above, and the first and fourth switchings generated by the PWM modulator and the FC voltage controller for the rising gate delay command value of a fixed value. The first rise delay adder that adds the first gate command value that turns the device on and off, and the second and third riser gate delay command values that have a fixed value generated by the PWM modulator and FC voltage controller. A second rise delay adder that adds a second gate command value that turns on / off the switching device, and a first fall delay adder that adds a fixed value fall gate delay command value to the first gate command value. A second falling delay adder that adds a fixed value falling gate delay command value to the second gate command value is provided in the first inverter unit, and a cross current current command value is added to the inverter unit output current command value. A proportional amplifier that multiplies the gain by subtracting the output current detection value of its own inverter unit from the value obtained by adding the cross current, and after inputting the cross current and changing the first gate command value from 0 to 1. The first integrating amplifier that operates when the sign of the inverter unit output current command value is positive, and the inverter unit output after the cross current is input and the first gate command value changes from 0 to 1. The second integrating amplifier that operates when the sign of the current command value is negative, and after the cross current is input and the first gate command value changes from 1 to 0, and the sign of the inverter unit output current command value is A third integrating amplifier that operates when it is positive, and a third that operates when the cross current is input and the first gate command value changes from 1 to 0, and when the sign of the inverter unit output current command value is negative. The four integrating amplifiers, the fifth integrating amplifier that operates after the cross current is input and the second gate command value changes from 0 to 1, and when the sign of the inverter unit output current command value is positive, and the above. After inputting the cross current and changing the second gate command value from 0 to 1, , The sixth integrating amplifier that operates when the sign of the inverter unit output current command value is negative, and after the second gate command value changes from 1 to 0 by inputting the cross current, and the inverter unit output current. The 7th integrating amplifier that operates when the sign of the command value is positive, and after the cross current is input and the 2nd gate command value changes from 1 to 0, and the sign of the inverter unit output current command value is negative. When the sign of the output current command value of the inverter unit is positive, the output of the proportional amplifier and the output of the first integrating amplifier are added and multiplied by -1. The value is set as the gate delay command value at the first rising edge, and when the sign of the inverter unit output current command value is negative, the value obtained by adding the output of the proportional amplifier and the output of the second integrating amplifier and multiplying by -1 is obtained. The gate delay command value for the first rise is defined as the gate delay command value for the second rise, which is the sum of the output of the proportional amplifier and the output of the third integrating amplifier when the sign of the inverter unit output current command value is positive. When the sign of the inverter unit output current command value is negative, the value obtained by adding the output of the proportional amplifier and the output of the fourth integrating amplifier is used as the second rising gate delay command value, and the inverter unit output current command is used. When the sign of the value is positive, the value obtained by adding the output of the proportional amplifier and the output of the fifth integrating amplifier and multiplying by -1 is used as the first falling gate delay command value, and the inverter unit output current command value. When the sign of is negative, the value obtained by adding the output of the proportional amplifier and the output of the sixth integrating amplifier and multiplying by -1 is used as the first falling gate delay command value, and the output current command value of the inverter unit. When the sign is positive, the value obtained by adding the output of the proportional amplifier and the output of the 7th integrating amplifier is used as the gate delay command value for the second falling edge, and when the sign of the inverter unit output current command value is negative, the proportional value is used. The gate delay command value calculation unit that outputs the sum of the output of the amplifier and the output of the eighth integrating amplifier as the second falling gate delay command value, and the first rising gate delay command value are the first. A third rise delay adder for adding the gate command value, a fourth rise delay adder for adding the second rise gate delay command value to the second gate command value, and the first fall gate delay command. The third falling delay adder that adds a value to the first gate command value and the second falling gate delay command value are added. It is characterized in that a fourth fall delay adder to be added to the second gate command value is provided in each of the second to N (an integer of N = 2 or more) inverter unit.

Further, as one aspect thereof, when the absolute value of the output current command value of the inverter unit is equal to or less than the threshold value, the update of the first to eighth integrating amplifiers is stopped.

Further, as one aspect thereof, the inverter unit output current command value is a value obtained by dividing the total value of the output current detection values of all the inverter units by the number of the inverter units.

Further, as one aspect thereof, the inverter unit output current command value is set to the output current detection value of the first inverter unit.

Further, as one aspect thereof, it is characterized in that the cross current command value = 0 in all the inverter units.

Further, as another embodiment, a first exclusive logical sum element that outputs 1 when both the first gate command value and the second gate command value are the same, and an output signal of the first exclusive logical sum element. A delay adder that delays only the fall for a predetermined time, a subtractor that calculates the deviation between the voltage detection signal of the flying capacitor of the first inverter unit and the voltage detection signal of the flying capacitor of the second to Nth inverter units, and the delay addition. The first switch that outputs the output of the subtractor if the output of the device is 1, and outputs 0 if the output of the delay multiplier is 0, and the code detector that detects the code of the output current command value of the inverter unit. The multiplier that outputs 1 if the voltage detection signal of the flying capacitor of the first inverter unit is larger than 1/2 of the voltage of the DC voltage source, and the code detector and the multiplier have the same output. When the output of the second exclusive logical sum element that outputs 1 and the output of the second exclusive logical sum element is 1, 1 is output, and if the output of the second exclusive logical sum element is 0, -1 is output. A second switch to output, a first multiplier that multiplies the outputs of the first switch and the second switch, and a second multiplier that multiplies the output of the first multiplier by the inverse of the capacitance of the flying capacitor. A third multiplier that multiplies the output of the second multiplier by the inverse of the duty ratio of the zero voltage output, and a limiter that sets upper and lower limits on the output of the third multiplier are provided, and the output of the limiter is the output of the limiter. It is characterized in that it is a cross current current command value.

Further, as another embodiment, if the voltage detection signal of the code detector for detecting the sign of the output current command value of the inverter unit and the flying capacitor of the first inverter unit is larger than 1/2 of the voltage of the DC voltage source. A comparer that outputs 1, an exclusive logic sum element that outputs 1 when both the sign detector and the comparer have the same output, and an exclusive logic sum element that outputs 1 if the output of the exclusive logic sum element is 1. The first switch that outputs -1 if the output of the exclusive logical sum element is 0, and the first that calculates the deviation between the voltage detection signal of the first inverter unit and the voltage detection signal of the second to Nth inverter units. A subtractor, a buffer that stores the output of the first subtractor one calculation cycle before, a second subtractor that subtracts the output of the buffer from the output of the first subtractor, and an output of the second subtractor. A first multiplier that multiplies the output of the switch, an integrator that integrates the output of the first multiplier, and a second multiplier that multiplies the output of the integrator by the output current command value of the inverter unit. The present invention is characterized in that the output of the second multiplier is set to the cross current current command value.

Further, as another embodiment, if the voltage detection signal of the code detector for detecting the code of the output current command value of the inverter unit and the flying capacitor of the first inverter unit is larger than 1/2 of the voltage of the DC voltage source. If the output of the comparer that outputs 1 and the output of the second exclusive logic sum element that outputs 1 when the outputs of the code detector and the comparer are the same and the output of the second exclusive logic sum element is 1. A second switch that outputs 1 and outputs -1 if the output of the second exclusive logical sum element is 0, a voltage detection signal of the first inverter unit, and a voltage detection signal of the second to Nth inverter units. A first subtractor that calculates the deviation between the above, a buffer that stores the output of the first subtractor one calculation cycle before, and a second subtractor that subtracts the output of the buffer from the output of the first subtractor. A first multiplier that multiplies the output of the second subtractor by the output of the second switch, an integrator that integrates the output of the first multiplier, and an inverter unit output current command for the output of the integrator. A second multiplier that multiplies the values, and outputs 1 when both the gate command value for turning on / off the first and fourth switching devices and the gate command value for turning on / off the second and third switching devices are the same. 1 Exclusive logic sum element, a delay adder that delays the output signal of the first exclusive logic sum element by a predetermined time by a falling edge, and if the output of the delay adder is 1, the output of the second multiplier is output. A first switch that outputs 0 if the output of the delay adder is 0 is provided, and the output of the first switch is used as the cross current command value.

Further, as another embodiment, if the voltage detection signal of the code detector for detecting the code of the output current command value of the inverter unit and the flying capacitor of the first inverter unit is larger than 1/2 of the voltage of the DC voltage source. If the output of the comparer that outputs 1 and the output of the second exclusive logic sum element that outputs 1 when both the output of the code detector and the comparer are the same, and the output of the second exclusive logic sum element are 1. A second switch that outputs 1 and outputs -1 if the output of the second exclusive logic sum element is 0, a voltage detection signal of the first inverter unit, and a voltage detection signal of the second to Nth inverter units. A first subtractor that calculates the deviation of the first subtractor, a buffer that stores the output of the first subtractor one calculation cycle before, and a second subtractor that subtracts the output of the buffer from the output of the first subtractor. A first adder that multiplies the output of the second subtractor by the output of the second switch, an adder that integrates the output of the first adder, and the inverter unit output current command value on the output of the adder. The second multiplier that multiplies, and the gate command value that turns on / off the first and fourth switching devices and the gate command value that turns on / off the second and third switching devices are both the same, and 1 is output. 1 Exclusive logical sum element, a delay adder that delays the output signal of the first exclusive logical sum element by a predetermined time by a falling edge, and if the output of the delay adder is 1, the output of the first subtractor is output. Then, if the output of the delay adder is 0, the first switch that outputs 0, the third multiplier that multiplies the output of the first switch and the output of the second switch, and the output of the third multiplier. A fourth adder that multiplies the inverse of the capacitance of the flying capacitor, a fifth adder that multiplies the output of the fourth adder by the inverse of the duty ratio of the zero voltage output, and the output of the fifth adder. A limiter for providing a lower limit value and an adder for adding the output of the second multiplier and the output of the limiter are provided, and the output of the adder is used as a cross flow current command value.

According to the present invention, it is possible to suppress the cross current in the cross current suppression control device of the power conversion circuit having a flying capacitor.

The block diagram which shows the cross current suppression control device in Embodiment 1. FIG. The block diagram which shows the structure of the FC voltage controller in Embodiment 1. FIG. The time chart which shows the suppression operation of the cross current in Embodiment 1. FIG. The block diagram which shows the cross current command value calculation part in Embodiment 2. The block diagram which shows an example of the cross current command value calculation part in Embodiment 3. FIG. The block diagram which shows another example of the cross current command value calculation part in Embodiment 3. FIG. The block diagram which shows the cross current command value calculation part in Embodiment 4. The block diagram which shows the kth cross flow current suppression control device at the time of expanding the inverter unit of Embodiment 1 to N units. The block diagram which shows the kth cross current command value calculation part when the inverter unit of Embodiment 2 is expanded to N units. FIG. 3 is a block diagram showing an example of a gate delay command value calculation unit for the kth unit when the inverter unit of the third embodiment is expanded to N units. FIG. 6 is a block diagram showing another example of the kth gate delay command value calculation unit when the inverter unit of the third embodiment is expanded to N units. The block diagram which shows the kth gate delay command value calculation part when the inverter unit of Embodiment 4 is expanded to N units. The figure which shows the power conversion circuit in Embodiment 1. FIG. The block diagram which shows the conventional cross current suppression control device. A time chart showing an example of the operation of a conventional cross current suppression control device. The figure which shows another example of the conventional power conversion circuit.

Hereinafter, embodiments 1 to 4 of the cross current suppression control device according to the present invention will be described in detail with reference to FIGS. 1 to 13.

[Embodiment 1]
The first embodiment suppresses the cross current of the power conversion circuit shown in FIG. In FIG. 13, N inverter units are connected in parallel to the DC voltage source Vdc, but in the first embodiment, it is assumed that two inverter units are connected in parallel to the DC voltage source Vdc.

Each inverter unit is located between the first to fourth switching devices sequentially connected in series to the DC voltage source Vdc, the common connection point of the first and second switching devices, and the common connection point of the third and fourth switching devices. FC is inserted in.

One end of the cross flow suppression reactor Lu is connected to the common connection point of the second and third switching devices. On the other end side of the cross flow suppression reactor Lu, a current detector for detecting the output currents Iinv1 and Iinv2 of each inverter unit is provided. Further, the other ends of the cross flow suppression reactor Lu of each inverter unit are connected to each other, and a cross flow suppression reactor Lu and a current detector for detecting the total value Iinv of the output current of the inverter unit are provided at the connection point. Has been done.

FIG. 1 shows the cross current suppression control device of the first embodiment. The cross-flow current suppression control device of the first embodiment has a configuration per phase in which the second inverter unit is controlled.

The PWM modulator 1 generates gate signals Gref1'and Gref2'by comparing the voltage command value Vref with the amplitude of the carrier triangle wave. The voltage command value Vref is given by feedforward, or may be given as an output of current control or voltage control calculated by a control unit of an inverter unit (not shown). The carrier triangle wave is output from a control unit of an inverter unit (not shown).

The FC voltage controller 2 is a gate command capable of controlling the FC voltage based on the obtained gate signals Gref1'and Gref2', the FC voltage detection signal VFC1 of the first inverter unit, and the output current Iinv1 of the first inverter unit. Convert to the values Gref1 and Gref2.

The gate command value Gref1 means that the switching devices T11 and T21 are turned on and the switching devices T14 and T24 are turned off at 1. The gate command value Gref2 means that the switching devices T12 and T22 are turned on and the switching devices T13 and T23 are turned off at 1.

The delay command value TD is a fixed value, and the gate command values Gref1 and Gref2 output to the first inverter unit are delayed by the value specified by the delay command value TD. Normally, the delay command value TD specifies a value of about 1/10 to 1/4 of the dead time of the switching device. The delay adder Delay U1 delays the rise of the gate command value Gref1 by the delay command value TD. The delay adder DelayD1 delays the fall of the gate command value Gref1 by the delay command value TD. The delay adder Delay U2 delays the rise of the gate command value Gref2 by the delay command value TD. The delay adder DelayD2 delays the fall of the gate command value Gref2 by the delay command value TD.

The dead time processors 3c and 3d add a dead time to the outputs of the delay adders DelayD1 and DelayD2, and output the gate signals of the switching devices T11, T12, T13, and T14.

The gate command values Gref1 and Gref2 are output to the gate delay command value calculation unit 4, and the delay command values DrefU1, DrefU2, DrefD1 and DrefD2 are output from the gate delay command value calculation unit 4.

The delay adder DelayU3 delays the rise of the gate command value Gref1 by the delay command value DrefU1. The delay adder DelayD3 delays the fall of the gate command value Gref1 by the delay command value DrefD1.

The dead time processor 3a adds a dead time to the output of the delay adder DelayD3, and outputs the gate signals of the switching devices T21 and T24.

The delay adder DelayU4 delays the rise of the gate command value Gref2 by the delay command value DrefU2. The delay adder DelayD4 delays the fall of the gate command value Gref2 by the delay command value Dref2.

The dead time processor 3b adds a dead time to the output of the delay adder DelayD4 and outputs the gate signals of the switching devices T22 and T23. The gate signals output by the dead time processors 3a to 3d are sent to the corresponding switching devices. Entered.

The gate delay command value calculation unit 4 is composed of the following.

The inverter unit output current command value is a signal Iinv / N obtained by dividing the detection signal of the output current Iinv1 of the first inverter unit or the detection signal of the total value Iinv of the output currents of each inverter unit by the number of parallel units N.

The absolute value converter ABS outputs the absolute value of the inverter unit output current command value. The comparator 5 determines whether or not the absolute value of the inverter unit output current command value exceeds the threshold value Is. The switch SW9 closes when the absolute value of the inverter unit output current command value exceeds the threshold value Is.

The sign detector 6 detects the sign of the inverter unit output current command value, and outputs 1 if it is positive and 0 if it is negative. The output of the code detector 6 is input to the switches SW11, SW12, SW31, SW32, SW51, SW52, SW71, SW72.

Further, the output of the code detector 6 is input to the switches SW21, SW22, SW41, SW42, SW61, SW62, SW81, SW82 after the logic is inverted by the NOT circuits 7a to 7d.

The adder 8 calculates the sum of the inverter unit output current command value and the cross current current command value. In the first embodiment, the cross current current command value is fixed at zero. The subtractor 9 subtracts the detection signal of the output current Iinv2 of the second inverter unit, which is the control target unit, from the output of the adder 8 and outputs the deviation. The low-pass filter LPF removes noise of high frequency components from the deviation. The output of the low-pass filter LPF is input to the proportional amplifier P and the switch SW9.

In the proportional amplifier P, the output of the low-pass filter LPF is proportionally calculated and output.

The configurations of the integrating amplifiers I1 and I2 are shown below. The output of the switch SW9 is input to the switches SW11 and SW21. The switch SW11 is closed if the sign of the inverter unit output current command value is positive. The switch SW21 is closed if the sign of the inverter unit output current command value is negative. The output of the switch SW11 is input to the integrating amplifier I1.

The switch SW12 is connected to the output of the integrator amplifier I1, and the switch SW12 is closed if the sign of the inverter unit output current command value is positive. The output of the switch SW21 is input to the integrating amplifier I2. The switch SW22 is connected to the output of the integrator amplifier I2, and the SW22 is closed if the sign of the unit output current command value is negative.

The outputs of the switches SW12 and SW22 are input to the adder 10a together with the output of the proportional amplifier P and added. The output of the adder 10a is multiplied by -1 to become the rising delay command value DrefU1 of the gate command value Gref1, which is input to the delay adder DelayU3.

The operation timing of the integrating amplifiers I1 and I2 is shown. The circuit that determines the timing is composed of the following.

The buffer Z-1 causes a delay of one calculation time for the gate command value Gref1. The AND element 11a calculates the logical sum of the gate command value Gref1 and the logical negation of the signal one calculation time before the gate command value Gref1, and when the gate command value Gref1 changes from 0 to 1, one calculation time Only 1 is output.

The delay adder 12a delays the output signal of the AND element 11a. The delay amount usually specifies dead time + TD to dead time x 2 + TD. The delay command value TD is a fixed value. The reason why the delay amount is set to (dead time + TD to dead time x 2 + TD) will be described later. The integrating amplifiers I1 and I2 operate according to the output of the delay adder 12a.

From the above, the integrator amplifiers I1 and I2 operate only once after the time (dead time + TD to dead time × 2 + TD) set by the delay adder elapses after the gate command value Gref1 changes from 0 to 1. ~ I8 has the same configuration. However, the following points are different.

(Operating conditions)
-The integration amplifiers I1 and I2 operate after the gate command value Gref1 changes from 0 to 1.
-The integration amplifiers I3 and I4 operate after the gate command value Gref1 changes from 1 to 0.
-The integration amplifiers I5 and I6 operate after the gate command value Gref2 changes from 0 to 1.
-The integration amplifiers I7 and I8 operate after the gate command value Gref2 changes from 1 to 0.

(Handling after addition with proportional amplifier P output)
-The output of the integrating amplifiers I1 and I2 is added to the output of the proportional amplifier P and then multiplied by -1 to obtain the delay command value DrefU1.
The output of the integrating amplifiers I3 and I4 is added to the output of the proportional amplifier P, and the delay command value DrefD1 is obtained as it is.
-The output of the integrating amplifiers I5 and I6 is added to the output of the proportional amplifier P and then multiplied by -1 to obtain the delay command value DrefU2.
-The outputs of the integrating amplifiers I7 and I8 are added to the outputs of the proportional amplifier P, and the delay command value DrefD2 is used as it is.

Patent Document 3 is an example of the FC voltage controller 2, and an example thereof is shown in FIG.

The comparator cmp1 determines whether or not the FC voltage detection signal VFC1 of the first inverter unit is larger than the FC voltage command value (1/2 of the voltage of the DC voltage source) Vdc / 2. The comparator cmp2 determines whether or not the output current Iinv1 is positive. The exclusive OR element XOR1 outputs a signal sel which becomes 1 when only one of the comparators cmp1 and cmp2 is 1.

The exclusive OR element XOR2 outputs 1 when either one of the gate signals Gref1'and Gref2' output from the PWM modulator 1 in the previous stage is 1. The hold device Hold outputs the signal sel as it is when both the gate signals Gref1'and Gref2'are 1 or both are 0, and outputs the previous output when only one of the gate signals Gref1'and Gref2' is 1. Hold.

The OR circuit OR1 outputs the OR of the gate signal Gref1'and the hold device Hold. The AND circuit AND1 outputs the logical product of the OR circuit OR1 and the gate signal Gref2'. The output of the AND circuit AND1 is the gate command value Gref1.

The OR circuit OR2 outputs the negative OR of the gate signal Gref1'and the output of the hold device Hold. The AND circuit AND2 outputs the logical product of the OR circuit OR2 and the gate signal Gref2'. The output of the AND circuit AND2 is the gate command value Gref2.

The PWM modulator 1 outputs the gate signals Gref1'and Gref2' based on the comparison between the voltage command value Vref and the carrier triangle wave.

(Explanation of action / operation)
The basic operation of the first embodiment is the same as the operation of the gate delay command value calculation unit 4 of the conventional method of Patent Document 2 shown in FIG. That is, the cross current is suppressed by detecting the cross current and adjusting the gate timing according to the magnitude of the cross current.

The proportional amplifier P detects the cross current just before switching, and adjusts the switching timing so that the cross current becomes zero at the next switching. The integrating amplifiers I1 to I8 detect the cross current after switching, estimate the individual difference of the switching device, learn the individual difference (characteristic variation of rise time and fall time) by the integration operation, and adjust the switching timing.

The first embodiment is intended to be applied to an FC type three-level inverter composed of four switching devices per phase. Therefore, as in the ninth embodiment of Patent Document 2, eight integrating amplifiers I1 to I8 are used in the control circuit per phase.

Next, the operation of each amplifier will be described.

[Gate timing adjustment by proportional amplifier P]
The deviation between the inverter unit output current command value and the output current Iinv2, that is, the cross current is input to the proportional amplifier via the low-pass filter LPF, and the gained value is output as the delay command value of the gate command value. When the cross current is positive, the output current Iinv2 is smaller than the command value.

At this time, the rise delay command values DrefU1 and DrefU2 become negative values, the rise of the gate command value is corrected for advancement, and the fall delay command values DrefD1 and DrefD2 become positive values, and the gate command value falls. Is corrected for delay. As a result, the period for which the inverter unit 2 outputs a positive voltage increases, so that the output current Iinv2 is promoted to increase. On the contrary, when the cross current is negative, the output current Iinv2 is reduced.

In the conventional method of FIG. 14, a hold function for storing the cross current at the carrier apex is arranged in front of the proportional amplifier P, and the delay command value output by the proportional amplifier P is obtained based on the cross current at the carrier apex. However, the gate command value delay control unit 4 of the first embodiment does not have the hold function.

Therefore, the delay command value output from the proportional amplifier P at the moment of switching is a value that reflects the cross current immediately before switching.

The operation of the proportional amplifier P according to the first embodiment is shown in FIG. Taking the intersection 3 as an example, in the first embodiment, since the delay command value is calculated based on the cross current immediately before switching, Iinv1 <Iinv2 (that is, negative cross current) is detected and the turn of the switching device T22. ON is delayed, an increase in the output current Iinv1 and a decrease in the output current Iinv2 are promoted, and the cross current can be reduced. On the other hand, in the configuration of Patent Document 2, the transverse current is increased as described above and shown in FIG.

[Gate timing adjustment by integration amplifier I1]
The cross current is input to the amplifier I1 via the low-pass filter LPF, gain is applied, and the integrated value is output as the delay command value of the gate. Since the front and rear switches SW11 and SW12 are closed when the sign of the output current Iinv1 is positive, the amplifier I1 integrates only when the output current sign is positive and outputs a command value.

The operation timing of the integrator amplifier I1 is after the gate command value Gref1 rises, and the output delay command value becomes DrefU1 and is reflected in the rise of the gate command value Gref1. When the gate command value Gref1 rises, the switching device T21 changes to ON and the switching device T24 changes to OFF. When the current code is positive, the current passes through the antiparallel diode of the switching device T24, so that the current path does not change even if the switching device T24 switches. The integrator amplifier I1 is in charge of adjusting the turn ON timing of the switching device T21.

[Gate timing adjustment by integration amplifier I2]
The condition for closing the switches SW21 and SW22 before and after the integrating amplifier I2 is that the sign of the output current Iinv1 is negative, unlike the integrating amplifier I1. At this time, the current passes through the antiparallel diode of the switching device T21. The integrator amplifier I2 is in charge of adjusting the turn-off timing of the switching device T24.

[Gate timing adjustment by integration amplifier I3]
The conditions for closing the switches SW31 and SW32 are the same as those of the amplifier I1 (switches SW11 and SW12). However, the operation timing is after the fall of the gate command value Gref1, and the output delay command value becomes DrefD1 and is reflected in the fall of the gate command value Gref1. Therefore, the integrator amplifier I3 is in charge of adjusting the timing of turning off the switching device T21.

[Gate timing adjustment by integrating amplifier I4]
Similarly, the integrator amplifier I4 is in charge of timing adjustment of the switching device T24 turn ON.

[Integral amplifiers I5 to I8]
The charge of each integrating amplifier is shown below.
I5: T22 turn ON
I6: T23 turn OFF
I7: T22 turn OFF
I8: T23 turn ON
In the conventional method of FIG. 14, a carrier vertex signal is input as an operation trigger of the integrating amplifier, and the operation timing of the integrating amplifier is set as the carrier vertex. However, in the first embodiment, it is detected that the gate command values Gref1 and Gref2 have changed, and a delay is added to trigger the operation of the integration amplifier. Therefore, the integration operation timing is immediately after the gate command values Gref1 and Gref2 signals are changed. It becomes.

Taking FIG. 3 as an example, immediately after the intersection 3, the output current is positive and the switching devices T12 and T22 change from OFF to ON (that is, the gate command value Gref2 changes from 0 to 1), so that the integrating amplifier I5 Operate. Immediately after the intersection 3, there is a cross current that remains as a result of gate timing adjustment by the proportional amplifier P.

The reason why the cross flow current remains is that the turn ON of the switching device T22 is too fast compared to the turn ON of the switching device T12, and the integrating amplifier I5 stores this cross flow current. Then, at the intersection 7 where the switching devices T12 and T22 turn ON, a command for slightly delaying the turn ON of the switching device T22 is output to reduce the cross current.

In Patent Document 2, by detecting the cross current after waiting for a while after switching, not only the switching timing shift but also the amount caused by the voltage drop is superimposed on the detected cross current, and both the timing shift and the voltage drop shift are applied to the integrating amplifier. Let them learn and compensate collectively.

However, if there is FC, resonance is added as a cause of cross current generation during the non-switching period. Resonance is not caused by the characteristic deviation of the switching element, but by the FC voltage deviation, and the magnitude of the FC voltage deviation changes with each switching. Therefore, the flow of the resonance current also differs with each switching, and learning by the integrating amplifier can be performed. It malfunctions.

Therefore, in the first embodiment, by detecting the current immediately after switching and limiting the compensation target to the switching timing shift, it is possible to prevent the cross current due to resonance from being superimposed on the detection signal and suppress the learning malfunction.

Patent Document 1 describes the reason why the timing at which the integrating amplifier operates is set after a certain delay time has elapsed immediately after the change of the gate signal. Since it is not possible to advance the gate timing, the gate timing of the first inverter unit, which is the reference unit, is delayed by a fixed value TD, and the delay of the second inverter unit, which is the controlled unit, is made smaller than the TD. Is progressing.

Therefore, the actual switching is delayed by about TD from the change of the gate command values Gref1 and Gref2, so that it is necessary to delay the operation of the integrating amplifier by a fixed value TD. Further, considering that a dead time is included, the actual switching is further delayed by the dead time from the change of the gate command values Gref1 and Gref2. Therefore, in order to surely input the current after the switching is completed to the integrating amplifier, it is necessary to wait at least (dead time + TD) from the change of the gate command values Gref1 and Gref2.

Further, considering that the switching noise is superimposed on the current detection signal, the influence of the noise can be suppressed by additionally waiting the current detection for about 2 μs to the dead time until the noise is attenuated.

The switch SW9 will be described. The switch SW9 is opened when the absolute value of the output current is small, and the update of the integrating amplifier is stopped. This is the same operation as in the third embodiment of Patent Document 2. The reason for stopping the update of the integrating amplifier when the absolute value of the output current is small is the same as follows.
-To prevent the control circuit from malfunctioning because the offset may be superimposed on the current detector and the current code may not be detected correctly.
-If the absolute value of the output current is small, the cross current generated is limited, and even if it is not controlled, the effect on the thermal duty is small and there is no risk of the switching device being destroyed.

The FC voltage controller 2 will be described. Unlike the NPC type and T type, the FC type 3-level inverter has two patterns for outputting zero voltage: a pattern for turning on the switching devices T11 and T13 and a pattern for turning on the switching devices T12 and T14. It is known as in Patent Document 3 that the FC voltage can be controlled by selecting a switching pattern according to the code of the current.

For example, when the FC is to be charged, the switching devices T11 and T13 may be turned on if the output current is positive, and the switching devices T12 and T14 may be turned on if the output current is negative. An example of a block that realizes this control is shown in FIG. In this FC voltage controller 2, the FC voltage detection signal VFC1 is compared with Vdc / 2, which is 1/2 of the voltage of the DC voltage source, by the comparator cmp1, and the sign of the inverter unit output current command value Iinv1 is assigned by the comparator cmp2. It is detected and the signal sel is calculated by the exclusive logical sum element XOR1 circuit.

The signal sel thus obtained indicates that the switching devices T1 and T3 should be turned on if 1, and the switching devices T2 and T4 should be turned on if 0. The hold device Hold in the subsequent stage is an OR circuit OR1, OR2 while outputting a zero voltage with a gate signal Gref1'= 0, Gref2'= 1 (or Gref1'= 1, Gref2'= 0) in order to prevent an increase in the number of switchings. This is to prevent the signal sel'input to the input from changing.

After that, the gate command values Gref1 and Gref2 are generated by the OR circuits OR1, OR2, and the AND circuits AND1 and AND2. Table 2 shows the relationship between the magnitude of the voltage detection signal VFC1 and the sign of the inverter unit output current command value Iinv1 and the obtained gate command values Gref1, Gref2, and FC charge / discharge.

The advantage of the first embodiment is that even under the condition that the resonance current is generated by the FC, the cross current can be correctly suppressed without increasing the cross current by the control. Further, the resonance can be reset by surely setting the cross current to zero at each switching.

The first embodiment also has some disadvantages. Since the integrating amplifiers I1 to I8 compensate only for the difference in switching timing and do not compensate for the deviation of the voltage drop, the cross current due to the deviation of the voltage drop increases. In addition, since resonance cannot be suppressed during the period when switching is not performed, an increase in cross current may occur due to resonance. However, as compared with the method of Patent Document 2, the expansion of the resonance current can be suppressed, so that the cross current can be reduced.

In addition, as an effective item for suppressing the cross current in configuring the control block, it is mentioned that the switching pattern is common to all the inverter units. In the unit parallel configuration, the FC of each unit can be individually controlled by selecting the switching pattern at the time of zero voltage output for each inverter unit. However, the number of combinations of switching devices that switch at the same time increases, and cross-current current suppression control becomes difficult.

For example, consider a state in which two inverter units are arranged in parallel, the switching devices T11, T12, T21, and T22 are currently ON, and each of the two units is outputting a voltage of + Vdc / 2. In order to switch to zero voltage output in this state, the first inverter unit turns off the switching device T12 and turns on the switching device T13. If different switching patterns are allowed, the second inverter unit may turn off the switching device T21 and turn on the switching device T24 to switch to zero voltage output.

At this time, the switching device T21 needs to be timed with the switching device T12 instead of the switching device T11, and the switching device T24 must also be timed with the switching device T13 instead of the switching device T14.

In order to deal with this, it is necessary to prepare two integrator amplifiers, which are in charge of turning off the switching device T21, the integrator amplifier based on the switching device T11 and the integrator amplifier based on the T12, and switch according to the switching pattern. , The control circuit becomes complicated.

Further, after switching, a circuit in which the FC of the first inverter unit and the FC of the second inverter unit are connected in series via a cross current suppression reactor is connected in parallel to the DC voltage source.

At this time, if VFC1 + VFC2 ≠ Vdc is established, resonance will occur. If the switching pattern is the same, resonance can be suppressed if VFC1 = VFC2 can be realized. However, if different switching patterns are allowed, it is necessary to establish VFC1 + VFC2 = Vdc, which makes it difficult to realize.

In order to avoid the above problems, the switching pattern is common to all inverter units. In FIG. 1, only the detection value of the FC voltage detection signal VFC1 of the first inverter unit is input to the FC voltage controller 2, and the switching pattern is selected so that only the voltage detection signal VFC1 becomes Vdc / 2. .. The voltage detection signal VFC2 cannot be controlled by this control circuit.

However, when the voltage detection signal VFC1 and the voltage detection signal VFC2 are different, the difference between the voltage detection signal VFC1 and the voltage detection signal VFC2 becomes small because the resonance current flows at the time of zero voltage output. Therefore, even if the voltage detection signal VFC2 is not controlled, the voltage detection signal FC2 does not deviate significantly from Vdc / 2, and the inverter can continue operation without any problem.

Further, since the switching pattern is common to all the inverter units, the FC voltage can be detected by only one inverter unit, so that there is an advantage that the voltage detector can be reduced and the cost can be reduced.

As shown above, according to the first embodiment, the cross current immediately after switching can be set to zero. Further, even when resonance occurs between the FC and the cross flow suppression reactor, unlike the method of Patent Document 2, the control does not malfunction and the cross flow current can be reduced. Further, since the FC voltage can be detected by only one unit, the voltage detector can be reduced and the cost can be reduced.

[Embodiment 2]
FIG. 4 shows a cross current command value calculation unit of the second embodiment.

The gate command values Gref1 and Gref2 are input from the FC voltage controller 2 of FIG. 1 (Embodiment 1). The exclusive OR element XOR3 outputs 1 when both the gate command values Gref1 and Gref2 are the same.

The delay adder DelayD5 delays the output signal of the exclusive OR element XOR3 by a predetermined time by the falling edge.

The subtractor 13 subtracts the voltage detection signal VFC2 of the FC of the second inverter unit from the voltage detection signal VFC1 of the FC of the first inverter unit, and the voltage detection signal VFC1 of the FC of the first inverter unit and the FC of the second inverter unit. The deviation from the voltage detection signal VFC2 of The signal of the delay adder DelayD5 is input to the switch SWD, and if the input is 1, the switch SWD outputs the deviation between the FC voltage detection signal VFC1 of the first inverter unit and the FC voltage detection signal VFC2 of the second inverter unit. , If the input is 0, the comparator cmp1 that outputs 0 detects whether or not the voltage detection signal VFC1 of the FC of the first inverter unit exceeds Vdc / 2. The code detector 14 outputs 1 if the sign of the inverter unit output current command value (Iinv1 or Iinv / N) is positive, and outputs 0 if the sign is negative.

The exclusive OR element XOR4 outputs 1 as an FC control signal only when the outputs of the comparator comp1 and the code detector 14 are the same. This FC control signal represents a switching pattern at the time of zero voltage output required for bringing the voltage detection signal VFC1 of the FC of the first inverter unit closer to Vdc / 2.

The FC control signal indicates that if it is 1, the switching devices T11 and T13 are turned on, and if it is 0, the switching devices T12 and T14 are turned on. The switch SWE inputs an FC control signal, outputs 1 if the input is 1, and outputs -1 if the input is 0. The multiplier 15 calculates the product of the output signal of the switch SWD and the output signal of the switch SWE.

The multiplier 16 calculates the product of the output of the multiplier 15 and the reciprocal of the FC capacitance CFC. For the FC capacitance CFC here, the rated value described in the data sheet of the capacitor or the like is used. The multiplier 17 inputs the voltage command value Vref, obtains the duty ratio (1- | Vref |) of the zero voltage output, and calculates the product of this reciprocal and the output of the multiplier 16. Since division when calculating the duty ratio has a large calculation load, the product of 1 + | Vref | may be approximately obtained.

The limiter 18 prevents the multiplier output from becoming abnormally large when the absolute value of the voltage command value Vref is close to 1. That is, the limiter 18 sets an upper and lower limit value in the output of the multiplication value 17 so that the absolute value of the output of the multiplication value 17 is equal to or less than a predetermined value, and sets the output of the limiter 18 as the output. The output of the limiter 18 becomes a cross flow current command value, and is input to the gate command value delay control unit 4 of the first embodiment shown in FIG.

In the second embodiment, the voltage detection signal VFC2 of the FC of the second inverter unit, which is a function that cannot be realized in the first embodiment, is controlled by changing the cross current command value which was fixed to zero in the first embodiment. 1 Added the function to match the FC voltage detection signal VFC1 of the inverter unit.

First, the deviation between the FC voltage detection signal VFC1 of the first inverter unit and the FC voltage detection signal VFC2 of the second inverter unit is calculated. Next, the switch SWD is used to switch so that the zero voltage is output and the cross current command value is output only during the period when the current flows through the FC. A current flows through the FC only when either one of the gate command values Gref1 and Gref2 is 1, and the FC voltage can be controlled at this time.

Therefore, when both the gate command values Gref1 and Gref2 are 0 or 1, a cross current command value is generated, and the next switching promotes the generation of a cross current according to the command value. In the next switching, unless there is a steep and large fluctuation in the voltage command value, only one of the gate command values Gref1 and Gref2 is always switched, and a current flows through the FC.

On the contrary, if either one of the gate command values Gref1 and Gref2 is 1, the cross current command value is set to 0, the current does not flow to the FC, and the voltage detection signal VFC2 of the FC of the second inverter unit cannot be controlled. No extra cross current is applied in the next switching.

Further, the code is switched by the switch SWE according to the switching pattern. For example, consider a case where Vdc / 2> VFC1> VFC2 and the sign of the output current Iinv1 is positive, and a zero voltage is output in this state.

When the switching devices T11, T21, T13, and T23 are turned on, the voltage detection signal VFC1 of the FC of the first inverter unit is charged and can approach Vdc / 2. When the switching devices T12, T22, T14, and T24 are turned on, the voltage detection signal VFC1 of the FC of the first inverter unit is discharged, and conversely, it is separated from Vdc / 2.

In this way, charging / discharging is switched according to the switching pattern, so it is necessary to appropriately switch the sign of the cross current command value. In the previous example, since Vdc / 2> VFC1, in the next switching, the pattern in which the switching devices T11, T21, T13, and T23 are turned on by FC voltage control is always selected.

Therefore, the switch SWE is turned up and the cross current command value is output with the switching code as it is. Since VFC1> VFC2, the sign of the cross current command value becomes positive, the output current Iinv2 is promoted to increase, and the voltage detection signal VFC2 of the FC of the second inverter unit is charged more than the voltage detection signal VFC1 of the FC of the first inverter unit. The voltage detection signal VFC2 of the FC of the second inverter unit can be brought closer to the voltage detection signal VFC1 of the FC of the first inverter unit.

Then, 1 / CFC is applied to the deviation after adjusting the sign to obtain the current required for adjusting the voltage detection signal VFC2 of the FC of the second inverter unit. Then, the reciprocal of the duty ratio (1- | Vref |) is multiplied. If the voltage command value Vref is 0, a zero voltage is always output during one carrier cycle, and all the generated cross currents pass through the FC. However, for example, if Vref = 0.5, the period during which zero voltage is output for one carrier cycle is halved. Therefore, in order to make the voltage detection signal VFC2 of the FC of the second inverter unit the intended voltage, 2 It is necessary to pass twice the cross current. The above adjustment can be performed by multiplying the reciprocal of the duty ratio of the zero voltage output.

Finally, when the voltage command value Vref becomes a value close to 1 or -1, the command value is limited by the limiter 18 so that the cross current does not flow too much, and is output to the gate command value delay control unit 4.

The delay adder DelayD5 will be described.

The integrating amplifiers I1 to I8 of the first embodiment are operated after a dead time + TD of about has elapsed after switching. When the cross current command value returns to 0 at the timing when the integrating amplifiers I1 to I8 are operated, the integrating amplifiers I1 to I8 compensate for the intentionally generated cross current, and the cross current does not flow unintentionally. It ends up. In order to operate normally, it is necessary to hold the cross current command value at the timing when the integrating amplifiers I1 to I8 are operated.

In order to realize the above, a delay adder DelayD5 is provided. The delay amount of the delay adder DelayD5 needs to be set to a value in which the dead time + TD has a little more margin, and the dead time × 2 + TD when considering noise attenuation.

As an effect of the second embodiment, it is possible to align the FC voltages that have been displaced due to some temporary disturbance, suppress the generation of resonance current, and reduce the cross current.

By combining the second embodiment with the first embodiment, when the deviation of the FC voltage for each unit, which is the cause of resonance, occurs due to a sudden disturbance, the FC voltage is intentionally passed by a cross current. Reduce the deviation. Therefore, resonance can be suppressed and the cross current can be made smaller.

[Embodiment 3]
FIG. 5 shows the gate command value delay control unit 4 of the third embodiment. Description of the same parts as in the second embodiment will be omitted.

The switch SWE performs the same operation as in the second embodiment. The subtractor 13 subtracts the voltage detection signal VFC2 of the FC of the second inverter unit from the voltage detection signal VFC1 of the FC of the first inverter unit, and the voltage detection signal VFC1 of the FC of the first inverter unit and the FC of the second inverter unit. The deviation from the voltage detection signal VFC2 of

The buffer Z-1 stores the deviation output by the subtractor 13. The subtractor 19 subtracts the output of the subtractor 13 and the deviation stored in the buffer Z-1, for example, one cycle before the carrier, and obtains the fluctuation amount of the deviation between one carrier cycle.

The multiplier 20 obtains the product of the fluctuation of the deviation and the switch SWE. The integration amplifier I9 inputs the output of the multiplier 20 and performs an integration operation. The multiplier 21 calculates the product of the output of the integrating amplifier I9 and the inverter unit output current command value (Iinv1 or Iinv / N). The output of the multiplier 21 becomes a cross current command value, and is input to the gate command value delay control unit 4 of the first embodiment shown in FIG.

The third embodiment also adds a function of controlling the voltage detection signal VFC2 of the FC of the second inverter unit by changing the cross current command value which was fixed to zero in the first embodiment. However, unlike the second embodiment, the capacity deviation (capacity difference) of the FC due to the inverter unit is estimated, and a cross current is generated according to the deviation.

First, the deviation between the FC voltage detection signal VFC1 of the first inverter unit and the FC voltage detection signal VFC2 of the second inverter unit is calculated. Next, the buffer Z-1 and the subtractor 19 detect the fluctuation within a certain section. If the cross current suppression control is operating normally, it can be considered that the currents passing through the FC of each inverter unit are almost equal. Therefore, if there is a difference in the voltage fluctuation of the FC, it can be determined that it is because the capacity of the FC is deviated.

The code is adjusted by using the switch SWE for this difference in voltage fluctuation. The operation of the switch SWE is exactly the same as in the second embodiment. The capacitance deviation is estimated by amplifying the voltage fluctuation after adjusting the sign with the integrating amplifier I9, and the obtained capacitance deviation is multiplied by the inverter output current command value (Iinv1 or Iinv / N) to obtain the cross current current command value. ..

The operation of the third embodiment will be described. For example, when Vdc / 2> VFC1, the output current is a positive value, the FC capacity of the second inverter unit is larger than the FC capacity of the first inverter unit, and the voltage detection signal VFC1 of the FC of the first inverter unit is the second inverter unit. Consider the case where the voltage detection signal of FC is more likely to fluctuate than VFC2.

In this case, a current flows into the FC to promote charging, but the increase in the voltage detection signal VFC2 of the FC of the second inverter unit becomes smaller than the voltage detection signal VFC1 of the FC of the first inverter unit, and the voltage fluctuation becomes a positive value. It is output, the switch SWE also becomes positive, and a positive value is input to the integrating amplifier I9.

As a result, the output value of the integrating amplifier I9 gradually increases, and the cross current current command value also gradually increases, prompting an increase in the output current Iinv2. Then, when the fluctuation of the FC voltage detection signal VFC1 of the first inverter unit and the fluctuation of the voltage detection signal VFC2 of the FC of the second inverter unit become equal, the increase of the integrated amplifier I9 output value stops.

The third embodiment also has an effect of reducing the cross current generated by the voltage drop deviation of the switching device. For example, when Vdc / 2> VFC1, the output current is a positive value, the FC capacity of the first inverter unit is equal to the FC capacity of the second inverter unit, but the voltage drop of the switching device of the second inverter unit is larger than that of the first inverter unit. Consider the case where a large current is difficult to pass.

At this time, the output current of the second inverter unit is smaller than that of the first inverter unit even if the cross current suppression control operates normally. Although the FC is charged, the voltage detection signal VFC1 of the FC of the first inverter unit increases more than the voltage detection signal VFC2 of the FC of the second inverter unit, and the fluctuation amount becomes a positive value. Since the switch SWE is also positive, a positive value is input to the integrating amplifier I9, the cross current command value gradually increases, and an increase in the output current Iinv2 is promoted. Since the FC capacitance is the same, the increase in the output value of the amplifier I9 stops when the output current Iinv1 and the output current Iinv2 match.

Unlike the second embodiment, the third embodiment is not limited to the period during which the zero voltage is output, and the cross current is constantly changed. This has the effect of reducing the cross current generated by the voltage drop deviation of the switching device.

For example, when a switching device having a small voltage drop deviation can be used in all the units, as shown in FIG. 6, an exclusive OR element XOR3, a delay adder D5, and a switch SWD are added as in the second embodiment. It is also possible to allow the cross current to flow only during the period when the zero voltage is output. At this time, the place where the switch SWD is added needs to be after the integrator amplifier I9.

Specifically, as shown in FIG. 6, the exclusive OR element XOR3 outputs 1 when both the gate command values Gref1 and Gref2 are the same. The delay adder DelayD5 delays the output signal of the exclusive OR element XOR3 by a predetermined time only when it falls. The switch SWD outputs the output of the multiplier 21 if the output of the delay adder DelayD5 is 1, and outputs 0 if the output of the delay adder DelayD5 is 0. The output of this switch SWD becomes the cross current current command value.

As an effect of the third embodiment, the deviation of the FC voltage can be made zero against a steady disturbance such as the difference in the capacitance of the FC and the deviation of the voltage drop of the switching device, resonance is suppressed, and the cross current is reduced. can do. However, unlike the second embodiment, there is no function of aligning FC voltages that have been displaced due to temporary disturbance.

By combining the third embodiment with the first embodiment, the difference in the fluctuation of the FC voltage of each inverter unit is detected, and the cross current is intentionally generated so that the difference becomes zero. Therefore, the deviation of the FC voltage generated by the steady disturbance such as the deviation of the FC capacitance and the deviation of the voltage drop of the switching device can be made zero, and the cross current can be reduced. It takes a while to adjust the cross current, but it can be adjusted automatically under the condition that a certain amount of current flows, and it can follow the temperature change and secular change of the FC capacity and the voltage drop of the switching device. it can.

[Embodiment 4]
FIG. 7 shows the cross current suppression control unit of the fourth embodiment. In the fourth embodiment, the cross current command values of the second embodiment and the third embodiment are simply added to obtain a new cross current command value.

In the second embodiment, the FC voltage that has been displaced due to the temporary disturbance can be made uniform, but the deviation of the FC voltage can be reduced but cannot be reduced to zero for a steady disturbance. Resonance will occur. On the other hand, in the third embodiment, on the contrary, steady disturbance can be compensated, but when a temporary disturbance occurs, the cross current increases.

Therefore, by adding the cross current current command values of the second embodiment and the third embodiment, the cross current can be made smaller in response to both disturbances.

In the second, third, and fourth embodiments, the cross current is intentionally passed in proportion to the capacitance shift of the FC, so that the cross current other than the resonance component naturally increases. However, since the resonance current generated between the FC and the cross current suppression reactor can be suppressed, the cross current can be suppressed to be smaller than when the method of Patent Document 2 is applied as it is or as compared with the first embodiment.

By combining the fourth embodiment with the first embodiment, the deviation of the FC voltage generated by both the sudden disturbance and the steady disturbance can be made zero, so that the cross current can be made smaller.

Specifically, as shown in FIG. 7, the exclusive OR element XOR3 outputs 1 when both the gate command values Gref1 and Gref2 are the same. The delay adder DelayD5 delays the output signal of the exclusive OR element XOR3 by a predetermined time only at the time of falling.

The subtractor 13 subtracts the voltage detection signal VFC2 of the FC of the second inverter unit from the voltage detection signal VFC1 of the FC of the first inverter unit, and the voltage detection signal VFC1 of the FC of the first inverter unit and the FC of the second inverter unit. The deviation from the voltage detection signal VFC2 of The signal of the delay adder DelayD5 is input to the switch SWD, and if the input is 1, the deviation between the FC voltage detection signal VFC1 of the first inverter unit and the FC voltage detection signal VFC2 of the second inverter unit is output, and the input is If it is 0, the comparator cmp1 that outputs 0 detects whether or not the voltage detection signal VFC1 of the FC of the first inverter unit exceeds Vdc / 2. The code detector 14 outputs 1 if the sign of the inverter unit output current command value (Iinv1 or Iinv / N) is positive, and outputs 0 if the sign is negative.

The exclusive OR element XOR4 outputs 1 as an FC control signal only when the outputs of the comparator comp1 and the code detector 14 are the same. The switch SWE inputs an FC control signal, outputs 1 if the input is 1, and outputs -1 if the input is 0. The multiplier 15 calculates the product of the output signal of the switch SWD and the output signal of the switch SWE.

The multiplier 16 calculates the product of the output of the multiplier 15 and the reciprocal of the FC capacitance CFC. The multiplier 17 inputs the voltage command value Vref, obtains the duty ratio (1- | Vref |) of the zero voltage output, and calculates the product of this reciprocal and the output of the multiplier 16. Since division when calculating the duty ratio has a large calculation load, the product of 1 + | Vref | may be approximately obtained.

The limiter 18 prevents the multiplier output from becoming abnormally large when the absolute value of the voltage command value Vref is close to 1.

The buffer Z-1 stores the deviation output by the subtractor 13. The subtractor 19 subtracts the output of the subtractor 13 and the deviation stored in the buffer Z-1, for example, one cycle before the carrier, and obtains the fluctuation amount of the deviation between one carrier cycle.

The multiplier 20 obtains the product of the fluctuation of the deviation and the switch SWE. The integration amplifier I9 inputs the output of the multiplier 20 and performs an integration operation. The multiplier 21 calculates the product of the output of the integrating amplifier I9 and the inverter unit output current command value (Iinv1 or Iinv / N).

The adder 22 adds the outputs of the limiter 18 and the multiplier 21. The output of the adder 22 becomes the cross current current command value.

The above embodiment has been described by taking two inverter units in parallel as an example. However, it can be expanded to any number of inverter units of 3 or more. As an example, FIG. 8 shows a control block of the kth inverter unit when the first embodiment is expanded in parallel with N or more inverter units. The gate command values Gref1 and Gref2 are output from the FC voltage controller as in FIG.

The inverter unit output current command value (Iinv1 or Iinv / N) is compared with its own output current Iinvk and input to a PI amplifier having the same configuration as in FIG. And the gate signals Tk1, Tk2, Tk3, and Tk4 to which the dead time is added are input to the kth inverter unit. The cross current command value k is zero.

9 to 12 are gate command value delay control units 4 of the kth inverter unit when the embodiments 2 to 4 are expanded in parallel with N inverter units. The reference FC voltage VFC1 is compared with its own FC voltage VFCk, and the obtained deviation is calculated exactly as in FIG. 7. The result obtained in this way is the cross current command value k, which is input to FIG.

With the above configuration, the resonance current due to the FC and the cross flow suppression reactor can be reduced and the cross flow current can be reduced even in the parallel configuration of three or more inverter units.

However, in the second to fourth embodiments, the FC voltage detector is required for all the inverter units. The above method can be combined with Patent Document 4 to further reduce the cross current.

1 ... PWM modulator 2 ... FC voltage controller 3a to 3d ... Dead time processor 4 ... Gate delay command value calculation unit 5 ... Comparer 6 ... Code detector 7a to 7d ... NOT circuit 8 ... Adder 9 ... Subtractor 10 ... adder 11a-11d ... AND element 12a-12d ... delay adder 13 ... subtractor 14 ... code detector 15 ... multiplier 16 ... multiplier 17 ... multiplier 18 ... limiter 19 ... subtractor 20 ... multiplier 21 … Multiplier 22… Adder

Claims (5)

A cross-flow current suppression control device that suppresses cross-flow current in a power conversion circuit in which two or more inverter units are connected in parallel to a DC voltage source.
The inverter unit is interposed between the first to fourth switching devices sequentially connected in series, the common connection point of the first and second switching devices, and the common connection point of the third and fourth switching devices. With a flying capacitor,
The cross current suppression control device is
A first rising delay adder that adds a fixed rising gate delay command value to a first gate command value that turns on / off the first and fourth switching devices generated by the PWM modulator and FC voltage controller. A second rising delay adder that adds a fixed rising gate delay command value to the second gate command value that turns on / off the second and third switching devices generated by the PWM modulator and FC voltage controller. A first falling delay adder that adds a fixed value falling gate delay command value to the first gate command value, and a fixed value falling gate delay command value added to the second gate command value. A second fall delay adder and a second fall delay adder are provided in the first inverter unit.
A proportional amplifier that multiplies the gain by subtracting its own inverter unit output current detection value from the value obtained by adding the cross current command value to the inverter unit output current command value as the cross current, and the first gate by inputting the cross current. The first integrating amplifier that operates after the command value changes from 0 to 1 and when the sign of the inverter unit output current command value is positive, and the cross current are input and the first gate command value changes from 0 to 1. After changing to, and after the second integrating amplifier that operates when the sign of the inverter unit output current command value is negative, and after the cross current is input and the first gate command value changes from 1 to 0, and , The third integrating amplifier that operates when the sign of the inverter unit output current command value is positive, and the inverter unit output current after the cross current is input and the first gate command value changes from 1 to 0. The fourth integrating amplifier that operates when the sign of the command value is negative, and after the cross current is input and the second gate command value changes from 0 to 1, and the sign of the inverter unit output current command value is positive. The fifth integrating amplifier that operates at the time of, and the sixth that operates after the cross current is input and the second gate command value changes from 0 to 1, and when the sign of the inverter unit output current command value is negative. The integrating amplifier, the seventh integrating amplifier that operates after the cross current is input and the second gate command value changes from 1 to 0, and when the sign of the inverter unit output current command value is positive, and the cross current. It has an eighth integrating amplifier that operates after a current is input and the second gate command value changes from 1 to 0, and when the sign of the inverter unit output current command value is negative, and the inverter unit output. When the sign of the current command value is positive, the value obtained by adding the output of the proportional amplifier and the output of the first integrating amplifier and multiplying by -1 is used as the first rising gate delay command value, and the inverter unit output current command is used. When the sign of the value is negative, the value obtained by adding the output of the proportional amplifier and the output of the second integrating amplifier and multiplying by -1 is used as the gate delay command value of the first rising edge of the inverter unit output current command value. When the sign is positive, the value obtained by adding the output of the proportional amplifier and the output of the third integrating amplifier is used as the gate delay command value for the first falling edge , and when the sign of the inverter unit output current command value is negative, the proportional value is used. The value obtained by adding the output of the amplifier and the output of the fourth integrating amplifier is used as the gate delay command value for the first falling edge , and the inverter unit is used. When the sign of the output current command value is positive, the value obtained by adding the output of the proportional amplifier and the output of the fifth integrating amplifier and multiplying by -1 is used as the second rising gate delay command value, and the output of the inverter unit. When the sign of the current command value is negative, the value obtained by adding the output of the proportional amplifier and the output of the sixth integrating amplifier and multiplying by -1 is used as the second rising gate delay command value, and the inverter unit output current command is used. When the sign of the value is positive, the value obtained by adding the output of the proportional amplifier and the output of the 7th integrating amplifier is set as the second falling gate delay command value, and when the sign of the inverter unit output current command value is negative. The gate delay command value calculation unit that outputs the sum of the output of the proportional amplifier and the output of the eighth integrator amplifier as the second falling gate delay command value, and the first rising gate delay command value are described above. A third rise delay adder that adds the first gate command value, a fourth rise delay adder that adds the second rise gate delay command value to the second gate command value, and the first fall gate. A third fall delay adder that adds a delay command value to the first gate command value, and a fourth fall delay adder that adds the second fall gate delay command value to the second gate command value. , Is provided in each of the second to second N (integer of N = 2 or more) inverter units, respectively. The cross-flow current suppression control device according to claim 1, wherein when the absolute value of the output current command value of the inverter unit is equal to or less than a threshold value, the update of the first to eighth integrating amplifiers is stopped. The cross-flow current suppression control device according to claim 1 or 2, wherein the inverter unit output current command value is a value obtained by dividing the total value of the output current detection values of all the inverter units by the number of the inverter units. The cross-flow current suppression control device according to claim 1 or 2, wherein the inverter unit output current command value is an output current detection value of the first inverter unit. The cross-flow current suppression control device according to any one of claims 1 to 4, wherein the cross-flow current command value = 0 in all the inverter units.

Images