JP2018129968A - Cross flow current suppression controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress cross flow current in the cross flow current suppression controller of a power conversion circuit having a flying capacitor.SOLUTION: A gate delay command value calculation unit 4 has a proportional amplifier P for multiplying a cross flow current by a gain, integration amplifiers I1-I8 for inputting the cross flow current by first switches SW11-SW81 operating by the sign of each inverter unit output current command value for every turn-ON and turn-OFF of each switching device, and second switches SW12-SW82 receiving signals from the integration amplifiers I1-I8, and operating by the sign of the inverter unit output current command value. After change of the gate command values Gref1, Gref2, it is operated to add the outputs from the proportional amplifier P and the second switches SW12-SW82, thus calculating a rising gate delay command value and a falling gate delay command value.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a power conversion circuit in which units of a multilevel inverter using a flying capacitor (hereinafter referred to as FC) system are connected in parallel, and relates to current duty equalization of each inverter unit.

Patent Document 1 discloses an example of an FC type three-level inverter. FIG. 13 shows an example of a power conversion circuit in which a plurality of these are connected in parallel. (Patent Document 1 shows a configuration of a three-phase inverter. On the other hand, FIG. 13 shows a configuration composed of a representative single-phase switching device and a flying capacitor. In the configuration, as in Patent Document 1, three-phase or single-phase output inverters are connected in parallel.)
Table 1 shows the switching pattern of the FC type 3 level inverter. When outputting zero voltage, the switching devices TN1 and TN3 are turned on, or the switching devices TN2 and TN4 are turned on to make the FC conductive.

  The output voltages in Table 1 are voltages with VDC = 2E and VfC1 = VfC2 = VfC3 = E in FIG. 13 and the potential at the midpoint of the VDC as a reference point.

  As shown in FIG. 13, when a plurality of such inverter units are connected in parallel to cope with an increase in capacity of the power conversion circuit, if there are individual differences in the inverter units, a difference occurs in the output current between the units, resulting in a cross current. Current is generated, and the current responsibility varies. As a result, heat is concentrated on a specific inverter unit and the life is shortened. In some cases, a problem occurs in that an abnormality occurs in the switching element due to overcurrent or overheating.

  As a countermeasure, there is a method of connecting a cross current suppressing reactor Lu to each inverter unit, but new problems such as an increase in cost, weight and loss occur. In order to solve this problem, a technique for reducing the cross current suppression reactor Lu as much as possible and suppressing the cross current by control has been studied.

Patent Document 2 is a technique for suppressing cross current by adjusting gate timing (timing of on / off signals) of a switching device. This technique has a feature that it operates so as to detect only the cross current at the peak of the carrier and to make it zero. In order for this method to operate correctly, the following conditions are required.
(1) The frequency of the fundamental wave is sufficiently small with respect to the frequency of the carrier triangular wave, and the carrier vertex is substantially equal to the center of one pulse of the output voltage.
(2) During the switching element conduction period, the current change has a constant slope as shown in FIG.

  If the above conditions are satisfied, the cross current at the peak of the carrier is approximately equal to the average value of the cross current at one pulse of the output current. If the cross current at the peak of the carrier is set to zero, the average value of the cross current at one pulse of the output current is also zero. it can.

  Patent Document 2 assumes application to an inverter having a low number of levels such as 2 levels and 3 levels without FC, and further assumes a case where the frequency of the carrier triangular wave is sufficiently higher than the fundamental wave. Further, it is assumed that the largest factor that changes the current during the switching element conduction period is a voltage drop deviation of the element. The above assumptions can be applied without any problem because the conditions for correctly operating the method of Patent Document 2 are satisfied. Patent Document 2 discloses a circuit shown in FIG. 14 as a cross current suppression control device for a power conversion circuit.

JP 2008-92651 A Patent No. 5979253 Patent No. 3301761 Japanese Patent Application No. 2006-151687

  If the method of Patent Document 2 is applied to an FC inverter as it is, a cross current may increase. For example, in FIG. 13, when the switching devices T11, T13, T21, T23, TN1, and TN3 are turned on to output zero voltage, the FCs of the inverter units are connected in parallel via the cross current suppression reactor Lu. This is because a resonance circuit is formed between the cross current suppressing reactors Lu and the resonance current is superimposed on the cross current.

  In addition, the condition necessary for the technique of Patent Document 2 to operate correctly due to resonance does not hold “the current change during the switching element conduction period has a constant slope”, and the technique of Patent Document 2 causes malfunction. Is also the cause.

  FIG. 15 shows an example of malfunction. Here, for simplification, it is assumed that the inverter units are in parallel, the output currents Iinv1 and Iinv2 are positive, the characteristics of the switching devices are the same, the switching timing is the same, and the voltage drops are the same.

  Since the output current Iinv1 and the output current Iinv2 are equal before the first intersection point 1 between the voltage command value Vref and the carrier triangular wave, the timing adjustment is not performed at the intersection point 1, and the switching devices T11 and T22 are turned off at the same timing. Therefore, the output current Iinv1 and the output current Iinv2 immediately after the intersection 1 are equal. However, the switching devices T11 and T21 are turned on, and the antiparallel diodes of the switching devices T13 and T23 are turned on to form a resonance circuit. For example, the output currents Iinv1 and Iinv2 change in a curve as shown in FIG.

  Since Iinv1> Iinv2 at the carrier vertex 2, the method of Patent Document 2 delays the turn-on of the switching device T12 by using a proportional amplifier and advances the turn-on of the switching device T22, thereby reducing the output current Iinv1 and increasing the output current Iinv2. Prompt. However, the magnitude relationship between the output current Iinv1 and the output current Iinv2 is switched by resonance at the intersection point 3 between the voltage command value Vref and the carrier triangular wave. As a result of the correction of the proportional amplifier, conversely, the difference between the output current Iinv1 and the output current Iinv2 (cross current) ) Will increase.

  Thereafter, the switching devices T11, T12, T21, and T22 are turned on, and the FC is disconnected. Therefore, resonance does not occur between the intersection point 3 and the intersection point 5. The proportional amplifier P detects the current at the carrier vertex 4, delays the turn-off of the switching device T12, and accelerates the turn-off of the switching device T22, so that the cross current immediately after the intersection 5 can be completely suppressed.

  However, resonance occurs again after the intersection 5. Since the output current Iinv1 and the output current Iinv2 are equal at the carrier vertex 6, the timing adjustment by the proportional amplifier P is not performed in the switching at the intersection 7, and only the adjustment by the integration amplifier I is performed.

  The integrating amplifier I detects the cross current at the carrier apex 4 and makes a misjudgment against the assumption that the cause of the increase in the cross current is that the turn-on timing of the switching device T12 is too late and the turn-on timing of the switching device T22 is too early. Wake up and advance the turn-on timing of the switching device T12 at the intersection 7 and delay the switching device T22 turn-on timing. As a result, an increase in the output current Iinv1 and a decrease in the output current Iinv2 are promoted, and the cross current becomes larger.

  As a countermeasure, as shown in Patent Document 4, if the resonance frequency between the FC and the cross current suppressing reactor is sufficiently lower than the carrier frequency and the voltage command value is adjusted so that the switching interval does not become long, the cross current caused by resonance The change of is reduced, and the method of Patent Document 2 can be applied.

  However, in order to lower the resonance frequency, it is necessary to increase the capacity of the FC and the reactor, which increases the weight, volume and cost of the apparatus. Further, when the carrier frequency is increased, the switching loss increases, and there is a problem of an increase in weight and cost due to a decrease in efficiency and an enhancement of the cooling mechanism.

  As another countermeasure, it is also effective to align the FC voltage of each inverter unit and suppress the occurrence of resonance. This can be achieved by equalizing the FC passing current if the FC capacities are equal, and by controlling the cross current to zero. However, if there is a difference in FC capacity due to manufacturing error, aging, temperature change, etc., even if the cross current can be controlled to zero, a difference will occur in the FC voltage and resonance will occur.

  Moreover, as shown in FIG. 16, it is also conceivable to connect the FCs of the respective inverter units with conductive wires so that the FC potential is common. In this case, some switching devices (T11 and T21, T14 and T24) are connected in parallel. At this time, in order to reduce a transient difference in element passing current, the lengths of the conductive wires of the respective switching devices and the shapes thereof must be aligned, and inductances parasitic on the conductive wires must be made as equal as possible.

  In addition, the circuit configuration becomes complicated as the number of inverter levels increases, and it must be realized with a limited volume, which makes it very difficult to design the main circuit. Furthermore, in order to reduce the steady difference in passing current, it is necessary to select switching devices that are connected in parallel so that the forward voltage drop Vce (sat) and the reverse voltage drop Vf are equal.

  As described above, in the cross current suppression control device of the power conversion circuit having a flying capacitor, it becomes a problem to suppress the cross current.

  The present invention has been devised in view of the above-described conventional problems. One aspect of the present invention is a cross current control device that suppresses a cross current in a power conversion circuit in which two or more inverter units are connected in parallel to a DC voltage source. The inverter unit is connected between the first to fourth switching devices sequentially connected in series, the common connection point of the first and second switching devices, and the common connection point of the third and fourth switching devices. The crossing current suppression control device, wherein the first and fourth switching signals generated by the PWM modulator and the FC voltage controller are used to generate a fixed gate delay command value. PWM modulation of the first rising delay adder that adds to the first gate command value to turn the device on and off, and the fixed gate delay command value at the rising edge And a second rising delay adder for adding to the second gate command value for turning on / off the second and third switching devices generated by the FC voltage controller, and a gate delay command value for the falling of a fixed value. A first inverter that adds a first falling delay adder that is added to the first gate command value, and a second falling delay adder that adds a fixed gate fall command value to the second gate command value; A proportional amplifier that multiplies the gain by using the value obtained by subtracting its own inverter unit output current detection value from the value obtained by adding the cross current command value to the inverter unit output current command value as the cross current, and the cross current. The first integration circuit that operates after the first gate command value changes from 0 to 1 and when the sign of the inverter unit output current command value is positive. And a second integrating amplifier that operates when the cross current is input and the first gate command value changes from 0 to 1, and the sign of the inverter unit output current command value is negative, and the cross current Is input, and when the sign of the inverter unit output current command value is positive, and the cross current is input, the first integral command value is changed from 1 to 0 and the sign of the inverter unit output current command value is positive. After the gate command value has changed from 1 to 0, and when the sign of the inverter unit output current command value is negative, the cross current is input and the second gate command value is changed from 0 After the change to 1 and after the sign of the inverter unit output current command value is positive, and the fifth integration amplifier that operates when the cross current is input and the second gate command value changes from 0 to 1, And A sixth integrating amplifier that operates when the sign of the inverter unit output current command value is negative; and after the cross current is input and the second gate command value changes from 1 to 0, and the inverter unit output current A seventh integrating amplifier that operates when the sign of the command value is positive, and the sign of the inverter unit output current command value is negative after the cross current is input and the second gate command value changes from 1 to 0 And an eighth integration amplifier that operates at the time, and when the sign of the inverter unit output current command value is positive, the output of the proportional amplifier and the output of the first integration amplifier are added and multiplied by -1. The value is the first rising gate delay command value, and when the sign of the inverter unit output current command value is negative, the output of the proportional amplifier and the output of the second integration amplifier are added and multiplied by -1. When the sign of the inverter unit output current command value is positive, a value obtained by adding the output of the proportional amplifier and the output of the third integrating amplifier is the second rising gate. When the sign of the inverter unit output current command value is negative, a value obtained by adding the output of the proportional amplifier and the output of the fourth integral amplifier is used as a second rising gate delay command value, and the inverter unit When the sign of the output current command value is positive, the value obtained by adding the output of the proportional amplifier and the output of the fifth integrating amplifier and multiplying by −1 is set as the first falling gate delay command value, and the inverter unit output When the sign of the current command value is negative, a value obtained by adding the output of the proportional amplifier and the output of the sixth integrating amplifier and multiplying by −1 is a first delay gate delay command. When the sign of the inverter unit output current command value is positive, a value obtained by adding the output of the proportional amplifier and the output of the seventh integral amplifier is set as a second falling gate delay command value, and the inverter unit output current A gate delay command value calculation unit that outputs a value obtained by adding the output of the proportional amplifier and the output of the eighth integration amplifier as a second falling gate delay command value when the sign of the command value is negative; A third rise delay adder for adding a rise gate delay command value to the first gate command value; and a fourth rise delay adder for adding the second rise gate delay command value to the second gate command value; A third falling delay adder for adding the first falling gate delay command value to the first gate command value, and a second falling gate delay command value. A fourth falling delay adder to be added to the second gate command value is provided in each of the second to Nth (N = 2 or larger integer) inverter units.

  Further, as one aspect thereof, when the absolute value of the inverter unit output current command value is equal to or less than a threshold value, updating of the first to eighth integration amplifiers is stopped.

  Further, as one aspect thereof, the inverter unit output current command value is a value obtained by dividing a total value of detected output current values of all inverter units by the number of inverter units.

  As one aspect thereof, the inverter unit output current command value is an output current detection value of the first inverter unit.

  Moreover, as one aspect thereof, the cross current command value = 0 is set in all inverter units.

  In another aspect, the first exclusive OR element that outputs 1 when both the first gate command value and the second gate command value are the same, and the output signal of the first exclusive OR element A delay adder that delays the falling time by a predetermined time; a subtractor that calculates a deviation between the voltage detection signal of the flying capacitor of the first inverter unit and the voltage detection signal of the flying capacitor of the second to Nth inverter units; and the delay addition A first switch that outputs the output of the subtractor if the output of the detector is 1, and outputs 0 if the output of the delay adder is 0, and a sign detector that detects the sign of the inverter unit output current command value A comparator that outputs 1 if the voltage detection signal of the flying capacitor of the first inverter unit is greater than ½ of the voltage of the DC voltage source, and the sign detection And the second exclusive OR element that outputs 1 when both the outputs of the comparator are the same, and 1 if the output of the second exclusive OR element is 1, and the second exclusive OR If the output of the element is 0, a second switch that outputs -1; a first multiplier that multiplies the outputs of the first switch and the second switch; and the output of the first multiplier A second multiplier that multiplies the reciprocal, a third multiplier that multiplies the output of the second multiplier by the reciprocal of the duty ratio of the zero voltage output, and a limiter that provides upper and lower limit values at the output of the third multiplier; The output of the limiter is used as the cross current command value.

  As another aspect, if the sign detector for detecting the sign of the inverter unit output current command value and the voltage detection signal of the flying capacitor of the first inverter unit are larger than ½ of the voltage of the DC voltage source A comparator that outputs 1, an exclusive OR element that outputs 1 when both the output of the sign detector and the comparator are the same, and 1 if the output of the exclusive OR element is 1 , A switch that outputs -1 if the output of the exclusive OR element is 0, and a first that calculates a deviation between the voltage detection signal of the first inverter unit and the voltage detection signal of the second to Nth inverter units. A subtractor; a buffer for storing the output of the first subtractor one operation period before; a second subtractor for subtracting the output of the buffer from the output of the first subtractor; and an output of the second subtractor. Before A first multiplier that multiplies the output of the switch; an integrator that integrates the output of the first multiplier; and a second multiplier that multiplies the output of the integrator by the inverter unit output current command value. The output of the second multiplier is the cross current command value.

  As another aspect, if the sign detector for detecting the sign of the inverter unit output current command value and the voltage detection signal of the flying capacitor of the first inverter unit are larger than ½ of the voltage of the DC voltage source A comparator that outputs 1; a second exclusive OR element that outputs 1 when the outputs of the sign detector and the comparator are the same; and an output of the second exclusive OR element is 1 A second switch that outputs 1 when the output of the second exclusive OR element is 0, a voltage detection signal of the first inverter unit, and a voltage detection signal of the second to Nth inverter units A first subtractor that calculates a deviation from the first subtractor, a buffer that stores an output of the first subtractor before one operation cycle, a second subtractor that subtracts the output of the buffer from the output of the first subtractor, The second A first multiplier that multiplies the output of the second switch by the output of the second switch; an integrator that integrates the output of the first multiplier; and the output of the integrator is multiplied by the inverter unit output current command value. 1st exclusive logic which outputs 1 when the gate command value which turns on / off the 2nd multiplier and the 1st, 4th switching device, and the gate command value which turns on / off the 2nd, 3rd switching device are the same A summing element, a delay adder that delays the output signal of the first exclusive OR element by a falling time for a predetermined time, an output of the second multiplier if the output of the delay adder is 1, and the delay A first switch that outputs 0 if the output of the adder is 0, and the output of the first switch is the cross current command value.

  As another aspect, if the sign detector for detecting the sign of the inverter unit output current command value and the voltage detection signal of the flying capacitor of the first inverter unit are larger than ½ of the voltage of the DC voltage source A comparator that outputs 1; a second exclusive OR element that outputs 1 when the outputs of the sign detector and the comparator are the same; and an output of the second exclusive OR element is 1 1 and outputs a -1 if the output of the second exclusive OR element is 0, a voltage detection signal of the first inverter unit, and a voltage detection signal of the second to Nth inverter units A first subtractor that calculates a deviation of the first subtractor, a buffer that stores an output of the first subtractor before one calculation cycle, a second subtractor that subtracts the output of the buffer from the output of the first subtractor, Second subtraction A first multiplier that multiplies the output of the second switch by the output of the second switch, an integrator that integrates the output of the first multiplier, and a second that multiplies the output of the integrator by the inverter unit output current command value. A first exclusive OR that outputs 1 when the gate command value for turning on / off the first and fourth switching devices and the gate command value for turning on / off the second and third switching devices are the same. A delay adder for delaying the output signal of the first exclusive OR element by a falling time for a predetermined time, and if the output of the delay adder is 1, the output of the first subtractor is output, and the delay addition is performed. A first switch that outputs 0 if the output of the multiplier is 0, a third multiplier that multiplies the output of the first switch and the output of the second switch, and the capacitance of the flying capacitor to the output of the third multiplier of A fourth multiplier that multiplies a number; a fifth multiplier that multiplies the output of the fourth multiplier by a reciprocal of a duty ratio of a zero voltage output; and a limiter that provides upper and lower limit values at the output of the fifth multiplier; And an adder for adding the output of the second multiplier and the output of the limiter, wherein the output of the adder is used as a cross current command value.

  ADVANTAGE OF THE INVENTION According to this invention, it becomes possible to suppress a cross current in the cross current suppression control apparatus of the power converter circuit which has a flying capacitor.

1 is a block diagram showing a cross current suppression control device in Embodiment 1. FIG. FIG. 2 is a block diagram illustrating a configuration of an FC voltage controller according to the first embodiment. 3 is a time chart showing a cross current suppression operation in the first embodiment. FIG. 5 is a block diagram showing a cross current command value calculation unit in Embodiment 2. FIG. 9 is a block diagram illustrating an example of a cross current command value calculation unit in the third embodiment. FIG. 10 is a block diagram showing another example of the cross current command value calculation unit in the third embodiment. The block diagram which shows the cross current command value calculation part in Embodiment 4. FIG. The block diagram which shows the kth cross current suppression control apparatus at the time of extending the inverter unit of Embodiment 1 to N units. The block diagram which shows the kth cross current command value calculating part at the time of extending the inverter unit of Embodiment 2 to N units. The block diagram which shows an example of the kth gate delay command value calculating part at the time of extending the inverter unit of Embodiment 3 to N units. The block diagram which shows the other examples of the kth gate delay command value calculating part at the time of extending the inverter unit of Embodiment 3 to N units. The block diagram which shows the kth gate delay command value calculating part at the time of extending the inverter unit of Embodiment 4 to N units. FIG. 3 is a diagram illustrating a power conversion circuit according to the first embodiment. The block diagram which shows the conventional cross current suppression control apparatus. The time chart which shows an example of operation | movement of the conventional cross current suppression control apparatus. The figure which shows the other example of the conventional power converter circuit.

  Hereinafter, Embodiments 1 to 4 of the cross current control device according to the present invention will be described in detail with reference to FIGS.

[Embodiment 1]
In the first embodiment, the cross current of the power conversion circuit shown in FIG. 13 is suppressed. In FIG. 13, N inverter units are connected in parallel to the DC voltage source Vdc, but in the first embodiment, two inverter units are connected in parallel to the DC voltage source Vdc.

  Each inverter unit is connected between the first to fourth switching devices sequentially connected in series to the DC voltage source Vdc, the common connection point of the first and second switching devices, and the common connection point of the third and fourth switching devices. FC is inserted in

  The common connection point of the second and third switching devices is connected to one end of the cross current suppressing reactor Lu. A current detector for detecting output currents Iinv1 and Iinv2 of each inverter unit is provided on the other end side of the cross current suppressing reactor Lu. The other ends of the cross current suppression reactor Lu of each inverter unit are connected to each other, and a current detector for detecting the cross current suppression reactor Lu and the total value Iinv of the inverter unit output current is provided at the connection point. It has been.

  FIG. 1 shows a cross current suppression control apparatus according to the first embodiment. The cross current suppression control device of the first embodiment has a configuration per phase with the second inverter unit as a control target.

  The PWM modulator 1 generates gate signals Gref1 'and Gref2' by comparing the voltage command value Vref and the amplitude of the carrier triangular wave. The voltage command value Vref is given by feedforward, or may be given as an output of current control or voltage control calculated by a control unit of an inverter unit (not shown). The carrier triangular wave is output from a control unit of an inverter unit (not shown).

  The FC voltage controller 2 is a gate command capable of controlling the FC voltage based on the obtained gate signals Gref1 ′ and Gref2 ′, the FC voltage detection signal VFC1 of the first inverter unit, and the output current Iinv1 of the first inverter unit. Converted to values Gref1 and Gref2.

  The gate command value Gref1 means that the switching devices T11 and T21 are turned ON by 1 and the switching devices T14 and T24 are turned OFF. The gate command value Gref2 means that the switching devices T12 and T22 are turned ON by 1 and the switching devices T13 and T23 are turned OFF.

  The delay command value TD is a fixed value, and the gate command values Gref1 and Gref2 output to the first inverter unit are delayed by a value specified by the delay command value TD. Normally, the delay command value TD designates a value about 1/10 to 1/4 of the dead time of the switching device. The delay adder DelayU1 delays the rise of the gate command value Gref1 by the delay command value TD. The delay adder DelayD1 delays the fall of the gate command value Gref1 by the delay command value TD. The delay adder DelayU2 delays the rise of the gate command value Gref2 by the delay command value TD. The delay adder DelayD2 delays the fall of the gate command value Gref2 by the delay command value TD.

  The dead time processors 3c and 3d add dead time to the outputs of the delay adders DelayD1 and DelayD2, and output the gate signals of the switching devices T11, T12, T13, and T14.

  The gate command values Gref1 and Gref2 are output to the gate delay command value calculation unit 4, and the delay command values DrefU1, DrefU2, DrefD1, and DrefD2 are output from the gate delay command value calculation unit 4.

  The delay adder DelayU3 delays the rise of the gate command value Gref1 by the delay command value DrefU1. The delay adder DelayD3 delays the fall of the gate command value Gref1 by the delay command value DrefD1.

  The dead time processor 3a adds dead time to the output of the delay adder DelayD3 and outputs the gate signals of the switching devices T21 and T24.

  The delay adder DelayU4 delays the rise of the gate command value Gref2 by the delay command value DrefU2. The delay adder DelayD4 delays the fall of the gate command value Gref2 by the delay command value Dref2.

The dead time processor 3b adds dead time to the output of the delay adder DelayD4 and outputs the gate signals of the switching devices T22 and T23. The gate signals output from the dead time processors 3a to 3d are sent to the corresponding switching devices. Entered.

  The gate delay command value calculation unit 4 is configured as follows.

  The inverter unit output current command value is a signal Iinv / N obtained by dividing the detection signal of the output current Iinv1 of the first inverter unit or the detection signal of the total value Iinv of each inverter unit output current by the number N of units in parallel.

  The absolute value converter ABS outputs the absolute value of the inverter unit output current command value. The comparator 5 determines whether or not the absolute value of the inverter unit output current command value exceeds the threshold value Ith. The switch SW9 is closed when the absolute value of the inverter unit output current command value exceeds the threshold value Ith.

  The sign detector 6 detects the sign of the inverter unit output current command value, and outputs 1 if positive and 0 if negative. The output of the sign detector 6 is input to the switches SW11, SW12, SW31, SW32, SW51, SW52, SW71, SW72.

  The output of the sign detector 6 is input to the switches SW21, SW22, SW41, SW42, SW61, SW62, SW81, SW82 after logical inversion by the NOT circuits 7a to 7d.

  The adder 8 calculates the sum of the inverter unit output current command value and the cross current command value. In the first embodiment, the cross current command value is fixed to zero. The subtracter 9 subtracts the detection signal of the output current Iinv2 of the second inverter unit that is the control target unit from the output of the adder 8, and outputs a deviation. The low pass filter LPF removes high frequency component noise from the deviation. The output of the low pass filter LPF is input to the proportional amplifier P and the switch SW9.

  In the proportional amplifier P, the output of the low-pass filter LPF is proportionally calculated and output.

  Hereinafter, the configuration of the integrating amplifiers I1 and I2 will be described. The output of the switch SW9 is input to the switches SW11 and SW21. The switch SW11 is closed if the sign of the inverter unit output current command value is positive. The switch SW21 is closed if the sign of the inverter unit output current command value is negative. The output of the switch SW11 is input to the integrating amplifier I1.

  A switch SW12 is connected to the output of the integrating amplifier I1, and the switch SW12 is closed if the sign of the inverter unit output current command value is positive. The output of the switch SW21 is input to the integrating amplifier I2. A switch SW22 is connected to the output of the integrating amplifier I2, and SW22 is closed if the sign of the unit output current command value is negative.

  The outputs of the switches SW12 and SW22 are input to the adder 10a and added together with the output of the proportional amplifier P. The output of the adder 10a is multiplied by −1 to become the rising delay command value DrefU1 of the gate command value Gref1, and is input to the delay adder DelayU3.

  The operation timing of the integrating amplifiers I1 and I2 will be described. The circuit for determining the timing is configured as follows.

  The buffer Z-1 causes a delay of one calculation time for the gate command value Gref1. The AND element 11a calculates the logical sum of the gate command value Gref1 and the logical negation of the signal one calculation time before the gate command value Gref1, and one calculation time when the gate command value Gref1 changes from 0 to 1 Only 1 is output.

The delay adder 12a delays the output signal of the AND element 11a. The delay amount normally designates dead time + TD to dead time × 2 + TD. The delay command value TD is a fixed value. The reason why the delay amount is (dead time + TD to dead time × 2 + TD) will be described later. The integrating amplifiers I1 and I2 operate according to the output of the delay adder 12a.

As described above, the integration amplifiers I1 and I2 operate only once after the time (dead time + TD to dead time × 2 + TD) set by the delay adder after the gate command value Gref1 changes from 0 to 1. Integration amplifier I3 ˜I8 has the same configuration. However, the following points are different.

(Operating conditions)
The integrating amplifiers I1 and I2 operate after the gate command value Gref1 changes from 0 to 1.
The integrating amplifiers I3 and I4 operate after the gate command value Gref1 changes from 1 to 0.
The integrating amplifiers I5 and I6 operate after the gate command value Gref2 changes from 0 to 1.
The integrating amplifiers I7 and I8 operate after the gate command value Gref2 changes from 1 to 0.

(Handling after addition with proportional amplifier P output)
The outputs of the integrating amplifiers I1 and I2 are added to the output of the proportional amplifier P and then multiplied by −1 to obtain the delay command value DrefU1.
The outputs of the integrating amplifiers I3 and I4 are added to the output of the proportional amplifier P and become the delay command value DrefD1 as it is.
The outputs of the integrating amplifiers I5 and I6 are added to the output of the proportional amplifier P and then multiplied by −1 to obtain the delay command value DrefU2.
The outputs of the integrating amplifiers I7 and I8 are added to the output of the proportional amplifier P and become the delay command value DrefD2 as it is.

  There exists patent document 3 as an example of FC voltage controller 2, The example is shown in FIG.

  The comparator cmp1 determines whether or not the FC voltage detection signal VFC1 of the first inverter unit is larger than the FC voltage command value (1/2 of the DC voltage source voltage) Vdc / 2. The comparator cmp2 determines whether or not the output current Iinv1 is positive. The exclusive OR element XOR1 outputs a signal sel that becomes 1 when only one of the comparators cmp1 and cmp2 is 1.

  The exclusive OR element XOR2 outputs 1 when either one of the gate signals Gref1 'and Gref2' output from the preceding PWM modulator 1 is 1. The hold device Hold outputs the signal sel as it is when both of the gate signals Gref1 ′ and Gref2 ′ are 1 or 0, and outputs the previous output when only one of the gate signals Gref1 ′ and Gref2 ′ is 1. Hold.

  The OR circuit OR1 outputs a logical sum of the gate signal Gref1 'and the hold device Hold. The AND circuit AND1 outputs a logical product of the OR circuit OR1 and the gate signal Gref2 '. The output of the AND circuit AND1 is a gate command value Gref1.

  The OR circuit OR2 outputs a negative logical sum of the gate signal Gref1 'and the output of the hold device Hold. The AND circuit AND2 outputs a logical product of the OR circuit OR2 and the gate signal Gref2 '. The output of the AND circuit AND2 is a gate command value Gref2.

  The PWM modulator 1 outputs gate signals Gref1 'and Gref2' based on the comparison between the voltage command value Vref and the carrier triangular wave.

(Description of action / operation)
The basic operation of the first embodiment is the same as the operation of the conventional gate delay command value calculation unit 4 of Patent Document 2 shown in FIG. That is, the cross current is suppressed by detecting the cross current and adjusting the gate timing according to the magnitude of the cross current.

  The proportional amplifier P detects the cross current immediately before switching, and adjusts the switching timing so that the cross current becomes zero in the next switching. The integrating amplifiers I1 to I8 detect the cross current after switching, estimate the individual difference of the switching device, learn the individual difference (rising time and fall time characteristic variation) by the integration operation, and adjust the switching timing.

  The first embodiment is intended to be applied to an FC type three-level inverter configured with four switching devices per phase. Therefore, as in the ninth embodiment of Patent Document 2, the control circuit per phase uses eight integrating amplifiers I1 to I8.

  Next, the operation of each amplifier will be described.

[Gate timing adjustment by proportional amplifier P]
The deviation between the inverter unit output current command value and the output current Iinv2, that is, the cross current is input to the proportional amplifier via the low pass filter LPF, and the value multiplied by the gain is output as the delay command value of the gate command value. When the cross current is positive, the output current Iinv2 is smaller than the command value.

  At this time, the rising delay command values DrefU1 and DrefU2 become negative values, and advance correction is applied to the rising of the gate command value, and the falling delay command values DrefD1 and DrefD2 become positive values and fall of the gate command value. Takes a delay correction. As a result, the inverter unit 2 increases the period during which a positive voltage is output, and thus promotes an increase in the output current Iinv2. Conversely, when the cross current is negative, the output current Iinv2 is reduced.

  In the conventional method of FIG. 14, a hold function for storing the cross current at the carrier apex is arranged before the proportional amplifier P, and the delay command value output from the proportional amplifier P is obtained based on the cross current at the carrier apex. However, the gate command value delay control unit 4 of the first embodiment does not have a hold function.

  For this reason, the delay command value output from the proportional amplifier P at the moment of switching is a value reflecting the cross current immediately before switching.

  The operation of the proportional amplifier P according to the first embodiment is shown in FIG. Taking the intersection 3 as an example, in the first embodiment, since the delay command value is calculated based on the cross current immediately before switching, Iinv1 <Iinv2 (that is, the negative cross current) is detected, and the turn of the switching device T22 is detected. ON is delayed, an increase in the output current Iinv1 and a decrease in the output current Iinv2 are promoted, and the cross current can be reduced. On the other hand, in the configuration of Patent Document 2, the cross current is increased as described above and as shown in FIG.

[Gate timing adjustment by integrating amplifier I1]
The cross current is input to the integrating amplifier I1 through the low-pass filter LPF, gain is applied, and the integrated value is output as a gate delay command value. Since the front and rear switches SW11 and SW12 are closed when the sign of the output current Iinv1 is positive, the integrating amplifier I1 performs integration only when the output current sign is positive and outputs a command value.

  The operation timing of the integrating amplifier I1 is after the gate command value Gref1 rises, and the output delay command value becomes DrefU1, which is reflected in the rise of the gate command value Gref1. When the gate command value Gref1 rises, the switching device T21 is turned on and the switching device T24 is turned off. When the current sign is positive, the current passes through the antiparallel diode of the switching device T24, so that the current path does not change even when the switching device T24 is switched. The integrating amplifier I1 is in charge of adjusting the turn-on timing of the switching device T21.

[Gate timing adjustment by integrating amplifier I2]
The condition for closing the switches SW21 and SW22 before and after the integrating amplifier I2 is that the sign of the output current Iinv1 is negative, unlike the integrating amplifier I1. At this time, the current passes through the antiparallel diode of the switching device T21. The integrating amplifier I2 is responsible for adjusting the turn-off timing of the switching device T24.

[Gate timing adjustment by integrating amplifier I3]
The conditions for closing the switches SW31 and SW32 are the same as those of the integrating amplifier I1 (switches SW11 and SW12). However, the operation timing is after the fall of the gate command value Gref1, and the output delay command value becomes DrefD1, which is reflected in the fall of the gate command value Gref1. Therefore, the integrating amplifier I3 is in charge of timing adjustment for turning off the switching device T21.

[Gate timing adjustment by integrating amplifier I4]
Similarly, the integrating amplifier I4 is in charge of timing adjustment of the switching device T24 turn ON.

[Integrating amplifiers I5 to I8]
The charge of each integrating amplifier is shown below.
I5: T22 turn ON
I6: T23 turn off
I7: T22 turn off
I8: T23 turn ON
In the conventional method of FIG. 14, a carrier vertex signal is input as an operation trigger of the integration amplifier, and the operation timing of the integration amplifier is set as the carrier vertex. However, in the first embodiment, it is detected that the gate command values Gref1 and Gref2 have changed, and an integration amplifier operation trigger is added with a delay. It becomes.

  Taking FIG. 3 as an example, immediately after the intersection 3, the output current is positive and the switching devices T12 and T22 change from OFF to ON (that is, the gate command value Gref2 changes from 0 to 1). Operate. Immediately after the intersection 3, there is a cross current that remains as a result of the gate timing adjustment by the proportional amplifier P.

  The reason why the cross current remains is that the turn-on of the switching device T22 is too fast compared to the turn-on of the switching device T12. The integral amplifier I5 stores this cross current. Then, a command for slightly delaying the turn-on of the switching device T22 is output at the intersection 7 where the switching devices T12 and T22 are turned on, thereby reducing the cross current.

  In Patent Document 2, after waiting for a while after switching, the cross current is detected, so that not only the switching timing shift but also the amount due to the voltage drop is superimposed on the detected cross current, and both the timing shift and the voltage drop shift are added to the integrating amplifier. Learn and compensate collectively.

  However, when FC is present, resonance is added as a cause of generation of a cross current during a period when switching is not performed. The resonance is not caused by the characteristic deviation of the switching element but by the FC voltage deviation. Since the magnitude of the FC voltage deviation changes every time switching is performed, the resonance current flows differently at each switching, and learning by the integrating amplifier is performed. It will malfunction.

  Therefore, in the first embodiment, the current immediately after switching is detected, and the compensation target is limited to the switching timing deviation, so that the cross current due to resonance can be prevented from being superimposed on the detection signal, and the learning malfunction can be suppressed.

  The reason why the integration amplifier operates in Patent Document 1 will be described after a certain delay time has passed immediately after the change of the gate signal. Since it is not possible to advance the gate timing, the gate timing of the first inverter unit, which is the reference unit, is delayed by a fixed value TD, and the delay of the second inverter unit, which is the control target unit, is made smaller than TD. Is going on.

  For this reason, the actual switching is delayed by about TD from the change of the gate command values Gref1 and Gref2, so that the operation of the integrating amplifier needs to be delayed by a fixed value TD. Further, considering that dead time enters, actual switching is further delayed by dead time than the change of the gate command values Gref1 and Gref2. For this reason, in order to reliably input the current after the switching is completed to the integrating amplifier, it is necessary to wait at least (dead time + TD) from the change of the gate command values Gref1 and Gref2.

  Further, considering that the switching noise is superimposed on the current detection signal, it is possible to suppress the influence of the noise by additionally waiting for the current detection for about 2 μs to the dead time until the noise is attenuated.

The switch SW9 will be described. The switch SW9 is opened when the absolute value of the output current is small, and the updating of the integrating amplifier is stopped. This is the same operation as Embodiment 3 of Patent Document 2. The reason for stopping the update of the integrating amplifier when the absolute value of the output current is small is the same as follows.
・ In order to prevent malfunction of the control circuit, there is a possibility that the current sign cannot be detected correctly due to the offset superimposed on the current detector.
・ If the absolute value of the output current is small, the generated cross current is limited, and even if it is not controlled, the influence on the heat duty is small and the switching device is not destroyed.

  The FC voltage controller 2 will be described. The FC type three-level inverter, unlike the NPC type and T type, has two types of switching patterns for outputting zero voltage: a pattern for turning on the switching devices T11 and T13 and a pattern for turning on the switching devices T12 and T14. It is known as in Patent Document 3 that the FC voltage can be controlled by selecting a switching pattern according to the sign of the current.

  For example, when it is desired to charge FC, the switching devices T11 and T13 may be turned on if the output current is positive, and the switching devices T12 and T14 may be turned on if the output current is negative. An example of a block for realizing this control is shown in FIG. In this FC voltage controller 2, the comparator cmp1 compares the FC voltage detection signal VFC1 with Vdc / 2 which is ½ of the voltage of the DC voltage source, and the comparator cmp2 compares the sign of the inverter unit output current command value Iinv1. The signal sel is calculated by the exclusive OR element XOR1 circuit.

  The signal sel thus obtained indicates that the switching devices T1 and T3 should be turned on if 1 and the switching devices T2 and T4 should be turned on if 0. In order to prevent an increase in the number of times of switching, the hold device Hold in the latter stage is OR circuits OR1 and OR2 while the gate signals Gref1 ′ = 0, Gref2 ′ = 1 (or Gref1 ′ = 1, Gref2 ′ = 0) and a zero voltage is being output. This is to prevent the signal sel ′ input to the input signal from changing.

  After that, gate command values Gref1, Gref2 are generated by the OR circuits OR1, OR2, AND circuits AND1, AND2. Table 2 shows the relationship between the magnitude of the voltage detection signal VFC1 and the sign of the inverter unit output current command value Iinv1, and the obtained gate command values Gref1, Gref2, and FC charge / discharge.

  The advantage of the first embodiment is that it can be correctly suppressed without increasing the cross current by the control even under the condition that the resonance current due to the FC is generated. Furthermore, the resonance can be reset by reliably setting the cross current to zero each time switching is performed.

  The first embodiment also has disadvantages. Since the integrating amplifiers I1 to I8 compensate only for the difference in switching timing and do not compensate for the voltage drop deviation, the cross current caused by the voltage drop deviation increases. In addition, since resonance during a period in which switching is not performed cannot be suppressed, an increase in cross current due to resonance may occur. However, since the expansion of the resonance current can be suppressed as compared with the method of Patent Document 2, the cross current can be reduced.

  In addition, as an effective item for suppressing the cross current in configuring the control block, it is mentioned that the switching pattern is common to all inverter units. In the unit parallel configuration, the FC of each unit can be individually controlled by selecting a switching pattern at the time of zero voltage output in each inverter unit. However, the number of combinations of switching devices that simultaneously switch increases and cross current suppression control becomes difficult.

  For example, let us consider a state in which two inverter units are arranged in parallel, the switching devices T11, T12, T21, and T22 are currently ON, and two units each output a voltage of + Vdc / 2. In order to switch to zero voltage output in this state, the first inverter unit turns off the switching device T12 and turns on the switching device T13. If different switching patterns are allowed, the second inverter unit may turn off the switching device T21 and turn on the switching device T24 to switch to zero voltage output.

  At this time, the switching device T21 needs to synchronize with the switching device T12, not the switching device T11, and the switching device T24 must also synchronize with the switching device T13, not the switching device T14.

  In order to cope with this, two integration amplifiers that are responsible for turning off the switching device T21, that is, an integration amplifier based on the switching device T11 and an integration amplifier based on the T12 must be prepared and switched according to the switching pattern. The control circuit becomes complicated.

  In addition, after switching, a circuit in which the FC of the first inverter unit and the FC of the second inverter unit are connected in series via the cross current suppressing reactor is connected in parallel to the DC voltage source.

  At this time, if VFC1 + VFC2 ≠ Vdc is established, resonance occurs. If the switching patterns are the same, resonance can be suppressed if VFC1 = VFC2 can be realized. However, if different switching patterns are permitted, it is necessary to establish VFC1 + VFC2 = Vdc, which makes realization difficult.

  In order to avoid the above problems, the switching pattern is common to all inverter units. In FIG. 1, only the detection value of the FC voltage detection signal VFC1 of the first inverter unit is input to the FC voltage controller 2, and the switching pattern is selected so that only the voltage detection signal VFC1 becomes Vdc / 2. . This control circuit cannot control the voltage detection signal VFC2.

  However, when the voltage detection signal VFC1 and the voltage detection signal VFC2 are different, the resonance current flows when the zero voltage is output, so that the difference between the voltage detection signal VFC1 and the voltage detection signal VFC2 becomes small. Therefore, even if the voltage detection signal VFC2 is not controlled, the voltage detection signal FC2 does not greatly deviate from Vdc / 2, and the inverter can continue to operate without any problem.

  In addition, since the switching pattern is common to all inverter units, only one inverter unit needs to be detected for the FC voltage, so there is an advantage that the voltage detector can be reduced and the cost can be reduced.

  As described above, according to the first embodiment, the cross current immediately after switching can be made zero. Even when resonance occurs between the FC and the cross current suppressing reactor, unlike the method of Patent Document 2, the control does not malfunction and the cross current can be reduced. Further, since only one unit needs to detect the FC voltage, the voltage detector can be reduced and the cost can be reduced.

[Embodiment 2]
FIG. 4 shows a cross current command value calculation unit according to the second embodiment.

  The gate command values Gref1 and Gref2 are input from the FC voltage controller 2 in FIG. 1 (Embodiment 1). The exclusive OR element XOR3 outputs 1 when the gate command values Gref1 and Gref2 are the same.

  The delay adder DelayD5 delays the output signal of the exclusive OR element XOR3 by a falling time for a predetermined time.

The subtracter 13 subtracts the FC voltage detection signal VFC2 of the second inverter unit from the FC voltage detection signal VFC1 of the first inverter unit, and the FC voltage detection signal VFC1 of the first inverter unit and the FC voltage detection signal of the second inverter unit. Is obtained from the voltage detection signal VFC2. The signal of the delay adder DelayD5 is input to the switch SWD. If the switch SWD is 1, the deviation between the FC voltage detection signal VFC1 of the first inverter unit and the FC voltage detection signal VFC2 of the second inverter unit is output. When the input is 0, 0 is output. The comparator cmp1 detects whether or not the FC voltage detection signal VFC1 of the first inverter unit exceeds Vdc / 2. The sign detector 14 outputs 1 if the sign of the inverter unit output current command value (Iinv1 or Iinv / N) is positive, and outputs 0 if it is negative.

  The exclusive OR element XOR4 outputs 1 as an FC control signal only when both the outputs of the comparator comp1 and the sign detector 14 are the same. This FC control signal represents a switching pattern at the time of zero voltage output necessary to bring the voltage detection signal VFC1 of the FC of the first inverter unit close to Vdc / 2.

  If the FC control signal is 1, it indicates that the switching devices T11 and T13 are turned on, and if 0, the switching devices T12 and T14 are turned on. The switch SWE receives an FC control signal. If the input is 1, the switch SWE outputs 1. If the input is 0, the switch SWE outputs -1. The multiplier 15 calculates the product of the output signal of the switch SWD and the output signal of the switch SWE.

  The multiplier 16 calculates the product of the output of the multiplier 15 and the reciprocal of the FC capacity CFC. As the FC capacity CFC here, a rated value described in a capacitor data sheet or the like is used. The multiplier 17 receives the voltage command value Vref, obtains the duty ratio (1- | Vref |) of the zero voltage output, and calculates the product of the reciprocal number and the output of the multiplier 16. Since division when obtaining the duty ratio has a large calculation load, the product of 1+ | Vref | may be obtained by approximation.

  The limiter 18 prevents the multiplier output from becoming abnormally large when the absolute value of the voltage command value Vref is close to 1. That is, the limiter 18 sets the upper and lower limit values for the output of the multiplication value 17 so that the absolute value of the output of the multiplication value 17 is equal to or less than a predetermined value, and outputs the limiter 18. The output of the limiter 18 becomes a cross current command value and is input to the gate command value delay control unit 4 of the first embodiment shown in FIG.

  The second embodiment controls the voltage detection signal VFC2 of the FC of the second inverter unit, which is a function that cannot be realized in the first embodiment, by changing the cross current command value that was fixed to zero in the first embodiment. Added a function to match the FC voltage detection signal VFC1 of 1 inverter unit.

  First, a deviation between the FC voltage detection signal VFC1 of the first inverter unit and the FC voltage detection signal VFC2 of the second inverter unit is calculated. Next, switching is performed by the switch SWD so that the cross current command value is output only during a period in which zero voltage is output and current flows through the FC. A current flows through the FC only when one of the gate command values Gref1 and Gref2 is 1. At this time, the FC voltage can be controlled.

  Therefore, a cross current command value is generated when both the gate command values Gref1 and Gref2 are 0 or 1, and the next switching is urged to generate a cross current as the command value. In the next switching, as long as there is no steep and large voltage command value fluctuation, only one of the gate command values Gref1 and Gref2 is always switched, and a current flows through the FC.

  On the other hand, if either one of the gate command values Gref1 and Gref2 is 1, the cross current command value is set to 0, the current does not flow through the FC, and the FC voltage detection signal VFC2 of the second inverter unit cannot be controlled. In the next switching, no excessive cross current flows.

  Further, the code is switched by the switch SWE according to the switching pattern. For example, consider a case where Vdc / 2> VFC1> VFC2 and the sign of the output current Iinv1 is positive and a zero voltage is output in this state.

  When the switching devices T11, T21, T13, and T23 are turned on, the FC voltage detection signal VFC1 of the first inverter unit is charged and can approach Vdc / 2. When the switching devices T12, T22, T14, and T24 are turned ON, the FC voltage detection signal VFC1 of the first inverter unit is discharged, and conversely, it is separated from Vdc / 2.

  As described above, since charging / discharging is switched according to the switching pattern, it is necessary to appropriately switch the sign of the cross current command value. In the previous example, since Vdc / 2> VFC1, a pattern in which the switching devices T11, T21, T13, and T23 are turned on by the FC voltage control is surely selected in the next switching.

  Therefore, the switch SWE is switched upward to output the cross current command value while keeping the sign as it is. Since VFC1> VFC2, the sign of the cross current command value becomes positive, and an increase in the output current Iinv2 is urged. The FC voltage detection signal VFC2 of the second inverter unit is charged more than the FC voltage detection signal VFC1 of the first inverter unit. Thus, the FC voltage detection signal VFC2 of the second inverter unit can be brought closer to the FC voltage detection signal VFC1 of the first inverter unit.

  Then, 1 / CFC is applied to the deviation after adjusting the sign to obtain a current necessary for adjusting the FC voltage detection signal VFC2 of the second inverter unit. Thereafter, the reciprocal of the duty ratio (1- | Vref |) is applied. If the voltage command value Vref is 0, a zero voltage is always output during one carrier cycle, and all of the generated cross current passes through the FC. However, for example, if Vref = 0.5, the period during which the zero voltage is output for one carrier cycle is halved. It is necessary to flow double current. The above adjustment can be performed by multiplying the reciprocal of the duty ratio of the zero voltage output.

  Finally, when the voltage command value Vref becomes a value close to 1 or −1, the command value is limited by the limiter 18 so as not to flow a cross current, and is output to the gate command value delay control unit 4.

  The delay adder DelayD5 will be described.

  The integrating amplifiers I1 to I8 according to the first embodiment operate after a post-switching dead time + TD has elapsed. When the cross current command value returns to 0 at the timing when the integration amplifiers I1 to I8 are operated, the intentional generation of the cross current is compensated by the integration amplifiers I1 to I8, and the cross current does not flow contrary to the intention. End up. In order to operate normally, it is necessary to hold the cross current command value at the timing when the integrating amplifiers I1 to I8 are operated.

  In order to realize the above, a delay adder DelayD5 is provided. The delay amount of the delay adder DelayD5 needs to be set to a value that gives a little more margin to the dead time + TD, and about dead time × 2 + TD if noise attenuation is considered.

  As an effect of the second embodiment, FC voltages that have shifted due to some temporary disturbance can be made uniform, the generation of resonance current can be suppressed, and the cross current can be reduced.

  When the second embodiment is combined with the first embodiment, if the FC voltage deviation for each unit, which is the cause of resonance, occurs due to sudden disturbance, the FC voltage can be generated by intentionally flowing a cross current. Reduce the deviation. Therefore, resonance can be suppressed and the cross current can be further reduced.

[Embodiment 3]
FIG. 5 shows the gate command value delay control unit 4 of the third embodiment. A description of the same parts as those in the second embodiment is omitted.

  The switch SWE performs the same operation as in the second embodiment. The subtracter 13 subtracts the FC voltage detection signal VFC2 of the second inverter unit from the FC voltage detection signal VFC1 of the first inverter unit, and the FC voltage detection signal VFC1 of the first inverter unit and the FC voltage detection signal of the second inverter unit. Is obtained from the voltage detection signal VFC2.

  The buffer Z-1 stores the deviation output from the subtracter 13. The subtracter 19 subtracts the output of the subtracter 13 and the deviation stored in the buffer Z-1, for example, one cycle before the carrier, and obtains the variation of the deviation between the carrier one cycle.

  The multiplier 20 calculates the product of the deviation variation and the switch SWE. The integration amplifier I9 receives the output of the multiplier 20 and performs an integration operation. The multiplier 21 calculates the product of the output of the integrating amplifier I9 and the inverter unit output current command value (Iinv1 or Iinv / N). The output of the multiplier 21 becomes a cross current command value and is input to the gate command value delay control unit 4 of the first embodiment shown in FIG.

  The third embodiment also adds a function of controlling the voltage detection signal VFC2 of the FC of the second inverter unit by changing the cross current command value that has been fixed to zero in the first embodiment. However, unlike the second embodiment, the capacity deviation (capacity difference) of the FC by the inverter unit is estimated, and a cross current corresponding to the deviation is generated.

  First, a deviation between the FC voltage detection signal VFC1 of the first inverter unit and the FC voltage detection signal VFC2 of the second inverter unit is calculated. Next, the fluctuation within a certain interval is detected by the buffer Z-1 and the subtracter 19. If the cross current suppression control is operating normally, the current passing through the FC of each inverter unit can be regarded as substantially equal. For this reason, if a difference occurs in the voltage fluctuation of the FC, it can be determined that this is because the capacity of the FC is shifted.

  The sign is adjusted using the switch SWE with respect to the difference in voltage fluctuation. The operation of the switch SWE is exactly the same as in the second embodiment. The capacity deviation is estimated by amplifying the voltage fluctuation after adjusting the sign with the integrating amplifier I9, and the obtained capacity deviation is multiplied by the inverter output current command value (Iinv1 or Iinv / N) to obtain the cross current command value. .

  The operation of the third embodiment will be described. For example, when Vdc / 2> VFC1, the output current is a positive value, the FC capacity of the second inverter unit is larger than the FC capacity of the first inverter unit, and the FC voltage detection signal VFC1 of the first inverter unit is the second inverter unit. Consider a case in which the voltage detection signal VFC2 is more likely to fluctuate than the FC voltage detection signal VFC2.

  In this case, the current flows into the FC and charging is promoted, but the increase in the FC voltage detection signal VFC2 of the second inverter unit is smaller than the FC voltage detection signal VFC1 of the first inverter unit, and the voltage fluctuation has a positive value. The switch SWE is also positive, and a positive value is input to the integrating amplifier I9.

  As a result, the output value of the integrating amplifier I9 gradually increases, the cross current command value gradually increases, and the increase of the output current Iinv2 is promoted. Then, when the fluctuation of the voltage detection signal VFC1 of the FC of the first inverter unit becomes equal to the fluctuation of the voltage detection signal VFC2 of the FC of the second inverter unit, the increase in the output value of the integrating amplifier I9 is stopped.

  The third embodiment also has an effect of reducing the cross current generated due to the voltage drop deviation of the switching device. For example, when Vdc / 2> VFC1, the output current is a positive value, the FC capacity of the first inverter unit is equal to the FC capacity of the second inverter unit, but the voltage drop of the switching device of the second inverter unit is lower than that of the first inverter unit. Consider a case where a large current is difficult to pass.

  At this time, even if the cross current suppression control operates normally, the output current of the second inverter unit is smaller than that of the first inverter unit. Although the FC is charged, the voltage detection signal VFC1 of the FC of the first inverter unit increases more than the voltage detection signal VFC2 of the FC of the second inverter unit, and the fluctuation becomes a positive value. Since the switch SWE is also positive, a positive value is input to the integrating amplifier I9, the cross current command value is gradually increased, and an increase in the output current Iinv2 is prompted. Since the FC capacities are the same, the increase in the output value of the integrating amplifier I9 stops when the output current Iinv1 and the output current Iinv2 coincide.

  Unlike the second embodiment, the third embodiment is not limited to the period in which zero voltage is output, but constantly changes the cross current. Thereby, there is an effect of reducing the cross current generated due to the voltage drop deviation of the switching device.

  For example, when a switching device with a small voltage drop deviation can be used in all units, as shown in FIG. 6, an exclusive OR element XOR3, a delay adder D5, and a switch SWD are added as in the second embodiment. Thus, it is possible to allow a cross current to flow only during a period during which zero voltage is output. At this time, the place where the switch SWD is added needs to be after the integrating amplifier I9.

  Specifically, as shown in FIG. 6, the exclusive OR element XOR3 outputs 1 when the gate command values Gref1 and Gref2 are the same. The delay adder DelayD5 delays the output signal of the exclusive OR element XOR3 for a predetermined time only at the falling time. The switch SWD outputs the output of the multiplier 21 if the output of the delay adder DelayD5 is 1, and outputs 0 if the output of the delay adder DelayD5 is 0. The output of this switch SWD becomes the cross current command value.

  As an effect of the third embodiment, the FC voltage deviation can be made zero with respect to a steady disturbance such as a difference in FC capacity or a voltage drop in the switching device, and the resonance is suppressed and the cross current is reduced. can do. However, there is no function for aligning FC voltages that have shifted due to temporary disturbances as in the second embodiment.

  By combining the third embodiment with the first embodiment, a difference in the FC voltage variation of each inverter unit is detected, and a cross current is intentionally generated so that the difference becomes zero. Therefore, the FC voltage shift caused by the steady disturbance such as the FC capacity shift and the voltage drop shift of the switching device can be made zero, and the cross current can be reduced. Although it takes a while to adjust the cross current, it can be adjusted automatically if a certain amount of current flows, and it can follow temperature changes and aging of the voltage drop of the FC capacity and switching devices. it can.

[Embodiment 4]
FIG. 7 shows a cross current suppression control unit according to the fourth embodiment. In the fourth embodiment, the cross current command values of the second and third embodiments are simply added to form a new cross current command value.

  In the second embodiment, FC voltages that have been shifted due to a temporary disturbance can be made uniform. On the other hand, the FC voltage shift can be reduced for a steady disturbance, but cannot be reduced to zero. Resonance will occur. On the other hand, Embodiment 3 can reversely compensate for a steady disturbance, but if a temporary disturbance occurs, the cross current increases.

  Therefore, by adding the cross current command values of the second embodiment and the third embodiment, it is possible to reduce the cross current corresponding to both disturbances.

  In the second, third, and fourth embodiments, a cross current that is proportional to the capacity displacement of the FC is intentionally flowed. Therefore, the cross current other than the resonance component naturally increases. However, since the resonance current generated between the FC and the cross current suppressing reactor can be suppressed, the cross current can be suppressed to a smaller value when the method of Patent Document 2 is applied as it is or when compared with the first embodiment.

  By combining the fourth embodiment with the first embodiment, it is possible to make the deviation of the FC voltage caused by both the sudden disturbance and the steady disturbance zero, so that the cross current can be further reduced.

  Specifically, as shown in FIG. 7, the exclusive OR element XOR3 outputs 1 when both the gate command values Gref1 and Gref2 are the same. The delay adder DelayD5 delays the output signal of the exclusive OR element XOR3 for a predetermined time only at the fall time.

The subtracter 13 subtracts the FC voltage detection signal VFC2 of the second inverter unit from the FC voltage detection signal VFC1 of the first inverter unit, and the FC voltage detection signal VFC1 of the first inverter unit and the FC voltage detection signal of the second inverter unit. Is obtained from the voltage detection signal VFC2. The signal of the delay adder DelayD5 is input to the switch SWD. If the input is 1, the deviation between the FC voltage detection signal VFC1 of the first inverter unit and the FC voltage detection signal VFC2 of the second inverter unit is output. If it is 0, 0 is output. The comparator cmp1 detects whether or not the voltage detection signal VFC1 of the FC of the first inverter unit exceeds Vdc / 2. The sign detector 14 outputs 1 if the sign of the inverter unit output current command value (Iinv1 or Iinv / N) is positive, and outputs 0 if it is negative.

  The exclusive OR element XOR4 outputs 1 as an FC control signal only when both the outputs of the comparator comp1 and the sign detector 14 are the same. The switch SWE receives an FC control signal. If the input is 1, the switch SWE outputs 1. If the input is 0, the switch SWE outputs -1. The multiplier 15 calculates the product of the output signal of the switch SWD and the output signal of the switch SWE.

  The multiplier 16 calculates the product of the output of the multiplier 15 and the reciprocal of the FC capacity CFC. The multiplier 17 receives the voltage command value Vref, obtains the duty ratio (1- | Vref |) of the zero voltage output, and calculates the product of the reciprocal number and the output of the multiplier 16. Since division when obtaining the duty ratio has a large calculation load, the product of 1+ | Vref | may be obtained by approximation.

  The limiter 18 prevents the multiplier output from becoming abnormally large when the absolute value of the voltage command value Vref is close to 1.

  The buffer Z-1 stores the deviation output from the subtracter 13. The subtracter 19 subtracts the output of the subtracter 13 and the deviation stored in the buffer Z-1, for example, one cycle before the carrier, and obtains the variation of the deviation between the carrier one cycle.

  The multiplier 20 calculates the product of the deviation variation and the switch SWE. The integration amplifier I9 receives the output of the multiplier 20 and performs an integration operation. The multiplier 21 calculates the product of the output of the integrating amplifier I9 and the inverter unit output current command value (Iinv1 or Iinv / N).

  The adder 22 adds the outputs of the limiter 18 and the multiplier 21. The output of the adder 22 becomes a cross current command value.

  The above embodiment has been described by taking the inverter unit 2 in parallel as an example. However, it can be expanded to an arbitrary number of inverter units of three or more. As an example, FIG. 8 shows a control block of the kth inverter unit when the first embodiment is expanded in parallel to N or more inverter units. The gate command values Gref1 and Gref2 are output from the FC voltage controller as in FIG.

  The inverter unit output current command value (Iinv1 or Iinv / N) is compared with its own output current Iinvk and input to the PI amplifier having the same configuration as in FIG. 1 to obtain the delay command value and delay it to the gate command values Gref1 and Gref2. The gate signals Tk1, Tk2, Tk3, and Tk4 to which the dead time is added are input to the k-th inverter unit. The cross current command value k is zero.

  9 to 12 show the gate command value delay control unit 4 of the k-th inverter unit when Embodiments 2 to 4 are expanded in parallel with N inverter units. The reference FC voltage VFC1 is compared with its own FC voltage VFCk, and the obtained deviation performs the same calculation as in FIG. The result thus obtained is a cross current command value k, which is input in FIG.

  With the above configuration, even in a parallel configuration of three or more inverter units, the resonance current due to the FC and the cross current control reactor can be reduced, and the cross current can be reduced.

  However, in Embodiments 2 to 4, an FC voltage detector is required in all inverter units. The above method can be combined with Patent Document 4 to further reduce the cross current.

DESCRIPTION OF SYMBOLS 1 ... PWM modulator 2 ... FC voltage controller 3a-3d ... Dead time processor 4 ... Gate delay command value calculating part 5 ... Comparator 6 ... Sign detector 7a-7d ... NOT circuit 8 ... Adder 9 ... Subtractor DESCRIPTION OF SYMBOLS 10 ... Adder 11a-11d ... AND element 12a-12d ... Delay adder 13 ... Subtractor 14 ... Sign detector 15 ... Multiplier 16 ... Multiplier 17 ... Multiplier 18 ... Limiter 19 ... Subtractor 20 ... Multiplier 21 ... multiplier 22 ... adder

Claims (9)

A cross current suppression control device for suppressing a cross current in a power conversion circuit in which two or more inverter units are connected in parallel to a DC voltage source,
The inverter unit is interposed between first to fourth switching devices sequentially connected in series, a common connection point of the first and second switching devices, and a common connection point of the third and fourth switching devices. And a flying capacitor
The cross current suppression control device is
A first rising delay adder for adding a fixed rising gate delay command value to a first gate command value for turning on / off the first and fourth switching devices generated by a PWM modulator and an FC voltage controller; A second rising delay adder for adding a fixed rising gate delay command value to a second gate command value for turning on and off the second and third switching devices generated by the PWM modulator and the FC voltage controller A first falling delay adder that adds a fixed falling gate delay command value to the first gate command value, and a fixed falling gate delay command value to the second gate command value A second falling delay adder is provided in the first inverter unit,
A proportional amplifier that multiplies the gain by using a value obtained by subtracting the detected inverter unit output current value from the value obtained by adding the cross current command value to the inverter unit output current command value, and the first gate to which the cross current is input. After the command value changes from 0 to 1, and when the sign of the inverter unit output current command value is positive, the cross current is input, and the first gate command value is changed from 0 to 1. And the second integration amplifier that operates when the sign of the inverter unit output current command value is negative, after the cross current is input and the first gate command value changes from 1 to 0, and A third integrating amplifier that operates when the sign of the inverter unit output current command value is positive, and after the cross current is input and the first gate command value changes from 1 to 0 And a fourth integrating amplifier that operates when the sign of the inverter unit output current command value is negative, and after the cross current is input and the second gate command value changes from 0 to 1, and the inverter unit output A fifth integrating amplifier that operates when the sign of the current command value is positive; and after the cross current is input and the second gate command value changes from 0 to 1, and the sign of the inverter unit output current command value is A sixth integrating amplifier that operates when negative, and a second operational amplifier that operates when the cross current is input and the second gate command value changes from 1 to 0 and when the sign of the inverter unit output current command value is positive 7 integral amplifier and the 8th product that operates when the cross current is input and the second gate command value changes from 1 to 0 and when the sign of the inverter unit output current command value is negative And when the sign of the inverter unit output current command value is positive, a value obtained by adding the output of the proportional amplifier and the output of the first integrating amplifier and multiplying by −1 is a first rising gate. When the sign of the inverter unit output current command value is negative, a value obtained by adding the output of the proportional amplifier and the output of the second integration amplifier and multiplying by -1 is used as the delay command value. When the sign of the inverter unit output current command value is positive, a value obtained by adding the output of the proportional amplifier and the output of the third integration amplifier is used as a second rising gate delay command value, and the inverter unit output current When the sign of the command value is negative, a value obtained by adding the output of the proportional amplifier and the output of the fourth integration amplifier is set as a second rising gate delay command value, and the inverter unit When the sign of the output current command value is positive, a value obtained by adding the output of the proportional amplifier and the output of the fifth integrating amplifier and multiplying by −1 is set as the first falling gate delay command value, and the inverter unit When the sign of the output current command value is negative, a value obtained by adding the output of the proportional amplifier and the output of the sixth integral amplifier and multiplying by -1 is set as the first falling gate delay command value, and the inverter unit output When the sign of the current command value is positive, the sum of the output of the proportional amplifier and the output of the seventh integration amplifier is used as the second falling gate delay command value, and the sign of the inverter unit output current command value is negative. A gate delay command value calculation unit that outputs a value obtained by adding the output of the proportional amplifier and the output of the eighth integration amplifier as a second falling gate delay command value, and the first rising gate A third rise delay adder for adding a delay command value to the first gate command value; a fourth rise delay adder for adding the second rise gate delay command value to the second gate command value; A third falling delay adder for adding a falling gate delay command value to the first gate command value; and a fourth rising edge for adding the second falling gate delay command value to the second gate command value. A cross current suppression control device comprising: a falling delay adder provided in each of the second to Nth (N = 2 or larger integer) inverter units.   2. The cross current suppression control apparatus according to claim 1, wherein when the absolute value of the inverter unit output current command value is equal to or less than a threshold value, updating of the first to eighth integrating amplifiers is stopped.   The cross current control control device according to claim 1, wherein the inverter unit output current command value is a value obtained by dividing a total value of output current detection values of all inverter units by the number of the inverter units.   The cross current control control device according to claim 1 or 2, wherein the inverter unit output current command value is an output current detection value of the first inverter unit.   5. The cross current suppression control apparatus according to claim 1, wherein all inverter units have a cross current command value = 0. A first exclusive OR element that outputs 1 when both the first gate command value and the second gate command value are the same;
A delay adder for delaying the output signal of the first exclusive OR element by a falling time for a predetermined time;
A subtractor for calculating a deviation between the voltage detection signal of the flying capacitor of the first inverter unit and the voltage detection signal of the flying capacitor of the second to Nth inverter units;
A first switch that outputs the output of the subtractor if the output of the delay adder is 1, and outputs 0 if the output of the delay adder is 0;
A sign detector for detecting the sign of the inverter unit output current command value;
A comparator that outputs 1 if the voltage detection signal of the flying capacitor of the first inverter unit is greater than ½ of the voltage of the DC voltage source;
A second exclusive OR element that outputs 1 when both the output of the sign detector and the comparator are the same;
A second switch that outputs 1 if the output of the second exclusive OR element is 1 and outputs -1 if the output of the second exclusive OR element is 0;
A first multiplier for multiplying the outputs of the first switch and the second switch;
A second multiplier that multiplies the output of the first multiplier by the reciprocal of the capacitance of the flying capacitor;
A third multiplier that multiplies the output of the second multiplier by the inverse of the duty ratio of the zero voltage output;
A limiter that provides upper and lower limits on the output of the third multiplier,
5. The cross current suppression control device according to claim 1, wherein an output of the limiter is the cross current command value. A sign detector for detecting the sign of the inverter unit output current command value;
A comparator that outputs 1 if the voltage detection signal of the flying capacitor of the first inverter unit is greater than ½ of the voltage of the DC voltage source;
An exclusive OR element that outputs 1 when the outputs of the sign detector and the comparator are both the same;
A switch that outputs 1 if the output of the exclusive OR element is 1 and outputs -1 if the output of the exclusive OR element is 0;
A first subtractor for calculating a deviation between the voltage detection signal of the first inverter unit and the voltage detection signals of the second to Nth inverter units;
A buffer for storing the output of the first subtracter before one operation cycle;
A second subtractor for subtracting the output of the buffer from the output of the first subtractor;
A first multiplier for multiplying the output of the second subtracter by the output of the switch;
An integrator for integrating the output of the first multiplier;
A second multiplier for multiplying the output of the integrator by the inverter unit output current command value;
The cross current control device according to any one of claims 1 to 4, wherein the output of the second multiplier is the cross current command value. A sign detector for detecting the sign of the inverter unit output current command value;
A comparator that outputs 1 if the voltage detection signal of the flying capacitor of the first inverter unit is greater than ½ of the voltage of the DC voltage source;
A second exclusive OR element that outputs 1 when both the output of the sign detector and the comparator are the same;
A second switch that outputs 1 if the output of the second exclusive OR element is 1 and outputs -1 if the output of the second exclusive OR element is 0;
A first subtractor for calculating a deviation between the voltage detection signal of the first inverter unit and the voltage detection signals of the second to Nth inverter units;
A buffer for storing the output of the first subtracter before one operation cycle;
A second subtractor for subtracting the output of the buffer from the output of the first subtractor;
A first multiplier for multiplying an output of the second subtracter by an output of the second switch;
An integrator for integrating the output of the first multiplier;
A second multiplier for multiplying the output of the integrator by the inverter unit output current command value;
A first exclusive OR element that outputs 1 when both the gate command value for turning on / off the first and fourth switching devices and the gate command value for turning on / off the second and third switching devices are the same;
A delay adder for delaying the output signal of the first exclusive OR element by a falling time for a predetermined time;
A first switch that outputs the output of the second multiplier if the output of the delay adder is 1, and outputs 0 if the output of the delay adder is 0;
The cross current suppression control device according to claim 1, wherein the output of the first switch is the cross current command value. A sign detector for detecting the sign of the inverter unit output current command value;
A comparator that outputs 1 if the voltage detection signal of the flying capacitor of the first inverter unit is greater than ½ of the voltage of the DC voltage source;
A second exclusive OR element that outputs 1 when both the output of the sign detector and the comparator are the same;
A second switch that outputs 1 if the output of the second exclusive OR element is 1 and outputs -1 if the output of the second exclusive OR element is 0;
A first subtractor for calculating a deviation between a voltage detection signal of the first inverter unit and a voltage detection signal of the second to Nth inverter units;
A buffer for storing the output of the first subtracter before one operation cycle;
A second subtractor for subtracting the output of the buffer from the output of the first subtractor;
A first multiplier for multiplying an output of the second subtracter by an output of the second switch;
An integrator for integrating the output of the first multiplier;
A second multiplier for multiplying the output of the integrator by the inverter unit output current command value;
A first exclusive OR element that outputs 1 when the gate command value for turning on / off the first and fourth switching devices and the gate command value for turning on / off the second and third switching devices are the same;
A delay adder for delaying the output signal of the first exclusive OR element by a falling time for a predetermined time;
A first switch that outputs the output of the first subtractor if the output of the delay adder is 1, and outputs 0 if the output of the delay adder is 0;
A third multiplier for multiplying the output of the first switch and the output of the second switch;
A fourth multiplier for multiplying the output of the third multiplier by the reciprocal of the capacitance of the flying capacitor;
A fifth multiplier for multiplying an output of the fourth multiplier by a reciprocal of a duty ratio of a zero voltage output;
A limiter for setting an upper limit on the output of the fifth multiplier;
An adder for adding the output of the second multiplier and the output of the limiter;
And the output of the adder is used as a cross current command value.

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