JP2008092651A - Power converter and power conversion system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To inhibit a ripple current from being increased, and reduce a switching loss of a power semiconductor in a power converter with a flying capacitor system. <P>SOLUTION: The power converter is provided with: an inverter main circuit for converting DC power supplied from DC intermediate circuits into AC power; a PWM control circuit for generating and outputting a PWM signal; and a voltage instruction generating circuit for generating a voltage instruction required for generating the PWM signal. The inverter main circuit (10) is provided with: switching elements (SW1a-SW4a) connected between a pair of positive and negative DC buses (11, 12) composing the DC intermediate circuits (Cp, Cn) in series; and a capacitor (Ca) connected between the connection end of the switching elements (SW1a, SW2a) and the connection end of the switching elements (SW3a, SW4a) in each phase. The DC power accumulated in the capacitor (Ca) is supplied from each of the DC intermediate circuits (Cp, Cn). <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a power conversion device, and more particularly, to a power conversion device including a flying capacitor type inverter circuit and a power conversion system configured using the power conversion device.

  A power conversion device including a flying capacitor type inverter circuit is disclosed in, for example, Non-Patent Document 1 and Non-Patent Document 2 below, and can effectively reduce a ripple component included in an output current. It is attracting attention as a device.

Seed Seed Fazel. "Comparison of Power Semiconductor Utilities, Losses and Harmonic Spectra of State-of-the-Art 4.16kV Multi-Level Voltage Source5D. In-Dong Kim "A Generalized Underland Subber for Flying Capacitor Multilevel Inverter and Converter" IEEE Transactions on Industrial Electronics. 51, no. 6 December 2004

  However, the power converters disclosed in Non-Patent Documents 1 and 2 have a problem that the ripple current of a capacitor used as a flying capacitor increases when the output voltage is small or when the load power factor is poor. . There is also a problem that the switching loss of the power semiconductor is large.

  The present invention has been made in view of the above, and even when the output voltage is small or the load power factor is bad, an increase in the ripple current of the capacitor used as the flying capacitor can be suppressed, Moreover, it aims at providing the power converter device which can reduce the switching loss of a power semiconductor, and the power converter system comprised using this power converter device.

  In order to solve the above-described problems and achieve the object, a power conversion device according to the present invention includes a first power storage unit, and a DC intermediate unit that supplies DC power stored in the first power storage unit. A circuit, an inverter main circuit for converting DC power supplied from the DC intermediate circuit into AC power, a PWM control circuit for generating and outputting a PWM signal for PWM control of the inverter main circuit, and generation of the PWM signal A voltage command generation circuit that generates a voltage command necessary for output to the PWM control circuit, and the inverter main circuit is connected between a pair of positive and negative DC buses constituting the DC intermediate circuit. The first to fourth switching elements connected in series, the second switching element connected between the connection end of the first and second switching elements and the connection end of the third and fourth switching elements. Comprising a power storage means, to each phase, the DC power accumulated in the second power storage unit, characterized in that it is supplied from the DC intermediate circuit.

  According to the power conversion device of the present invention, the first to fourth switching elements connected in series between the pair of positive and negative DC buses of the DC intermediate circuit having the second power storage means, the first and second The second power storage means connected between the connection ends of the switching elements and the connection ends of the third and fourth switching elements is provided for each phase, and direct current power to the second power storage means is provided. Since the control as supplied from the DC intermediate circuit is performed, an increase in the ripple current flowing through the first power storage means and the second power storage means can be suppressed, and the switching loss of the power semiconductor can be reduced. The effect that it can reduce is acquired.

  Hereinafter, embodiments of a power conversion device according to the present invention will be described in detail with reference to the drawings. In addition, this invention is not limited by the following embodiment.

Embodiment 1 FIG.
(Configuration of power converter)
First, the structure of the power converter device concerning Embodiment 1 is demonstrated with reference to FIGS. 1-3.

  FIG. 1 is a diagram illustrating a configuration example of an inverter main circuit that constitutes a power conversion device according to a first embodiment of the present invention, and illustrates a power conversion device configured for driving a motor that drives a motor (IM). Yes. The inverter main circuit 10 of the power conversion device shown in the figure includes switching elements (SW1a to SW4a), switching elements (SW1b to SW4b), and switching elements (SW1c to SW4c), and these switching elements are each phase (a phase). , B-phase, c-phase) are connected in series, and the switching element group for each phase is a DC bus 11 that is the positive DC bus of the DC intermediate circuit (Cp, Cn). They are connected in parallel with the DC bus 12 which is a negative DC bus. In addition, the connection point of the first switching element (SW1a for the a phase) and the second switching element (SW2a for the a phase) constituting each switching element group, and the third switching element (in the a phase) If there is, a voltage clamp circuit (Ca) is connected between the connection point of SW3a) and the connection point of the fourth switching element (SW4a in the case of the a phase). Further, the control terminals of the switching elements include control input terminals (S1a to S4a, S1b to S4b, S1c to S4c) and output terminals (a1, b1, power supply for supplying electric power to an electric motor (IM) as a load). c1) is provided.

  Note that the DC intermediate circuit mentioned above is a general term for circuit units connected to the DC buses 11 and 12 in the power converter, and in FIG. 1, a capacitor ( Cp, Cn). The voltage clamp circuit is a circuit section for clamping a predetermined voltage between the predetermined switching elements in each of the switching element groups described above to a predetermined voltage. In the configuration of FIG. 1, the voltage clamping circuit is a main component of the circuit section. Are represented by capacitors (Ca, Cb, Cc). These capacitors (Ca, Cb, Cc) are configured such that the potentials at both ends thereof are variably controlled by turning on and off predetermined switching elements. The characteristics are called flying capacitors. Yes. Moreover, the power converter device provided with these flying capacitors is classified as a power converter device of a flying capacitor system. It goes without saying that the DC intermediate circuit capacitors (Cp, Cn) and the voltage clamp circuit capacitors (Ca, Cb, Cc) can be replaced by other components having the ability to store DC power.

  In the configuration of FIG. 1, the IGBT is shown as being used as a switching element of the inverter main circuit. However, for example, a MOSFET, a GTO, or a combination of these elements may be used.

  FIG. 2 is a diagram illustrating a configuration example of a rectifier circuit used in the power conversion device according to the first embodiment of the present invention. The rectifier circuit shown in the figure includes a transformer (Tr1), a rectifier (Rec1), a charging current limiting resistor (R1), a thyristor (Thy1), and the like. The charging current limiting resistor (R1) is a resistance element for limiting the charging current to the capacitors (Cp, Cn, Ca to Cc), and the thyristor (Thy1) is the charging current limiting resistor (R1) after completion of the initial charging. Is a control element for short-circuiting. In addition, this rectifier circuit has a function of maintaining a constant voltage (Vdc: 2 × Edc) during operation of the capacitors (Cp, Cn) constituting the DC intermediate circuit, and capacitors (Ca to Cc) constituting the voltage clamp circuit. ) Of the respective voltages (Vca to Vcc) and a function of keeping the voltage during operation constant.

  FIG. 3 is a diagram illustrating a configuration example of a PWM control circuit (for one phase) included in the power conversion device according to the first embodiment of the present invention. The PWM control circuit shown in the figure includes a PWM signal generation first circuit 21 and a PWM signal generation second circuit 22 for generating a PWM signal.

  The PWM signal generation first circuit 21 is on the input end side, and the input end thereof is the input end of the voltage command Vref_a, the input end of the two sets of carrier wave signals (Vcp, Vcm), and the both end voltages of the DC intermediate circuit (that is, the DC bus). Voltage between 11 and 12 (hereinafter referred to as “DC intermediate circuit voltage”) Vdc input terminal, 50% value input terminal of DC intermediate circuit voltage (Vdc), current output to the a phase of the motor as a load (hereinafter referred to as “DC intermediate circuit voltage”) "A-phase output current" or simply "output current") input terminal to which a current equivalent to (same polarity) is input, voltage clamp circuit voltage (hereinafter referred to as "voltage clamp circuit voltage") input terminal, An input terminal for a set value (Vhs) of 1, an input terminal for a predetermined second set value (Vhr), an input terminal for a predetermined third set value (Vls), an input terminal for a predetermined fourth set value (Vlc), And clock signal input It has 12 input terminals.

  On the other hand, the PWM signal generation second circuit 22 is on the output end side, and the output end has PWM signal output ends (S16a to S4a) for PWM control of the a-phase switching elements (SW1a to SW4a), respectively. is doing. The circuit shown in FIG. 3 shows a configuration for one phase, and it goes without saying that this circuit is provided for each phase.

(Operation of power converter)
Next, the operation of the power conversion apparatus according to the first embodiment will be described with reference to FIGS. In addition, FIG. 4 is a figure which shows the example of a switching waveform of the power converter device concerning Embodiment 1 of this invention.

  The capacitors (Cp, Cn) of the DC intermediate circuit are charged to the rated DC voltage (Vdc = 2 × Ed) by the rectifier circuit of FIG. The capacitor (Ca) of the voltage clamp circuit has a function of clamping the voltage applied to the electric motor (IM) to Ed. Here, the PWM control circuit shown in FIG. 3 receives the voltage command (Vref_a) shown in (1) of FIG. 4 and two sets of carrier waves (Vcp, Vcn) as input signals, and (2)-( The switching signal shown in 5) is output from its own output terminal (S1a to S4a). These switching signals are input to the control terminals (S1a to S4a) of the power semiconductor switches (SW1a to SW4a) in FIG. On the other hand, switching from the output terminal (a1) to the input terminal (a2) of the electric motor (IM) is input to the DC intermediate circuit voltage (+ 2Ed), the voltage clamp circuit voltage (Ed), and the control terminals (S1a to S4a). An output current (for a phase) determined based on the action of the signal is output. The waveform at this time is a voltage of three gradations (Va: a-phase output voltage) of (+ Ed, 0, −Ed) in which the fundamental wave voltage is proportional to the voltage command (Vref_a) as shown in (6) of FIG. ), And desired electric power is supplied to the electric motor (IM).

  In the present embodiment, a more detailed description of the creation method according to the voltage command (Vref_a) is omitted. To give an example, for example, when vector control is performed on a power conversion device for driving an electric motor, the a-phase output current (Ia) is controlled to be equal to a predetermined current signal (Iref_a). The voltage command (Va) corresponds to this voltage command (Vref_a).

  In the above description, regarding the inverter main circuit configuration (FIG. 1) and the PWM control circuit (FIG. 3), the configuration of one phase (a phase) is shown, but the other phases (b phase, c phase) It becomes the same composition about. The DC intermediate circuit is composed of two positive and negative capacitors (Cp, Cn) and the intermediate potential is grounded, but this is for convenience of explanation, and it is composed of a single capacitor. Moreover, even if it is composed of two capacitors, the intermediate potential is often ungrounded.

  In the above description, the case where the power conversion device is configured for driving the electric motor has been described. However, when the power conversion device is used for power system stabilization, the output terminal (a1, b1, c1) has an electric motor ( Needless to say, a commercial power supply (CM) is connected instead of (IM). It is widely known that the voltage command (Va) in this case is given as an output of a current control system in power system stabilization control, for example.

  In the above description, the power conversion device is configured with three phases, but is not limited to three phases, and can be configured as a two-phase power conversion device or a multiphase power conversion device with four or more phases. Needless to say.

(Control algorithm of PWM control circuit)
Next, a control algorithm of the PWM control circuit shown in FIG. 3 will be described. Note that the PWM control circuit of FIG. 3 shows an example in which various logic elements are used to realize the control algorithm according to the first embodiment.

  In FIG. 3, the PWM signal generation first circuit 21 determines the polarity of the voltage command (Vref_a) corresponding to the a-phase output voltage (Va) controlled according to the power to be supplied to the motor. (Cmp1), a second comparator (Cmp2) that receives the positive carrier wave (Vcp) and the voltage command (Vref_a) as input, and a negative carrier wave (Vcn) and a voltage command (Vref_a). A third comparator (Cmp3) that determines the magnitude as an input, and the voltage clamp circuit voltage (Vca) is the sum of the 50% value of the DC intermediate circuit voltage (Vdc) and the predetermined first set value (Vhs). The fourth comparator (Cmp4) for detecting whether or not the voltage exceeds the voltage clamp circuit voltage (Vca) is greater than the sum of the 50% value of the DC intermediate circuit voltage (Vdc) and the predetermined second set value (Vhr). Decline The fifth comparator (Cmp5) for detecting whether or not the voltage clamp circuit voltage (Vca) has reduced the sum of the 50% value of the DC intermediate circuit voltage (Vdc) and the predetermined third set value (Vls) A sixth comparator (Cmp6) for detecting whether or not, and whether or not the voltage clamp circuit voltage (Vca) exceeds the sum of the 50% value of the DC intermediate circuit voltage and the predetermined fourth set value (Vlr) A seventh comparator (Cmp7) for detecting whether or not the voltage clamp circuit voltage (Vca) based on the output of the fourth comparator (Cmp4) and the output of the fifth comparator (Cmp5). Is based on the outputs of the first storage device (FF1), the sixth comparator (Cmp6), and the seventh comparator (Cmp7) that store a state in which the DC intermediate circuit exceeds 50% of the DC intermediate circuit. The voltage of the voltage clamp circuit is 5 of the DC intermediate circuit. When the second storage device (FF2) that stores the state lower than% and the first storage device (FF1) operate, the above state is stored while the second storage device (FF2) A third storage device (FF3) that releases the above state when operated is provided.

  The PWM signal generation second circuit 22 is configured as a circuit unit having the following functions. That is, the polarity of the voltage Vref_a (positive polarity: 1, negative polarity: 0), the polarity of the current Ia (positive polarity: 1, negative polarity: 0), and the polarity of the third storage device (FF3) (first storage device) (FF1) in operation: 1, second storage device (FF2) in operation: 0) exclusive OR is 0, or first storage device (FF1) is inoperative (non-operation: 0) When the second memory device (FF2) is also non-operation (non-operation: 0), the power semiconductor (SW1a) is driven by the output of the first comparator (Cmp1), and the power semiconductor (SW2a) The second semiconductor (Cmp2) and the third comparator (Cmp3) are driven by the logical sum output, and the power semiconductor (SW3a) is connected to the reverse polarity of the second comparator (Cmp2) and the third comparator (Cmp3). ) And the power semiconductor (SW4a) is driven by the first comparator (C4). It is driven by the output of the reverse polarity of mp1).

  Contrary to the above case, the polarity of the voltage Vref_a (positive polarity: 1, negative polarity: 0), the polarity of the current Ia (positive polarity: 1, negative polarity: 0), and the polarity of the third storage device (FF3) The exclusive OR of (when the first storage device (FF1) is operating: 1, when the second storage device (FF2) is operating: 0) is 1, and the first storage device (FF1) is not operating. (Non-operation: 0) or when the second memory device (FF2) is non-operation (non-operation: 0), the power semiconductor (SW1a) is connected to the second comparator (Cmp2) and the third comparator ( Cmp3) is driven by the logical sum output, the power semiconductor (SW2a) is driven by the output of the first comparator (Cmp1), and the power semiconductor (SW3a) is the output of the reverse polarity of the first comparator (Cmp1). The power semiconductor (S4a) is driven by the reverse polarity of the second comparator (Cmp2) and the third comparator (Cmp2). It is driven by the output of the logical sum of the reverse polarity of mp3).

  As a result of the above operation, in the inverter main circuit of the power converter, the switching states of the power semiconductor switches (SW1a to SW4a) are, for example, the DC intermediate circuit voltage (Vdc) and the voltage clamp circuit voltage (Vca). When the ratio is 2: 1, PWM control is performed with the PWM waveforms shown in (2) to (5) of FIG.

  Further, when the voltage ratio between the DC intermediate circuit voltage (Vdc) and the voltage clamp circuit voltage (Vca) changes from 2: 1, for example, PWM control is performed with the PWM waveforms shown in (2) to (5) of FIG. Become so. By these PWM controls, the voltage ratio between the DC intermediate circuit voltage (Vdc) and the voltage clamp circuit voltage (Vca) is controlled to maintain this voltage ratio of 2: 1.

(The simulation result in the power converter device of Embodiment 1)
Next, simulation results in the power conversion apparatus according to Embodiment 1 will be described with reference to FIGS. 6 to 10. Here, FIG. 6 is a figure which shows the simulation result in the power converter device of Embodiment 1 of this invention, and the simulation result concerning a prior art is shown in FIG. 7 for the comparison. The simulation result of FIG. 7 is a case where control is performed based on the PWM waveform shown in FIG. 8, and the PWM waveform at this time is generated using, for example, a conventional PWM control circuit as shown in FIG. Is done. FIG. 10 is a diagram showing a comparison result with the related art relating to the ripple current flowing in the DC intermediate circuit and the voltage clamp circuit.

(Simulation conditions-various parameters in the inverter main circuit)
In the present embodiment, the following values are used as various parameters in the inverter main circuit when performing the simulation.
(1) Output frequency f = 50 Hz of power converter
(2) Carrier frequency Fc = 10 kHz
(3) Output voltage (phase voltage) Va = 115 Vrms (corresponding to a line voltage of 200 Vrms)
(4) Output current (phase current) Ia = 100 Arms
(5) DC intermediate circuit voltage Vdc = 2 × Ed = 300V (rated voltage)
(6) Capacitor capacitance Ca of the voltage clamp circuit = 13.8 mF
(7) Electric motor (load) internal impedance Z = 0.367mH + 0.0115Ω (star connection conversion)
(8) Current phase 30 ° (phase lag)

Among the above, when determining the capacitor capacity of the voltage clamp circuit, the concept of the equivalent capacity of the voltage clamp circuit can be used in the comparison with the output capacity of the power converter. Here, the equivalent capacity of the voltage clamp circuit and the output capacity of the power converter are given by the following equations.
Equivalent capacity = 2 × π × f × (capacitor capacity) × (power converter output voltage) ^ 2
Output capacity = √ (3) x (rated voltage) x (rated current)

  In addition, it is preferable to use a capacitor having a capacitance value such that the equivalent capacitance represented by the above formula is 20 times or less of the output capacitance of the power converter, and a capacitance such that the equivalent capacitance is 5 to 10 times the output capacitance. More preferably, the capacitor has a value.

  For example, if the output capacity of the power converter is 38 kVA, the output voltage (Va) of the power converter is 220 V, the output current (Ia) is 100 Arms, and the capacitor capacity of the voltage clamp circuit (Ca) is 13.8 mF in this case The equivalent capacitance of the voltage clamp circuit is 2 × 3.14 × 60 × 13.8 mF × 220V × 220V = 250 kVA, and the capacitor capacity is 6.6 times the output capacity 38 kVA of the power converter. Become.

(Simulation conditions-Setting parameters in the PWM control circuit)
In the present embodiment, the following values are used as setting parameters in the PWM control circuit when performing simulation.
(1) First set value Vhs = 0.9V
(2) Second set value Vhr = 0V
(3) Third set value Vls = −0.9V
(4) Fourth set value Vlr = −0V

(simulation result)
In FIG. 6, for example, power is stored in the voltage clamp circuit (Ca) around 4 ms, and the power semiconductor switch (SW1a or SW4a) while the voltage (Vca) is rising (the portion indicated by K1 or K2). It turns out that either of these is turned on, and the power semiconductor switches (SW2a and SW3a) are switched at the carrier frequency (equivalent to 10 kHz). In addition, while the power is discharged from the voltage clamp circuit (Ca) and the voltage (Vca) is decreasing (part indicated by K3 and K4), one of the power semiconductor switches (SW2a or SW3a) is turned on, It can be seen that the semiconductor switch (SW1a or SW4a) is switched at a carrier frequency (equivalent to 10 kHz).

  This operation is performed under the control of the PWM control circuit. Now, assuming that the DC intermediate circuit voltage (Vdc) is constant at Vdc = 300V, Vhs = 0.9V as shown in the setting parameter, the first storage device (FF1) has 150V + 0.9V = 150. Set at 9V and reset at 150V. On the other hand, since Vls = −0.9V, the second storage device (FF2) is set at 150V−0.9V = 149.1V and reset at 150V. As a result, as shown in (3) of FIG. 6, power is stored / discharged appropriately by the voltage clamp circuit (Ca), while unnecessary switching operations are reduced. As is clear from comparison between FIG. 6 (Embodiment 1) and FIG. 7 (conventional example), in Embodiment 1, the number of switching times of the power semiconductor switches (SW1a to SW4a) is reduced to about 50%. You can see that.

  FIG. 10 shows a comparison result of ripple currents flowing in the DC intermediate circuit and the voltage clamp circuit when the output current Ia = 100 (Arms) and the current phase 30 ° are constant and the output voltage (Va) is changed. Is shown. As shown in the figure, in this embodiment, for example, when the output voltage of the power converter is 200 V, the ripple current of the DC intermediate circuit is 43.1 (Arms), and the ripple current of the voltage clamp circuit is 42.6 (Arms). On the other hand, in the conventional example, the ripple current of the DC intermediate circuit is 44.5 (Arms), the ripple current of the voltage clamp circuit is 42.7 (Arms), and in the region where the output voltage is high. It can be seen that the ripple current reduction effect is high.

  In the present embodiment, as a simulation result in the power conversion device for driving an electric motor, the output voltage under each condition of output frequency 50 (Hz), output current 100 (Arms), and current phase 30 ° (phase delay). Although the case where (Va) is changed is shown, it is needless to say that the entire current phase from 0 ° to 360 ° can be stably controlled as in the case of the current phase 30 °. In the present embodiment, the DC intermediate circuit voltage (Vdc) is also shown as a constant voltage (2 × Ed). For example, when a rectifier such as a diode rectifier is used in the rectifier circuit of FIG. The DC intermediate circuit voltage (Ed) always varies, but even in such a case, the voltage of the voltage clamp circuit (Ca) is always controlled to the set value of 50% with respect to the variation. Needless to say.

Embodiment 2. FIG.
The second embodiment is configured using the inverter main circuit shown in FIG. 1, the rectifier circuit shown in FIG. 2, the PWM control circuit shown in FIG. 3, etc., and particularly used in a power conversion device for power system stabilization. A preferred embodiment is shown. In addition, the power conversion device for stabilizing the power system supplies reactive power to the power system, so that the average value of the power flowing into the voltage clamp circuit becomes 0, and voltage fluctuation does not occur. It is also a form. Note that the basic operation is the same as or equivalent to that of the first embodiment, and the characteristics of the operation will be described here with simulation results.

(Simulation conditions)
The simulation conditions according to the second embodiment are the same as those of the first embodiment except for the following conditions. It is assumed that a power system is connected as a load to the inverter main circuit of FIG.
(1) Device capacity of voltage clamp circuit = 27.6 mF
(2) First set value Vhs = 9V
(3) Third set value Vls = −9V

(simulation result)
FIG. 11 is a diagram illustrating a simulation result in the power conversion device according to the second embodiment of the present invention. A reactive current (Ia) delayed by 90 ° from the phase of the voltage command (Vref_a) is transferred from the power conversion device to the power system. The waveform of each part when it is supplied to is shown. In FIG. 11, the power semiconductor switches (SW1a to SW4a) are switching-controlled by the PWM control circuit shown in FIG. 3, and in particular, the power semiconductor switches (SW1a, SW4a) are switched at 50 Hz corresponding to the power supply frequency. . It can also be seen that the voltage clamp circuit voltage (Vca) is also stably controlled between 146V and 152V.

  FIG. 11 shows the case where the current phase is 90 ° behind the voltage phase, but the same applies to the case where the current phase is 90 ° advanced.

  As described above, when the configuration and the control method according to the present embodiment are applied as the power conversion device for power system stabilization, the switching frequency of the power semiconductor switch (SW1a, SW4a) is set to, for example, a frequency of several kHz. To a commercial frequency (50/60 Hz), and the peripheral circuits (cooling structure, snubber circuit, snubber energy regeneration circuit, etc.) of the power semiconductor switch can be reduced in size and cost.

  Further, the power semiconductor switch (SW1a, SW4a) can be further reduced by changing to a switch having a large switching loss but a small conduction loss. Furthermore, since the switching frequency can be increased while suppressing the loss of the entire power semiconductor device, the harmonic filter and the noise filter can be reduced in size and cost. As for the control method of the voltage command (Vref_a), it is widely known that the voltage command (Vref_a) may be controlled according to the reactive power injected into the system, and the description thereof is omitted in the present embodiment. To do.

Embodiment 3 FIG.
The second embodiment is configured using the inverter main circuit shown in FIG. 1, the rectifier circuit shown in FIG. 2, the PWM control circuit shown in FIG. 3, and the like, and in particular, the drive frequency of the electric motor (IM) as a load is For example, a preferred embodiment is shown in the case where driving is performed by an order of magnitude higher than normal 50/60 Hz, for example, 500 Hz. Further, when the driving frequency is driven by an order of magnitude, the equivalent capacitance of the voltage clamp circuit is also increased by an order of magnitude, so that the embodiment is focused on the fact that voltage fluctuation is less likely to occur. Note that the basic operation is the same as or equivalent to that of the first embodiment, and the characteristics of the operation will be described here with simulation results.

(Simulation conditions)
The simulation conditions according to the third embodiment are the same as those of the second embodiment except for the output frequency (f) of the power conversion device. It is assumed that an electric motor is connected as a load to the inverter main circuit of FIG.
・ Output frequency f = 500Hz of power converter

(simulation result)
FIG. 12 is a diagram illustrating a simulation result in the power conversion device according to the third embodiment of the present invention. The power semiconductor switches (SW1a to SW4a) are subjected to switching control by the PWM control circuit illustrated in FIG. Referring to (4) of FIG. 12, the power semiconductor switch (SW1a) performs the switching operation 6 times during 2 ms of 4 to 6 ms. On the other hand, since the period of the modulation frequency of 10 kHz is 0.1 ms, in the case of the modulation frequency of 10 kHz, 20 switching operations are performed in 2 ms. This means that in the power conversion device according to the present embodiment, the switching operation of the power semiconductor switches (SW1a, SW4a) is reduced to about 1/3 compared to the conventional power conversion device shown in FIG. It means that.

  As a result, in the power conversion device of the present embodiment, it is possible to reduce the size and cost of peripheral circuits (such as a cooling structure, a snubber circuit, a snubber energy regeneration circuit) of the power semiconductor switch. Further, the power semiconductor switch (SW1a, SW4a) can be further reduced by changing to a switch having a large switching loss but a small conduction loss. Furthermore, since the switching frequency can be increased while suppressing the loss of the entire power semiconductor device, the harmonic filter and the noise filter can be reduced in size and cost.

<Prerequisites for explaining the fourth to sixth embodiments>
By the way, the power converters shown in the first to third embodiments mainly have the purpose of reducing the switching loss and the ripple current of the voltage clamp circuit when the output voltage and the load power factor are high. In the fourth to sixth embodiments described above, the effect is exhibited in the entire region of the output voltage or the entire region of the load power factor. More specifically, by modulation of a voltage command, one carrier wave (Vcp or Vcn) of two carrier waves (Vcp, Vcn) is changed from a modulation system (bipolar modulation) using two carrier waves (Vcp, Vcn). ) Pseudo-modulation method (unipolar modulation) is applied to add a return mode that could not be achieved with the conventional technology, enabling further reduction of ripple current and element loss of voltage clamp circuit or DC intermediate circuit It is what.

Embodiment 4 FIG.
Next, a power converter according to the fourth embodiment will be described. FIG. 13: is a figure which shows the structural example of the voltage command generation circuit which can be used for the power converter device concerning Embodiment 4 of this invention. This embodiment is configured by using the inverter main circuit shown in FIG. 1, the rectifier circuit shown in FIG. 2, the PWM control circuit shown in FIG. 3, the voltage command generation circuit shown in FIG. 13, and the like. An embodiment suitable for use in a three-phase power converter is shown.

  The voltage command generation circuit shown in FIG. 13 includes an offset voltage generation unit 25 that generates an offset voltage to be added to each phase voltage (Va, Vb, Vc) at a predetermined level. In FIG. 13, an offset voltage generator 25 includes a comparator, a multiplexer (MUX), an adder, a modulation signal generator (± Vmax), and the like, and is used as an output of a current controller when performing vector control of an electric motor, for example. Each phase voltage (Va, Vb, Vc) of the three-phase voltage signal to be input is input, and the maximum voltage with a phase width of 60 ° is centered on the positive and negative maximum values in each phase voltage (Va, Vb, Vc). A modulated signal (Voffset) is generated (see FIG. 14 described later). This modulation signal is added to each phase voltage (Va, Vb, Vc) to become a voltage command (Vref_a, Vref_b, Vref_c), and is used as an input signal to the input terminal Vref_a of the PWM control circuit shown in FIG. The

  FIG. 14 is a diagram illustrating a waveform example of an output signal of the voltage command generation circuit illustrated in FIG. More specifically, the upper part of FIG. 14 shows the voltage waveform (Va, Vb, Vc) of each phase in the three-phase voltage signal and the output waveform (Voffset) of the offset voltage generator 25, and the lower part of FIG. Indicates output waveforms (Vref_a, Vref_b, Vref_c) of the voltage command generation circuit. In the lower part of the figure, for example, between 3.3 ms and 6.6 ms, the voltage commands (Vref_a, Vref_b, Vref_c) all have a positive polarity between 93 V and 150 V, so the PWM control circuit shown in FIG. Thus, all three phases are PWM-modulated by the carrier wave (Vcp).

(Simulation conditions)
The simulation conditions according to the fourth embodiment are the same as those of the first embodiment except for the output voltage (Va) of the power conversion device.
Output voltage (phase voltage) Va = 23Vrms (corresponding to line voltage 40Vrms)

(simulation result)
FIG. 15 is a diagram illustrating a simulation result in the power conversion device according to the fourth embodiment of the present invention. The power semiconductor switches (SW1a to SW4a) are switching-controlled by the PWM control circuit illustrated in FIG. As shown in (1) of FIG. 15, the voltage command (Vref_a) is adjusted to the maximum voltage equivalent (= 150 V) during 3.3 ms to 6.6 ms (about 60 ° interval). Therefore, in this section, the power semiconductor switches (SW1a, SW2a) are controlled to be in the ON state as shown in (4) to (7) of FIG. 15 based on the control of the PWM control circuit of FIG. Since the power semiconductor switches (SW3a, SW4a) are controlled to be in an OFF state, the voltage clamp circuit voltage (Vca) maintains a constant voltage.

  In addition, between 0 and 3.3 ms, the power semiconductor switch (SW1a) is controlled to be in an off state and the power semiconductor switch (SW4a) is controlled to be in an on state, and the power semiconductor switches (SW2a and SW3a) are controlled. Are PWM controlled to alternately turn on and off.

  Furthermore, between 6.6 and 10.0 ms, when the power semiconductor switch (SW2a, SW3a) is PWM controlled to be alternately turned on and off, the power semiconductor switch (SW1a) is controlled to be turned off, In addition, when the power semiconductor switch (SW4a) is controlled to be in an on state and the power semiconductor switches (SW1a, SW4a) are alternately controlled to be in an on / off state, the power semiconductor switch (SW2a) is in an off state. The power semiconductor switch (SW3a) is controlled to be on.

  Note that in the interval of 10 to 20 ms, control completely contrasting with the above control is performed. Therefore, the voltage clamp circuit voltage (Vc1) is stably controlled through these one-cycle sections (0 to 20 ms), and the output current (Ia) is more sinusoidally controlled.

  FIG. 16 shows the conventional ripple current flowing in the DC intermediate circuit and the voltage clamp circuit when the output current Ia = 100 (Arms) and the current phase 30 ° are constant and the output voltage (Va) is changed. Comparison results with technology are shown. As shown in the figure, for example, in the present embodiment, the ripple current of the voltage clamp circuit when the output voltage of the power converter is 40 V is 40.8 (Arms), whereas in the conventional example, The ripple current of the voltage clamp circuit is 91.3 (Arms) (out of the region), and it can be seen that there is a remarkable effect in reducing the ripple current particularly in the region where the output voltage is low.

Embodiment 5. FIG.
Next, a power converter according to the fifth embodiment will be described. FIG. 17 is a diagram illustrating a configuration example of a voltage command generation circuit that can be used in the power conversion device according to the fifth embodiment of the present invention. The present embodiment is configured by using the inverter main circuit shown in FIG. 1, the rectifier circuit shown in FIG. 2, the PWM control circuit shown in FIG. 3, the voltage command generation circuit shown in FIG. 15, and the like. An embodiment suitable for use in a three-phase power converter is shown.

  The voltage command generation circuit shown in FIG. 17 includes an offset voltage generation unit 27 that generates an offset voltage to be added to each phase voltage (Va, Vb, Vc). In FIG. 17, the offset voltage generation unit 27 includes six sets of unit voltage generators (Uu, Uz, Uv, Ux) that output unit voltages every 1/6 cycle in synchronization with reference currents (Iref_a, Iref_b, Iref_c). , Uw, Uy), six sets of multipliers (M1, M2, M3, M4, M5, M6) and 14 sets of adders / subtracters (S1 to S6, A1 to A8) to generate a modulation signal (Voffset) (See FIG. 18 described later). The modulation signal (offset) is added to each phase voltage (Va, Vb, Vc) to become a voltage command (Vref_a, Vref_b, Vref_c), and is input to the input terminal Vref_a of the PWM control circuit shown in FIG. Signal.

  18 is a diagram showing a waveform example of an output signal of the voltage command generation circuit shown in FIG. More specifically, the upper part of FIG. 18 shows the voltage waveform (Va, Vb, Vc) of each phase in the three-phase voltage signal and the output waveform (Voffset) of the offset voltage generator 27, and the lower part of FIG. Indicates output waveforms (Vref_a, Vref_b, Vref_c) of the voltage command generation circuit. In the lower part of the figure, for example, between 5 ms and 8 ms, the voltage commands (Vref_a, Vref_b, Vref_c) are all positive in the range of 93V to 150V. Therefore, the PWM control circuit shown in FIG. All of the phases will be PWM modulated by the carrier wave (Vcp).

(Simulation conditions)
The simulation conditions according to the fifth embodiment are the same as those of the fourth embodiment.

(simulation result)
FIG. 19 is a diagram showing a simulation result in the power conversion device according to the fifth embodiment of the present invention. The power semiconductor switches (SW1a to SW4a) are switching-controlled by the PWM control circuit shown in FIG. As shown in (1) of FIG. 19, the voltage command (Vref_a) is adjusted to the maximum voltage equivalent (= 150V) in the vicinity of the positive peak of the current signal (Ia) (section of 5.0 ms to 8.33 ms). Has been. Therefore, in this section, the power semiconductor switches (SW1a, SW2a) are controlled to be on as shown in (4) to (7) of FIG. 19 based on the control of the PWM control circuit of FIG. Since the power semiconductor switches (SW3a, SW4a) are controlled to be in an OFF state, the voltage clamp circuit voltage (Vca) maintains a constant voltage.

  In addition, the power semiconductor switches (SW1a, SW4a) are alternately turned on / off in a positive section (1.67 to 5.0 ms, 8.33 to 11.67 ms) other than near the peak of the current signal (Ia). When the PWM control is performed in this state, the power semiconductor switch (SW2a) is controlled to be in the OFF state, and the power semiconductor switch (SW3a) is controlled to be in the ON state, so that the power semiconductor switches (SW2a, SW3a) are alternately When PWM control is performed in the on / off state, the power semiconductor switch (SW1a) is controlled in the off state, and the power semiconductor switch (SW4a) is controlled in the on state.

  Similarly, in the vicinity of the negative peak of the current signal (Ia) (section of 15.0 to 18.33 ms), the voltage command (Vref_a) is adjusted to the minimum voltage equivalent (= −150 V). In this section, Since the power semiconductor switches (SW1a, SW2a) are controlled to be turned off and the power semiconductor switches (SW3a, SW4a) are controlled to be turned on, the voltage clamp circuit voltage (Vca) maintains a constant voltage.

  Also, in the negative section (sections from 11.67 to 15.0 ms, 18.33 to 20.0 ms) other than the vicinity of the peak of the current signal (Ia), the power semiconductor switches (SW1a and SW4a) are alternately turned on and off. When the PWM control is performed in this state, the power semiconductor switch (SW2a) is controlled to be on, and the power semiconductor switch (SW3a) is controlled to be off, so that the power semiconductor switches (SW2a, SW3a) are alternately When PWM control is performed in the on / off state, the power semiconductor switch (SW1a) is controlled to be in an on state, and the power semiconductor switch (SW4a) is controlled to be in an off state.

  Therefore, the voltage clamp circuit voltage (Vc1) is stably controlled through these one-cycle sections (0 to 20 ms), and the output current (Ia) is also controlled more sinusoidally.

  FIG. 20 shows the conventional ripple current flowing in the DC intermediate circuit and the voltage clamp circuit when the output current Ia = 100 (Arms) and the current phase 30 ° are constant and the output voltage (Va) is changed. Comparison results with technology are shown. As shown in the figure, for example, in the present embodiment, the ripple current of the voltage clamp circuit when the output voltage of the power converter is 20 V is 28.9 (Arms), whereas in the conventional example, The ripple current of the voltage clamp circuit is 95.6 (Arms) (out of the region), and it can be seen that there is a remarkable effect in reducing the ripple current particularly in the region where the output voltage is low.

  In this embodiment, as apparent from FIG. 19, since switching control is not performed near the peak value of the output current (Ia), the reliability of the apparatus is improved as compared with the conventional example. And low loss can be easily realized.

  In this embodiment, the case where the current phase is delayed by 30 ° with respect to the voltage phase has been described. However, the phase shift of the output voltage (Va) with respect to the voltage phase is −30 ° to 30 °, or 150 °. Even in any range of ˜210 °, the same effect as described above can be obtained.

  On the other hand, when the phase difference between the two exceeds 30 °, each phase of each of the six unit voltage generators (Uu, Uz, Uv, Ux, Uw, Uy) that outputs a unit voltage every 1/6 cycle is output. By fixing the phase difference from the voltages (Va, Vb, Vc) at a maximum of ± 30 °, the ripple current flowing in the DC intermediate circuit and the voltage clamp circuit can be reduced.

  Further, FIG. 21 shows the simulation result when the drive frequency of the electric motor is driven by one digit higher from, for example, normal 50/60 Hz to, for example, 500 Hz in the power conversion device according to the present embodiment, as in the third embodiment. FIG. As in the third embodiment, it can be seen that the switching frequency of the power semiconductor switches (SW1a, SW4a) is reduced to the commercial frequency equivalent.

  Therefore, when the power conversion device of the present embodiment is used for driving an electric motor, the switching frequency of the power semiconductor switches (SW1a, SW4a) can be reduced, for example, from a frequency of several kHz to a commercial frequency (50/60 Hz). In addition, it is possible to reduce the size and cost of peripheral circuits (cooling structure, snubber circuit, snubber energy regeneration circuit, etc.) of the power semiconductor switch.

  In the power converter according to the present embodiment, for example, when a GTO is used as a power semiconductor switch, the capacity of the snubber circuit for processing the energy of the anode reactor inserted in series with the GTO at the time of current interruption is reduced. can do. Further, by configuring the outer elements (elements corresponding to SW1a and SW4a) with elements having a large switching loss but a small common loss, a further reduction in loss can be realized. Furthermore, for example, the cooling structure can be further simplified by providing cooling fins for removing heat generated by the GTO only on one side.

Embodiment 6 FIG.
Next, a power converter according to the sixth embodiment will be described. FIG. 22 is a diagram illustrating a configuration example of a voltage command generation circuit that can be used in the power conversion device according to the sixth embodiment of the present invention. The present embodiment is configured by using the inverter main circuit shown in FIG. 1, the rectifier circuit shown in FIG. 2, the PWM control circuit shown in FIG. 3, the voltage command generation circuit shown in FIG. 22, and the like. An embodiment suitable for use in a three-phase power converter is shown.

  The voltage command generation circuit shown in FIG. 22 adds the third harmonic signal obtained by adding a predetermined offset signal to each phase voltage (Va, Vb, Vc) adjusted to a predetermined level, as shown in FIG. A voltage command (Vref_a, Vref_b, Vref_c: refer to FIG. 23 described later) to be input to the input terminal Vref_a of the PWM control circuit is generated and output.

(Simulation conditions)
The simulation conditions according to the sixth embodiment are the same as those of the first embodiment except for the following conditions.
(1) Output voltage Va = 11.5 Vrms of power converter (corresponding to a line voltage of 20 Vrms)
(2) Third harmonic voltage V3f = 1.92 Vrms (equivalent to Va × 1/6)
(3) Offset voltage Voffset = ± 135 V (50 Hz rectangular wave)

(simulation result)
FIG. 23 is a diagram showing a simulation result in the power conversion device according to the sixth embodiment of the present invention. The power semiconductor switches (SW1a to SW4a) are switching-controlled by the PWM control circuit shown in FIG. As shown in (1) of FIG. 23, the voltage command (Vref_a, Vref_b, Vref_c) greatly changes in a step shape between the positive half cycle and the negative half cycle, but the line voltage is the voltage command (Vref_a). The output current (Ia) changes in a sine wave shape. As basic operations, as shown in (4) to (7) of FIG. 23, the power semiconductor switch (SW1a) is on and the power semiconductor switch (SW4a) is on when the voltage command (Vref_a) is positive. While the power semiconductor switches (SW2a, SW3a) are alternately PWM controlled to be turned on / off while being controlled to be in an off state, if the voltage clamp circuit voltage (Vca) exceeds about 151V, the power The semiconductor switch (SW2a) is turned on and the power semiconductor switch (SW3a) is controlled to be turned off, and the power semiconductor switches (SW1a, SW4a) are alternately PWM controlled to be turned on / off, and the voltage clamp circuit The voltage (Vca) is controlled to be a constant voltage.

  Further, in the interval where the voltage command (Vref_a) is negative, the power semiconductor switch (SW1a) is controlled to be off and the power semiconductor switch (SW4a) is controlled to be on, and the power semiconductor switches (SW2a, SW3a) are alternately turned on. -PWM control is performed in an off state, but when the voltage clamp circuit voltage (Vca) falls below about 150 V, the power semiconductor switch (SW2a) is turned off and the power semiconductor switch (SW3a) is controlled to be on. At the same time, the power semiconductor switches (SW1a, SW4a) are alternately PWM controlled to turn on and off, and the voltage clamp circuit voltage (Vca) is controlled to be a constant voltage.

  FIG. 24 shows the conventional ripple current flowing in the DC intermediate circuit and the voltage clamp circuit when the output current Ia = 100 (Arms) and the current phase 30 ° are constant and the output voltage (Va) is changed. Comparison results with technology are shown. As in the fourth and fifth embodiments, it can be seen that there is a significant effect in reducing the ripple current in the region where the output voltage is low.

  In the present embodiment, a simulation was performed in an operation region in which the output voltage of the power conversion device as described above is low frequency, low voltage, and low current (equivalent to 50 Hz, line voltage 20 Vrms). In such an operation region, the offset voltage (Voffset) may be a direct current, for example, instead of a rectangular wave. By performing such control, for example, in the power conversion devices according to the second and third embodiments, it is possible to suppress the occurrence of ground potential fluctuations that fluctuate at a frequency three times the operating frequency, which is further stabilized. Power supply is possible.

  Also, when the load is large and the output current (Ia) increases, the switching frequency between the power semiconductor switches (SW1a and SW4a or SW2a and SW3a) is biased and the temperature rise becomes unbalanced. By smoothly switching the offset voltage (Voffset) to, for example, a trapezoidal wave with a period of, for example, several hundreds msec, which is a transient thermal time constant of the power semiconductor switch, it is possible to suppress an increase in these imbalances, and to be more stable Driving becomes possible.

Embodiment 7 FIG.
The seventh embodiment is a preferred embodiment related to the initial charging of the voltage clamp circuit (Ca). In the PWM control circuit shown in FIG. 3, the voltage ratio between the DC intermediate circuit voltage (Vdc) and the voltage clamp circuit voltage (Vc) can be controlled to be constant as described above. It is also an embodiment focusing on the fact that a voltage clamp circuit can be configured without using an auxiliary power supply. Hereinafter, the operation will be described based on the simulation result.

(Simulation conditions-various parameters in the inverter main circuit)
In the present embodiment, the following values are used in addition to the conditions of the first embodiment as various parameters in the inverter main circuit when performing the simulation.
(1) Voltage command Vref_a = 0V
(2) Initial value of DC intermediate circuit voltage (Vdc = 2 × Ed) = 0V
(3) Initial value of voltage clamp circuit voltage (Vca) = 0V

(Simulation conditions-Setting parameters in the PWM control circuit)
In the present embodiment, the following values are used as setting parameters in the PWM control circuit when performing simulation.
(1) First set value Vhs = 0V
(2) Second set value Vhr = 0V
(3) Third set value Vls = 0V
(4) Fourth set value Vlr = 0V

(simulation result)
FIG. 25 is a diagram illustrating a simulation result according to the seventh embodiment of the present invention. This simulation was carried out under the condition that the DC intermediate circuit voltage (Vdc) increased to 300 V from the time 0.0 seconds to the time 1.0 seconds, that is, the voltage increase rate was 300 V / 1 second. The voltage clamp circuit voltage (Vca) is determined based on the output ratio (Vca / Vdc) set as the ratio of the voltage clamp circuit voltage (Vca) to the DC intermediate circuit voltage (Vdc). The output ratio is set to 50% (1/2: refer to the input terminal “50%” in FIG. 3).

  As shown in FIG. 25, the voltage clamp circuit voltage (Vca) is 50% of the voltage value (DC intermediate circuit voltage (Vdc)) determined based on the output ratio as the DC intermediate circuit voltage (Vdc) increases. %), And the voltage clamp circuit voltage can be stably charged without using a rectifier circuit as shown in FIG.

  In this simulation, the initial charging of the voltage clamp circuit voltage (Vca) was performed under the conditions of the initial value of the DC intermediate circuit voltage (Vdc) = 0 V and the initial value of the voltage clamp circuit voltage (Vca) = 0 V. Needless to say, the same effect can be obtained at any initial value.

Embodiment 8 FIG.
The eighth embodiment shows another embodiment different from the seventh embodiment relating to the initial charging of the voltage clamp circuit (Ca), and FIG. 26 is a diagram showing a simulation result according to the embodiment. .

  In the present embodiment, for example, the voltage clamp circuit voltage (Vca) and the DC intermediate circuit voltage (Vdc) are connected via the semiconductor switches (SW1a, SW4a), and the initial charge described above is performed by the semiconductor switch (SW1a, After the voltage clamp circuit voltage (Vca) reaches a voltage level (Vca_Level, 150 V in the above example) determined based on the output ratio, the semiconductor switches (SW1a, SW4a) are turned off. Control is performed. As shown in FIG. 26, the voltage clamp circuit voltage (Vca) reaches 150 V after 0.5 seconds (voltage increase rate: 300 V / 1 second, output ratio: 1/2), which is a set value. It can be seen that reliable and stable charging with respect to the clamp circuit voltage is performed.

Embodiment 9 FIG.
The ninth embodiment shows another embodiment different from the seventh and eighth embodiments related to the initial charging of the voltage clamp circuit (Ca), and FIG. 27 shows the simulation result according to the embodiment. It is.

(Simulation conditions)
The simulation conditions according to the ninth embodiment are the same as those of the seventh embodiment except for the initial value of the DC intermediate circuit voltage (Vdc) with respect to the parameters for initial charging.
・ Initial value of DC intermediate circuit voltage (Vdc = 2 × Ed) = 0V
Other parameters are the same as those in the first embodiment.
In the present embodiment, in the PWM control circuit shown in FIG. 3, the output ratio is linearly increased from 0% to 50% from time 0.0 seconds to 1.0 seconds. .

(simulation result)
As shown in FIG. 27, the voltage clamp circuit voltage (Vca) rises linearly to 50% of the DC intermediate circuit voltage (Vdc) according to the control curve (Vca_ref) of (Vca_level), and the voltage clamp The circuit voltage can be stably charged.

  In this simulation, the initial charging of the voltage clamp circuit voltage (Vca) was performed under the condition that the initial value of the voltage clamp circuit voltage (Vca) = 0 V, but the same effect can be obtained even at an arbitrary initial value. Needless to say.

Embodiment 10 FIG.
The tenth embodiment shows a configuration example of a power conversion device that can continue operation even when a commercial power supply fails, and shows a preferred embodiment when the configuration is applied as a power conversion device for driving an electric motor. Is. In FIG. 28, power storage element capacitors (Bfa) are added to both ends of the capacitors (Ca to Cc) constituting the voltage clamp circuit, but the basic operation is the same as that of the first embodiment or Here, the operation will be described with simulation results.

(Simulation conditions)
The simulation conditions according to the tenth embodiment are the same as those in the first embodiment except for the following conditions.
(1) Output voltage (phase voltage) Va = 100 Vrms (corresponding to line voltage 173 Vrms)
(2) Output voltage Vbfa of the power storage element capacity (Bfa) = 150V
(3) Commercial power supply voltage 230Vrms (phase voltage)
(4) Impedance of commercial power supply Zcm = 100uH
The power storage element capacity (Bfa) is assumed to be, for example, a secondary battery, and its output is always constant.

(simulation result)
FIG. 29 is a diagram showing a simulation result in the power conversion device according to the tenth embodiment of the present invention, and shows waveforms of respective parts at normal time (non-power failure time). As shown in FIG. 29, the voltage command (Vref_a) is about 90 Vrms (phase voltage), and the output current (Ia) is also about 90 Arms. The DC intermediate circuit voltage is also controlled to about 300V ± 1V. Note that the voltage (Vca) of the voltage clamp circuit to which the power storage element (Bfa) is connected is constant in the output voltage (Vbfa) of the power storage element (Bfa) at 150 V. Therefore, in the PWM control circuit shown in FIG. Both the first memory device (FF1) and the second memory device (FF2) do not operate, and the power semiconductor switches (SW1a to SW4a) are switched in the switching pattern shown in FIG. 4 (hereinafter referred to as “switching mode”). (Note the difference between the unit and scale of the horizontal axis in FIG. 3 and FIG. 29).

  FIG. 30 is a diagram showing a simulation result in the power conversion device according to the tenth embodiment of the present invention, and shows each part waveform when a power failure occurs at time t = 0.03 seconds.

  In FIG. 30, before the occurrence of a power failure, the voltage command (Vref_a) is about 66 Vrms (phase voltage), the output current (Ia) is about 70 Arms, and flows from the commercial power supply (CM) via the rectifier (Rec). Since the DC intermediate circuit (Cp, Cn) is charged by the DC current (Idc), the DC intermediate circuit voltage (Vdc) is maintained at a voltage of about 300V ± 1V. On the other hand, after the occurrence of a power failure at time t = 0.03 seconds, the direct current (Idc) becomes zero, but the current (Ia) supplied to the electric motor (IM) is stably supplied. It can be understood that the operation can be continued.

  The operation during a power failure will be described in more detail. As shown in (2) of FIG. 30, when a power failure occurs, the DC intermediate circuit voltage (Vdc) once decreases, but when the voltage (Vdc) becomes 296 V or less. Since the first storage device (FF1) in the PWM control circuit of FIG. 3 is set, the PWM control circuit is in the switching mode shown in FIG. In this switching mode, power is supplied from the power storage element (Bfa) to the DC intermediate circuit (Cp, Cn), and the DC intermediate circuit voltage (Vdc) rises. On the other hand, if this control continues, the DC intermediate circuit voltage (Vdc) rises and exceeds 300V, so the first storage device (FF1) is reset this time and the DC intermediate circuit voltage (Vdc) is again set to 296V. descend. This sequence is repeated until power is restored or until the energy of the power storage element (Bfa) is released.

  In this embodiment, when the ratio between the DC intermediate circuit voltage (Vdc) and the voltage clamp circuit voltage (Vca) is 2 to 1, the power of the power storage element (Bfa) is switched by the switching mode as shown in FIG. Is supplied to the DC intermediate circuit (Cp, Cn), and the power of the DC intermediate circuit (Cp, Cn) is regenerated to the power storage element (Bfa) by the switching mode shown in FIG. Therefore, by performing control to switch between the switching mode shown in FIG. 4 and the switching mode shown in FIG. 5, it is possible to positively perform power input / output (supply, regeneration) control with respect to the power storage element (Bfa).

  In this embodiment, the output ratio is set to ½ so that the ratio between the voltage clamp circuit voltage (Vca) and the DC intermediate circuit voltage (Vdc) is controlled to be approximately 1: 2. However, by changing the output ratio, it is possible to perform power control on the power storage element (Bfa) during normal operation.

Embodiment 11 FIG.
FIG. 31 is a diagram of a configuration example of the power conversion device according to the eleventh embodiment. Embodiment 11 shows an embodiment in which two power converters are connected to a DC intermediate circuit, and in FIG. 31, the power converter (10a) that is one of the power converters. Is connected to the input terminal of the commercial power source CM, and the output terminal of the power converter (10b) which is the other power converter is connected to the input terminal of the electric motor (IM).

  In the configuration shown in FIG. 31, power is exchanged between the commercial power source (CM) and the electric motor (IM) via two power converters, but is supplied to the commercial power source (CM) and the electric motor (IM). In any current, for example, a sine wave as shown in FIG. 6 is obtained, and a great advantage is obtained that no special countermeasure against harmonics is required.

Embodiment 12 FIG.
For example, as apparent from the inverter main circuit configuration of the power converter shown in FIG. 1, the voltage applied to the power semiconductor switches (SW1a, SW4a) is the DC intermediate circuit voltage (2 × Ed) and the voltage. It becomes a difference voltage from the clamp circuit voltage (Ed). On the other hand, for example, when a power failure occurs, if there is a difference between the decrease rate of the DC intermediate circuit voltage (2 × Ed) and the decrease rate of the voltage clamp circuit voltage (Ed), the power semiconductor switches (SW1a, SW4a) The applied voltage varies with respect to. Here, when the rate of decrease of the DC intermediate circuit voltage (2 × Ed) is smaller than the rate of decrease of the voltage clamp circuit voltage (Ed), the applied voltage to the power semiconductor switches (SW1a, SW4a) increases. Therefore, it is preferable to make the discharge time constant of the voltage clamp circuit longer than the DC intermediate circuit discharge time constant so that the voltage applied to the power semiconductor switches (SW1a, SW4a) is not more than Ed.

  In each of the above-described embodiments, the PWM control circuit shown in FIG. 3 is used, and various preferred embodiments related to the voltage command generation circuit for generating a suitable reference signal to be input to the PWM control circuit. Although described, it is not limited to a suitable configuration for each embodiment. For example, an equivalent function or an equivalent algorithm may be realized by S / W processing by a CPU or H / W processing by an ASIC, and an effect equivalent to the effect obtained in each of the above embodiments can be obtained. Needless to say.

  As described above, the power conversion device according to the present invention is useful as a power conversion device for driving an electric motor and stabilizing a power system.

It is a figure which shows the structural example of the inverter main circuit which comprises the power converter device concerning Embodiment 1 of this invention. It is a figure which shows the structural example of the rectifier circuit used for the power converter device concerning Embodiment 1 of this invention. It is a figure which shows the structural example of the PWM control circuit (for 1 phase) which comprises the power converter device concerning Embodiment 1 of this invention. It is a figure which shows the example of a switching waveform of the power converter device concerning Embodiment 1 of this invention. It is a figure which shows the example of a switching waveform different from FIG. 4 of the power converter device concerning Embodiment 1 of this invention. It is a figure which shows the simulation result in the power converter device of Embodiment 1 of this invention. It is a figure which shows the simulation result in the power converter device of a prior art. It is a figure which shows the example of a switching waveform of the power converter device concerning a prior art. It is a figure which shows the structural example of the PWM control circuit concerning a prior art. It is a figure which shows the comparison result with the prior art concerning the ripple current which flows into a direct current | flow intermediate circuit and a voltage clamp circuit. It is a figure which shows the simulation result in the power converter device of Embodiment 2 of this invention. It is a figure which shows the simulation result in the power converter device of Embodiment 3 of this invention. It is a figure which shows the structural example of the voltage command generation circuit which can be used for the power converter device concerning Embodiment 4 of this invention. It is a figure which shows the example of a waveform of the output signal of the voltage command generation circuit shown in FIG. It is a figure which shows the simulation result in the power converter device of Embodiment 4 of this invention. It is a figure which shows the comparison result with the prior art of the ripple current which flows into the direct current | flow intermediate circuit comprised in Embodiment 4 of this invention, and a voltage clamp circuit. It is a figure which shows the structural example of the voltage command generation circuit which can be used for the power converter device concerning Embodiment 5 of this invention. It is a figure which shows the example of a waveform of the output signal of the voltage command generation circuit shown in FIG. It is a figure which shows the simulation result in the power converter device of Embodiment 5 of this invention. It is a figure which shows the comparison result with the prior art of the ripple current which flows into the direct current | flow intermediate circuit comprised in Embodiment 5 of this invention, and a voltage clamp circuit. It is a figure which shows the other simulation result different from FIG. 19 in the power converter device of Embodiment 5 of this invention. It is a figure which shows the structural example of the voltage command generation circuit which can be used for the power converter device concerning Embodiment 6 of this invention. It is a figure which shows the simulation result in the power converter device of Embodiment 6 of this invention. It is a figure which shows the comparison result of the ripple current which flows into the direct current | flow intermediate circuit comprised in Embodiment 6 of this invention, and a voltage clamp circuit. It is a figure which shows the simulation result concerning Embodiment 7 of this invention. It is a figure which shows the simulation result concerning Embodiment 8 of this invention. It is a figure which shows the simulation result concerning Embodiment 9 of this invention. It is a figure which shows one application example of the power converter device concerning Embodiment 10 of this invention. It is a figure which shows the simulation result (at the time of a non-power failure) in the power converter device of Embodiment 10 of this invention. It is a figure which shows the simulation result (at the time of a power failure) in the power converter device of Embodiment 10 of this invention. It is a figure which shows the structural example of the power converter device concerning Embodiment 11 of this invention.

Explanation of symbols

10 Power converter inverter main circuit 11 DC bus (positive side)
12 DC bus (negative electrode side)
21 PWM signal generation first circuit 22 PWM signal generation second circuit 25, 27 Offset voltage generation unit 30 Current phase Cp, Cn Capacitor (DC intermediate circuit)
Ca, Cb, Cc capacitors (voltage clamp circuit)
CM Commercial power IM motor

Claims (11)

A DC intermediate circuit having first power storage means and supplying DC power stored in the first power storage means, and an inverter main circuit for converting DC power supplied from the DC intermediate circuit into AC power A PWM control circuit that generates and outputs a PWM signal for PWM control of the inverter main circuit, a voltage command generation circuit that generates a voltage command necessary for generating the PWM signal and outputs the voltage command to the PWM control circuit, In a power conversion device comprising:
The inverter main circuit is:
First to fourth switching elements connected in series between a pair of positive and negative DC buses constituting the DC intermediate circuit;
Second power storage means connected between the connection ends of the first and second switching elements and the connection ends of the third and fourth switching elements;
For each phase,
DC power stored in the second power storage means is supplied from the DC intermediate circuit. The second power storage means is a capacitor;
The capacitor has a capacitance value such that an equivalent capacitance represented by the following equation (1) is 20 times or less of an output capacitance of the inverter main circuit represented by the following equation (2). The power conversion device according to claim 1.
Equivalent capacity = 2 × π × (Output frequency) × (Capacity value) × (Device rated voltage) ^ 2 (1)
Output capacity = √ (3) x (equipment rated voltage) x (equipment rated current) (2)   The power converter according to claim 2, wherein the capacitor has a capacitance value such that the equivalent capacitance is in a range of 5 to 10 times the output capacitance of the inverter main circuit. The PWM control circuit is
A first comparator for determining a polarity of a voltage command output from the voltage command generation circuit;
A second comparator for determining the magnitude of a positive polarity carrier wave for determining a switching frequency when PWM controlling the first to fourth switching elements and the voltage command;
A third comparator for determining the magnitude of the negative polarity carrier wave that determines the switching frequency and the voltage command;
With
When an output ratio (output ratio: real number greater than 0 and less than 1) is preset as a ratio of the output voltage of the second power storage means to the output voltage of the DC intermediate circuit,
When the output voltage of the second power storage means is equal to a value obtained by multiplying the output voltage of the DC intermediate circuit by the output ratio, the first switching element or the output voltage based on the output of the first comparator The switching control of any of the fourth switching elements is performed, and both the second switching element and the third switching element are controlled based on the outputs of the second comparator and the third comparator. Switching control,
When the output voltage of the second power storage means is different from a value obtained by multiplying the output voltage of the DC intermediate circuit by the output ratio, the second switching element or the output voltage based on the output of the first comparator The switching control of any of the third switching elements is performed, and both the first switching element and the fourth switching element are controlled based on the outputs of the second comparator and the third comparator. Switching control,
The power conversion apparatus according to claim 1. The PWM control circuit is
A first comparator for determining a polarity of a voltage command output from the voltage command generation circuit;
A second comparator for determining the magnitude of a positive polarity carrier wave for determining a switching frequency when PWM controlling the first to fourth switching elements and the voltage command;
A third comparator for determining the magnitude of the negative polarity carrier wave that determines the switching frequency and the voltage command;
With
When an output ratio (output ratio: real number greater than 0 and less than 1) is preset as a ratio of the output voltage of the second power storage means to the output voltage of the DC intermediate circuit,
The polarity of the voltage command, the polarity of the output current of the inverter main circuit, the polarity of the difference value between the output voltage of the second power storage means and the voltage obtained by multiplying the output voltage of the DC intermediate circuit by the output ratio, When the output of the exclusive OR according to the three polarities is 0,
Controlling the first switching element by the output of the first comparator;
Controlling the second switching element by an output of a logical sum of an output of the second comparator and an output of the third comparator;
Controlling the third switching element by an output of a logical sum of an output of the reverse polarity of the second comparator and an output of the reverse polarity of the third comparator;
Controlling the fourth switching element with the output of the reverse polarity of the first comparator;
The polarity of the voltage command, the polarity of the output current of the inverter main circuit, the polarity of the differential output between the output voltage of the second power storage means and the voltage obtained by multiplying the output voltage of the DC intermediate circuit by the output ratio, When the output of the exclusive OR according to the polarities of the three is 1,
Controlling the first switching element with an output of a logical sum of an output of the second comparator and an output of the third comparator;
Controlling the second switching element by the output of the first comparator;
Controlling the third switching element with an output of reverse polarity of the first comparator;
The fourth switching element is controlled by an output of a logical sum of an output of reverse polarity of the second comparator and an output of reverse polarity of the third comparator;
The power conversion apparatus according to claim 1.   The power conversion apparatus according to claim 4 or 5, wherein the output ratio is set to ½. The voltage command generation circuit includes:
In the section of 1/6 cycle centered on the positive peak value of the phase voltage of one phase, it exhibits a substantially constant voltage value offset to the positive side, and the negative peak value of the phase voltage of the one phase is In the central 1/6 cycle section, an offset is generated that exhibits a substantially constant voltage value offset to the negative electrode side, and that each 1/6 cycle section is alternately and periodically repeated as an offset signal. A signal generation circuit;
An adder for adding the offset signal to each phase voltage adjusted to a predetermined level;
With
The output of the adder is PWM-modulated by the positive polarity carrier in the positive section of the offset signal, and all phases by the negative polarity carrier in the negative section of the offset signal. The power conversion device according to claim 4, wherein the power conversion device is adjusted so as to be PWM-modulated.   5. The voltage command generation circuit outputs a signal obtained by adding a third harmonic signal in which a predetermined offset voltage is superimposed on each phase voltage adjusted to a predetermined level as a voltage command signal. The power converter device of any one of -6.   When the first power storage means is initially charged, the initial power with respect to the second power storage means is set so that the voltage of the second power storage means is the output ratio times the output voltage of the DC intermediate circuit. The power converter according to any one of claims 4 to 8, wherein charging is performed together.   The initial charge of the second power storage means is performed by varying the output ratio in the PWM control circuit from 0 to a set value after the establishment of the output voltage of the DC intermediate circuit. The power conversion device according to any one of 8. A plurality of the power conversion devices according to any one of claims 1 to 10,
A power conversion system characterized in that the DC buses of the plurality of power converters are connected to each other and the output terminal of at least one power converter is connected to a commercial power source.

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