KR101627505B1

KR101627505B1 - Uninterruptible Power Supply

Info

Publication number: KR101627505B1
Application number: KR1020150147177A
Authority: KR
Inventors: 이인환
Original assignee: 성신전기공업(주)
Priority date: 2015-10-22
Filing date: 2015-10-22
Publication date: 2016-06-07

Abstract

In particular, in order to minimize the direct current component contained in the output voltage of the 3-level uninterruptible power supply, the control unit of the rectifier is divided into a rectifier voltage / current control unit, a rectifier current offset instruction unit, A PWM duty generator, and a rectifier PWM converter, and the inverter control unit includes an inverter voltage control unit, an inverter voltage offset automatic control unit, an inverter voltage offset manual command unit, an inverter PWM duty generator, and an inverter PWM converter, The rectifier PWM duty generating unit balances the rectifier input current by using the command value of the current offset command unit to remove the voltage deviation of the DC link and also uses the output value generated from the inverter voltage offset automatic control unit and the inverter voltage offset manual command unit Inverter PWM duty generation section adjusts the balance of the inverter output voltage, Wherein the rectifier PWM conversion unit determines the sign of the duty output from the rectifier PWM duty generating unit to minimize the unbalance of the input current, thereby improving the stability and minimizing the DC voltage flowing into the load side device. Level inverter PWM signal, and the inverter PWM converter determines a sign of the duty output from the inverter PWM duty generator to generate a 3-level inverter PWM signal that minimizes the unbalance of the output voltage .

Description

[0001] Uninterruptible Power Supply [0002]

The present invention relates to an uninterruptible power supply, and more particularly, to a three-level uninterruptible power supply capable of PWM control with minimized direct current deviation.

Up to now, the technology of the uninterruptible power supply has been steadily developed. Recently, uninterruptible power supply devices employing three-level technology, which is superior to the conventional two-level method, are being released.

Compared with the existing 2-level uninterruptible power supply, the 3-level uninterruptible power supply can reduce the inductance value of the filter reactor by the frequency multiplication effect with the efficiency characteristic superior to the existing 2-level due to the neutral point clamping effect, 50%. &Lt; / RTI > The efficiency increase, the inductance and the reduction of the electromagnetic wave have the effect of lowering the cost of the device and improving the reliability. In addition, the efficiency of the 3-level uninterruptible power supply increases, thereby reducing power loss during operation and reducing operating costs.

However, the non-transformer type two-level and three-level uninterruptible power supply apparatus using a neutral line has a common problem that the DC voltage is contained in the output of the uninterruptible power supply unit due to the uneven impedance of the DC link capacitor and the asymmetry of the rectifier and the inverter PWM . If DC voltage is included in the inverter output voltage as described above, noise and an overheating phenomenon are generated in the transformer and reactor installed on the load side, which seriously deteriorates the reliability of the uninterruptible power supply. Also, when a plurality of uninterruptible power supply units are operated in parallel, the DC partial voltages included in the outputs of the respective uninterruptible power supply units may increase the circulating current, thereby hindering the parallel operation.

However, in the 3-level uninterruptible power supply, the number of driver circuits for driving semiconductor devices and semiconductors is twice that of the 2-level, and if the characteristics of the increased circuits are not uniform, the asymmetry of the PWM There is a deepening feature. In addition, the complex three-level PWM conversion process further enhances the asymmetry of the PWM. Therefore, in order to secure the stability of the load side equipment and the parallel operation, a means for calibrating the PWM balance of the 3-level rectifier and the inverter and a 3-level PWM conversion means for minimizing the PWM unbalance are required.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an uninterruptible power supply apparatus capable of minimizing a deviation of a DC voltage generated in DC link capacitors of a system and minimizing a content of a DC voltage generated in an inverter output voltage.

Another problem to be solved by the present invention is to provide an uninterruptible power supply device in which the DC voltage included in the AC output is minimized to protect the load device and the stability of parallel operation is improved.

In order to solve the above problems, the present invention can provide an uninterruptible power supply including a three-level rectifier that minimizes a DC bias.

This apparatus generates a rectifier reference input current I_ref by using an error between the target DC link voltage Vdc_pfc and the detected actual DC link voltage Vdcp + Vdcn, and uses the error between the rectifier reference input current I_ref and the actual rectifier input current I_pfc A rectifier voltage / current controller for generating a sinusoidal rectifier input current control amount and storing the sinusoidal rectifier input current control amount in a sine_value and outputting the sine_value value, a current offset command unit for storing and outputting a manual rectifier input current correction signal input through an input device, A rectifier PWM duty generator for receiving a value of sine_value and a value of i_offset to control a balance of a rectifier input current and calculating a control value for DC link voltage balance and storing the calculated control value in duty; Level rectifier PWM signal to the rectifier gate driver.

In the present invention, the voltage / current controller uses the error of the rectifier reference input current I_ref and the actual rectifier input current I_pfc to maintain the rectifier output voltage at the target DC link voltage Vdc_pfc, and at the same time, 1, a sinusoidal rectifier input current control amount sine_value can be generated.

In the present invention, the rectifier PWM duty generator determines the duty of the sinwt output from the PLL. If the sinwt sign is equal to or greater than zero, the duty is determined using Equation 1: Duty = (PWM_full_duty + i_offset) sine_value, If the sign of the sinwt output from the PLL is judged to be less than zero, the duty can be determined using Equation 2: Duty = (PWM_full_duty - i_offset) sine_value. Here, PWM_full_duty is 100% PWM duty, i_offset is the input value of the manual rectifier input current calibration signal, and sine_value is a sinusoidal rectifier input current control amount.

In the present invention, when the sign of the value stored in the Duty is equal to or greater than zero in the rectifier PWM duty generator, the rectifier PWM synthesizer stores the value stored in the Duty in the PWM PDC1 of the DSP, stores the zero value in the PWM PDC2, If the sign of the value stored in the Duty output from the rectifier PWM duty generator is less than zero, the zero value is stored in the PWM PDC1 of the DSP, and the result stored in the duty cycle multiplied by (-) is stored in the PWM PDC2, - Four PWM signals can be generated to drive the level rectifier.

In the present invention, the PWM rectifier of the uninterruptible power supply is a three-phase three-level PWM rectifier, and the rectifier voltage / current control unit, the current offset command unit, the rectifier PWM duty cycle unit, Phase PWM rectifiers in phase with each other.

According to an aspect of the present invention, there is provided an uninterruptible power supply including a three-level inverter that minimizes a DC bias.

This apparatus includes an inverter voltage control unit for inputting an error err of a target inverter output voltage Va_ref and a detected actual inverter output voltage Va to a voltage controller to output a sinusoidal inverter voltage control amount sine_value, A voltage offset automatic control unit for increasing the value of the calibration signal a_offset by +1 and decreasing the value of the calibration signal a_offset by -1 if the value of the first output voltage Vdcp is smaller than the second output voltage Vdcn, A voltage offset manual command section which is manually inputted from the input device and outputs a calibration signal m_offset 202 for calibrating unbalance of the inverter output voltage, and a voltage offset manual command section which outputs the sinusoidal inverter voltage control amount sine_value, the calibration signal a_offset, m_offset is input and the control value for controlling the inverter output voltage balance is calculated and stored in the duty cycle. And an inverter PWM synthesizer for generating a 3-level PWM signal using the duty value and outputting the 3-level PWM signal to an inverter gate driver.

In the present invention, the inverter PWM synthesizer calculates a control value that controls the inverter output voltage to a normal value and maintains the first output voltage Vdcp and the second output voltage Vdcn of the DC link stage at the same level, And output it to the inverter PWM synthesis section.

In the present invention, the PWM duty generator determines the duty of the sinwt output from the PLL. If the sinwt sign is equal to or greater than zero, the duty is determined using Equation 3: Duty = (PWM_full_duty + m_offset) * sine_value + a_offset Duty = (PWM_full_duty - m_offset) * sine_value + a_offset can be used to determine the duty if the sign of sinwt is less than zero. Herein, PWM_full_duty is 100% PWM duty, m_offset is the manual inverter output voltage calibration signal input value, sine_value is a sinusoidal inverter output voltage control amount, and a_offest is a correction value output from the voltage offset automatic control unit.

In the present invention, if the sign of the value stored in the Duty is equal to or greater than zero in the inverter PWM duty generation unit, the PWM PWM synthesis unit stores the value stored in the duty in the PWM PDC1 of the DSP and stores the zero value in the PWM PDC2 A zero value is stored in the PWM PDC1 of the DSP if the sign of the value stored in the Duty output from the inverter PWM duty generator is less than zero and a result value obtained by multiplying the value stored in the duty by (-) is stored in the PWM PDC2 .

In the present invention, the PWM inverter of the uninterruptible power supply is a three-phase three-level PWM inverter, and the inverter voltage control unit, the voltage offset automatic control unit, the voltage offset manual command unit, the inverter PWM duty generator, The combining unit can control each single phase of the three-phase three-level PWM inverter in a phase of 120 degrees each.

As described above, according to the means of the present invention, the balance between the input current and the DC link voltage is corrected using the rectifier input current calibration signal i_offset set in the keypad on the front side of the equipment, and the DC deviation Level rectifier that minimizes the output voltage of the inverter and also provides an inverter output voltage manual calibration signal m_offset set in the keypad on the front side of the equipment and an automatic calibration signal a_offset using the DC voltage deviation, A simple 3-level inverter PWM conversion means is provided that minimizes the voltage and minimizes the DC deviation through the PWM converter of the 3-level inverter.

1 is a block diagram of a 3-level rectifier controller of an uninterruptible power supply according to the present invention;
FIG. 2 is a diagram for explaining a phenomenon in which a rectifier input current is operated asymmetrically due to a nonuniform circuit constant in a single-phase three-level rectifier;
3 is a diagram for explaining a necessary condition of a PWM signal for driving four IGBTs constituting a single-phase three-level rectifier;
4 is a block diagram of a three-level inverter control apparatus of an uninterruptible power supply according to the present invention;
5 is a diagram for explaining a phenomenon in which an inverter output voltage is asymmetrically operated due to a nonuniform circuit constant in a single-phase three-level inverter;
6 is a diagram for explaining a necessary condition of a PWM signal for driving four IGBTs constituting a single-phase three-level inverter.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order that the present invention may be easily understood by those skilled in the art. In the description of the present invention, the same parts are denoted by the same reference numerals, and repetitive description thereof will be omitted.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and should provide a further description of the claimed invention. Reference numerals are shown in detail in the preferred embodiments of the present invention, examples of which are shown in the drawings. Wherever possible, the same reference numbers are used in the description and drawings to refer to the same or like parts.

The present invention may be implemented or applied through other embodiments. In addition, the detailed description may be modified or modified in accordance with the aspects and applications without departing substantially from the scope, spirit and other objects of the invention.

For example, the single-phase three-level rectifier and the single-phase three-level inverter are exemplified in the following embodiments, but those skilled in the art can apply the three-phase three-level rectifier and the three-phase three-level inverter.

1 is a block diagram of a 3-level rectifier controller of an uninterruptible power supply according to the present invention.

Referring to FIG. 1, an apparatus for controlling three-level rectifiers of an uninterruptible power supply according to the present invention includes a rectifier voltage / current controller 110, a current offset command unit 120, a PWM duty generator 130, A PWM converter 140, and a rectifier gate driver 150 as main components. The PWM duty generator 130 includes a PLL code determiner 131, a positive offset adder 132, and a negative offset adder 133. The 3-level PWM conversion unit 140 includes a duty code determination unit 141, a positive determination unit 142, and a negative determination unit 143.

The rectifier voltage / current controller 110 generates a rectifier reference input current I_ref 113 by using an error between the target DC link voltage Vdc_pfc 111 and the detected actual DC link voltage Vdcp + Vdcn 112, The rectifier output voltage is maintained at Vdc_pfc by using the error between the I_ref 113 and the actual rectifier input current I_pfc 114 and a sinusoidal control amount sine_value 134 for controlling the rectifier input current to be equal to 1, Is outputted in a state opposite to the rectifier input voltage.

The offset command unit 120 generates a calibration signal i_offset 122 for calibrating the unbalance of the rectifier input current in the keypad 121 provided on the front portion of the uninterruptible power supply.

The PWM duty generator 130 determines the sign of the sinwt 135 output from the PLL (not shown). If the sign of the sinwt 135 is equal to or greater than zero, the PWM duty generator 130 determines the duty using Equation 1 below

Duty = (PWM_full_duty + i_offset) sine_value (1)

The PWM duty generator 130 determines the sign of the sinwt 135 output from the PLL (not shown) and determines the duty using Equation 2 if the sign of sinwt 135 is less than zero .

Duty = (PWM_full_duty - i_offset) x sine_value (2)

In the present invention, when the input current is calibrated by the rectifier voltage / current controller 110, the rectifier output voltage may be transient. Therefore, in order to calibrate the balance of the input current, the PWM duty generator 130 performs balance correction of the input current instead of the rectifier voltage / current controller 110 of FIG.

[Balance calibration operation of input current]

As shown in FIG. 2, when the rectifier input current is asymmetrically operated due to uneven circuit constants in a single-phase three-level rectifier, an asymmetrical DC voltage is applied to the capacitors C1 165 and C2 166 connected to the rectifier output do. For example, as shown in (b) of FIG. 2, if the input current of the section having the input voltage of (+) is large, the entire DC link voltage Vdcp + Vdcn is maintained constant, A phenomenon occurs in which the voltage Vdcp (171) deviates more than the lower capacitor voltage Vdcn (172).

On the contrary, if the input current of the section where the input voltage is (-) is large as shown in (c) of FIG. 2, the entire DC link voltage Vdcp + Vdcn is maintained constant while the lower capacitor voltage Vdcn A phenomenon occurs in which the upper capacitor voltage Vdcp (172) deviates more than the upper capacitor voltage Vdcp (171).

When the asymmetrical DC voltage is switched by the inverter to generate an AC voltage, the rectifier input current must be recovered symmetrically because the inverter AC output voltage contains DC voltage and adversely affects the load side. Therefore, the rectifier input current should be adjusted so that the waveform of the (+) interval of the rectifier input current and the waveform of the (-) interval of the rectifier input current are kept constant. If the rectifier input current is calibrated in the positive or negative range, the DC voltage is transient until the calibration is completed due to the change in the total current. Therefore, The calibration operation should be performed by applying the same control amount having a different polarity.

When the input current of the section in which the rectifier input voltage is positive due to the uneven circuit constant shown in (b) of FIG. 2 occurs more than the input current of the section in which the input voltage is negative (-), When Vdcp deviates more than Vdcn, i_offset 122 having a negative sign is set in the front keypad 121. The i_offset 122 having the negative value is summed with the value stored in the register PWM_full_duty 136 according to Equation 1 in an interval in which the input voltage is positive so that the overall value is smaller than the value stored in the register PWM_full_duty 136 . When the result is multiplied by the sinusoidal control amount sine_value 134 output from the rectifier voltage / current control unit, the value becomes a sinusoidal duty value and is stored in the register duty 137. The duty value stored in the register duty 137 drives the rectifier IGBT through the 3-level PWM conversion unit 140 and decreases the amount of input current in the period in which the input voltage is positive. The i_offset 122 having the negative value is subtracted from the value stored in the register PWM_full_duty 136 according to Equation 2 in an interval in which the input voltage is negative so that the overall value is smaller than the value stored in the register PWM_full_duty 136 . When the result is multiplied by the sinusoidal control amount sine_value 134 output from the rectifier voltage / current control unit, the value becomes a sinusoidal duty value and is stored in the register duty 137. The 3-level PWM converter 140 converts the value stored in the register Duty 137 into a 3-level PWM signal to drive the rectifier IGBT and reduces the amount of input current in the interval in which the input voltage is negative.

On the other hand, when the input current of the rectifier input voltage is positive (+), the input current is less than the input current of negative (-), or when the DC link voltage Vdcp is less than Vdcn, (1) and (2) by setting the value of i_offset (122) with the input voltage is increased and the input voltage is increased in the period in which the input voltage is positive and decreased in the period in which the input voltage is negative.

Therefore, if the same calibration operation is performed only in the PWM duty generator 130 in the interval of (+) and (-) of the input voltage as described above, the rectifier voltage / current controller 110 may be burdened And has the advantage of effectively correcting the deviation of the input current and the deviation of the DC voltage while minimizing the transient phenomenon that may occur during the balance adjustment.

[3-level PWM signal waveform generation]

First, we discuss the requirements of the PWM signal driving four IGBTs constituting a single-phase three-level rectifier.

Referring to FIG. 3, Q2 163 charges the C1 165 by generating an input current in the (+) direction in an interval in which the input voltage is positive. Q2 '164 must provide a current flow path from the neutral point N 168 to the point P1 167 in the off period of the Q2 163 in the period in which the input voltage is positive. Q1 '162 should provide a current flow path from the point P1 167 to the neutral point N 168 in the period in which the input voltage is positive. When the Q2 163 and the Q2 '164 operate simultaneously, the dead time must be set so that the C2 166 is short-circuited.

Q1 (161) generates the input current in the (-) direction in the interval in which the input voltage is negative (-), thereby charging C2 (166). Q1 '162 should provide a current flow path in the direction of neutral point N (168) from point P1 (167) in the off period of Q1 (161) in the interval where the input voltage is negative. Q2 '164 should provide a current flow path from the neutral point N (168) to the point P1 (167) in the interval where the input voltage is negative. When the Q1 161 and the Q1 '162 operate simultaneously, the dead time must be set so that no case may occur at any time because the C1 165 is short-circuited.

The value stored in the register Duty 137 output from the PWM duty generator 130 of FIG. 1 includes an (-) value because it is an array of numbers that vibrate by a sine function. Therefore, the value input to the PWM register of the DSP (not shown) It can not be done. A period in which the sign of the value stored in the register Duty 137 is positive corresponds to a period in which the input voltage is negative and a period in which the sign of the value stored in the register Duty 137 is negative, (+).

In FIG. 3, in order to generate a negative polarity in the negative input voltage range, Q1 switches to generate an input current, Q1 'performs a complementary operation with Q1, , Q2 stops operating, and Q2 'must satisfy the requirement of continuity of continuity with the neutral line in the interval where the input voltage is negative (-).

Also, in FIG. 3, in order to generate a positive (+) current in the positive input voltage range, Q2 performs switching for generating an input current, Q2 'performs a complementary operation to Q2, , Q1 stops operating, and Q1 'must meet the requirement to be continuously conductive with the neutral line in the (+) period of the input voltage.

Also, in the equilibrium state, the duty of the PWM waveform applied to Q1 and Q2 within one cycle of the input voltage is generally considered to be the same.

Therefore, the Duty 137 value of the section in which the value of the register Duty 137 is positive is used for IGBT Q1 161 and Q1 '162 without sign conversion, and the value of the register Duty 137 is (-) is used for IGBT Q2 (163) and Q2 '(164).

Accordingly, in order to divide the duty value 137 stored in the PWM data value into IGBTs Q1 161, Q1 '162, Q2 163, and Q2' 164, the PWM duty generator 130 If the number of the value stored in the output register Duty 137 is more than zero, the Duty 137 is stored in the PWM register PDC1 144 of the DSP (not shown) and the zero value is stored in the PDC2 145 . When the value of Duty 137 is stored in the PDC1 144 at the sign of the value of the duty 137, when the sign of the input voltage is negative, the value of the Duty 137 of the PWM main output register PDC1_H 146 of the PDC1 144 And supplies a complementary value of the PDC1_H 146 including the dead time to the IGBT Q1 '162 via the PWM complementary output register PDC1_L147. If the sign of the Duty 137 value is equal to or greater than zero and the zero value is stored in the PDC2 145, the output of the PWM main output register PDC2_H 148 of the PDC2 145 in the period in which the sign of the input voltage is negative, Q2 163 and the complement value of PDC2_H 148 is supplied to IGBT Q2 '164 via the PWM complement output register PDC2_L 149 in a "high " state.

If the sign of the value stored in the register Duty 137 output from the PWM duty generator 130 is less than zero, the zero value is stored in the PWM register PDC1 144 of the DSP (not shown) 145 stores a value of -Duty (137). When the sign of the Duty 137 value is less than zero and the zero value is stored in the PDC1 144, the output of the PWM main output register PDC1_H 146 of the PDC1 144 in the period of the sign of the input voltage is positive, Q1 161 and the complement of the PDC1_H 146 is supplied to the IGBT Q1 '162 via the PWM complement output register PDC1_L 147 in a "high" state. If the value of the Duty 137 is less than zero and the value of -Duty 137 is stored in the PDC2 145, the PWM main output register PDC2_H 148 of the PDC2 145 in the period in which the sign of the input voltage is positive, To the IGBT Q2 163 and the complement value of the PDC2_H 148 is supplied to the IGBT Q2 '164 via the PWM complementary output register PDC2_L 149 including the dead time.

As shown in FIG. 3, the IGBTs Q1 and Q2 for generating the input current and the IGBTs Q1 'and Q2' for the neutral point clamping in the (+) and (- Level rectifier PWM signals that minimize the unbalance of the input current.

4 is a block diagram of a three-level inverter control apparatus for an uninterruptible power supply according to the present invention.

4, an apparatus for controlling three-level inverter of an uninterruptible power supply according to the present invention includes a voltage control unit 180, an offset automatic control unit 190, an offset manual command unit 200, a PWM duty generation unit 210, And a 3-level PWM converter 220, as main components.

The PWM duty generator 210 includes a PLL code determiner 211, a positive offset adder 212, and a negative offset adder 213.

The 3-level PWM converter 220 includes a duty code determiner 221, a positive decision unit 222, and a negative decision unit 223.

The voltage controller 180 inputs the target inverter output voltage Va_ref 182 and the detected actual inverter output voltage Va 181 error err 183 to the voltage controller 184 to output the sine wave control amount sine_value 185 And the polarity is the same as the inverter output voltage. The voltage controller 184 may use various controllers such as a PI controller (not shown), a PR controller (not shown), or a fuzzy controller (not shown) according to the designer's intention.

The offset automatic control unit 190 increases the value of the calibration signal a_offset 193 by 1 if the value of the Vdcp 191 is greater than Vdcn 192 and increases the value of the calibration signal a_offset 193 by 1 if the value of Vdcp 191 is less than Vdcn 192 The value of the signal a_offset (193) is decremented by -1 and output.

The offset manual command unit 200 outputs a calibration signal m_offset 202 for manually adjusting the unbalance of the inverter output voltage in the keypad 201 installed in the front portion of the uninterruptible power supply.

The PWM duty generator 210 determines the sign of the sinwt 215 output from the PLL (not shown). If the sign of the sinwt 215 is equal to or greater than zero, the PWM duty generator 210 determines the duty using Equation (3)

Duty = (PWM_full_duty + m_offset) sine_value + a_offset (Equation 3)

The PWM duty generator 210 determines the sign of the sinwt 215 output from the PLL (not shown), and determines the duty using Equation 4 if the sign of the sinwt 215 is less than zero .

Duty = (PWM_full_duty - m_offset) sine_value + a_offset (4)

[Unbalance correction of inverter output voltage]

As shown in FIG. 5, when an asymmetrical DC voltage is applied to the capacitors C1 245 and C2 246 connected to the rectifier output or due to a nonuniform circuit constant, the inverter output voltage becomes asymmetrical. As described above, the asymmetrical inverter output voltage contains the DC partial voltage, which causes the transformer and reactor connected to the output to be damaged, so that the inverter output voltage must be recovered symmetrically.

In order to recover the inverter output voltage symmetrically, the inverter output voltage should be adjusted so that the waveform of the (+) period of the inverter output voltage matches the waveform of the (-) period of the inverter output voltage while maintaining the effective value of the inverter output voltage constant. However, when the inverter output voltage is calibrated by the voltage control unit, the load on the controller is increased, and there is a possibility that the inverter output voltage is excessively increased. Therefore, in order to eliminate the burden of the voltage controller 180 and to calibrate the balance of the inverter output voltage, the PWM duty generator 210 performs the balance correction operation of the inverter output voltage.

5 (b), when the voltage of the section having the inverter output voltage of (+) is larger than that of the section of negative (-), the value of the negative m_offset 202 is set in the front keypad 201 .

The m_offset 202 having the negative value in the interval where the inverter output voltage is positive is added to the value stored in the register PWM_full_duty 216 by Equation 3 so that the overall value is smaller than the value stored in the register PWM_full_duty 216 do. When the resultant value is multiplied by the sinusoidal control amount sine_value 214 output from the voltage controller 180, the value becomes a sinusoidal duty value and is summed with the a_offset 193 which is an automatic offset instruction value and stored in the register duty 217. The value of the a_offset 193 is set to a very small value so as not to affect the sine wave characteristic of the inverter output waveform.

The duty value stored in the register duty 217 drives the inverter IGBT by the 3-level PWM via the 3-level PWM converter 220 and decreases in size of the inverter output voltage in the interval where the inverter output voltage is (+). . Also, in the interval where the inverter output voltage is negative, the m_offset 202 having the negative value is subtracted from the value stored in the register PWM_full_duty by Equation (4), so that the overall value is larger than the value stored in the register PWM_full_duty. When the resultant value is multiplied by the sinusoidal control amount sine_value 214 output from the voltage control unit, the value becomes a sinusoidal duty value and is summed with the a_offset 193 which is the automatic offset instruction value and stored in the register Duty 217.

The 3-level PWM converter 220 converts the value stored in the register duty 217 into a 3-level PWM signal to drive the inverter IGBT. In the interval in which the inverter output voltage is negative, .

As described above, since the calibration of the upper and lower waveforms is performed without the operation of the voltage control unit 180, it is possible to minimize the transition of the output during the balance calibration.

On the contrary, if the inverter output voltage of the section having the inverter output voltage of positive (+) duration is smaller than the negative (-) section as shown in (b) of FIG. 5, positive m_offset 202 ) And the equations (3) and (4) are performed, the magnitude of the inverter output voltage is increased in the period in which the inverter output voltage has a positive magnitude and decreased in the negative period.

Equations (3) and (4) can be used to correct the balance of the inverter output voltage without increasing or decreasing the output voltage when correcting the balance of the inverter output voltage. Also, the comparatively large DC deviation due to the impedance difference between C1 (245) and C2 (246) of FIG. 5 is obtained by manually inputting and removing the m_offset 202 at the initial setting of the equipment, And is automatically removed using the a_offset (193).

[3-level PWM signal generation for inverter]

First, the requirements of the PWM signal driving four IGBTs constituting a single-phase three-level inverter will be described.

Referring to FIG. 6, T1 241 generates an inverter output voltage having a positive polarity with respect to neutral point N (248). T1 '242 should provide a current flow path from point P2 247 to neutral point N 248 in the off period of T1 241 during the period when the inverter output voltage is positive. T2 '244 must provide a current flow path from the neutral point N (248) to the point P2 (247) in the interval in which the inverter output voltage is positive. If the T1 241 and the T1 '242 operate simultaneously, the dead time must be set so that the C1 245 will not be operated simultaneously in any case since the C1 245 is short-circuited.

T2 243 generates an inverter output voltage whose polarity is negative with respect to neutral point N 248. T2 '244 should provide a current flow path from neutral point N (248) to point P2 (247) in the interval where the inverter output voltage is negative. T1 '242 should provide a current flow path from the point P2 247 to the neutral point N 248 in the interval where the inverter output voltage is negative. When the T2 243 and the T2 '244 operate simultaneously, the dead time must be set so that the C2 246 is short-circuited so that no case of simultaneous operation occurs.

Since the value stored in the register Duty 217 output from the PWM duty generator 210 includes a negative value because it is an array of numbers vibrated by the sin function, it can not be input to the PWM register of the DSP (not shown) State. The period in which the sign of the value stored in the register Duty 217 is (+) corresponds to the period in which the output voltage is (+). A period in which the sign of the value stored in the register Duty 217 is negative corresponds to a period in which the output voltage is negative.

In order to generate the output voltage of the section where the output voltage is positive in FIG. 6, T 1 switches to generate an output voltage, T 1 'provides a current flow to the neutral line while performing a complementary operation with T 1, , And T2 'must satisfy the requirement of continuity with the neutral line in the (+) interval of the output voltage.

In order to generate the output voltage of the section where the output voltage is negative in FIG. 6, T 2 switches to generate an output voltage, T 2 'provides a current flow to the neutral line while performing a complementary operation with T 2, The operation must be stopped and T1 'must satisfy the requirement of continuity with the neutral line in the interval of the output voltage (-).

It is also assumed that the duty of the PWM waveform applied to T1 and T2 within one period of the output voltage in the equilibrium state is generally the same.

Therefore, the value of the duty (217) of the section in which the value of the register Duty 217 in FIG. 4 is (+) is used for the IGBT T1 241 and T1 '242 without code conversion, and the value of the register Duty 217 is (-) is used for IGBT T2 (243) and T2 '(244).

Therefore, in order to divide the duty value 217 stored in the PWM data value into the IGBT T1 241, T1 '242, T2 243, and T2' 244 in FIG. 6, The value of Duty 217 is stored in the PWM register PDC1 224 of the DSP (not shown) if the value of the value stored in the register Duty 217 output from the register 210 . If the value of Duty 217 is stored in the PDC1 224 when the sign of the value of the duty 217 in FIG. 4 is zero or more, the output of the PWM main output register PDC1_H (217) of the PDC1 224 226 to the IGBT T1 241 and the complement value of the PDC1_H 226 to the IGBT T1 '242 via the PWM complementary output register PDC1_L 227, including the dead time. When the sign of the Duty value 217 is zero or more and the zero value is stored in the PDC2 225, the output of the PWM main output register PDC2_H 228 of the PDC2 225 in the period in which the sign of the output voltage is positive, T2 243 and the complement value of PDC2_H 228 is supplied to the IGBT T2 '244 via the PWM complementary output register PDC2_L 229 in a "high " state.

The sign of the value stored in the register Duty 217 output from the PWM duty generator 210 is checked and if it is less than zero, the zero value is stored in the PWM register PDC1 224 of the DSP (not shown) Stores the value of -Duty (217). When the sign of the Duty value 217 is less than zero and the zero value is stored in the PDC1 224, the output of the PWM main output register PDC1_H 226 of the PDC1 224 in the period in which the sign of the output voltage is negative, And supplies a complementary value of PDC1_H 226 to the IGBT T1 '242 via the PWM complementary output register PDC1_L 227 in a " high " state. When the sign of the value of the duty (217) is less than zero and the value of -Duty (217) is stored in the PDC2 225, the output of the PWM main output register PDC2_H (229) of the PDC2 225 And supplies a complementary value of the PDC2_H 228 to the IGBT T2 'through the PWM complementary output register PDC2_L (229) including the dead time.

6, the IGBTs T1 and T2 for generating the output voltage in the (+) and (-) periods and the IGBTs T1 'and T2' for neutral point clamping in the steady state, Level inverter PWM signals that minimize the unbalance of the output voltage.

Claims

An uninterruptible power supply comprising an upper capacitor and a lower capacitor connected in series to a rectifier output,
The voltage of the upper capacitor and the lower capacitor is a DC link voltage,
A rectifier reference input current I_ref is generated by using an error between the target DC link voltage Vdc_pfc and the detected actual DC link voltage Vdcp + Vdcn, and a rectifier input current I_ref is generated using the error between the rectifier reference input current I_ref and the actual rectifier input current I_pfc A rectifier voltage / current controller for generating a current control amount and storing it in a register sine_value;
A current offset instruction unit for storing a rectifier input current calibration signal input through a keypad of the uninterruptible power supply unit in a register i_offset;
A rectifier PWM duty generator for receiving a value of the register sine_value and a value of the register i_offset and controlling a balance of a rectifier input current and calculating a control value for DC link voltage balance and storing the calculated control value in a register duty; And
And a rectifier PWM synthesizer for generating a 3-level PWM signal using the register duty value and outputting the 3-level PWM signal to a rectifier gate driver.

The method according to claim 1,
Wherein the voltage /
A sinusoidal rectifier input current control amount for controlling the rectifier input current I_ref and the actual rectifier input current I_pfc to maintain the rectifier output voltage at the target DC link voltage Vdc_pfc and to control the rectifier input current to be 1 lt; RTI ID = 0.0 > sine_value. < / RTI >

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The method according to claim 1,
The rectifier PWM synthesizer includes:
If the sign of the value stored in the Duty is equal to or greater than zero in the rectifier PWM duty generator, the value stored in Duty is stored in PDC1, which is a PWM register inside the DSP, and the zero value is stored in PDC2, which is a PWM register in the DSP.
If the sign of the value stored in the Duty output from the rectifier PWM duty generator is less than zero, a zero value is stored in PDC1 of the DSP, and a result stored in Duty is multiplied by the value stored in Duty, And the PMW signal for driving the rectifier can be generated.

The method according to any one of claims 1, 2, and 4,
Wherein the PWM rectifier of the uninterruptible power supply unit is a three-phase three-level PWM rectifier, and the rectifier voltage / current controller, the current offset command unit, the rectifier PWM duty cycle unit, Level PWM rectifier, and controls each single phase of the three-level PWM rectifier.

An uninterruptible power supply comprising an upper capacitor and a lower capacitor connected in series to a rectifier output,
The voltage of the upper capacitor and the lower capacitor is a DC link voltage,
The upper capacitor and the lower capacitor are connected to an inverter,
An inverter voltage controller for inputting the error err of the target inverter output voltage Va_ref and the detected actual inverter output voltage Va to a voltage controller to output a sinusoidal inverter voltage control amount sine_value;
If the value of the first output voltage Vdcp of the upper capacitor is larger than the second output voltage Vdcn of the lower capacitor, the value of the calibration signal a_offset is increased by +1 and the value of the first output voltage Vdcp is smaller than the second output voltage Vdcn A voltage offset automatic control unit decreasing the value of the calibration signal a_offset by -1 and outputting it;
A voltage offset manual command unit for storing, in a register m_offset, a calibration signal for correcting unbalance of an inverter output voltage inputted through a keypad of the UPS;
An inverter PWM duty generator for receiving the sinusoidal inverter voltage control amount sine_value, the calibration signal a_offset, and the calibration signal m_offset to calculate a control value for controlling the inverter output voltage balance and storing the control value in a register Duty;
And an inverter PWM synthesizer for generating a 3-level PWM signal using the register duty value and outputting the 3-level PWM signal to an inverter gate driver.

The method according to claim 6,
The inverter voltage control unit includes:
A control value for controlling the inverter output voltage to a normal value and for keeping the first output voltage Vdcp and the second output voltage Vdcn of the DC link end to be the same is calculated and stored in the duty and outputted to the inverter PWM combining section Features uninterruptible power supply.

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The method according to claim 6,
Wherein the inverter PWM synthesizer comprises:
If the sign of the value stored in the Duty is equal to or greater than zero in the inverter PWM duty generation unit, the value stored in the Duty is stored in the PDC1, which is a PWM register in the DSP, and the zero value is stored in the PWM register, PDC2 in the DSP;
A zero value is stored in the PDC1 of the DSP if the sign of the value stored in the Duty output from the inverter PWM duty generation unit is less than zero and a result value obtained by multiplying the value stored in the duty by (-) is stored in the PDC2. Uninterruptible power supply.

10. The method according to any one of claims 6, 7, and 9,
Wherein the PWM inverter of the uninterruptible power supply unit is a three-phase three-level PWM inverter, and the inverter voltage control unit, the voltage offset automatic control unit, the voltage offset manual command unit, the inverter PWM duty cycle unit, Phases of the three-phase three-level PWM inverter in phase with each other.