JP6834239B2 - Logic generator and logic generation method - Google Patents

Description

The present invention relates to a logic generator and a logic generator.

Conventionally, a control system including a control device that monitors a control target while collecting data from the control target and controls the control target based on the collected data or the like has been used in a plant or the like. The control device included in the control system performs various controls using the control logic created in advance. This control logic may be created using a graphic language such as an FBD (function block diagram) language (see, for example, Patent Document 1).

Japanese Unexamined Patent Publication No. 2004-213277

When creating logic using the FBD language, one signal is described by one line. Therefore, there is an advantage that the signal flow is easy to understand visually. On the other hand, as the number of signals increases, it is necessary to individually describe the corresponding lines, which may increase the labor for creating logic. In addition, since it is necessary to individually correct the signal line when the signal line described once is corrected, there is room for improvement in terms of accuracy.

The present invention has been made in view of the above, and an object of the present invention is to provide a logic generation device and a logic generation method capable of more easily generating highly accurate control logic.

In order to achieve the above object, the logic generation device according to one embodiment of the present invention is a logic generation device that is interpreted and executed in a control device that controls a controlled object to generate control logic in the FBD language, and is the control logic. A structure definition information that defines a structure signal line that integrates the plurality of signal lines while individually holding information related to the plurality of signal lines included in the above, and a description using the structure definition information. It has an acquisition unit for acquiring logic information related to the control logic, and a generation unit for generating control logic using the structure definition information by using the information acquired in the acquisition unit.

In the above logic generator, control logic using the structure definition information is generated. In this way, by generating the control logic using the structure signal line defined by the structure definition information, it is possible to make the control logic written in the FBD language easier to understand visually. Since the number of signal lines to be described in the control logic can be reduced, the work required for the user to generate the control logic can be reduced, and the control logic can be generated with high accuracy. Further, by using the structure signal line in which the information related to the plurality of signal lines included in the control logic is individually held, it is possible to handle the plurality of signal lines individually, and the utilization range of the structure signal line. Can be expanded.

Here, the structure definition information individually identifies the plurality of signal lines collected as the structure signal lines and is used in the control logic to specify specific signal lines included in the plurality of signal lines. The mode may include identifier information that can only describe.

As described above, in the structure definition information, identifier information is individually added to the signal lines included in the structure signal lines. Therefore, it is possible to easily take out only a specific signal line from the signal lines described as the structure signal line and describe it in the control logic, which saves labor for the user to create the control logic. Will be done.

Further, an expansion unit that changes the control logic that uses the structure definition information generated in the generation unit to a description that does not use the structure definition information, and a description that does not use the structure definition information in the expansion unit. It is possible to further have an output unit that outputs the control logic changed to.

As described above, in the expansion unit, the control logic generated by using the structure definition information can be changed to a description that does not use the structure definition information, and can be configured to be output from the output unit. If so, it is possible to change the description to one that does not use the structure and send it to the device that does not hold the structure definition information itself, so we introduced the generation of control logic using the structure definition information. It is not necessary to ensure compatibility with other devices, and it is possible to more easily introduce the generation of control logic using the structure definition information.

The logic generation method according to one embodiment of the present invention is interpreted and executed in a control device that controls a controlled object, and a logic that generates control logic in the FBD language using a logic generating device composed of one or more devices. A structure definition information that defines a structure signal line that combines the plurality of signal lines into one while individually holding information related to a plurality of signal lines included in the control logic, which is a generation method, and the relevant An acquisition step for acquiring logic information related to the control logic described using the structure definition information, and a generation step for generating a control logic using the structure definition information using the information acquired in the acquisition step. And, including.

According to the logic generation method according to one embodiment of the present invention, the control logic described in the FBD language can be visually easily understood and should be described in the control logic as in the logic generation device described above. Since the number of signal lines can be reduced, the work required by the user to generate the control logic can be reduced, and the control logic can be generated with high accuracy. Further, by using the structure signal line in which the information related to the plurality of signal lines included in the control logic is individually held, it is possible to handle the plurality of signal lines individually, and the utilization range of the structure signal line. Can be expanded.

According to the present invention, there is provided a logic generator and a logic generation method capable of more easily generating highly accurate control logic.

It is a schematic block diagram of the control system including the logic generation apparatus which concerns on one Embodiment of this invention. It is a figure explaining the structure definition information. It is a figure explaining the structure signal line which used the structure definition information. It is a figure which shows the example of the block sheet described by using the structure definition information. It is a flowchart which shows the logic generation method which concerns on one Embodiment of this invention. It is a figure explaining the development of the control logic. It is a figure explaining the development of the control logic.

Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the accompanying drawings. In the description of the drawings, the same elements are designated by the same reference numerals, and duplicate description will be omitted.

FIG. 1 is a schematic configuration diagram of a control system according to an embodiment of the present invention. The control system 1 is, for example, a system applied in a plant or the like, and is a system that collects data indicating the state of the device to be controlled and controls the device to be controlled based on the data and other information. is there.

The control system 1 includes a logic generation device 10, a control device 20, and a control target device 30.

The logic generation device 10 is a device that generates control logic for the control device 20 to control the control target device 30. Control logic is a logic program written in the function block diagram (FBD) language. The control logic is composed of a plurality of logics for executing an operation based on the information related to the controlled device 30.

The logic generation device 10 also generates a memory map corresponding to the control logic. The memory map is allocation information indicating the allocation of addresses (memory addresses) for each signal used in the control logic, and is generated for each control logic. The memory map defines the correspondence between each signal used in the control logic and the address where each signal is stored. The control logic and memory map generated by the logic generation device 10 are sent to the control device 20.

The logic generation device 10 is a communication module that communicates with other devices such as a CPU (Central Processing Unit), a RAM (Random Access Memory) and a ROM (Read Only Memory) that are main storage devices, and a control device 20. It is also configured as a computer equipped with hardware such as an auxiliary storage device such as a hard disk. Then, by operating these components, the function as the logic generation device 10 described later is exhibited. Each functional part of the logic generator 10 will be described later.

The control device 20 is a device that controls the control target device 30. The control device 20 acquires data from the control target device 30 and executes a control logic to perform an operation related to the control of the control target device 30. The control device 20 includes an execution engine 21, an input / output unit 22, and a memory 23.

The execution engine 21 has a function of interpreting and executing the control logic. The input / output unit 22 has a function of receiving data or the like from the controlled target device 30 and instructing the controlled target device 30 to execute a process or the like based on the result of executing the control logic by the execution engine 21. .. The memory 23 has a function of storing each signal used in the control logic being executed. As described above, the address assignment for each signal is defined by the memory map which is the allocation information. The memory 23 stores each signal at an assigned address according to a memory map corresponding to the control logic.

The control target device 30 is a device to be controlled by the control device 20 in the control system 1. Examples of the controlled device 30 include an operating device in a plant. Upon receiving the instruction from the control device 20, the control target device 30 performs operation control and the like based on the instruction. Further, the control target device 30 transmits the operation data or the like acquired by the own device to the control device 20 based on the instruction from the control device 20. In this way, the control target device 30 controls the operation by transmitting information indicating the state of the own device to the control device 20 and receiving an instruction corresponding to the state of the own device from the control device 20.

Note that FIG. 1 shows a case where the control device 20 and the control target device 30 constituting the control system 1 are each one, but the control device 20 and the control target device 30 are each included in the control system 1. You may. In this case, the control device 20 may be configured to control a plurality of control target devices 30.

Each functional part of the logic generator 10 will be described. The logic generation device 10 includes a storage unit 11, a logic information acquisition unit 13 (acquisition unit) included in the user interface 12, a structure definition unit 14 (acquisition unit) included in the user interface 12, and a generation unit 15. A development unit 16 and an output unit 17 are included.

The storage unit 11 holds the structure definition information which is the information related to the structure defined in the structure definition unit 14 described later. The information held in the storage unit 11 is used when the control logic is generated and expanded. In addition, the storage unit 11 also holds the control logic generated by the generation unit 15. When the timing of generating the control logic in the logic generation device 10 and the timing of outputting the control logic to another device or the like are different, the generated control logic is stored in the storage unit 11 and the necessary timing is stored. It is preferable to perform the output processing in.

The user interface 12 is a part that outputs the input to the logic generation device 10 by the user and the result of the processing by the logic generation device 10 in response to the input from the user. The user interface 12 includes a logic information acquisition unit 13 and a structure definition unit 14.

The logic information acquisition unit 13 has a function of acquiring logic information necessary for generating control logic. The logic information is, for example, information for specifying a signal included in the control logic, information for specifying signal processing, and the like. The logic information is created by the user operating the user interface 12. The logic information related to the generation of the control logic acquired by the logic information acquisition unit 13 is sent to the generation unit 15.

The structure definition unit 14 has a function of acquiring structure definition information that defines a “structure signal” used when a user creates logic information necessary for creating a control logic. The structure will be described later. The structure definition information is also created by the user operating the user interface 12. The structure definition information acquired by the structure definition unit 14 is sent to the storage unit 11 and stored in the storage unit 11.

The generation unit 15 has a function of generating a control logic and a memory map based on the logic information and the structure definition information. The generation unit 15 generates control logic based on the logic information sent from the logic information acquisition unit 13 and the structure definition information acquired by the structure definition unit 14 and stored in the storage unit 11. The function of the generation unit 15 is realized by, for example, a CPU.

The generation unit 15 generates control logic based on the logic information and the structure definition information. In the generation unit 15, for each signal line created by the user and included in the logic information acquired by the logic information acquisition unit 13, a wire number for specifying a signal line necessary for actually performing processing is assigned. Control logic is generated by performing processing such as allocation. The memory map generated by the generation unit 15 is information for specifying a memory area to be allocated to each signal included in the control logic. In the control logic, the signals specified by the signal lines include signals used for external input / output of the control device 20 (hereinafter, also referred to as signals for external input / output) and calculations performed inside the control device 20. There is a signal used (hereinafter, also referred to as a signal for internal calculation). In the memory map, the address to which each of these signals is assigned is specified.

The control logic and the memory map generated by the generation unit 15 are stored in the storage unit 11 and sent to the output unit 17.

The expansion unit 16 includes a description using the “structure signal” included in the control logic stored in the storage unit 11 when transmitting the control logic and the memory map to the control device 20. It has a function to change to no description. The function of the expansion unit 16 is realized by, for example, a CPU. Although the details will be described later, the control logic transmitted to the control device 20 is converted so as not to include the description related to the structure signal. The expansion unit 16 is a functional unit that is responsible for changing the control logic so that the description related to the structure signal is not included. The expansion unit 16 performs the above processing when the user or the control device 20 or the like instructs the control device 20 to transmit the control logic and the memory map. The control logic and memory map generated by the expansion unit 16 are sent to the output unit 17.

The output unit 17 has a function of outputting the control logic and the memory map generated by the generation unit 15 to a monitor, a printer, or the like. The function of the output unit 17 is realized by, for example, a communication module. The output unit 17 also has a function of transmitting the control logic and the memory map whose description has been changed by the expansion unit 16 to the control device 20. Whether to output the control logic described using the structure signal or the control logic not described using the structure signal may be specified by the user, depending on the output destination. May be specified in advance.

When the control logic and the memory map are output from the output unit 17 to the control device 20, the control device 20 executes the control logic transmitted from the output unit 17 of the logic generation device 10. At the same time, the control device 20 assigns an address according to the memory map transmitted from the output unit 17.

Here, the "structure signal" used in the logic generator 10 will be described. The structure signal is a concept newly used in the logic generator 10 according to the present embodiment. As described above, the logic generation device 10 is a device that generates control logic based on a user operation. In order to improve the accuracy of the control logic while improving the convenience of the user, the "structure signal" is defined in the logic generator 10, and the "structure signal" is used by using the "replacement block" as the function block. Write control logic.

The "structure signal" defined in the logic generator 10 is a signal in which a plurality of signal lines are combined into one signal line in a state where information related to each signal line is individually held. However, how many signal lines related to what kind of signal (for example, analog / digital) are collected and treated as a "structure signal" depends on the logic of the first stage and the second stage. Therefore, when the types and numbers of signal lines included in the "structure signal" are different from each other, it is necessary to define the "structure signal" respectively. Therefore, the definition of "structure signal" is prepared individually when the types and number of signal lines are different from each other, that is, for each "type" of the structure signal.

In the control logic, a process of collecting a plurality of signal lines into a "structure signal" and a process of extracting individual signal lines from a plurality of signals included in the "structure signal" may occur. Therefore, a "replacement block" is used in the control logic. The "replacement block" is to combine a plurality of signal lines into one signal line as a "structure signal" and to divide one signal line as a "structure signal" into a plurality of signal lines based on the definition. It is a function block that does things. Further, when outputting only a part of the signal lines of the "structure signal" represented by one signal line in the control logic, "individual" for designating the individual signals included in the "structure signal". A "signal extraction block" is used.

FIG. 2 is a diagram showing an example of the definition of “structure signal”. FIG. 3 is a diagram illustrating a “replacement block”. Further, FIG. 4 is a diagram showing an example of control logic described using the “structure signal” defined in FIG. 2 and the “replacement block” shown in FIG.

As described above, the "structure signal" is a signal that aggregates a plurality of signal lines, but what kind of signal line and how many signal lines are aggregated differs depending on the situation. That is, the "type" of the "structure signal" is different. Therefore, when the types and numbers of signals included in the "structure signal" are different from each other, it is necessary to define the "structure signal" respectively.

2 (A) and 2 (B) show structure definition information that defines structure signals of different “types”. This structure definition information is information stored in the storage unit 11. FIG. 2A shows the structure definition information in which the structure signal having the model name “ST1” is defined. Further, FIG. 2B shows the structure definition information in which the structure signal having the model name “ST2” is defined. In the structure definition information, signal type information (signal type) and identifier information (identifier) are associated with each of a plurality of signal lines included in the structure. The signal type information is information for specifying the type of signal line, and the identifier information is information for specifying each signal line.

The structure definition information related to ST1 type in FIG. 2 (A) shows that three signal lines are grouped as a structure signal, one of which is analog (ANALOG) and the remaining two. Indicates that it is digital (DIGITAL). Further, it is shown that one analog signal line has an identifier "val" and the two digital signal lines have identifiers "cond1" and "cond2", respectively.

The structure definition information related to ST2 type in FIG. 2 (B) shows that three signal lines are grouped as a structure signal, but two of them are digital (DIGITAL). The other signal type is indicated by "STRUCT ST1", and the structure signal indicated by "ST1" is associated with the signal type. In this way, it is also possible to define a structure signal in which the structure signals are combined. Further, in the structure definition information related to the ST2 type shown in FIG. 2B, it is shown that the two digital signal lines have the identifiers “button1” and “button2”, respectively. On the other hand, the structure signal shown as "ST1" is actually a combination of three signal lines as shown in FIG. 2 (A). Therefore, as shown in FIG. 2B, the identifiers are actually associated with the three identifiers “val”, “cond1”, and “cond2” that refer to the ST1 type structure definition information.

FIG. 3 shows a “replacement block” when the ST1 type structure signal shown in FIG. 2 (A) is used in the control logic. FIG. 3A shows a “PACK” block that combines a plurality of signal lines into one structure signal based on ST1 type structure definition information. "P1 = ST1" is associated with the "PACK" block as a parameter, indicating that the "PACK" block is a replacement block related to the ST1 type structure signal. By using the "PACK" block, the three signal lines of the analog signal "AI0001" and the digital signals "DI0001" and "DI0002" can be combined into one structure signal line. A wire number of "$ VV0001" is assigned to the structure signal line after combining the three signal lines into one. This wire number is used to identify this structural signal line in the control logic.

However, as described above, in the structure signal, a plurality of signal lines are held in a state where the information related to each signal line is individually held. Therefore, the three signal lines grouped as "$ VV0001" are individually assigned line numbers. In addition, individual signals can be specified by using the information for specifying the structure signal line and the definition of the structure.

In FIG. 2A, there is an example in which the individual signals included in the structure signal line “$ VV0001” shown in FIG. 3A are described using the information for specifying the structure signal line and the definition of the structure. , The wire number (solid wire number) actually assigned to each signal is shown. As shown in FIG. 2A, the three signal lines included in the structure signal line “$ VV0001” are “$ VV0001.val” and “$ VV0001.cond1” by using the identifier of the structure definition information. , "$ VV0001.cond2" can be distinguished. In the control logic, the user can handle the signals individually by using this method of specifying the individual signals. Further, each signal indicated as "$ VV0001.val", "$ VV0001.cond1", and "$ VV0001.cond2" is actually referred to as "$ EE7001", "$ LL7001", and "$ LL7002", respectively. A wire number is assigned. The solid wire number of each signal included in the structure signal is used in the memory map. In the memory map, the memory address to which the signal is assigned is set in association with the solid wire number. As described above, since the solid wire number mainly specifies the signal used in the internal processing, the solid wire number is not shown to the user. Therefore, the user can handle each signal by using the identifier without recognizing the information related to the assigned wire number.

In FIG. 2B, an example in which individual signals included in the structure signal line “$ VV0003” defined using the ST2 type are described using information for specifying the structure signal line and the definition of the structure. And the solid wire number assigned to each signal. As shown in FIG. 2B, the structure ST1 is incorporated in the structure ST2. Therefore, the structure signal lines in the structure ST2 are actually two signal lines defined by the structure definition information of ST2 type and three signal lines defined by the structure definition information of ST1. , Are summarized. At this time, as shown in FIG. 2B, among the signal lines included in the structure signal line “$ VV0003”, the two signal lines defined in the structure definition information of ST2 are the structure definition information. It is possible to distinguish between "$ VV0003.button1" and "$ VV0003.button2" by using the identifier of. On the other hand, for the three signal lines included in the structure ST1 incorporated in the structure ST2, "$ VV0003.ST1.val" and "$ VV0003" are used by using the definition in the structure definition information of ST1 type. It can be expressed as ".ST1.cond1" and "$ VV0003.ST1.cond2". Therefore, even when another structure is incorporated in a specific structure, individual signals can be specified by using the above method. Also in the case shown in FIG. 2B, "$ VV0003.button1", "$ VV0003.button2", "$ VV0003.ST1.val", "$ VV0003.ST1.cond1", "$ VV0003.ST1" Each of the five signals labeled ".cond2" is actually assigned the wire numbers "$ LL9000", "$ LL9001", "$ EE9001", "$ EE9010", and "$ EE9011", respectively. This point is common to the example shown in FIG. 2 (A).

Returning to FIG. 3, FIG. 3B shows an “UNPACK” block that divides one structure signal into three signal lines based on the ST1 type structure definition information. "P1 = ST1" is associated with the "UNPACK" block as a parameter, indicating that the "UNPACK" block is a replacement block related to the ST1 type structure signal. By using the "UNPACK" block, one structure signal line is divided into one analog signal "AO001" and two digital signals "DO0001" and "DO0002" based on the ST1 type structure definition information. It can be divided into three signal lines.

In the control logic, as described above, the substitution block associated with the structure definition information is used to combine the structure signal lines and decompose the structure signal lines. The structure definition information is associated with the control logic, but is treated as information different from the control logic. Therefore, the structure definition information can be applied to different signal lines. Further, in the control logic, it is described using a replacement block in which the "type" of the structure is specified.

FIG. 4 shows an example of a block sheet which is a sheet in which control logic is described by using a replacement block by using the two structure definition information defined in FIG. The block sheet shown in FIG. 4 is information created by the user for generating control logic, and is information corresponding to logic information provided by the user. That is, the information and the like related to the solid wire number assigned by the generation unit 15 of the logic generation device 10 are not included.

In FIG. 4, three signals are put together by the “PACK” block B1 shown to use the ST1 type structure definition information, and the structure signal line indicated by the wire number “$ VV0001” is created. Further, the structure signal line represented by the wire number "$ VV0001" is branched, and one of them is used in the "MACRO" block B2. When the structure signal line is not used, five signal lines are input to the "MACRO" block B2 instead of the three signal lines including the structure signal line. By using the body signal line, it is possible to describe in a state where the signal line input to the "MACRO" block B2 is reduced. In the "MACRO" block B2, the structure signal line is also used for the output. Specifically, the signal line represented by the wire number "$ VV0002" corresponds to the structure signal line.

Further, the other side of the structure signal line indicated by the branched line number "$ VV0001" is input to the "PACK" block B3 shown to use the ST2 type structure definition information. In the ST2 type structure, as shown in FIG. 2B, it is defined that the third signal is the ST1 type structure signal line. Therefore, two signal lines and one structure signal line are input to the "PACK" block B3 based on the information shown in FIG. 2 (B). Then, the ST2 type structure signal line is output as the line number "$ VV0003".

The structure signal line indicated by the wire number "$ VV0001" is branched, and one is input to the "SCF2" block and the other is shown to use ST2 type structure definition information "UNPACK". Is input to block B4. As a result, two signal lines and an ST1 type structure signal line indicated as "$ VV0004" are output based on the ST2 type structure definition information.

Further, FIG. 4 shows an example in which individual signals of the structure signal are taken out and used. The lower side of FIG. 4 shows an example in which signals described as two blocks B5 and B6 using the "individual signal extraction block" are input to the "AND" block B7. In blocks B5 and B6, signal names using identifiers of "$ VV0002.on" and "$ VV0003.on" are described, respectively, and structures specified by "$ VV0002" and "$ VV0003", respectively. In the signal line, it is shown that the signal is identified by the identifier "on".

As shown in FIG. 4, it is preferable that the structure signal is described separately from other individual signals. As a result, the structure signal and other signals can be easily distinguished, so that modifications and the like can be easily performed. Similarly, it is preferable that the "individual signal extraction block" indicating that individual signals included in the structure signal are extracted is also described separately from other individual signals.

In this way, in the control logic, the control logic written in the FBD language can be easily visually understood by describing using the structure signal line defined by the structure signal information. At the same time, since the number of signal lines to be described in the control logic can be reduced, the work required by the user to generate the control logic can be reduced.

Here, a logic generation method in the logic generation device 10 will be described with reference to FIG. FIG. 5 is a flowchart showing a logic generation method according to an embodiment of the present invention.

First, the user creates logic information and structure definition information using the user interface 12. That is, the user interface 12 acquires the logic information and the structure definition information (acquisition step). As a result, the generation unit 15 generates the control logic using the structure definition information (S01: generation step). The generation unit 15 also generates a memory map corresponding to the control logic. The control logic and memory map generated in the generation unit 15 are output from the output unit 17 as needed. Further, the control logic, the memory map, and the structure definition information are stored in the storage unit 11 (S02). The above two steps are steps performed when the logic generation device 10 generates control logic based on a user's instruction.

Next, when it becomes necessary to transmit the control logic and the memory map to the control device 20, the expansion unit 16 performs a process related to the expansion of the structure included in the control logic based on the user's instruction or the like. It is done (S03). Then, the control logic after expansion is output from the output unit 17 to the control device 20 (S04). As described above, in the logic generation device 10, the control logic using the structure is generated by using the structure definition information. On the other hand, when the control logic is transmitted to the control device 20, the control logic is changed to a description that does not use a structure. This process is called "expansion".

6 and 7 show a method of expanding the description related to the structure in the control logic. FIG. 6 (A) shows the control logic described by using the ST1 type structure definition information shown in FIG. 2 (A), and has the same description as in FIG. 3 (A). In FIG. 6A, the line number of the structure signal line is "$ VV0001", and the solid line numbers of the three signals included in the structure signal are "$ EE8001", "$ LL8001", and "$ LL8002". It shows that. The "expansion" in the present embodiment is to convert the control logic shown in FIG. 6 (A) into a solid wire number without using the "PACK" block. Specifically, as shown in FIG. 6 (B), the three signals on the input side and the solid wire number corresponding to each signal included in the structure signal are equivalent to the "AEQ" block or "LEQ" block. Perform the process of connecting with the blocks indicating. As a result, the signals on the three input sides and the solid wire numbers of the three signals included in the structure signal can be individually connected. As for the "UNPACK" block, the solid wire number corresponding to each signal included in the structure signal and the signal on the output side can be obtained by substituting using the block showing equivalent as in the "PACK" block. Can be connected individually.

FIG. 7 describes a method of developing an “individual signal extraction block” related to a structure signal. In FIG. 7A, the structure definition information that defines the structure in which the two signal lines are combined as the ST3 type is used. Then, in FIG. 7A, the signals specified by the identifiers “on” are individually extracted from the two structure signal lines “$ VV0001” and “$ VV0002” using the ST3 type structure definition information. , The control logic to enter in the "AND" block is shown. Here, it is assumed that the solid line numbers "$ EE8001" and "$ LL8001" are assigned to the two signal lines included in the structure signal line "$ VV0001", respectively. Further, it is assumed that the solid line numbers "$ EE8002" and "$ LL8002" are assigned to the two signal lines included in "$ VV0002", respectively. In this case, the solid line numbers of the signal lines described as "$ VV0001.on" and "$ VV0002.on" in the "individual signal extraction block" are "$ LL8001" and "$ LL8002". Therefore, as shown in FIG. 7B, the signal line described by the “individual signal extraction block” is converted into a block with a solid line number. As a result, the control logic can be changed to a description that does not use the "individual signal extraction block", that is, a description that does not use the structure defined by the structure definition information.

As described above, since the concept related to the structure is defined and used in the logic generation device 10, when the control logic is transmitted to another device such as the control device 20, the description related to the structure is described. It can be converted so that it is not used.

As described above, in the logic generation device 10 and the logic generation method according to the present embodiment, a plurality of signal lines included in the control logic are described by substituting one structure signal line by using the structure definition information. can do. Therefore, it is possible to save labor in creating the control logic by the user. In addition, when the description uses the structure signal line, the number of signal lines included in the control logic can be reduced, so that a mistake may occur especially when the number of signal lines increases and becomes complicated. Etc. can be reduced. Therefore, it is possible to more easily generate highly accurate control logic.

Further, according to the structure definition information, the plurality of signal lines are combined into one as a structure signal line in a state where the information related to the plurality of signal lines included in the control logic is individually held. Therefore, since a plurality of signal lines can be handled individually even after they are combined into one as a structure signal line, the description of the signal line can be flexibly changed in the control logic. Further, even when a structure signal line is input to a block for performing numerical calculation such as a macro, individual numerical calculation or the like can be preferably performed.

Further, when the information related to the plurality of signal lines included in the control logic is individually held, a plurality of information in the memory map which is the information specifying the memory area to be allocated to each signal included in the control logic. When allocating a memory area for each signal included in the signal line of, for example, it is not necessary to allocate a continuous memory area, and a flexible response becomes possible. Therefore, it is also useful in creating a memory map.

Further, in the above-mentioned logic generator 10, the structure definition information is individually set for the signal line included in the structure signal line so that the specific signal line included in the structure signal line can be taken out and described. The identifier information is given to. Therefore, it is possible to easily extract and describe only a specific signal line from the signal lines described as the structure signal line, and the labor saving for the user to create the control logic is realized. ..

Further, in the logic generation device 10, the control logic generated by using the structure definition information can be expanded in the expansion unit 16 in a state where the structure definition information is not used and output from the output unit 17. ing. Therefore, the structure definition information is used because it is possible to change the description to one that does not use the structure and transmit it to a device that does not hold the structure definition information itself, such as the control device 20. When introducing the generation of control logic, it is not necessary to ensure compatibility with other devices, and it is possible to more easily introduce the generation of control logic using the structure definition information.

The embodiments described above show an example of the present invention. The logic generation device and the logic generation method according to the present invention are not limited to the above-described embodiment, and may be modified or applied to other objects without changing the gist described in each claim. Good.

For example, the logic generation device 10 may be configured by one device as described in the above embodiment, or may be configured by a combination of a plurality of devices. Further, the number of the control device 20 and the control target device 30 constituting the control system 1 may be plural. In this case, for example, the control device 20 may be configured to control a plurality of control target devices 30.

Further, in the above-mentioned logic generation device 10, when the control logic is output to the control device 20, the expansion unit 16 changes (expands) the control logic to a description that does not use the structure definition information, and then outputs the control logic. It was a premise. However, for example, when the control device 20 also holds the structure definition information, the output of the control logic described using the structure definition information does not affect the interpretation and execution. May be configured to omit the deployment in the deployment unit 16 and output to another device such as the control device 20.

1 Control system 10 Logic generator 11 Storage unit 12 User interface 13 Logic information acquisition unit 14 Structure definition unit 15 Generation unit 16 Deployment unit 17 Output unit 20 Control device 21 Execution engine 22 Input / output unit 23 Memory 30 Control target device

Claims (4)

A interpret and control logic that will be executed in the control apparatus for controlling a controlled object, a logic generator for generating the control logic written in FBD language,
A structure definition information that defines a structure signal line that integrates the plurality of signal lines into one while individually holding information related to the plurality of signal lines included in the control logic, and the structure definition information. The acquisition unit that acquires the logic information related to the control logic described using
A generation unit that generates control logic using the structure definition information using the information acquired in the acquisition unit, and a generation unit.
Logic generator with. The structure definition information individually identifies the plurality of signal lines collected as the structure signal lines and is used in the control logic to describe only specific signal lines included in the plurality of signal lines. The logic generator according to claim 1, which includes identifier information that can be used. An expansion unit that changes the control logic that uses the structure definition information generated in the generation unit to a description that does not use the structure definition information.
An output unit that outputs the control logic changed to a description that does not use the structure definition information in the expansion unit,
The logic generator according to claim 1 or 2, further comprising. A interpret and control logic that will be executed in the control apparatus for controlling a control object, the control logic written in FBD language, logic generating method for generating with a configured logic generating device by one or more devices And
A structure definition information that defines a structure signal line that integrates the plurality of signal lines into one while individually holding information related to the plurality of signal lines included in the control logic, and the structure definition information. The acquisition step to acquire the logic information related to the control logic described using
A generation step that generates control logic using the structure definition information using the information acquired in the acquisition step, and a generation step.
Logic generation method including.

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