JP6790541B2 - Logic update device and logic update method - Google Patents

Description

The present invention relates to a logic update device and a logic update method.

Conventionally, there has been known a method of updating the control logic of a control device while the control device that controls the control target is continuously operated. For example, Patent Document 1 describes a method of switching the control logic by placing both the control logic before and after the change on the memory. In this method, among the variables that make up the control logic after the change, the variables that are changed from the variables that make up the control logic before the change and the newly added variables are initialized, and then the control logic is changed. Will be done.

JP-A-2002-63045

When the control logic is updated, the memory address may be automatically assigned to the signal used in the control logic for update instead of being manually assigned by the user. In this case, although the burden on the user can be reduced, there is a possibility that the memory address is not assigned properly, and there is room for improvement.

The present invention has been made in view of the above, and an object of the present invention is to provide a logic update device and a logic update method capable of appropriately allocating a memory address when updating a control logic.

In order to achieve the above object, the logic update device according to one embodiment of the present invention generates a second control logic executed in the control device instead of the first control logic executed in the control device controlling the controlled object. A logic updater used in a storage means for storing first allocation information indicating allocation of a memory address of a control device for each signal used in the first control logic, a second control logic, and a second control logic. A generation means for generating a second allocation information indicating the allocation of the memory address of the control device for each signal to be performed, and an output means for outputting the second control logic and the second allocation information are provided, and the generation means is the first. When the signal used in the second control logic is included in the first allocation information by referring to the allocation information, the memory address of the control device assigned to the signal in the first allocation information is the signal. Generates second allocation information so that it can be allocated to.

According to the findings of the present inventors, in the case where the operation result of the control logic is affected by the operation result up to the previous time, if the allocation of the memory address holding the operation result up to the previous time changes, an appropriate operation result is obtained. It may not be obtained. Therefore, in the logic update device according to one embodiment of the present invention, the generation means refers to the first allocation information, and when the signal used in the second control logic is included in the first allocation information, the first is The second allocation information is generated so that the memory address of the control device assigned to the signal in the allocation information is assigned to the signal. Therefore, even if the control logic is changed, the allocation of the memory address that holds the operation result up to the previous time is maintained. As a result, it is possible to appropriately allocate the memory address accompanying the update of the control logic so that an appropriate calculation result can be obtained even when the calculation result of the control logic is affected by the calculation result up to the previous time.

Here, the generation means refers to the first allocation information, and if the signal used in the second control logic is not included in the first allocation information, the generation means is allocated to another signal in the first allocation information. The second allocation information can be generated so that a memory address different from the memory address of the control device is assigned to the signal.

With the above configuration, among the signals used in the second control logic, the signals not used in the first control logic are not assigned to other signals in the first allocation information. The memory address of the controller is assigned. Therefore, for example, it is suppressed that the signal newly added by the second control logic is affected by the value held with respect to the signal used by the first control logic.

In the logic update method according to one embodiment of the present invention, the second control logic executed in the control device instead of the first control logic executed in the control device controlling the controlled object is composed of one or more devices. This is a logic update method generated by using the logic update device, which is a storage step for storing the first allocation information indicating the allocation of the memory address of the control device for each signal used in the first control logic, and the second control. A generation step for generating the second allocation information indicating the allocation of the memory address of the control device for each signal used in the logic and the second control logic, and an output step for outputting the second control logic and the second allocation information. The generation step refers to the first allocation information, and if the signal used in the second control logic is included in the first allocation information, it is assigned to the signal in the first allocation information. The second allocation information is generated so that the memory address of the control device is assigned to the signal.

According to the logic update method according to one embodiment of the present invention, an appropriate calculation result can be obtained even when the calculation result of the control logic is affected by the calculation results up to the previous time, as in the logic update device described above. In addition, the memory address can be appropriately assigned when the control logic is updated.

According to the present invention, there is provided a logic update device and a logic update method capable of appropriately allocating a memory address when updating a control logic.

It is a schematic block diagram of the control system which concerns on one Embodiment of this invention. It is a figure which shows an example of a macro. It is a figure which shows an example of the control logic using the macro of FIG. It is a figure which shows an example of the memory map corresponding to the control logic of FIG. It is a flowchart which shows the logic update method which concerns on one Embodiment of this invention. It is a figure which shows an example of the control logic for execution and the control logic for update. It is a figure which shows an example of the memory map during execution and the memory map for update. It is a figure which shows the memory map for update generated by the logic update apparatus which concerns on a comparative example.

Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the accompanying drawings. In the description of the drawings, the same elements are designated by the same reference numerals, and duplicate description will be omitted.

FIG. 1 is a schematic configuration diagram of a control system according to an embodiment of the present invention. The control system 1 is, for example, a system applied in a plant or the like, and is a system that collects data indicating the state of the device to be controlled and controls the device to be controlled based on the data and other information. is there. The control system 1 includes a logic update device 10, a control device 20, and a control target device 30.

The logic update device 10 is a control logic (second control logic) executed in the control device 20 instead of the control logic (first control logic) (hereinafter, also referred to as an executing control logic) executed in the control device 20. It is a device that generates (hereinafter, also referred to as control logic for updating). The control logic is, for example, a logic program created in a function block diagram (FBD) language or the like. The control logic is composed of a plurality of logics for executing an operation based on the information related to the controlled device 30. The control logic is updated for, for example, a change in a variable to be monitored by the control target device 30, a change in a part of the logic, or the like.

The logic update device 10 further generates a memory map (second allocation information) (hereinafter, also referred to as a memory map for update) corresponding to the control logic for update. The memory map is allocation information indicating the allocation of addresses (memory addresses) for each signal used in the control logic, and is generated for each control logic. The memory map defines the correspondence between each signal used in the control logic and the address where each signal is stored. The update control logic and the update memory map generated by the logic update device 10 are sent to the control device 20. The control logic being executed and the memory map being executed may be generated by the logic update device 10 or may be generated by an external device.

The logic update device 10 is a communication module that communicates with other devices such as a CPU (Central Processing Unit), a RAM (Random Access Memory) and a ROM (Read Only Memory) that are main storage devices, and a control device 20. It is also configured as a computer equipped with hardware such as an auxiliary storage device such as a hard disk. Then, by operating these components, the function as the logic update device 10 is exhibited. Each functional part of the logic update device 10 will be described later.

The control device 20 is a device that controls the control target device 30. The control device 20 acquires data from the control target device 30 and executes a control logic to perform an operation related to the control of the control target device 30. The control device 20 includes an execution engine 21, an input / output unit 22, and a memory 23.

The execution engine 21 has a function of interpreting and executing the control logic. The input / output unit 22 has a function of receiving data or the like from the controlled target device 30 and instructing the controlled target device 30 to execute a process or the like based on the result of executing the control logic by the execution engine 21. .. The memory 23 has a function of storing each signal used in the control logic being executed. As described above, the address assignment for each signal is defined by the memory map which is the allocation information. The memory 23 stores each signal at an assigned address according to a memory map (first allocation information) (hereinafter, also referred to as an execution memory map) corresponding to the control logic being executed.

The control target device 30 is a device to be controlled by the control device 20 in the control system 1. Examples of the controlled device 30 include an operating device in a plant. Upon receiving the instruction from the control device 20, the control target device 30 performs operation control and the like based on the instruction. Further, the control target device 30 transmits the operation data or the like acquired by the own device to the control device 20 based on the instruction from the control device 20. In this way, the control target device 30 controls the operation by transmitting information indicating the state of the own device to the control device 20 and receiving an instruction corresponding to the state of the own device from the control device 20.

Each functional part of the logic update device 10 will be described. The logic update device 10 includes a storage unit 11 (storage means), an acquisition unit 13 (acquisition means) included in the user interface 12, a generation unit 14 (generation means), and an output unit (output means) 15. Consists of.

The storage unit 11 has a function of storing the control logic being executed and the memory map being executed. The function of the storage unit 11 is realized by, for example, a RAM or a ROM. The running memory map shows the address assignment for each signal used in the running control logic. When the control logic being executed and the memory map being executed are generated by the logic updater 10, the storage unit 11 stores them when, for example, the control logic being executed and the memory map being executed are generated. .. When the control logic being executed and the memory map being executed are generated by an external device, the storage unit 11 stores these when receiving, for example, the control logic being executed and the memory map being executed from the external device. Remember.

The user interface 12 has a function of performing input to the logic update device 10 by the user and output of the result of processing by the logic update device 10 in response to the input from the user. The user interface 12 includes an acquisition unit 13.

The acquisition unit 13 has a function of acquiring change information which is information related to a change in the control logic during execution. The change information is, for example, information indicating a change from the running control logic in the update control logic. The change information is created by the user operating the user interface 12. Since the logic update device 10 has a function of creating change information in this way, when the change information needs to be corrected, the logic update device 10 can easily correct the change information. The generation of control logic for update is started when the change information is created. The change information acquired by the acquisition unit 13 is sent to the generation unit 14.

The generation unit 14 has a function of generating a control logic for update and a memory map for update. The function of the generation unit 14 is realized by, for example, a CPU. The generation unit 14 generates the control logic for update based on the change information sent from the acquisition unit 13. For example, the generation unit 14 reads the control logic being executed from the storage unit 11 and then changes the control logic being executed based on the change information to generate the control logic for update.

The signals used in the control logic include signals used for external input / output of the control device 20 (hereinafter, also referred to as signals for external input / output) and signals used for calculations performed inside the control device 20. (Hereinafter, it is also called a signal for internal calculation). In the present embodiment, in the memory 23, an address for storing each signal for external input / output is explicitly assigned by the user. On the other hand, an address for storing each signal for internal calculation is automatically assigned by the generation unit 14. In this way, the generation unit 14 automatically assigns addresses, so that the burden on the user related to address allocation can be reduced.

Macros may be defined for control logic that has the same structure but differs only in the value of each signal. The use of such macros improves the diversion of control logic. FIG. 2 is a diagram showing an example of a macro. As shown in FIG. 2, macro A returns a value obtained by integrating the input signals. FIG. 3 is a diagram showing an example of control logic using the macro of FIG. FIG. 4 is a diagram showing an example of a memory map corresponding to the control logic of FIG. As shown in FIG. 4, the first half of the memory map is allocated to signals for external input / output. Specifically, addresses 1 to 4 are assigned to signals for external input / output. The address immediately after the address assigned to the signal for external input / output is assigned to the signal for internal calculation. Specifically, addresses 5 to 8 are assigned to signals for external input / output. The latter half of the memory map, specifically, addresses 9 and 10 are unused addresses to which no signal used in the control logic is assigned.

In the control logic of FIG. 3, macro A is used twice as macro A1 and macro A2. The signals used in macro A1 and macro A2 need to be stored in different addresses so that the logic operations of macro A1 and macro A2 are not influenced by each other. For example, although the signal "MACRO_ANALOG1" is the same signal on macro A1 and macro A2, the assigned addresses need to be different. Therefore, as shown in FIG. 4, the signals "IN_ANALOG1", "ANALOG_RESULT1", "A1_MACRO_ANALOG1", and "A1_MACRO_ANALOG2" used in the macro A1 are assigned addresses 1, 2, 5, and 6, respectively. Addresses 3, 4, 7, and 8 are assigned to the signals "IN_ANALOG2", "ANALOG_RESULT2", "A2_MACRO_ANALOG1", and "A2_MACRO_ANALOG2" used in the macro A2, respectively.

The generation unit 14 refers to the memory map being executed stored in the storage unit 11, and when the signal used in the control logic for update is included in the memory map being executed, the memory map being executed is used. A memory map for update is generated so that the address assigned to this signal is also assigned to this signal in the memory map for update. Details of the address assignment by the generation unit 14 will be described later. In the present embodiment, the generation unit 14 assigns an address to each signal for internal calculation used in the control logic for update. The generation unit 14 has a relationship between each signal for internal calculation and an address assigned by the generation unit 14 for each signal for internal calculation, each signal for external input / output, and each signal for external input / output. A memory map for update is generated as information including the relationship with the address explicitly assigned by the user for each signal.

The update control logic and the update memory map generated by the generation unit 14 are sent to the output unit 15. The update control logic and the update memory map are also sent to the storage unit 11. In the storage unit 11, the update control logic and the update memory map sent from the generation unit 14 are stored as the control logic being executed and the memory map being executed.

The output unit 15 has a function of transmitting the update control logic and the update memory map generated by the generation unit 14 to the control device 20. The function of the output unit 15 is realized by, for example, a communication module. In the control device 20, the update control logic transmitted from the output unit 15 is executed in place of the execution control logic. At the same time, the control device 20 assigns an address according to the update memory map transmitted from the output unit 15.

Next, a logic update method using the logic update device 10 will be described with reference to FIGS. 1 and 5 to 7. FIG. 5 is a flowchart showing a logic updating method according to an embodiment of the present invention. Prior to the process shown in FIG. 5, the storage unit 11 stores the control logic being executed and the memory map being executed (memory step). Subsequently, as shown in FIG. 5, the acquisition unit 13 acquires the change information (S11). The change information is created by the user operating the user interface 12. The acquisition unit 13 acquires the created change information and sends it to the generation unit 14.

FIG. 6 is a diagram showing an example of the control logic during execution and the control logic for update. In the running control logic shown in FIG. 6A, the macro A, which doubles the input signal and returns the integrated value, is used once as the macro A1. In the update control logic shown in FIG. 6B, the macro A that returns the integrated value of the input signals is used once as the macro A1. In this example, the execution control logic shown in FIG. 6 (a) is modified to delete the logic surrounded by the broken line L, and the update macro A1 shown in FIG. 6 (b) is generated. Will be done. Therefore, the change information in this example is the information that the logic surrounded by the broken line L in FIG. 6A is deleted.

Next, the generation unit 14 generates the control logic for update based on the change information sent from the acquisition unit 13 (S12). Subsequently, the generation unit 14 generates a memory map for update (S13 to S15: generation step). First, the generation unit 14 refers to the memory map being executed, and determines whether or not the signal used in the control logic for update is included in the memory map being executed (S13). In the present embodiment, each signal for internal calculation used in the control logic for update is used as an allocation target signal, and the determination process of S13 is performed on these allocation target signals.

When the signal to be allocated is included in the running memory map (Yes in S13), the same address as the address assigned to the signal to be allocated in the running memory map is updated. Also in the memory map, it is assigned to the signal to be allocated (S14). On the other hand, when the signal to be allocated is not included in the memory map being executed (No in S13), the address is an unused address in the memory map being executed (hereinafter, an unused address in the memory map being executed). (Also also referred to as) is assigned to the signal to be allocated in the memory map for update (S15). As a signal that is not included in the memory map being executed, for example, a signal newly added by the control logic for update can be considered. It can be said that the generation unit 14 assigns an address different from the address assigned to the other signals in the executing memory map to the newly added signal to be assigned. The generation unit 14 allocates unused addresses in the memory map being executed, for example, in order from the front.

The generation unit 14 describes the relationship between each signal for internal calculation and the address thus assigned to each signal for internal calculation, each signal for external input / output, and each signal for external input / output. A memory map for update is generated as information including the relationship with the address explicitly assigned by the user. The generation unit 14 stores the generated macro A1 for update as the control logic for update and the memory map for update in the storage unit 11 and sends them to the output unit 15.

FIG. 7 is a diagram showing an example of a memory map being executed and a memory map for updating. In the running memory map shown in FIG. 7A, for each signal "IN_ANALOG1" and "ANALOG_RESULT1" for external input / output used in the running macro A1 as the running control logic, Addresses 1 and 2 are assigned. Addresses 3 to 5 are assigned to each signal "A1_MACRO_ANALOG1", "A1_MACRO_ANALOG2", and "A1_MACRO_ANALOG3" for internal calculation used in the macro A1 being executed.

In the update memory map shown in FIG. 7 (b), the external input / output signals "IN_ANALOG1" and "ANALOG_RESULT1" used in the update macro A1 are the same as the running memory map. Addresses 1 and 2 are pre-assigned by the user. The internal calculation signals "A1_MACRO_ANALOG2" and "A1_MACRO_ANALOG3" used in the update macro A1 are both included in the running memory map (that is, corresponding to the case of Yes in S13 above). Therefore, the addresses assigned to these signals in the running memory map are also assigned to these signals by the generation unit 14 in the memory map for update. Specifically, the signal "A1_MACRO_ANALOG2" is assigned the address 4 assigned in the running memory map, and the signal "A1_MACRO_ANALOG3" is assigned the address 5 assigned in the running memory map. Is assigned.

Subsequently, the output unit 15 outputs the update macro A1 and the update memory map (S16: output step). Specifically, the output unit 15 transmits the update macro A1 and the update memory map to the control device 20. When the control device 20 receives the update macro A1 and the update memory map, the macro A1 being executed during the operation of the control device 20 is switched to the update macro A1 and the running memory map is switched. Is switched to the memory map for update. As a result, the controlled device 30 is controlled by the macro A1 for updating.

According to the logic update device 10 and the logic update method according to the present embodiment described above, address allocation associated with the update of the control logic can be appropriately performed. This point will be described below with reference to a comparative example.

FIG. 8 is a diagram showing a memory map for update generated by the logic update device according to the comparative example. As described above, in the logic update device 10 according to the present embodiment, the generation unit 14 refers to the memory map being executed and generates a memory map for update. On the other hand, in the logic update device according to the comparative example, the generation unit uses the address immediately after the address assigned to the signal for external input / output for internal calculation without referring to the memory map being executed. Allocate the signals in order from the front. Therefore, different addresses are assigned to the same signal between the executing macro A1 and the updating macro A1.

As described above, the executing macro A1 returns the integrated value of the input signals, and the updating macro A1 returns the integrated value of the input signals doubled. That is, the calculation results of the macro A1 being executed and the macro A1 for updating are both affected by the past amount (calculation results up to the previous time). The past amount is held as the value of the signal "A1_MACRO_ANALOG3". In the running memory map, as shown in FIG. 7A, the address 5 is assigned to the signal "A1_MACRO_ANALOG3" for internal calculation. On the other hand, in the memory map for update, the address 4 is assigned to the same signal as shown in FIG. Therefore, if the control logic of the control device 20 is updated while the control device 20 is in operation, an appropriate calculation result may not be obtained because the past amount is acquired from the address 4 instead of the address 5 in the calculation immediately after the update. There is.

On the other hand, in the logic update device 10 and the logic update method according to the present embodiment, the generation unit 14 refers to the memory map being executed, and the signal to be allocated is included in the memory map being executed. , Generates an update memory map so that the address assigned to this signal in the running memory map is also assigned to this signal in the update memory map. Therefore, if the signal "A1_MACRO_ANALOG3" is assigned the address 5 in the running memory map, the address 5 is also assigned to the signal "A1_MACRO_ANALOG3" in the update memory map. Therefore, even if the macro A1 in which the control logic is being executed is switched to the macro A1 for update during the operation of the control device 20, the address of the signal "A1_MACRO_ANALOG3" in which the past amount is retained is the same, and therefore an appropriate calculation The result is obtained. As described above, in the logic update device 10 and the logic update method, the layout of the memory map for update is generated while maintaining the layout of the memory map being executed as much as possible. As a result, even if the control logic is updated, the control device 20 can stably control the control target device 30.

If the signal to be allocated is not included in the memory map being executed, the generation unit 14 updates the memory map so that the unused address in the memory map being executed is allocated to the signal to be allocated. To generate. That is, among the signals used in the control logic for update, the unused addresses in the memory map being executed are assigned to the signals not used in the control logic being executed. Therefore, for example, it is suppressed that the signal newly added in the control logic for update is affected by the value held for the signal used in the control logic being executed.

The embodiments described above show an example of the present invention. The logic updating device and the logic updating method according to the present invention are not limited to the above-described embodiment, and may be modified or applied to other objects without changing the gist described in each claim. Good.

For example, the logic update device 10 may be configured by one device as described in the above embodiment, or may be configured by a combination of a plurality of devices. Further, the number of the control device 20 and the control target device 30 constituting the control system 1 may be plural. In this case, for example, the control device 20 may be configured to control a plurality of control target devices 30.

If the signal to be allocated is not included in the memory map being executed, the generation unit 14 allocates the address assigned to the other signal in the memory map being executed to the signal to be allocated. As such, a memory map for update may be generated. That is, the address assigned in the memory map for update with respect to the signal to be allocated is not limited to the unused address in the memory map being executed. For example, an address to which a signal is assigned in the running memory map but not used in the update control logic is assigned to the signal to be assigned in the update memory map. It can be configured to be assigned. The generation unit 14 can assign such addresses to the signals to be assigned, for example, in order from the front. As a result, a continuous free area can be easily secured in the memory 23 after allocation.

The storage unit 11 stores not only the control logic being executed and the memory map being executed, but also a plurality of past control logics and a plurality of past memory maps, refers to the past memory maps, and is a memory for updating. It may be configured to generate a map. The past control logic is the control logic executed by the control device 20 after the time when the control device 20 was last reset. The control logic being executed is one of a plurality of past control logics, and is the newest control logic among the plurality of past control logics. The past memory map is a memory map showing the address assignment for each signal used in the past control logic. The running memory map is one of a plurality of past memory maps, and is the newest memory map among the plurality of past memory maps.

In this configuration, when the generation unit 14 assigns an address as a signal to be allocated as a signal for internal calculation, if the signal to be allocated is not included in the running memory map, another memory map in the past is newly added. It is referred to in order, and it is further determined whether or not the signal to be assigned is included in the signal. If it is included, the generation unit 14 assigns the same address as the address assigned in the past memory map to the signal to be assigned. If not included, the generation unit 14 assigns the signal to be assigned an unused address that satisfies the condition that it is different from any of the addresses assigned to the other signals in the plurality of past memory maps.

For example, the signal "A1_MACRO_ANALOG1" for internal calculation used in the macro A1 being executed is not used in the macro A1 for update. Therefore, the address 3 assigned to the signal in the running memory map is not used in the update memory map and becomes an unused address. However, this address 3 is included in the running memory map and does not satisfy the above conditions. Therefore, even if the signal to be assigned is a signal newly added by the control logic for update, the address 3 is not assigned. The generation unit 14 limits the use of the address assigned in the past memory map to the signals used in the past control logic that are not used in the update control logic, and the memory for update. It can be said to generate a map. As a result, the value of the signal "A1_MACRO_ANALOG1" is retained without being overwritten. By holding the value of the signal in this way, the held value can be used when this signal is reused later. The generation unit 14 can be configured to consider the above conditions only when there is an unused address satisfying the above conditions.

Further, the logic update device 10 does not have to have a function of creating change information. In this case, the change information can be configured to be acquired by the acquisition unit 13 after being created by the external device. As a result, the configuration of the logic update device 10 can be simplified. Further, the change information is not limited to the information indicating the change from the control logic being executed in the control logic for update. Further, the generation unit 14 may generate the control logic for update without using the change information (based on information different from the change information). In addition, the generation unit 14 may also be configured to perform an error check for confirming whether the control logic after generation is correct (whether it operates properly).

1 Control system 10 Logic updater 11 Storage unit 12 User interface 13 Acquisition unit 14 Generation unit 15 Output unit 20 Control unit 21 Execution engine 22 Input / output unit 23 Memory 30 Control target device

Claims (6)

A logic updater that generates a second control logic executed in the control device instead of the first control logic executed in the control device that controls the controlled object.
A storage means for storing the first allocation information indicating the allocation of the memory address of the control device to each signal used in the first control logic, and
The second control logic, and a generation means for generating second allocation information indicating the allocation of the memory address of the control device to each signal used in the second control logic.
The second control logic and the output means for outputting the second allocation information are provided.
The generation means refers to the first allocation information, and when the signal used in the second control logic is included in the first allocation information, the first allocation information allocates the signal to the signal. The second allocation information is generated so that the assigned memory address of the control device is assigned to the signal .
When the signal used in the second control logic is not included in the first allocation information, the generation means refers to the signal and the signal not used in the second control logic. A logic update device that generates the second allocation information so that the memory address of the control device allocated by the allocation information is allocated . A logic updater that generates a second control logic executed in the control device instead of the first control logic executed in the control device that controls the controlled object.
A storage means for storing the first allocation information indicating the allocation of the memory address of the control device to each signal used in the first control logic, and
The second control logic, and a generation means for generating second allocation information indicating the allocation of the memory address of the control device to each signal used in the second control logic.
The second control logic and the output means for outputting the second allocation information are provided.
The generation means refers to the first allocation information, and when the signal used in the second control logic is included in the first allocation information, the first allocation information allocates the signal to the signal. The second allocation information is generated so that the assigned memory address of the control device is assigned to the signal .
The storage means stores third allocation information indicating the allocation of the memory address of the control device to each signal used in the third control logic executed before the first control logic in the control device.
When the signal used in the second control logic is not included in the first allocation information, the generation means refers to the third allocation information, and the signal is included in the third allocation information. When , a logic update device that generates the second allocation information so that the memory address of the control device assigned to the signal in the third allocation information is assigned to the signal . It said generating means is a case where a signal that is used in the previous SL second control logic is not included in the first allocation information, when said signal is not included in the third allocation information, the first The second allocation information is generated so that a memory address different from the memory address of the control device assigned to the other signal in the first allocation information and the third allocation information is assigned to the signal. , The logic update device according to claim 2 . The storage means stores a plurality of the third allocation information indicating the allocation of the memory address of the control device for each signal used in the plurality of the third control logics.
The generation means according to claim 2 or 3, wherein when the signal used in the second control logic is not included in the first allocation information, the generation means refers to a plurality of the third allocation information in chronological order. Logic updater. Logic update that generates the second control logic executed in the control device instead of the first control logic executed in the control device that controls the control target by using a logic update device composed of one or more devices. It's a method
A storage step for storing the first allocation information indicating the allocation of the memory address of the control device to each signal used in the first control logic, and
A generation step for generating the second control logic and a second allocation information indicating the allocation of the memory address of the control device for each signal used in the second control logic, the second control logic, and the second allocation. The generation step includes an output step for outputting information, and the generation step refers to the first allocation information, and if the signal used in the second control logic is included in the first allocation information, the first allocation information is included. The second allocation information is generated so that the memory address of the control device assigned to the signal in the first allocation information is assigned to the signal .
In the generation step, when the signal used in the second control logic is not included in the first allocation information, the first is described for the signal and for the signal not used in the second control logic. A logic update method for generating the second allocation information so that the memory address of the control device allocated in the allocation information is allocated . Logic update that generates the second control logic executed in the control device instead of the first control logic executed in the control device that controls the control target by using a logic update device composed of one or more devices. It's a method
A storage step for storing the first allocation information indicating the allocation of the memory address of the control device to each signal used in the first control logic, and
A generation step for generating the second control logic and a second allocation information indicating the allocation of the memory address of the control device for each signal used in the second control logic, the second control logic, and the second allocation. The generation step includes an output step for outputting information, and the generation step refers to the first allocation information, and if the signal used in the second control logic is included in the first allocation information, the first allocation information is included. The second allocation information is generated so that the memory address of the control device assigned to the signal in the first allocation information is assigned to the signal .
The storage step stores third allocation information indicating the allocation of the memory address of the control device to each signal used in the third control logic executed before the first control logic in the control device.
When the signal used in the second control logic is not included in the first allocation information, the generation step refers to the third allocation information, and the signal is included in the third allocation information. When , a logic update method for generating the second allocation information so that the memory address of the control device assigned to the signal in the third allocation information is assigned to the signal .

Images