JP6833916B2 - データ処理装置、人工知能チップ及び電子機器 - Google Patents
データ処理装置、人工知能チップ及び電子機器 Download PDFInfo
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Description
Claims (11)
- 処理対象データを格納する少なくとも1つの入力メモリと、
外部処理命令を読み取り、前記外部処理命令を解析することでデータ読み取りアドレス、データ書き込みアドレス及び操作コマンドを取得し、前記データ読み取りアドレスに応じて前記入力メモリから処理対象データを読み取り、前記操作コマンドに従って前記処理対象データを処理して、多重処理後の出力データ及び対応するデータ書き込みアドレスを取得し、データ書き込みリクエストを発する少なくとも1つのデータ転送部と、
少なくとも1つのデータ転送部からのデータ書き込みリクエストの受信に応答して、前記データ転送部の出力データ及び対応するデータ書き込みアドレスを受信し、受信された出力データ及びデータ書き込みアドレスから、1つのデータ転送部の出力データ及び対応するデータ書き込みアドレスをストローブして出力するとともに、書き込みイネーブル信号を送信する少なくとも1つの多重調停部と、
前記多重調停部からの書き込みイネーブル信号の受信に応答して、前記多重調停部から出力データ及び対応するデータ書き込みアドレスを受信するとともに、受信された前記出力データを、対応するデータ書き込みアドレスに書き込む少なくとも1つの出力メモリと、を備えるデータ処理装置。 - 前記データ転送部は、
読み取られた前記外部処理命令を解析するとともに解析操作を実行するフロントエンド復号化部であって、前記解析操作は、前記外部処理命令からデータ読み取りアドレス、データ書き込みアドレス及び操作コマンドを抽出して、前記入力メモリにデータ読み取りリクエストを発し、前記入力メモリによって前記データ読み取りリクエストの受信に応答して送信された処理対象データを、データキューにバッファリングし、抽出された前記操作コマンドをコマンドキューにバッファリングすることを含むフロントエンド復号化部と、
前記コマンドキューの操作コマンドに応じて前記データキューにおける処理対象データを処理して、出力データを得る少なくとも1つの処理部とを備える請求項1に記載の装置。 - 前記フロントエンド復号化部によって実行される解析操作は、
前記操作コマンドがデータ転送コマンドであるかそれともデータ転置コマンドであるかを判定し、前記操作コマンドがデータ転送コマンドである場合に、前記フロントエンド復号化部は前記入力メモリから送信された処理対象データを各処理部にブロードキャストし、前記操作コマンドがデータ転置コマンドである場合に、前記フロントエンド復号化部は前記入力メモリから送信された処理対象データを、対応する少なくとも1つの処理部に送信することをさらに含み、
ここでは、各処理部には対応するデータ読み取りアドレスのオフセットが予め設定されている請求項2に記載の装置。 - 前記フロントエンド復号化部は、前記外部処理命令を解析した後に、読み取られた前記外部処理命令がシングルステップ実行命令であるかそれともバッチ処理命令であるかを判定し、
前記外部処理命令がシングルステップ実行命令である場合に、前記解析操作を実行し、
前記外部処理命令がバッチ処理命令である場合に、前記解析操作を予め設定された回数繰り返し実行し、毎回の解析操作が実行された度に、データ読み取りアドレス及びデータ書き込みアドレスを、予め設定されたアドレスのオフセットストライドに基づいて調整する請求項3に記載の装置。 - 前記処理部は、
前記データキューから処理対象データを読み取るデータレジスタと、
前記コマンドキューから操作コマンドを読み取るコマンドレジスタと、
前記コマンドレジスタのコマンドに従ってステータス制御を行うステートマシンと、
前記ステートマシンの制御に従って、前記データレジスタから処理対象データを選択して出力するマルチプレクサと、を備える請求項2に記載の装置。 - 前記ステートマシンはさらに、前記外部処理命令から解析されたデータ書き込みアドレスを前記コマンドレジスタから受信し、受信されたデータ書き込みアドレスと、前記処理部によって予め設定された書き込みアドレスのオフセットとに基づいて、出力データのデータ書き込みアドレスを計算するとともに、データ書き込みリクエストと、前記出力データのデータ書き込みアドレスとを前記多重調停部に送信する請求項5に記載の装置。
- 前記多重調停部は、アービタとセレクタとを備える調停ユニットを少なくとも1つ備え、前記アービタは、各データ転送部における処理部の出力データを調停し、調停結果に応じて、1つの処理部の出力データと、対応するデータ書き込みアドレスとを選択して出力するように前記セレクタを制御し、前記出力メモリに書き込みイネーブル信号を送信する請求項5に記載の装置。
- 前記出力メモリは、前記多重調停部から出力された書き込みイネーブル信号と、出力データと、対応するデータ書き込みアドレスとを受信し、前記書き込みイネーブル信号の制御下で、前記出力データを対応するデータ書き込みアドレスに書き込む請求項7に記載の装置。
- 前記入力メモリ及び前記出力メモリがオンチップメモリである請求項1〜8のいずれか一項に記載の装置。
- 請求項1〜9のいずれか一項に記載のデータ処理装置を備える人工知能チップ。
- 中央処理装置と、請求項10に記載の人工知能チップとを備える電子機器。
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CN113138802B (zh) * | 2021-04-29 | 2024-03-05 | 上海阵量智能科技有限公司 | 命令分发装置、方法、芯片、计算机设备及存储介质 |
CN115902595B (zh) * | 2023-02-20 | 2023-07-14 | 之江实验室 | 一种芯片测试系统以及芯片测试方法 |
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