JP6787550B2 - Printed circuit board - Google Patents
Printed circuit board Download PDFInfo
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- JP6787550B2 JP6787550B2 JP2019003328A JP2019003328A JP6787550B2 JP 6787550 B2 JP6787550 B2 JP 6787550B2 JP 2019003328 A JP2019003328 A JP 2019003328A JP 2019003328 A JP2019003328 A JP 2019003328A JP 6787550 B2 JP6787550 B2 JP 6787550B2
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- 229910000679 solder Inorganic materials 0.000 claims description 20
- 238000007689 inspection Methods 0.000 claims description 13
- 230000003014 reinforcing effect Effects 0.000 claims description 6
- 239000010410 layer Substances 0.000 description 181
- 238000004519 manufacturing process Methods 0.000 description 30
- 238000000034 method Methods 0.000 description 24
- 239000012790 adhesive layer Substances 0.000 description 8
- 230000005856 abnormality Effects 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- 239000002390 adhesive tape Substances 0.000 description 5
- 238000005530 etching Methods 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 230000001678 irradiating effect Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000007792 addition Methods 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000012217 deletion Methods 0.000 description 1
- 230000037430 deletion Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4623—Manufacturing multilayer circuits by laminating two or more circuit boards the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/007—Manufacture or processing of a substrate for a printed circuit board supported by a temporary or sacrificial carrier
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
Description
本発明は印刷回路基板に関するものである。 The present invention relates to a printed circuit board.
コンピュータ産業が発達するにつれて、さらに高い性能を有し、さらに低廉な費用で生産できる集積回路（ダイ、ｄｉｅ）に対する技術が発達している。これに伴い、多数のダイ（ｄｉｅ）を含むパッケージ基板に対する技術も開発されている。 As the computer industry develops, technologies for integrated circuits (dies) that have higher performance and can be produced at lower cost are being developed. Along with this, a technique for a package substrate including a large number of dies has also been developed.
本発明の一側面によれば、複数のダイ（Ｄｉｅ）を電気的に連結するための高密度のブリッジ（ｂｒｉｄｇｅ）回路を具備したブリッジ回路層、ブリッジ回路層が内蔵されブリッジ回路よりも密度が低い低密度回路を具備した低密度回路層を含み、ブリッジ回路層の一面または他面には接続パッドが形成され、接続パッドはビアまたはソルダーバンプを通じて低密度回路と電気的に連結され、ブリッジ回路層は、露出されないように低密度回路層の絶縁層により覆われる印刷回路基板が提供される。 According to one aspect of the present invention, a bridge circuit layer provided with a high-density bridge circuit for electrically connecting a plurality of dies (Dies), a bridge circuit layer is incorporated, and the density is higher than that of a bridge circuit. It contains a low density circuit layer with a low low density circuit, a connection pad is formed on one or the other side of the bridge circuit layer, and the connection pad is electrically connected to the low density circuit through vias or solder bumps to form a bridge circuit. A printed circuit board is provided in which the layer is covered with an insulating layer of a low density circuit layer so that it is not exposed.
以下、本発明に係る印刷回路基板およびその製造方法の実施例を、添付図面を参照して詳細に説明するが、説明において、同一または対応する構成要素は同じ図面番号を付与し、これに対する重複する説明は省略する。 Hereinafter, examples of the printed circuit board and the method for manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings, but in the description, the same or corresponding components are given the same drawing number and duplicated thereto. The description to be made is omitted.
また、本発明で用いられる第１、第２などの用語は、同一または相応する構成要素を区別するための識別記号に過ぎず、同一または相応する構成要素が第１、第２などの用語によって限定されるものではない。 Further, the terms such as 1st and 2nd used in the present invention are merely identification symbols for distinguishing the same or corresponding components, and the same or corresponding components are referred to by the terms such as 1st and 2nd. It is not limited.
また、結合とは、各溝性要素間の接触関係において、各溝性要素間に物理的に直接接触する場合だけを意味するのではなく、他の構成が各溝性要素の間に介在されて、該他の構成に構成要素がそれぞれ接触されている場合までも包括する概念として用いられる。 Further, the bond does not mean only the case where the grooved elements are in direct physical contact with each other in the contact relationship between the grooved elements, but other configurations are interposed between the grooved elements. Therefore, it is used as a concept that includes the case where each component is in contact with the other configuration.
＜印刷回路基板＞
図１は本発明の一実施例に係る印刷回路基板を示した図面である。図１を参照すれば、本発明の一実施例に係る印刷回路基板は高密度のブリッジ回路層１００、低密度回路層１５０およびソルダーバンプ１８０／ビア２８０を含む。
<Printed circuit board>
FIG. 1 is a drawing showing a printed circuit board according to an embodiment of the present invention. Referring to FIG. 1, the printed circuit board according to an embodiment of the present invention includes a high density bridge circuit layer 100, a low density circuit layer 150 and a solder bump 180 / via 280.
ブリッジ回路層１００は印刷回路基板に実装される複数のダイ（ｄｉｅ、１、２）を互いに電気的に連結させるダイ間のインターコネクション（ｄｉｅ ｔｏ ｄｉｅ ｉｎｔｅｒｃｏｎｎｅｃｔｉｏｎ）を遂行する。ダイ１、２は集積回路であって、複数のダイ１、２を互いに連結させるためには小さい空間に非常に密集した連結回路が必要である。ブリッジ回路層１００は高密度のブリッジ回路１１０を具備して印刷回路基板に実装される複数のダイ１、２を互いに連結させることができる。例えば、ブリッジ回路１１０は複数のダイ１、２と接続する複数のパッド１１２と複数のパッド１１２を連結する微細回路パターン１１４を含むことができる。 The bridge circuit layer 100 carries out an interconnection between dies that electrically connects a plurality of dies (dies, 1, 2) mounted on a printed circuit board to each other. The dies 1 and 2 are integrated circuits, and in order to connect a plurality of dies 1 and 2 to each other, a very dense connection circuit is required in a small space. The bridge circuit layer 100 includes a high-density bridge circuit 110, and a plurality of dies 1 and 2 mounted on a printed circuit board can be connected to each other. For example, the bridge circuit 110 can include a plurality of pads 112 that connect the plurality of dies 1 and 2 and a fine circuit pattern 114 that connects the plurality of pads 112.
ブリッジ回路層１００において、ブリッジ回路１１０の幅と回路間の間隔は後述する低密度回路層１５０に形成される低密度回路１６０の幅と回路間の間隔に比べて微細に形成される。また、ブリッジ回路１１０はブリッジ回路層１００の内蔵後に外層に形成された外層回路１７０より微細に形成され得る。例えば、ブリッジ回路１１０は半導体工程などにより形成し、低密度回路１６０はＳＡＰ工程（Ｓｅｍｉ−Ａｄｄｉｔｉｖｅ Ｐｒｏｃｅｓｓ）、Ｍ−ＳＡＰ工程（Ｍｏｄｉｆｉｅｄ Ｓｅｍｉ−Ａｄｄｉｔｉｖｅ Ｐｒｏｃｅｓｓ）またはテンティング（ｔｅｎｔｉｎｇ）工程などの基板工程によって形成することができる。またはブリッジ回路１１０を基板工程のうち相対的に精密なＳＡＰ工程で形成し、低密度回路１６０は相対的に精密度が劣る基板工程であるＭ−ＳＡＰ工程またはテンティング工程などで形成することができる。 In the bridge circuit layer 100, the width of the bridge circuit 110 and the spacing between the circuits are formed to be finer than the width of the low-density circuit 160 formed in the low-density circuit layer 150, which will be described later, and the spacing between the circuits. Further, the bridge circuit 110 may be formed more finely than the outer layer circuit 170 formed in the outer layer after the bridge circuit layer 100 is built in. For example, the bridge circuit 110 is formed by a semiconductor process or the like, and the low density circuit 160 is formed by a substrate process such as an SAP process (Semi-Adaptive Process), an M-SAP process (Modified Semi-Adaptive Process), or a tenting process. Can be formed. Alternatively, the bridge circuit 110 may be formed in a relatively precise SAP process among the substrate processes, and the low density circuit 160 may be formed in an M-SAP process or a tenting process which is a relatively inferior substrate process. it can.
ブリッジ回路層１００は、ダイ１、２と直接連結され得るように一面にパッドが形成され、パッドに複数のダイ１、２が直接結合され得る。このとき、ブリッジ回路層１００の一面は印刷回路基板の外層となり得る。 The bridge circuit layer 100 has a pad formed on one surface so that it can be directly connected to the dies 1 and 2, and a plurality of dies 1 and 2 can be directly connected to the pad. At this time, one surface of the bridge circuit layer 100 can be an outer layer of the printed circuit board.
また、ブリッジ回路層１００の一面上に付加的に外層が形成され、外層にはダイ１、２とブリッジ回路１１０を連結させる外層回路１７０が形成され得る。図１に示されたように、外層回路１７０はダイ１、２との連結のためのパッドを含んでブリッジ回路１１０のパッド１１２と連結され得る。外層回路１７０は微細なブリッジ回路１１０が直接ソルダリングされて損傷することを防止することができる。 Further, an outer layer may be additionally formed on one surface of the bridge circuit layer 100, and an outer layer circuit 170 for connecting the dies 1 and 2 and the bridge circuit 110 may be formed on the outer layer. As shown in FIG. 1, the outer layer circuit 170 may be coupled to the pad 112 of the bridge circuit 110, including a pad for coupling with the dies 1 and 2. The outer layer circuit 170 can prevent the fine bridge circuit 110 from being directly soldered and damaged.
一方、ダイ１、２のインターフェイス規格（端子の配置など）に合わせるため、外層回路１７０はブリッジ回路１１０とダイ１、２を繋ぐ配線をファンアウト（ｆａｎ−ｏｕｔ）させるファンアウト回路パターンを含むことができる。換言すれば、ブリッジ回路層１００において稠密に形成されたブリッジ回路１１０は、ファンアウト回路パターンを通じて低密度回路層１５０の外層において広く分散させることができる。ファンアウト回路パターンは各ダイ１、２のインターフェイス規格に合わせて印刷回路基板の外層に形成されたパッドを含むことができる。これによって、ブリッジ回路１１０はダイ１、２の規格に影響を受けることなく自由に設計することができるので、ブリッジ回路１１０の設計自由度を高めることができる。 On the other hand, in order to match the interface standards of dies 1 and 2 (terminal arrangement, etc.), the outer layer circuit 170 includes a fan-out circuit pattern that fan-outs the wiring connecting the bridge circuit 110 and dies 1 and 2. Can be done. In other words, the bridge circuit 110 densely formed in the bridge circuit layer 100 can be widely dispersed in the outer layer of the low density circuit layer 150 through the fan-out circuit pattern. The fan-out circuit pattern can include pads formed on the outer layer of the printed circuit board according to the interface standards of the dies 1 and 2. As a result, the bridge circuit 110 can be freely designed without being affected by the standards of the dies 1 and 2, so that the degree of freedom in designing the bridge circuit 110 can be increased.
本発明のブリッジ回路層１００はウェハーのような支持層を含まない。したがって、ブリッジ回路層１００は低密度回路層１５０と容易に電気的に連結され得る。シリコンウェハーのような支持層を含まない構造を有することによって、ブリッジ回路層１００の厚さを薄くするとともに低密度回路層１５０で短い電気的経路を具現することができる。ブリッジ回路層１００の他面を通じて低密度回路層１５０と上下に直接電気的連結が可能であるため電気的特性を向上することができ、ブリッジ回路層１００の設計自由度も高めることができる。支持層を含まずブリッジ回路層１００を形成する具体的方法は製造方法にて後述する。 The bridge circuit layer 100 of the present invention does not include a support layer such as a wafer. Therefore, the bridge circuit layer 100 can be easily electrically connected to the low density circuit layer 150. By having a structure that does not include a support layer such as a silicon wafer, the thickness of the bridge circuit layer 100 can be reduced and a short electrical path can be realized in the low density circuit layer 150. Since it is possible to directly electrically connect the low-density circuit layer 150 vertically through the other surface of the bridge circuit layer 100, the electrical characteristics can be improved and the degree of freedom in designing the bridge circuit layer 100 can be increased. A specific method for forming the bridge circuit layer 100 without including the support layer will be described later in the manufacturing method.
ブリッジ回路１１０は電気検査に利用される検査回路パターン１３０をさらに含むことができる。図２６を参照すれば、ブリッジ回路１１０の異常有無を確認できる検査回路パターン１３０をブリッジ回路１１０に形成し、これをブリッジ回路層１００の他面に露出させることができる。他面の露出された検査回路パターン１３０に検査装備を接続してブリッジ回路１１０の異常有無を容易に確認することができる。 The bridge circuit 110 may further include an inspection circuit pattern 130 used for electrical inspection. With reference to FIG. 26, an inspection circuit pattern 130 capable of confirming the presence or absence of abnormality in the bridge circuit 110 can be formed in the bridge circuit 110 and exposed on the other surface of the bridge circuit layer 100. By connecting the inspection equipment to the exposed inspection circuit pattern 130 on the other surface, it is possible to easily confirm the presence or absence of abnormality in the bridge circuit 110.
低密度回路層１５０はブリッジ回路層１００を内蔵し、ブリッジ回路１１０に比べて密度の低い低密度回路１６０を具備する。印刷回路基板でダイ１、２間のインターコネクションを遂行するブリッジ回路１１０以外の残りの回路は、ブリッジ回路１１０のような高密度回路で構成する必要性が少ない。したがって、低密度回路層１５０には歩留まりが高く、安価な低密度回路が形成されることが好ましい。 The low-density circuit layer 150 includes a bridge circuit layer 100, and includes a low-density circuit 160 having a lower density than the bridge circuit 110. The remaining circuits other than the bridge circuit 110 that performs the interconnection between the dies 1 and 2 on the printed circuit board need not be configured by a high-density circuit such as the bridge circuit 110. Therefore, it is preferable that the low-density circuit layer 150 has a high-yield, inexpensive low-density circuit.
図１に示されたように、低密度回路層１５０の絶縁層１５４の一部にブリッジ回路層１００を内蔵することができる。ブリッジ回路層１００は低密度回路層１５０に比べて高い密度の回路層を有するため、層の間隔が低密度回路層１５０の層の間隔より狭く形成される。例えば、低密度回路層１５０中の一つの絶縁層に複数層のブリッジ回路層１００が内蔵され得る。内蔵されたブリッジ回路層１００は低密度回路層１５０の外層によって覆われ得る。このとき、外層回路１７０が形成されてブリッジ回路１１０とダイ１、２を連結させる。一方、ブリッジ回路層１００が直接ダイ１、２と連結される時には外層が形成されずにブリッジ回路層１００が露出され得る。 As shown in FIG. 1, the bridge circuit layer 100 can be incorporated in a part of the insulating layer 154 of the low density circuit layer 150. Since the bridge circuit layer 100 has a circuit layer having a higher density than the low-density circuit layer 150, the layer spacing is formed to be narrower than the layer spacing of the low-density circuit layer 150. For example, a plurality of bridge circuit layers 100 may be incorporated in one insulating layer in the low density circuit layer 150. The built-in bridge circuit layer 100 may be covered by an outer layer of the low density circuit layer 150. At this time, the outer layer circuit 170 is formed to connect the bridge circuit 110 and the dies 1 and 2. On the other hand, when the bridge circuit layer 100 is directly connected to the dies 1 and 2, the bridge circuit layer 100 can be exposed without forming an outer layer.
低密度回路層１５０の低密度回路１６０はブリッジ回路層１００に向かうパッド１６４およびこれと連結される回路パターン１６２を具備することができる。低密度回路１６０のパッド１６４はブリッジ回路１１０の接続パッド１１６と連結されて低密度回路層１５０とブリッジ回路層１００を上下に直接連結することができる。 The low-density circuit 160 of the low-density circuit layer 150 can include a pad 164 toward the bridge circuit layer 100 and a circuit pattern 162 connected thereto. The pad 164 of the low-density circuit 160 is connected to the connection pad 116 of the bridge circuit 110, and the low-density circuit layer 150 and the bridge circuit layer 100 can be directly connected vertically.
低密度回路層１５０は印刷回路基板の剛性を高める補強部材１５２を含むことができる。例えば、図１に示されたように、中心部に補強部材１５２を具備した低密度回路層１５０を形成し、ブリッジ回路層１００を内蔵させることができる。一方、図２に示されたように、補強部材を利用しないコアレス構造で低密度回路層２５０が形成されることもある。 The low density circuit layer 150 can include a reinforcing member 152 that increases the rigidity of the printed circuit board. For example, as shown in FIG. 1, a low-density circuit layer 150 having a reinforcing member 152 at a central portion can be formed, and a bridge circuit layer 100 can be incorporated therein. On the other hand, as shown in FIG. 2, the low-density circuit layer 250 may be formed in a coreless structure that does not use a reinforcing member.
低密度回路層１５０には印刷回路基板に必要な電子部品３が実装され得る。低密度回路層１５０はブリッジ回路層１００に比べて広い外部面積を確保するため、電子部品の配置が容易である。低密度回路層１５０に実装された電子部品は後述するソルダーバンプ１８０を通じてブリッジ回路１１０とも電気的に連結され得る。 The electronic component 3 required for the printed circuit board can be mounted on the low-density circuit layer 150. Since the low-density circuit layer 150 secures a wider external area than the bridge circuit layer 100, it is easy to arrange electronic components. The electronic components mounted on the low-density circuit layer 150 can also be electrically connected to the bridge circuit 110 through the solder bump 180 described later.
ソルダーバンプ１８０は低密度回路１６０とブリッジ回路１１０を連結させる。図１を参照すれば、ブリッジ回路層１００に向かう低密度回路１６０のパッド１６４上にソルダーバンプを形成し、ここにブリッジ回路層１００の接続パッド１１６を装着させてソルダーバンプとブリッジ回路１１０を連結することができる。ソルダーバンプを通じてブリッジ回路１１０と低密度回路１６０は上下に直接連結され得る。 The solder bump 180 connects the low density circuit 160 and the bridge circuit 110. Referring to FIG. 1, a solder bump is formed on the pad 164 of the low-density circuit 160 toward the bridge circuit layer 100, and the connection pad 116 of the bridge circuit layer 100 is mounted therein to connect the solder bump and the bridge circuit 110. can do. The bridge circuit 110 and the low density circuit 160 can be directly connected vertically through the solder bump.
図２を参照すれば、低密度回路１６０とブリッジ回路１１０はビア２８０を通じて連結され得る。内蔵されたブリッジ回路層２００の他面に低密度回路２６０をビルドアップ（ｂｕｉｌｄ−ｕｐ）して形成し、ブリッジ回路２１０の接続パッド２１６と低密度回路１６０を、ビア２８０を通じて連結させることができる。 With reference to FIG. 2, the low density circuit 160 and the bridge circuit 110 may be connected through via 280. A low-density circuit 260 is built-up on the other surface of the built-in bridge circuit layer 200, and the connection pad 216 of the bridge circuit 210 and the low-density circuit 160 can be connected through the via 280. ..
＜印刷回路基板の製造方法＞
図３〜図１４は本発明の一実施例に係る印刷回路基板の製造方法を示した図面である。本発明の一実施例に係る印刷回路基板の製造方法は、補強部材１５２を具備した低密度回路層１５０に高密度のブリッジ回路層１００をソルダーバンプ１８０を利用して結合し、内蔵させる方法を例示する。
<Manufacturing method of printed circuit board>
3 to 14 are drawings showing a method of manufacturing a printed circuit board according to an embodiment of the present invention. The method for manufacturing a printed circuit board according to an embodiment of the present invention is a method in which a high-density bridge circuit layer 100 is coupled to a low-density circuit layer 150 provided with a reinforcing member 152 by using a solder bump 180 and incorporated therein. Illustrate.
本発明の一実施例に係る印刷回路基板の製造方法は、低粗度の第１キャリア５にブリッジ回路層１００を形成する段階、第２キャリア６を仮接合する段階、ブリッジ回路層１００を埋め立てる段階を含む。 The method for manufacturing a printed circuit board according to an embodiment of the present invention includes a step of forming a bridge circuit layer 100 on a low-roughness first carrier 5, a step of temporarily joining a second carrier 6, and a step of filling the bridge circuit layer 100. Including stages.
低粗度の第１キャリア５にブリッジ回路層１００を形成する段階では、低粗度の第１キャリア５に高密度のブリッジ（ｂｒｉｄｇｅ）回路１１０を具備したブリッジ回路層１００を形成する。シリコンウェハーのような支持層がなくても微細なブリッジ回路１１０を高密度に形成するために、粗度が非常に低い第１キャリア５上に微細な回路パターンを形成する。例えば、第１キャリア５としてはガラス基板を用いることができ、算術平均粗度（Ｒａ）は０．０５ｕｍ以下であり得る。第１キャリア５は後述する第２キャリア６および第３キャリア７に比べて非常に低い粗度を有する。 At the stage of forming the bridge circuit layer 100 on the low-roughness first carrier 5, the bridge circuit layer 100 provided with the high-density bridge circuit 110 is formed on the low-roughness first carrier 5. In order to form the fine bridge circuit 110 at high density without a support layer such as a silicon wafer, a fine circuit pattern is formed on the first carrier 5 having a very low roughness. For example, a glass substrate can be used as the first carrier 5, and the arithmetic mean roughness (Ra) can be 0.05 um or less. The first carrier 5 has a very low roughness as compared with the second carrier 6 and the third carrier 7, which will be described later.
図３を参照すれば、低粗度のガラス基板に離型層５ａを形成し、スパッタリング（ｓｐｕｔｔｅｒｉｎｇ）して平坦度の高いシード層５ｂを形成することができる。 With reference to FIG. 3, a release layer 5a can be formed on a low-roughness glass substrate and sputtered to form a seed layer 5b having a high flatness.
図４を参照すれば、平坦なシード層５ｂをベースに微細回路パターン１１４と絶縁層１２０をビルドアップして複数のブリッジ回路１１０を一度に形成することができる。微細なブリッジ回路１１０を形成するために半導体工程または精密なＳＡＰ工程（Ｓｅｍｉ−Ａｄｄｉｔｉｖｅ Ｐｒｏｃｅｓｓ）などが遂行され得る。このとき、ダイ１、２側に向かうブリッジ回路層１００の一面が上面になるように形成し、上面に露出されたブリッジ回路１１０のパッド１１２を利用して回路の異常有無を確認する電気検査を遂行することができる。 With reference to FIG. 4, a plurality of bridge circuits 110 can be formed at once by building up the fine circuit pattern 114 and the insulating layer 120 based on the flat seed layer 5b. A semiconductor process, a precise SAP process (Semi-Adaptive Process), or the like can be performed to form the fine bridge circuit 110. At this time, one surface of the bridge circuit layer 100 facing the dies 1 and 2 is formed so as to be the upper surface, and the pad 112 of the bridge circuit 110 exposed on the upper surface is used to perform an electrical inspection to confirm the presence or absence of an abnormality in the circuit. Can be carried out.
第２キャリア６を仮接合する段階では、ブリッジ回路層１００に仮接合される第２キャリア６を接合し、ブリッジ回路層１００から第１キャリア５を分離する。ブリッジ回路層１００を低密度回路層１５０に内蔵させるために、加工および移動が便利な第２キャリア６をブリッジ回路層１００に仮接合させる。 At the stage of temporarily joining the second carrier 6, the second carrier 6 temporarily joined to the bridge circuit layer 100 is joined, and the first carrier 5 is separated from the bridge circuit layer 100. In order to incorporate the bridge circuit layer 100 into the low-density circuit layer 150, a second carrier 6 that is convenient to process and move is temporarily joined to the bridge circuit layer 100.
図５を参照すれば、ブリッジ回路層１００の一面に接着および分離が容易な接着層６ａを形成し、この接着層６ａに第２キャリア６を接着させることができる。例えば、接着層６ａとしては、ＵＶ剥離型粘着テープを使用することができる。ＵＶ剥離型粘着テープは紫外線が照射されると粘着力が低下するため、以後第２キャリア６の分離を容易にすることができる。 With reference to FIG. 5, an adhesive layer 6a that can be easily adhered and separated can be formed on one surface of the bridge circuit layer 100, and the second carrier 6 can be adhered to the adhesive layer 6a. For example, as the adhesive layer 6a, a UV peeling type adhesive tape can be used. Since the adhesive strength of the UV release type adhesive tape decreases when it is irradiated with ultraviolet rays, it is possible to facilitate the separation of the second carrier 6 thereafter.
図６を参照すれば、第２キャリア６の接合した後、ブリッジ回路層１００を持ち上げて第１キャリア５からブリッジ回路層１００を分離する。第１キャリア５とシード層５ｂの間には離型層５ａが介在されており、ブリッジ回路層１００は容易に分離され得る。 Referring to FIG. 6, after joining the second carrier 6, the bridge circuit layer 100 is lifted to separate the bridge circuit layer 100 from the first carrier 5. A release layer 5a is interposed between the first carrier 5 and the seed layer 5b, and the bridge circuit layer 100 can be easily separated.
図７を参照すれば、シード層５ｂをエッチングなどで除去し、ブリッジ回路層１００の他面に接着層５ｃと保護フィルム５ｄを付着することができる。このとき、シード層５ｂをエッチングなどで除去した後、露出されたブリッジ回路１１０を利用して回路の異常有無を確認する電気検査を遂行することができる。図２６を参照すれば、ブリッジ回路１１０の異常有無を確認できる検査回路パターン１３０がブリッジ回路１１０に形成され、ブリッジ回路層１００の他面に露出され得る。他面の露出された検査回路パターン１３０に検査装備を接続してブリッジ回路１１０の異常有無を容易に確認することができる。 With reference to FIG. 7, the seed layer 5b can be removed by etching or the like, and the adhesive layer 5c and the protective film 5d can be attached to the other surface of the bridge circuit layer 100. At this time, after removing the seed layer 5b by etching or the like, it is possible to carry out an electrical inspection for confirming the presence or absence of abnormality in the circuit by using the exposed bridge circuit 110. With reference to FIG. 26, an inspection circuit pattern 130 for confirming the presence or absence of abnormality in the bridge circuit 110 can be formed in the bridge circuit 110 and exposed on the other surface of the bridge circuit layer 100. By connecting the inspection equipment to the exposed inspection circuit pattern 130 on the other surface, it is possible to easily confirm the presence or absence of abnormality in the bridge circuit 110.
図８を参照すれば、複数で形成されたブリッジ回路層１００を切断してそれぞれ分離させることができる。 With reference to FIG. 8, a plurality of bridge circuit layers 100 formed can be cut and separated from each other.
ブリッジ回路層１００を埋め立てる段階では、低密度回路を具備した低密度回路層１５０にブリッジ回路層１００を結合して埋め立てる。低密度回路層１５０の内部にブリッジ回路層１００が配置されるように低密度回路層１５０の絶縁層１５４にブリッジ回路層１００を埋め立てることができる。また、低密度回路１６０とブリッジ回路１１０はソルダーバンプ１８０を通じて電気的に連結される。 At the stage of burying the bridge circuit layer 100, the bridge circuit layer 100 is coupled to the low-density circuit layer 150 provided with the low-density circuit and buried. The bridge circuit layer 100 can be embedded in the insulating layer 154 of the low density circuit layer 150 so that the bridge circuit layer 100 is arranged inside the low density circuit layer 150. Further, the low density circuit 160 and the bridge circuit 110 are electrically connected through the solder bump 180.
図９を参照すれば、中心部に補強部材１５２を具備して低密度回路１６０を有する低密度回路層１５０を準備する。低密度回路１６０はブリッジ回路層１００に向かうパッド１６４を具備し、パッド１６４にはソルダーバンプ１８０が形成されて準備され得る。一方、図２５に示されたように、ブリッジ回路層１００の他面にブリッジ回路１１０と連結される接続パッド１１６を形成し、接続パッド１１６上にソルダーバンプ１１８を形成することもできる。 Referring to FIG. 9, a low density circuit layer 150 having a reinforcing member 152 at the center and a low density circuit 160 is prepared. The low density circuit 160 includes pads 164 towards the bridge circuit layer 100, and solder bumps 180 may be formed and prepared on the pads 164. On the other hand, as shown in FIG. 25, a connection pad 116 connected to the bridge circuit 110 may be formed on the other surface of the bridge circuit layer 100, and a solder bump 118 may be formed on the connection pad 116.
図１０を参照すれば、第２キャリア６に接合されたブリッジ回路層１００から保護フィルム５ｄを除去し、ブリッジ回路１１０の他面、すなわち接着層５ｃが形成された面を低密度回路層１５０に向かって加圧して低密度回路層１５０にブリッジ回路層１００を結合させる。このとき、ソルダーバンプは接着層５ｃを貫通してブリッジ回路１１０の他面にある接続パッド１１６と連結され、低密度回路１６０とブリッジ回路１１０を電気的に連結させることができる。第２キャリア６はＵＶ剥離型粘着テープに紫外線を照射した後、容易に分離することができる。一方、ブリッジ回路層１００の剛性補強のために第２キャリア６は分離されずに残され得る。このとき、ブリッジ回路層１００は第２キャリア６に仮接着されるのではなく、堅固に結合される。 Referring to FIG. 10, the protective film 5d is removed from the bridge circuit layer 100 bonded to the second carrier 6, and the other surface of the bridge circuit 110, that is, the surface on which the adhesive layer 5c is formed is formed on the low density circuit layer 150. Pressurize toward the low density circuit layer 150 to couple the bridge circuit layer 100. At this time, the solder bump penetrates the adhesive layer 5c and is connected to the connection pad 116 on the other surface of the bridge circuit 110, so that the low density circuit 160 and the bridge circuit 110 can be electrically connected. The second carrier 6 can be easily separated after irradiating the UV release type adhesive tape with ultraviolet rays. On the other hand, the second carrier 6 may be left unseparated to reinforce the rigidity of the bridge circuit layer 100. At this time, the bridge circuit layer 100 is not temporarily bonded to the second carrier 6, but is firmly bonded.
図１１を参照すれば、ブリッジ回路層１００が結合された低密度回路層１５０に絶縁層１５４をさらに積層してブリッジ回路層１００を埋め立てることができる。このとき、ブリッジ回路１１０と連結された外層回路１７０パターンをさらに形成することができる。外層回路１７０はダイ１、２と連結されるパッドを含むことができる。 With reference to FIG. 11, the insulating layer 154 can be further laminated on the low-density circuit layer 150 to which the bridge circuit layer 100 is coupled to fill the bridge circuit layer 100. At this time, the outer layer circuit 170 pattern connected to the bridge circuit 110 can be further formed. The outer layer circuit 170 can include pads connected to dies 1 and 2.
図１２および図１３を参照すれば、ブリッジ回路層１００が内蔵された低密度回路層１５０にさらにソルダーレジスト層１９０を形成することができる。ソルダーレジスト層１９０にはダイ１、２と連結されるパッドを選択的に露出させるオープニングが形成され得、露出されたパッド上にはソルダーバンプ１９５が形成され得る。 With reference to FIGS. 12 and 13, a solder resist layer 190 can be further formed on the low-density circuit layer 150 in which the bridge circuit layer 100 is incorporated. The solder resist layer 190 may be formed with an opening that selectively exposes the pads connected to the dies 1 and 2, and solder bumps 195 may be formed on the exposed pads.
図１４を参照すれば、ブリッジ回路層１００が内蔵された低密度回路層１５０に複数のダイ１、２を実装することができる。複数のダイ１、２は外層回路１７０を通じてブリッジ回路１１０に連結され、ブリッジ回路１１０を通じて複数のダイ１、２間の連結がなされ得る。また、印刷回路基板に必要な他の電子部品３も低密度回路層１５０に実装され得る。低密度回路層１５０に実装された電子部品３は低密度回路１６０を通じてブリッジ回路１１０に電気的に連結され得る。 With reference to FIG. 14, a plurality of dies 1 and 2 can be mounted on the low-density circuit layer 150 in which the bridge circuit layer 100 is built. The plurality of dies 1 and 2 may be connected to the bridge circuit 110 through the outer layer circuit 170, and the plurality of dies 1 and 2 may be connected through the bridge circuit 110. In addition, other electronic components 3 required for the printed circuit board can also be mounted on the low-density circuit layer 150. The electronic components 3 mounted on the low density circuit layer 150 can be electrically connected to the bridge circuit 110 through the low density circuit 160.
図１５〜図２４は本発明の他の実施例に係る印刷回路基板の製造方法を示した図面である。本発明の他の実施例に係る印刷回路基板の製造方法は、高密度のブリッジ回路層２００に低密度回路層２５０をビルドアップ（ｂｕｉｌｄ−ｕｐ）してブリッジ回路層２００を内蔵してビア２８０を通じて二つの回路層を連結させる方法を例示する。 15 to 24 are drawings showing a method of manufacturing a printed circuit board according to another embodiment of the present invention. In the method for manufacturing a printed circuit board according to another embodiment of the present invention, the low density circuit layer 250 is built up on the high density bridge circuit layer 200, and the bridge circuit layer 200 is built in the via 280. A method of connecting two circuit layers through is illustrated.
図１５を参照すれば、シード層７ａが形成された第３キャリア７を準備し、シード層７ａ上に一部の低密度回路２６０ａを形成することができる。 With reference to FIG. 15, a third carrier 7 on which the seed layer 7a is formed can be prepared, and a part of the low-density circuit 260a can be formed on the seed layer 7a.
図１６を参照すれば、第２キャリア６'に接合されたブリッジ回路層２００から保護フィルムを除去し、ブリッジ回路２１０の接着層５ｃ'が形成された面を第３キャリア７に向かって加圧してシード層７ａにブリッジ回路層２００を結合させる。このとき、前述した一実施例とは異なり、本実施例のブリッジ回路層２００は前述した実施例のブリッジ回路層１００が裏返された形態で形成される。換言すれば、複数のダイ１、２が連結されるブリッジ回路層１００の一面が第１キャリア５に向かって形成される。したがって、ブリッジ回路層２００の一面に接着層５ｃ'が形成され、他面にはＵＶ剥離型粘着テープ６ａ'で第２キャリア６'に結合されるように形成される。 Referring to FIG. 16, the protective film is removed from the bridge circuit layer 200 joined to the second carrier 6', and the surface of the bridge circuit 210 on which the adhesive layer 5c'is formed is pressed toward the third carrier 7. The bridge circuit layer 200 is coupled to the seed layer 7a. At this time, unlike the above-described one embodiment, the bridge circuit layer 200 of this embodiment is formed in a form in which the bridge circuit layer 100 of the above-described embodiment is turned inside out. In other words, one surface of the bridge circuit layer 100 to which the plurality of dies 1 and 2 are connected is formed toward the first carrier 5. Therefore, the adhesive layer 5c'is formed on one surface of the bridge circuit layer 200, and is formed on the other surface so as to be bonded to the second carrier 6'with the UV release type adhesive tape 6a'.
図１７を参照すれば、第２キャリア６'はＵＶ剥離型粘着テープ６ａ'に紫外線を照射した後、容易に分離することができる。一方、ブリッジ回路層２００の剛性補強のために第２キャリア６'は分離されずに残され得る。このとき、ブリッジ回路層２００は第２キャリア６'に仮接着されるのではなく、堅固に結合される。 With reference to FIG. 17, the second carrier 6'can be easily separated after irradiating the UV release type adhesive tape 6a'with ultraviolet rays. On the other hand, the second carrier 6'can be left unseparated to reinforce the rigidity of the bridge circuit layer 200. At this time, the bridge circuit layer 200 is not temporarily bonded to the second carrier 6', but is firmly bonded.
図１８を参照すれば、第３キャリア７のシード層７ａに結合されたブリッジ回路層２００に絶縁層２５２を積層してブリッジ回路層２００を埋め立てる。このとき、以後のビルドアップのための平坦度を確保するために絶縁層２５２上に別途のフィルムなどを付着して加圧するか真空で圧着させることができる。 Referring to FIG. 18, the insulating layer 252 is laminated on the bridge circuit layer 200 coupled to the seed layer 7a of the third carrier 7 to fill the bridge circuit layer 200. At this time, in order to secure the flatness for the subsequent build-up, a separate film or the like can be attached on the insulating layer 252 and pressed or pressure-bonded in a vacuum.
図１９を参照すれば、ブリッジ回路層２００の他面に形成された接続パッド２１６にビア２８０を連結し、低密度回路層２５０をビルドアップで形成する。ブリッジ回路層２００はビア２８０を通じて低密度回路２６０と上下に直接連結される。 With reference to FIG. 19, the via 280 is connected to the connection pad 216 formed on the other surface of the bridge circuit layer 200, and the low density circuit layer 250 is formed by build-up. The bridge circuit layer 200 is directly connected vertically to the low density circuit 260 through the via 280.
図２０を参照すれば、第３キャリア７を分離し、シード層７ａをエッチングなどで除去することができる。図２１を参照すれば、ブリッジ回路層２００の一面に追加でビルドアップし、ブリッジ回路２１０の一面に形成されたパッド２１２と連結された外層回路２７０パターンをさらに形成することができる。外層回路２７０はダイ１、２と連結されるパッドを含むことができる。 With reference to FIG. 20, the third carrier 7 can be separated and the seed layer 7a can be removed by etching or the like. With reference to FIG. 21, it is possible to additionally build up on one surface of the bridge circuit layer 200 to further form an outer layer circuit 270 pattern connected to the pad 212 formed on one surface of the bridge circuit 210. The outer layer circuit 270 can include pads connected to dies 1 and 2.
図２２および図２３を参照すれば、ブリッジ回路層２００が内蔵された低密度回路層２５０にソルダーレジスト層２９０を形成することができる。ソルダーレジスト層２９０にはダイ１、２と連結されるパッドを選択的に露出させるオープニングが形成され得、露出されたパッド上にはソルダーバンプ２９５が形成され得る。 With reference to FIGS. 22 and 23, the solder resist layer 290 can be formed on the low density circuit layer 250 in which the bridge circuit layer 200 is incorporated. The solder resist layer 290 may be formed with an opening that selectively exposes the pads connected to the dies 1 and 2, and solder bumps 295 may be formed on the exposed pads.
図２４を参照すれば、ブリッジ回路層２００が内蔵された低密度回路層２５０に複数のダイ１、２を実装することができる。複数のダイ１、２は外層回路２７０を通じてブリッジ回路２１０に連結され、ブリッジ回路２１０の微細な回路パターン２１４を通じて複数のダイ１、２間の連結がなされ得る。また、印刷回路基板に必要な他の電子部品３も低密度回路層２５０に実装され得る。低密度回路層２５０に実装された電子部品は低密度回路２６０を通じてブリッジ回路２１０と電気的に連結され得る。 With reference to FIG. 24, a plurality of dies 1 and 2 can be mounted on the low density circuit layer 250 in which the bridge circuit layer 200 is built. The plurality of dies 1 and 2 may be connected to the bridge circuit 210 through the outer layer circuit 270, and may be connected between the plurality of dies 1 and 2 through the fine circuit pattern 214 of the bridge circuit 210. In addition, other electronic components 3 required for the printed circuit board can also be mounted on the low-density circuit layer 250. The electronic components mounted on the low density circuit layer 250 may be electrically connected to the bridge circuit 210 through the low density circuit 260.
以上、本発明の一実施例について説明したが、該当技術分野で通常の知識を有した者であれば特許請求の範囲に記載された本発明の思想から逸脱しない範囲内で、構成要素の付加、変更、削除または追加などによって本発明を多様に修正および変更させることができ、このような変更物ないし均等物も本発明の権利範囲に属する。 An embodiment of the present invention has been described above, but if the person has ordinary knowledge in the relevant technical field, the components are added within the range that does not deviate from the idea of the present invention described in the claims. The present invention can be modified and changed in various ways by modification, deletion or addition, and such modifications or equivalents also belong to the scope of the present invention.
１、２ ダイ
５ 第１キャリア
６ 第２キャリア
７ 第３キャリア
１００、２００ ブリッジ回路層
１１０、２１０ ブリッジ回路
１３０ 検査回路パターン
１５０、２５０ 低密度回路層
１６０、２６０ 低密度回路
１７０、２７０ 外層回路
１８０ ソルダーバンプ
２８０ ビア
1, 2 Die 5 1st carrier 6 2nd carrier 7 3rd carrier 100, 200 Bridge circuit layer 110, 210 Bridge circuit 130 Inspection circuit pattern 150, 250 Low density circuit layer 160, 260 Low density circuit 170, 270 Outer layer circuit 180 Solder bump 280 via
Claims (8)
前記ブリッジ回路層が内蔵され、前記ブリッジ回路よりも密度が低い低密度回路を具備した低密度回路層、および、
前記ブリッジ回路層を覆う前記低密度回路層の絶縁層に形成され、前記複数のダイと前記ブリッジ回路を連結させる外層回路を含み、
前記ブリッジ回路は前記ブリッジ回路層の一側に配置された第１パッドおよび前記一側の反対側である他側に配置された第２パッドを含み、
前記第１パッドは第１ビアを通じて前記外層回路と連結され、
前記第２パッドは前記低密度回路層と第２ビアまたはソルダーバンプを通じて連結され、
前記ブリッジ回路層は、露出されないように前記低密度回路層の絶縁層により覆われる、印刷回路基板。 A bridge circuit layer comprising a high-density bridge circuit for electrically connecting a plurality of dies .
A low-density circuit layer having a built-in bridge circuit layer and a low-density circuit having a lower density than the bridge circuit , and
An outer layer circuit formed in an insulating layer of the low-density circuit layer covering the bridge circuit layer and connecting the plurality of dies and the bridge circuit is included.
The bridge circuit includes a first pad arranged on one side of the bridge circuit layer and a second pad arranged on the other side opposite to the one side.
The first pad is connected to the outer layer circuit through the first via and is connected to the outer layer circuit.
The second pad is connected to the low density circuit layer through a second via or solder bump.
A printed circuit board in which the bridge circuit layer is covered with an insulating layer of the low density circuit layer so as not to be exposed.
前記複数の第１パッドは前記複数のダイと接続し、
前記ブリッジ回路は、前記複数の第１パッドを連結する微細回路パターンをさらに含む、請求項１に記載の印刷回路基板。 The first pad is a plurality of first pads.
The plurality of first pads are connected to the plurality of dies.
It said bridge circuit further comprises, printed circuit board according to claim 1 minute circuit pattern for connecting the front Symbol plurality of first pads.
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| KR102101712B1 (en) * | 2018-03-21 | 2020-04-21 | (주)심텍 | Printed Circuit Board with Bridge Substrate |
| KR102648090B1 (en) * | 2019-05-17 | 2024-03-18 | 삼성전자주식회사 | Wiring substrate and semiconductor package comprising the same |
| JP2021093516A (en) | 2019-12-11 | 2021-06-17 | インテル・コーポレーション | Composite bridge die-to-die interconnection for integrated circuit package |
| KR20220015573A (en) | 2020-07-31 | 2022-02-08 | 삼성전기주식회사 | Printed circuit board and manufacturing method for the same |
| KR20220065550A (en) | 2020-11-13 | 2022-05-20 | 삼성전기주식회사 | Connection structure embedded substrate |
| CN113035827B (en) * | 2021-02-25 | 2022-07-05 | 日月光半导体制造股份有限公司 | Semiconductor package device and method of manufacturing the same |
| KR20230075176A (en) | 2021-11-22 | 2023-05-31 | 삼성전기주식회사 | Printed circuit board |
| KR20240045007A (en) * | 2022-09-29 | 2024-04-05 | 엘지이노텍 주식회사 | Semiconductor package |
| KR20240044946A (en) * | 2022-09-29 | 2024-04-05 | 엘지이노텍 주식회사 | Semiconductor package |
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| CN106165092B (en) * | 2014-02-26 | 2020-02-18 | 英特尔公司 | Embedded multi-device bridge with through-bridge conductive via signal connection |
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