JP6757791B2 - インメモリ処理及び狭幅データポートを備えたコンピュータデバイス - Google Patents

インメモリ処理及び狭幅データポートを備えたコンピュータデバイス Download PDF

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JP6757791B2
JP6757791B2 JP2018516124A JP2018516124A JP6757791B2 JP 6757791 B2 JP6757791 B2 JP 6757791B2 JP 2018516124 A JP2018516124 A JP 2018516124A JP 2018516124 A JP2018516124 A JP 2018516124A JP 6757791 B2 JP6757791 B2 JP 6757791B2
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address
storage
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cache
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JP2018534666A (ja
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ドゥヴォー，ファブリス
ロイ，ジャン−フランソワ
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アップメム
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4009—Coupling between buses with data restructuring
    • G06F13/4018—Coupling between buses with data restructuring with data-width conversion
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G06F13/128—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine for dedicated transfers to a network
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1678—Details of memory controller using bus width
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/52—Protection of memory contents; Detection of errors in memory contents

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Human Computer Interaction (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Quality & Reliability (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Memory System (AREA)
JP2018516124A 2015-10-01 2016-09-27 インメモリ処理及び狭幅データポートを備えたコンピュータデバイス Expired - Fee Related JP6757791B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
FR1559321A FR3042049A1 (enExample) 2015-10-01 2015-10-01
FR1559321 2015-10-01
FR1650186A FR3042050B1 (fr) 2015-10-01 2016-01-11 Dispositif informatique muni de traitement en memoire et de ports d'acces etroits
FR1650186 2016-01-11
PCT/FR2016/052450 WO2017055732A1 (fr) 2015-10-01 2016-09-27 Dispositif informatique muni de traitement en memoire et de ports d'acces etroits

Publications (2)

Publication Number Publication Date
JP2018534666A JP2018534666A (ja) 2018-11-22
JP6757791B2 true JP6757791B2 (ja) 2020-09-23

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JP2018516124A Expired - Fee Related JP6757791B2 (ja) 2015-10-01 2016-09-27 インメモリ処理及び狭幅データポートを備えたコンピュータデバイス

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US (1) US10884657B2 (enExample)
EP (1) EP3356945B1 (enExample)
JP (1) JP6757791B2 (enExample)
CN (1) CN108139989B (enExample)
FR (2) FR3042049A1 (enExample)
WO (1) WO2017055732A1 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3066842B1 (fr) 2017-05-24 2019-11-08 Upmem Logique de correction de row hammer pour dram avec processeur integre
US10592121B2 (en) * 2017-09-14 2020-03-17 Samsung Electronics Co., Ltd. Quasi-synchronous protocol for large bandwidth memory systems
CN112181865B (zh) * 2020-09-09 2024-05-31 北京爱芯科技有限公司 地址编码方法、装置、解码方法、装置及计算机存储介质
FR3115395A1 (fr) 2020-10-16 2022-04-22 Upmem Dispositif semi-conducteur comprenant un empilement de puces et puces d’un tel empilement
CN114048157B (zh) * 2021-11-16 2024-08-13 安徽芯纪元科技有限公司 一种内部总线地址重映射装置
FR3159453A1 (fr) 2024-02-21 2025-08-22 Upmem dispositif informatique

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5745791A (en) * 1992-09-16 1998-04-28 Intel Corporation System for interfacing first and second components having different data path width by generating first and second component address to read data into buffer
JPH08147076A (ja) * 1994-11-22 1996-06-07 Seiko Epson Corp 情報処理装置
US5634013A (en) * 1995-05-03 1997-05-27 Apple Computer, Inc. Bus bridge address translator
US5818844A (en) * 1996-06-06 1998-10-06 Advanced Micro Devices, Inc. Address generation and data path arbitration to and from SRAM to accommodate multiple transmitted packets
JPH10222459A (ja) * 1997-02-10 1998-08-21 Hitachi Ltd 機能メモリとそれを用いたデータ処理装置
US6754741B2 (en) * 2001-05-10 2004-06-22 Pmc-Sierra, Inc. Flexible FIFO system for interfacing between datapaths of variable length
JP2003346500A (ja) * 2002-05-29 2003-12-05 Hitachi Ltd 半導体集積回路及びそのテスト方法
JP5992713B2 (ja) * 2012-03-30 2016-09-14 株式会社ソニー・インタラクティブエンタテインメント メモリシステム、その制御方法及び情報処理装置

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Publication number Publication date
CN108139989A (zh) 2018-06-08
EP3356945A1 (fr) 2018-08-08
EP3356945B1 (fr) 2019-09-04
US10884657B2 (en) 2021-01-05
JP2018534666A (ja) 2018-11-22
WO2017055732A1 (fr) 2017-04-06
FR3042050B1 (fr) 2019-11-01
CN108139989B (zh) 2021-05-25
FR3042050A1 (enExample) 2017-04-07
US20180260161A1 (en) 2018-09-13
FR3042049A1 (enExample) 2017-04-07

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