JP6707927B2 - Method for manufacturing silicon carbide semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a silicon carbide semiconductor device of a vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor) using a silicon carbide substrate and having particularly excellent dielectric breakdown voltage characteristics.

Since silicon carbide has a band gap that is about three times that of silicon, an electron saturation drift velocity that is about twice that of silicon, and a dielectric breakdown voltage that is about an order of magnitude higher than that of silicon, it has excellent controllability of electrical conductivity at high temperatures and high frequency. In addition, it has attracted attention as a substrate material for high breakdown voltage power devices capable of controlling large power, and silicon carbide power devices of various structures such as Schottky barrier diodes and insulated gate field effect transistors have been developed.

In a silicon carbide power device, since the impurity diffusion coefficient of silicon carbide is small and a thermal diffusion method like silicon cannot be applied, an ion implantation method is widely used when forming the first conductivity type region type and the second conductivity type region. It is used.

A method of performing ion implantation at a temperature of 150° C. or lower using a resist mask formed by dry etching a photoresist formed on the surface of a drift layer grown on a silicon carbide substrate is disclosed (for example, See Patent Document 1 below.).

On the other hand, when high-concentration ion implantation is performed on silicon carbide at a low temperature of 150° C. or lower, there is a problem that the crystallinity of the implanted region deteriorates and the device performance tends to deteriorate. In order to prevent this, it is necessary to perform ion implantation in a high temperature atmosphere of 300° C. or higher. However, it is conceivable that the resist mask made of a resin or an organic solvent is deteriorated at a high temperature of 300° C. or higher, which makes dimensional control difficult.

JP, 2009-49363, A

It is known that an inorganic insulating film such as a SiO ₂ film, which is stable to relatively high temperature conditions, can be used as a mask for ion implantation, and a method of opening an ion implantation region having a width of submicron to several microns in the inorganic insulating film. As such, a dry etching method capable of anisotropic etching is widely used. However, there is a problem that the surface of the ion-implanted region is excessively etched (overetched) by plasma or active species generated during dry etching, resulting in a depression. For example, when such a recess is formed when the source region of the SiC-MOSFET is formed by ion implantation, the film thickness of the gate oxide film formed on the surface of the source region after that becomes non-uniform, and insulation occurs when a high voltage is applied. It will cause destruction.

In view of the above problems, it is an object of the present invention to realize a good ion implantation region selection ratio and at the same time suppress damage to the substrate during ion implantation. Another object of the present invention is to provide a silicon carbide semiconductor device having excellent dielectric breakdown voltage characteristics.

In order to solve the above-mentioned problems and achieve the object of the present invention, a method for manufacturing a silicon carbide semiconductor device according to the present invention provides a silicon carbide epitaxial layer on a first main surface of a first conductivity type silicon carbide substrate. A step of forming, a step of forming a first inorganic insulating film on the surface of the silicon carbide epitaxial layer, and a second inorganic film having a higher etching rate and a larger film thickness than the first inorganic insulating film on the first inorganic insulating film. A step of forming an insulating film, a step of forming a photoresist pattern on the surface of the second inorganic insulating film, and a step of forming a mask part and an ion implantation part in the first inorganic insulating film using the photoresist pattern. A step of implanting ions into the silicon carbide epitaxial layer from the ion implanting part, wherein the step of forming the first inorganic insulating film is performed by CVD of an inorganic film containing nitrogen. A step of forming the ion-implanted portion, and the step of forming the ion-implanted portion removes the second inorganic insulating film of the ion-implanted portion by dry etching the second inorganic insulating film using the photoresist pattern. And a step of removing the first inorganic insulating film remaining on the bottom of the ion-implanted portion by wet etching.

Further, the method for manufacturing a silicon carbide semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the first inorganic insulating film has a thickness of 50 nm or more and 120 nm or less.

A method of manufacturing a silicon carbide semiconductor device according to the present invention includes a step of forming a silicon carbide epitaxial layer on a first main surface of a first conductivity type silicon carbide substrate, and a first step on the surface of the silicon carbide epitaxial layer. A step of forming an inorganic insulating film, and a second inorganic insulating film made of silicon oxide, NSG, PSG or FSG having a higher etching rate and a larger film thickness than the first inorganic insulating film on the first inorganic insulating film. A step of forming a photoresist pattern on the surface of the second inorganic insulating film, a step of forming a mask portion and an ion implantation portion in the first inorganic insulating film using the photoresist pattern, A method of manufacturing a silicon carbide semiconductor device, comprising a step of implanting ions into the silicon carbide epitaxial layer from an ion implantation part, wherein the step of forming the first inorganic insulating film is a step of forming a silicon film by a CVD method. And a step of forming the ion-implanted portion, dry etching the second inorganic insulating film using the photoresist pattern, and removing the second inorganic insulating film of the ion-implanted portion, and a step of removing the first inorganic insulating film remaining on the bottom of the ion implantation portion by wet etching based on the difference in etching rate of the first inorganic insulating film and the second inorganic insulating film, the endpoint monitor Is characterized in that the dry etching is completed with an end point at which the emission intensity of 310 nm indicating CO bond starts to decrease .

Further, the method for manufacturing a silicon carbide semiconductor device according to the present invention is characterized in that, in the above-mentioned invention, the first inorganic insulating film has a thickness of 50 nm or more and 200 nm or less.

According to the above-mentioned invention, the first inorganic insulating film can be made to have a predetermined thickness, the ion shielding property of the ion implantation mask can be enhanced, and the first inorganic insulating film can be stably left on the bottom surface of the opening. As a result, damage to the bottom of the opening due to dry etching can be reliably suppressed, and the opening size of the ion implantation mask can be controlled with high accuracy.

According to the present invention, it is possible to realize a good ion implantation region selection ratio and at the same time suppress damage to the substrate during ion implantation. Further, it is possible to provide a silicon carbide semiconductor device having excellent dielectric breakdown voltage characteristics.

FIG. 1 is a sectional view showing a manufacturing process of a silicon carbide semiconductor device according to first and second embodiments of the present invention. (Part 1) FIG. 2 is a cross-sectional view showing a manufacturing process of the silicon carbide semiconductor device according to the first and second embodiments of the present invention. (Part 2) FIG. 3 is a cross-sectional view showing a manufacturing process of the silicon carbide semiconductor device according to the first and second embodiments of the present invention. (Part 3) FIG. 4 is a sectional view showing a manufacturing process of the silicon carbide semiconductor device according to the first and second embodiments of the present invention. (Part 4) FIG. 5 is a cross-sectional view showing a manufacturing process of the silicon carbide semiconductor device according to the first and second embodiments of the present invention. (Part 5) FIG. 6 is a cross-sectional view showing a manufacturing process of the silicon carbide semiconductor device according to the first and second embodiments of the present invention. (Part 6) FIG. 7 is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to the example of the present invention.

Embodiments according to the present invention will be described in detail below with reference to the accompanying drawings. In the present specification and the accompanying drawings, electrons or holes are the majority carriers in the layers or regions prefixed with n or p. Further, + and − added to n and p mean that the impurity concentration is higher and the impurity concentration is lower than that of the layer or region to which they are not applied, respectively. Note that, in the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same configurations, and duplicate description will be omitted. In the present specification, in the Miller index notation, “−” means a bar attached to the index immediately after it, and “−” is added before the index to represent a negative index.

(Embodiment 1)
1 to 6 are cross-sectional views showing the manufacturing process of the silicon carbide semiconductor device according to the first embodiment of the present invention. First, as shown in FIG. 1, a first conductivity type n ⁻ -type silicon carbide epitaxial layer 12 is laminated on one main surface of silicon carbide substrate 11.

Next, the first inorganic insulating film 21 is formed on the surface of the n ⁻ type silicon carbide epitaxial layer 12. As the first inorganic insulating film 21, a SiON film formed by a plasma CVD method using SiH ₄ , N ₂ O and NH ₃ gas can be applied.

Next, a second inorganic insulating film 22 having a higher etching rate and a larger film thickness than the first inorganic insulating film 21 is formed on the surface of the n ⁻ type silicon carbide epitaxial layer 12. The second inorganic insulating film 22 is a silicon oxide film formed by a plasma CVD (Chemical Vapor Deposition) method or a low-pressure CVD method, an NSG (None-doped Silicon Glass) formed by a normal-pressure CVD method, a PSG (Phosphorus Silicon Glass), and an FSG (Fluon Fluor). Each film of Glass) can be applied.

Next, as shown in FIG. 2, a photoresist is applied to the surface of the second inorganic insulating film 22, and the photoresist is patterned by exposure and development to form a resist pattern 14.

Next, as shown in FIG. 3, dry etching is performed on the second inorganic insulating film 22 using methane tetrafluoride (CF ₄ ) and argon (Ar) using the resist pattern 14 as a mask. Since the etching rates of SiON and silicon oxide are different by about 1.5 times, the etching is terminated with the end point at which the emission intensity of about 310 nm, which indicates CO bond, starts to decrease in the end point monitor.

Next, as shown in FIG. 4, the first inorganic insulating film 21 in the opening of the resist pattern 14 is removed by wet etching, and the silicon carbide substrate (n ⁻ -type silicon carbide epitaxial layer 12) in the opening of the resist pattern 14 is removed. Expose. For wet etching, buffered hydrofluoric acid, an aqueous solution of hydrogen fluoride, or the like can be used.

Next, as shown in FIG. 5, the resist pattern 14 is removed by ashing. Through the above steps, the ion implantation mask 24 including the ion implantation portion and the mask portion is formed.

Next, as shown in FIG. 6, using the ion implantation mask 24, phosphorus ions or nitrogen ions are implanted if n-type, aluminum ions or the like are implanted if p-type. An n region or p region 17 is formed in the opening of the ion implantation mask 24.

Here, by setting the film thickness of the first inorganic insulating film 21 to 50 nm or more and 120 nm or less, the ion shielding property of the ion implantation mask 24 is enhanced, and the first inorganic insulating film 21 is stably left on the bottom surface of the opening. You can As a result, damage to the bottom of the opening due to dry etching can be reliably suppressed, and the opening size of the ion implantation mask 24 can be controlled with high accuracy.

(Embodiment 2)
Next, a method for manufacturing the silicon carbide semiconductor device according to the second embodiment of the present invention will be described. The second embodiment will also be described with reference to FIGS.

First, as shown in FIG. 1, n ⁻ type silicon carbide epitaxial layer 12 is laminated on one main surface of silicon carbide substrate 11. Next, the first inorganic insulating film 21 is formed on the surface of the n ⁻ type silicon carbide epitaxial layer 12. As the first inorganic insulating film, a polysilicon film or an amorphous silicon film formed by a plasma CVD method using SiH ₄ and Ar gas can be applied.

Next, a second inorganic insulating film 22 having a higher etching rate and a larger film thickness than the first inorganic insulating film 21 is formed on the surface of the n ⁻ type silicon carbide epitaxial layer 12. As the second inorganic insulating film 22, a silicon oxide film formed by a plasma CVD method or a low pressure CVD method, NSG, PSG, FSG formed by a normal pressure CVD method, or the like can be applied.

Next, as shown in FIG. 2, a photoresist is applied to the surface of the silicon oxide film 22, and the photoresist is patterned by exposure and development to form a resist pattern 14.

Next, as shown in FIG. 3, dry etching is performed using CF ₄ and Ar using the resist pattern 14 as a mask. As in the case of the first embodiment, the difference between the etching rates of silicon and silicon oxide is used to finish the etching with the end point at which the emission intensity of about 310 nm indicating CO bond in the end point monitor starts to decrease.

Next, as shown in FIG. 4, the first inorganic insulating film 21 in the opening of the resist pattern 14 is removed by wet etching, and the silicon carbide substrate (n ⁻ -type silicon carbide epitaxial layer 12) in the opening of the resist pattern 14 is removed. Expose. For wet etching, an aqueous solution or the like in which hydrofluoric acid and nitric acid are mixed can be used.

Next, as shown in FIG. 5, the resist pattern 14 is removed by ashing. Through the above steps, the ion implantation mask 24 including the ion implantation portion and the mask portion is formed.

Next, as shown in FIG. 6, using the ion implantation mask 24, phosphorus ions or nitrogen ions are implanted if n-type, aluminum ions or the like are implanted if p-type. An n region or p region 17 is formed in the opening of the ion implantation mask 24.

Here, by setting the film thickness of the first inorganic insulating film 21 to 50 nm or more and 200 nm or less, the ion shielding property of the ion implantation mask can be improved and the first inorganic insulating film 21 can be stably left on the bottom surface of the opening. it can. As a result, damage to the bottom of the opening due to dry etching can be reliably suppressed, and the opening size of the ion implantation mask can be controlled with high accuracy.

The surface shape of the ion implantation portion of the silicon carbide semiconductor device manufactured by the manufacturing method according to the first embodiment of the present invention was verified. FIG. 7 is a sectional view showing the structure of the MOSFET according to the example of the present invention.

First, a 100 nm-thick SiON film is formed on the surface of the first conductivity type n ⁻ type silicon carbide epitaxial layer 12 formed on the (0001) plane of the 4H—SiC silicon carbide substrate 11 by using the plasma CVD method. did. Next, a 1200 nm-thickness NSG film was formed on the surface of the SiON film by the atmospheric pressure CVD method. Next, an ion implantation mask was formed according to the first embodiment, and Al ions were implanted to form a second conductivity type p ⁺ base region 31.

Next, p ⁻ type silicon carbide epitaxial layer 32 was grown on the surface of n ⁻ type silicon carbide epitaxial layer 12. Next, according to the first embodiment, p ⁻ type silicon carbide epitaxial layer 32 is implanted with p ions to implant n type source region 33, Al ions are implanted to implant p type source contact region 34, and nitrogen ions are implanted into JFET. Region 35 was formed.

After forming the p-type breakdown voltage portion on the outer periphery, activation annealing was performed at about 1600° C., and then the gate oxide film 36, the gate electrode 37, and the source contact electrode 38 were formed to manufacture a MOSFET.

In addition, as a comparative example, an ion implantation mask in which an oxide film in an ion implantation portion is sufficiently removed by dry etching from a 1200 nm-thickness NSG film formed by a conventional manufacturing method by a conventional manufacturing method is used. A MOSFET was manufactured using the above.

As a result, in the comparative example, a step of about 5 nm was formed at the end portion of the source contact portion where the ion implantation was performed, but in the example, the entire ion implanted portion was flat. As described above, according to the example, the element withstand voltage of the example can be greatly improved from about 460 V of the conventional example to 720 V by flattening as compared with the comparative example.

It was also confirmed that the MOSFET using the ion implantation mask formed according to the second embodiment can also achieve the same effect as that of the above-described embodiment.

In the above, the present invention is not limited to the above-described embodiments, but can be variously modified without departing from the spirit of the present invention, and can be applied to various methods for manufacturing silicon carbide semiconductor devices manufactured using an ion implantation method. Is effective. For example, the present invention is similarly applicable when the p-type and the n-type are exchanged, or when the silicon carbide substrate and the epitaxial layer grown on the main surface of the silicon carbide substrate have the same conductivity type. The same holds true when a silicon carbide substrate having a crystal polymorph other than 4H—SiC is used as the substrate.

As described above, the method for manufacturing a silicon carbide semiconductor device according to the present invention is useful for manufacturing a silicon carbide semiconductor device using silicon carbide as a semiconductor material. In particular, it is particularly effective in manufacturing a vertical MOSFET having excellent dielectric breakdown voltage characteristics.

11 Silicon Carbide Substrate 12 n ^- Type Silicon Carbide Epitaxial Layer 13 Inorganic Insulating Film 14 Resist Pattern 15 SiO ₂ Film Remaining at Bottom of Opening 16 Ion Implantation Mask 17 Ion Implanting Region 21 First Inorganic Insulating Film 22 Second Inorganic Insulation Film 31 p ⁺ base region 32 p ⁻ type silicon carbide epitaxial layer 33 n ⁺ type source region 34 p ⁺ type source contact region 35 JFET region 36 gate insulating film 37 gate electrode 38 source contact electrode

Claims (4)

Forming a silicon carbide epitaxial layer on the first main surface of the first conductivity type silicon carbide substrate;
A step of forming a first inorganic insulating film on the surface of the silicon carbide epitaxial layer,
A step of forming a thick second inorganic insulating film having a higher etching rate than the first inorganic insulating film on the first inorganic insulating film;
A step of forming a photoresist pattern on the surface of the second inorganic insulating film,
Forming a mask portion and an ion implantation portion in the first inorganic insulating film using the photoresist pattern,
And a step of implanting ions into the silicon carbide epitaxial layer from the ion implantation part, the method comprising:
The step of forming the first inorganic insulating film comprises the step of forming an inorganic film containing nitrogen by a CVD method,
A step of forming the ion-implanted portion, dry etching the second inorganic insulating film using the photoresist pattern, and removing the second inorganic insulating film of the ion-implanted portion,
Removing the first inorganic insulating film remaining on the bottom of the ion-implanted portion by wet etching,
A method of manufacturing a silicon carbide semiconductor device, comprising: The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the thickness of the first inorganic insulating film is 50 nm or more and 120 nm or less. Forming a silicon carbide epitaxial layer on the first main surface of the first conductivity type silicon carbide substrate;
A step of forming a first inorganic insulating film on the surface of the silicon carbide epitaxial layer,
A step of forming on the first inorganic insulating film a second inorganic insulating film made of any one of silicon oxide, NSG, PSG, and FSG, which has a higher etching rate than the first inorganic insulating film and has a thicker film thickness;
A step of forming a photoresist pattern on the surface of the second inorganic insulating film,
Forming a mask portion and an ion implantation portion in the first inorganic insulating film using the photoresist pattern,
And a step of implanting ions into the silicon carbide epitaxial layer from the ion implantation part, the method comprising:
The step of forming the first inorganic insulating film includes the step of forming a silicon film by a CVD method,
A step of forming the ion implantation part, a step of performing dry etching on the second inorganic insulating film using the photoresist pattern, and removing the second inorganic insulating film of the ion implantation part;
Removing the first inorganic insulating film remaining on the bottom of the ion-implanted portion by wet etching ,
Based on the difference in the etching rates of the first inorganic insulating film and the second inorganic insulating film, the dry etching is terminated with the end point at which the emission intensity of 310 nm indicating CO bond starts to decrease by the end point monitor. A method of manufacturing a characteristic silicon carbide semiconductor device. The method for manufacturing a silicon carbide semiconductor device according to claim 3, wherein the thickness of the first inorganic insulating film is 50 nm or more and 200 nm or less.

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