JP2006041166A - Method for forming ion injection mask and silicon carbide device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for forming an ion implantation mask, having steep side faces whose patterns, are less likely to be tapered. <P>SOLUTION: A silicon dioxide film 21x as a first film and an Al film 22x as a second film are successively deposited on a substrate, and a resist mask Re1 is formed on the Al film 22x. The resist mask Re1 is used as an etching mask, the Al film 22x is patterned, an Al mask 22 as an intermediate mask is formed, the resist mask Re1 and the Al mask 22 are used as an etching mask; and the silicon dioxide film 21x is patterned so that a silicon dioxide mask 21 can be formed as an ion implantation mask. Afterwards, the resist mask Re1 and the Al mask 22 are removed, and ion is injected into a high resistance SiC layer 2 at a high temperature of 150°C or higher, by using the silicon dioxide mask 21, so that a p-well region 3 being an impurity diffused layer can be formed. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method of forming an ion implantation mask used during a manufacturing process of a silicon carbide device and a silicon carbide device using the same, and more particularly to a countermeasure for forming a fine pattern.

  In recent years, compound semiconductors have physical properties different from Si, such as a wide band gap and high carrier mobility, and thus are expected to be applied to various fields. For example, since silicon carbide (SiC) has a large band gap and high dielectric breakdown characteristics, application to a low-loss power device is expected.

  For example, active semiconductor devices that can be formed on a silicon carbide substrate include bipolar transistors (BJT), junction field effect transistors (JFET), electrostatic induction transistors (SIT), insulated gate field effect transistors (MISFET), There are a Schottky junction gate type field effect transistor (MESFET), an insulated gate bipolar transistor (IGBT), a single gate type static induction thyristor (SGSITH), and the like. Each of these devices is a three-terminal device, two main terminals (emitter and collector, source and drain or cathode and anode) corresponding to the inlet and outlet of the main current path through which a current flows, and a control terminal ( Base or gate).

  Bipolar devices always have a pn junction between main terminals, and an operating current can be obtained by flowing carriers of two types of conductivity over a potential barrier formed at the pn junction. Between the main terminals of the field effect transistor (unipolar device), there may be only a semiconductor layer of the same conductivity type, and a pn junction is not necessary in the main current path of the field effect transistor. A single conductivity type carrier flows in the main current path of the field effect transistor.

  For example, in the formation of silicon carbide power devices, impurities (dopants) are introduced into semiconductor layers not only in bipolar devices but also in unipolar devices by in-situ doping during epitaxial growth or ion implantation. It is common to use either method.

  In silicon carbide power devices, due to the property that impurities are difficult to diffuse in silicon carbide, ion implantation for controlling conductivity in silicon carbide is positioned as an important technique among these techniques. ing.

  By using the ion implantation method, it is possible to form a fine pattern of an impurity diffusion layer having different conductivity types, and the applicability in device formation is extremely high. In particular, in all the devices described above, miniaturization of the device structure is an extremely important issue in order to reduce the on-resistance.

  By the way, in the case of ion implantation into silicon carbide, whether it is a p-type dopant or an n-type dopant, high-temperature implantation at 500 ° C. or higher must be performed in order to minimize defect damage (for example, Patent Document 1). Therefore, it is common to use an ion implantation mask (hard mask) made of a silicon dioxide film, a nitride film or the like having a heat resistance of 500 ° C. or more as a mask material. Moreover, these ion implantation masks require a thickness of several μm.

On the other hand, in order to form an ion implantation mask by patterning a silicon dioxide film, a nitride film or the like, a method of performing wet etching or dry etching using a resist pattern formed by photolithography as a mask is used.
JP 2001-196629 (paragraph [0032])

  Here, when a hard mask is formed by patterning an oxide film, a nitride film, etc. by wet etching having isotropic etching characteristics, the ion implantation mask is required to have a thickness of several μm. The inclination of the side surface of the mask from the direction perpendicular to the substrate surface increases. As a result, in the thinned portion of the ion implantation mask, ions are allowed to pass to some extent during ion implantation, so that it is difficult to form a fine pattern of the impurity diffusion layer.

  Therefore, when an impurity diffusion layer having a fine pattern containing a specific conductivity type dopant is formed by ion implantation, a dry etching having anisotropic etching characteristics is used as a method for forming an ion implantation mask, and a steep side surface is formed. It is considered preferable to form an ion implantation mask.

  However, when patterning for forming the ion implantation mask is performed by dry etching, the etching rate of the resist film as the etching mask is high, so that it is actually difficult to make the side surface of the ion implantation mask steep.

  In addition, since the resist film is etched at a high rate, the pattern of the ion implantation mask tends to be thin, and it is difficult to maintain high accuracy of the pattern of the ion implantation mask.

  As a result, even if high energy ion implantation is performed using a conventional ion implantation mask, it is difficult to form a fine pattern of the impurity diffusion layer.

  An object of the present invention is to provide a method for forming an ion implantation mask that has a steep side surface and is difficult to be thinned.

  A method for forming an ion implantation mask according to the present invention is a method for forming an ion implantation mask used in a manufacturing process of a silicon carbide device, and is formed immediately above a first film serving as an ion implantation mask than the first film. In this method, an intermediate mask made of a thin second film is formed, and the intermediate mask is used as an etching mask when patterning the first film.

  By this method, when the intermediate film is formed by patterning the second film, the shape of the resist mask is not significantly deformed because the second film is thin. Then, when the ion implantation mask is formed by patterning the second film, even if the shape of the resist mask is collapsed, the ion implantation mask is hardly thinned due to the presence of the intermediate mask. Therefore, an ion intermediate mask having a steep side surface can be obtained, and a fine pattern of the impurity diffusion layer can be formed in the substrate.

  When forming the ion implantation mask, it is preferable to pattern the first film by dry etching that can easily realize anisotropic etching characteristics.

Since the second film is made of a material that is smaller than the etching rate of the first film when forming the ion implantation mask, the deformation of the shape of the intermediate mask is suppressed, and the thinning of the ion implantation mask is more effective. It is suppressed.

  The first film serving as the ion implantation mask is preferably a film made of oxide or nitride.

  Since the second film serving as the intermediate mask is a metal film, particularly an Al film, the etching rate of the intermediate mask when patterning the first film can be reduced.

  Further, by patterning the metal film by wet etching, an intermediate mask can be formed with the resist mask remaining, and the resist mask can also be used as an etching mask when forming the ion implantation mask.

  The second film preferably has a thickness sufficient to remain until the etching of the first film is completed when the ion implantation mask is formed.

  In the silicon carbide device of the present invention, the distance between the flat portion and the side surface at the bottom surface of the ion implantation region is not more than the depth of the ion implantation region.

  As a result, the formation range of the ion implantation region as designed is almost ensured, so that it is possible to form a fine pattern of the impurity diffusion layer using the ion implantation mask as described above.

  According to the present invention, since an ion implantation mask having a steep side surface can be formed, it is possible to form a fine pattern of an impurity diffusion layer having a different conductivity type on a silicon carbide substrate using this ion implantation mask. Thus, it becomes possible to form a low-loss device up to the theoretical limit of the material and silicon carbide.

  FIG. 1 is a cross-sectional view showing the structure of a storage MISFET and a double injection MISFET using an SiC substrate according to an embodiment of the present invention. Although only a partial cross-sectional structure is disclosed in FIG. 1, the planar structure of the MISFET has a structure as disclosed in FIG. 2 or FIG. 10 of the international application PCT / JP01 / 07810, for example.

As shown in FIG. 1, this double-implant MISFET has a low-resistance SiC substrate 1 containing an n-type impurity (dopant) having a concentration of 1 × 10 ¹⁸ cm ⁻³ or more, and a main surface of the SiC substrate 1. A high resistance SiC layer 2 which is provided and is doped with an n-type impurity having a concentration of about 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁶ cm ^−3, and a concentration on a part of the surface portion of the high resistance SiC layer 2. Is doped with a p-type impurity of 1 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ , and a concentration of about 1 × 10 ¹⁹ cm ⁻ is formed in a part of the p well region 3. A source region 6 formed by doping ³ n-type impurities and a p ⁺ contact region formed by doping a portion of the p-well region 3 located immediately below the source region with a high-concentration p-type impurity 11, source region 6, p-well region 3, and high resistance SiC
A channel layer 5 including a laminated doped layer structure formed over the layer 2, a gate insulating film 7 made of a thermal oxide film provided on the surface of the channel layer 5, and provided on the gate insulating film 7 Provided on the gate electrode 10 made of an Al alloy film and on the wall surface of the trench that reaches the p ⁺ contact region 11 through the source region 6 and is in contact with the p ⁺ contact region 11 and the source region 7 A source electrode 8 and a drain electrode 9 formed so as to be in ohmic contact with the back surface of the SiC substrate 1 are provided.

Each of the source region 6 that is an n-type semiconductor layer and the high-resistance SiC layer 2 are in an electrically connected state via a channel layer 5 that is an n-type semiconductor layer. In addition, a part of the channel layer 5 located above the source region is removed. The source electrode 8, the source region 6 and the p ⁺ contact region 11 are heat-treated so as to be in ohmic contact with each other.
SiC substrate 1 and drain electrode 9 are in ohmic contact with each other.

Here, in the silicon carbide device of the present embodiment, as shown in FIG. 1, the impurity concentration profile of the ion implantation region (for example, p-well region 3) is A as the distance between the flat portion on the lower surface and the side surface. When the depth of the ion implantation region is D, the relationship of A ≦ D is established. This is true not only for the p well region 3 but also for the source region 6 and the p ⁺ contact region 11. However, for the p + contact region 11, the depth from the substrate surface at the time of ion implantation is D.

  That is, the formation range of the ion implantation region as designed is almost ensured by the implantation mask forming method of the present invention. This is because ion implantation is performed using an implantation mask having a steep side surface, as will be described later.

  FIGS. 2A to 2E and FIGS. 3A to 3E are cross-sectional views showing manufacturing steps of the double injection MISFET of this embodiment.

  First, in the step shown in FIG. 2A, a high resistance SiC layer 2 having a higher resistance (lower dopant concentration) than that of the SiC substrate 1 is epitaxially grown on the low resistance SiC substrate 1.

  Next, in the step shown in FIG. 2B, for example, a TEOS film is deposited, a silicon dioxide film 21x (first film) having a thickness of 3 μm is deposited on the high-resistance SiC layer 2, and then vapor deposition is performed. Then, an Al film 22x (second film) having a thickness of about 0.2 μm is deposited on the silicon dioxide film 21x. Thereafter, photolithography is performed to form a resist mask Re1 in which a P well formation region is opened on the Al film 22x.

Next, in the step shown in FIG. 2C, the Al film 22x is patterned by phosphoric acid wet etching using the resist mask Re1 as an etching mask to form an Al mask 21 (intermediate mask). Subsequently, the silicon dioxide film 21x is patterned by dry etching using the resist mask Re1 and the Al mask 22 as an etching mask to form a silicon dioxide mask 21 (ion implantation mask). At this time, although the silicon dioxide film 21x is a thick film having a thickness of 3 μm, for example, I using a gas such as CHF ₃ is used.
By performing the CP etching, the silicon dioxide mask 21 having a steep side surface can be formed. Then, the Al mask 22 and the resist mask Re1 are removed, and the silicon dioxide mask 21 is used to hold a substrate at a high temperature of 500 ° C. or higher, and p-type impurities are partially formed on the surface portion of the high resistance SiC layer 2. Ion implantation is performed to form the p-well region 3. The concentration of the p-type impurity in the p-well region 3 is usually about 1 × 10 ¹⁷ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ , and the depth of the p-well region 3 is about 1 μm so as not to pinch off.

  Next, in the step shown in FIG. 2D, the silicon dioxide mask 21, the Al mask 22 and the resist mask Re1 are removed, and annealing is performed to activate the implanted impurities, and then the p-well region 3 and A channel layer 5 containing an n-type impurity is epitaxially grown on the surface of the high resistance SiC layer 2.

Next, in the step shown in FIG. 2E, for example, a TEOS film is deposited, a silicon dioxide film 24x (first film) having a thickness of 3 μm is deposited on the channel layer 5, and then vapor deposition is performed. Then, an Al film 25x (second film) having a thickness of about 0.2 μm is deposited on the silicon dioxide film 24x. afterwards,
Photolithography is performed to form a resist mask Re2 having an opening in the source formation region on the Al film 25x.

Next, in the step shown in FIG. 3A, the Al film 25x is patterned by phosphoric acid-based wet etching using the resist mask Re2 as an etching mask to form an Al mask 25 (intermediate mask). Subsequently, the silicon dioxide film 24x is patterned by dry etching using the resist mask Re2 and the Al mask 25 as an etching mask to form a silicon dioxide mask 24 (ion implantation mask). At this time, for example, by performing ICP etching using a gas such as CHF ₃ , the silicon dioxide mask 24 having a sharp side surface can be formed. Then, the Al mask 25 and the resist mask Re2 are removed, and the silicon dioxide mask 24 is used to hold the substrate at a high temperature of 500.degree. By performing ion implantation of the type impurity, a source region 6 that penetrates the channel layer 5 and reaches the inside of the p-well region 3 is formed. At this time, the source region 6 that is an n-type semiconductor layer and the high-resistance SiC layer 2 are in an electrically connected state via a channel layer 5 that is an n-type semiconductor layer.

Next, in the step shown in FIG. 3B, ion implantation of high-concentration p-type impurities is performed to form a p ⁺ contact region 11 in a part of the p-well region 3 located immediately below the source region 6. To do.
Then, the silicon dioxide mask 24, the Al mask 25 and the resist mask Re2 are removed, and annealing for activating the impurities implanted into the p ⁺ contact region 11 and the source region 6 is performed. Further, after forming the trench 4 penetrating the source region 6 and reaching the upper portion of the p ⁺ contact region 11, the exposed surface portions of the channel layer 5, the source region 6 and the p ⁺ contact region 11 are thermally oxidized. Then, a gate insulating film 7 made of a thermal oxide film is formed.

  Next, in the step shown in FIG. 3C, the portion of the gate insulating film 7 on the wall surface of the groove 4 and the portion around the groove 4 are removed.

  Next, in the step shown in FIG. 3D, the source electrode 8 is formed on the portion of the source region 6 where the gate insulating film 7 is removed and exposed. Further, drain electrode 9 is formed on the back surface of SiC substrate 1.

Next, the gate electrode 10 is formed on the gate insulating film 7 in the step shown in FIG. The source electrode 8, the source region 7 and the p ⁺ contact region 11 are in ohmic contact, and S
Heat treatment is performed so that the iC substrate 1 and the drain electrode 9 are in ohmic contact.

  Here, the process shown in FIG. 2C or FIG. 3A, which is a high-temperature ion implantation process in the manufacturing process, will be described.

  FIG. 4 is a cross-sectional view showing the shape of each mask before ion implantation in the step shown in FIG. 2C or FIG. As shown in the figure, a silicon dioxide mask 21 (or 24), an Al mask 22 (or 25), and a resist mask Re1 (or Re2) are sequentially formed on the substrate from below. When the silicon dioxide mask 21 (or 24) is formed by etching the silicon dioxide film 21x (or 24x), the silicon dioxide film 21 (or 24) has a very large thickness of 3 μm. Time etching is required, and the resist mask Re1 (or Re2) becomes thinner from the outline shown by the broken line to the outline shown by the solid line. However, the Al mask 22 (or 25) is hardly thinned when the silicon dioxide film 21x (or 24x) is etched. This is because the mask (Al mask) for patterning the silicon dioxide mask 21 (or 24), which is a high-temperature ion implantation mask (hard mask), is made of a material having a higher etching selectivity than the silicon dioxide film 21 (or 24). This is because it is configured.

  As a result, the side surface of the silicon dioxide mask 21 (or 24) shows a steep shape with a small inclination from the direction perpendicular to the surface of the substrate, so that high energy ion implantation is performed in the substrate, When the impurity diffusion layers having different conductivity types (in this embodiment, the p-well region 3 and the source region 6) are formed adjacent to each other, a relatively thin portion at the end of the ion implantation mask Therefore, the range in which ions are implanted into the substrate without being blocked is narrowed, and the boundary region between impurity diffusion layers formed in the substrate is reduced. Therefore, it is possible to form a fine impurity diffusion region pattern, and to form a low-loss device up to the theoretical limit of silicon carbide.

  The inclination of the side surface of the ion implantation mask 21 (or 24) from the direction perpendicular to the substrate surface is preferably 60 ° or less, and more preferably 30 ° or less.

  The high temperature ion implantation mask in the present invention preferably retains the function of the ion implantation mask even at a high temperature of 300 ° C. or higher, and more preferably retains the function of the ion implantation mask even at a high temperature of 500 ° C. or higher. preferable.

  In the present embodiment, the high temperature ion implantation mask is composed of a silicon dioxide film that can maintain the function of the ion implantation mask even at a high temperature of 1000 ° C. or higher. As the silicon dioxide film, a film deposited using a method such as plasma CVD, LTO, or HTO can be used. When a plasma TEOS film is used, a silicon dioxide film having a thickness of 3 μm can be grown by CVD for 1 hour. In place of the silicon dioxide film, various oxide films other than the silicon dioxide film, nitride films such as a silicon nitride film, oxynitride films, and polysilicon films may be used.

  Further, a material other than Al, such as Ni, can be used for the metal film for patterning the silicon film or the silicon film to form the high temperature ion implantation mask. In addition, a polysilicon film, a silicon nitride film, or the like can be used instead of the metal film. However, it is preferable that the high temperature ion implantation mask is made of a material that is difficult to be etched, that is, a material having a high etching selectivity with respect to the high temperature ion implantation mask.

  The ion implantation mask forming method of the present invention is not limited to the insulated gate field effect transistor (MISFET) in the above embodiment, but also a bipolar transistor (BJT), a junction field effect transistor (JFET), and a static induction transistor (SIT). , Schottky junction gate field effect transistor (MESFET), insulated gate bipolar transistor (IGBT), single gate type static induction thyristor (SGSITH), and the like.

  The thickness of an ion implantation mask made of an oxide film, a nitride film or the like is generally 1 μm or more, but it is meaningful to apply the present invention when the thickness is 0.5 μm or more. The thickness of the intermediate mask made of a metal film is preferably about 0.1 to 0.3 times that of the ion implantation mask.

  A method for forming an ion implantation mask and a silicon carbide device according to the present invention include a device having impurity diffusion layers of different conductivity types on a silicon carbide substrate, such as a bipolar transistor (BJT), a junction field effect transistor (JFET), or an electrostatic induction. Devices such as transistors (SIT), insulated gate field effect transistors (MISFET), Schottky junction gate field effect transistors (MESFET), insulated gate bipolar transistors (IGBT), single gate static induction thyristors (SGSITH) It can be used when manufacturing these.

It is sectional drawing which shows the structure of accumulation | storage type | mold MISFET using the SiC substrate which concerns on embodiment of this invention, and double injection type MISFET. (A)-(e) is sectional drawing which shows the first half part in the manufacturing process of the double injection type MISFET of embodiment. (A)-(e) is sectional drawing which shows the second half part in the manufacturing process of the double injection type MISFET of embodiment. It is sectional drawing which shows the shape of each mask before the ion implantation in the process shown in FIG.2 (c) or FIG.3 (a).

Explanation of symbols

1 SiC substrate 2 High resistance SiC layer 3 p well region 4 p + contact region 5 channel layer 6 source region 7 gate insulating film 8 source electrode 9 drain electrode 10 gate electrode 11 p ⁺ contact region 21 silicon dioxide mask (ion implantation mask)
21x silicon dioxide film (first film)
22 Al mask (intermediate mask)
22x Al film Re1 Resist mask 24 Ion implantation mask 24x Silicon dioxide film (first film)
25 Intermediate mask 25x Al film Re1 resist mask

Claims (9)

A method for forming an ion implantation mask used in a manufacturing process of a silicon carbide device, comprising:
Depositing a first film made of a material that retains the function of an ion implantation mask at a high temperature of 300 ° C. or higher;
Forming a second film thinner than the first film on the first film (b);
Forming a resist mask having an opening in a portion located above the impurity diffusion layer formation region on the second film;
(D) forming an intermediate mask for patterning the first film by patterning the second film using the resist mask as an etching mask;
And (e) forming an ion implantation mask by patterning the first film using at least the intermediate mask as an etching mask. The method for forming an ion implantation mask according to claim 1,
In the step (e), the ion implantation mask is formed by patterning the first film by dry etching. In the formation method of the ion implantation mask according to claim 1 or 2,
In the step (b), a method of forming an ion implantation mask, wherein a film made of a material smaller than the etching rate of the first film in the step (e) is formed as the second film. In the formation method of the ion implantation mask as described in any one of Claims 1-3,
In the step (a), a method of forming an ion implantation mask, wherein a film made of an oxide or a nitride is formed as the first film. In the formation method of the ion implantation mask as described in any one of Claims 1-4,
In the step (b), a method for forming an ion implantation mask, wherein a metal film is formed as the second film. In the formation method of the ion implantation mask according to claim 5,
In the step (b), an ion implantation mask is formed by forming an Al film as the metal film. The method for forming an ion implantation mask according to claim 1,
In the step (d), the ion implantation mask is formed by patterning the second film by wet etching. In the formation method of the ion implantation mask according to any one of claims 1 to 7,
The method of forming an ion implantation mask, wherein the second film has a thickness sufficient to remain until etching of the first film is completed in the step (d). In a silicon carbide device having at least one ion implantation region,
The silicon carbide device, wherein a distance between a flat portion and a side surface at a bottom surface of the ion implantation region is equal to or less than a depth of the ion implantation region.

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