JP6699826B2 - Optical logic circuit - Google Patents

Description

  The present invention relates to an optical logic circuit that performs a logical operation in an optical circuit or a mixed circuit of an optical circuit and an electric circuit.

  In order to improve the processing speed, current electronic arithmetic circuits are devised so that their chip size and element size are made as small as possible. The reason is that the resistance (R) and the capacitance (C) in the circuit greatly control the propagation of signals, and therefore the only way to increase the operation speed is to reduce the chip size and element size. For this reason, devices are packed in narrow-area logic blocks and cores, and devices such as multi-core/many cores have been devised, but the wiring to connect these cores has a new "delay". And the limit to speeding up the calculation is becoming apparent.

  On the other hand, an optical wiring or an optical pass gate used in optical communication or the like can propagate an optical signal independent of C and R in the wiring path. Further, with the progress of nanophotonics, the energy consumption of the optical gate has been dramatically improved, and the energy cost [J/bit] thereof is about the same level for the CMOS gate and the light. Therefore, various studies have been made on opticalizing communication in and between chips.

  However, in the conventional research, there is a problem that the delay caused by the calculation cannot be solved because the calculation path (critical path) that controls the calculation time of the circuit is not considered. Therefore, in order to fundamentally solve the problem of delay occurring at the operation level, it is necessary to advance not only the optical wiring within the chips or between the chips and the optical gate, but also the opticalization down to the transistor level with finer granularity.

  Here, the connection form in which a signal is input from the electrical control port side of the optical gate is defined as a cascade connection, and the form in which the light propagation paths of the switches are continuously connected is defined as a serial connection. For example, assuming an optoelectronic circuit in which serial connection and cascade connection are mixed, the portion of the cascade connection serves as a boundary between light and electricity, and the optical signal propagating in the circuit at the boundary is once converted into electricity (OE (Optical -Electrical) conversion). Since this conversion is rate-controlled by an electric circuit, a circuit that frequently uses OE conversion has little merit in using light. Therefore, the boundary between light and electricity, that is, the location and number of cascade connections are important points in the circuit configuration. An optical circuit based on a BDD (binary decision diagram) has been proposed as a circuit in which OE conversion is not arranged in the optical propagation path.

For example, Non-Patent Document 1 discloses a configuration of an adder (X+Y arithmetic circuit) in which an OE converter is not arranged in a carry signal path for addition. FIG. 19 shows a full adder composed of 2×2 optical switches. Here, X _i and Y _i are binary signals forming the input signals X and Y of the i-th digit, S _i is a signal indicating the addition result of X _i and Y _i , and C _i is a carry from the (i-1)th digit. The signal, bar C _i, is the negative signal for signal C _i . Further, in FIG. 19, 100a (100a0 to 100a2) and 100c (100c0 to 100c2) are demultiplexers, and 101a (101a0 to 101a2), 101b (101b0 to 101b2), 101c (101c0 to 101c2) are 2×2 optical switches. is there.

In the circuit shown in FIG. 19, the optical switch 101 arranged at each node of a large tree structure (BDD circuit) based on BDD is electrically controlled by the signals X _i and Y _i . As a result, it is not necessary to control each node with the optical signal, and it is possible to execute the operation only by propagating the optical signal to the electrically controlled path.

  A circuit based on BDD has a three-stage configuration including an upper stage (2×2 optical switch 101a), a middle stage (2×2 optical switch 101b), and a lower stage (2×2 optical switch 101c), and a carry calculation ( carry is executed, the negative operation of the carry operation (carry bar) is executed in the lower stage, and the addition (sum) of each digit is executed in the middle stage. The operations of each stage are related to each other. Therefore, the BDD-based circuit has a large number of optical path intersections for connecting the upper, middle, and lower circuits, which complicates the configuration and makes it difficult to realize the circuit configuration. there were.

Tetsuya Asai, Yoshihito Amamiya, Masanori Koshiba, "Photonic Crystal Integrated Device Based on BDD", IEICE General Conference, SC-1-4, 2000

  The present invention has been made to solve the above problems, and an object of the present invention is to provide an optical logic circuit that can achieve both simplification of the circuit configuration and high-speed operation.

The optical logic circuit of the present invention is required for the logical operation according to the plurality of input signals of corresponding bits when performing the logical operation of a plurality of N-bit (N is an integer of 2 or more) input signals. It is to be noted that, in accordance with the first logic circuit for each bit that outputs the propagation signal to the upper bit, the plurality of input signals of the corresponding bit, and the propagation signal from the lower bit, the logical operation for each bit is performed. A second logic circuit for each bit for outputting a result, wherein at least a part of the first and second logic circuits is an optical circuit, and 0, 1 is assigned to different wavelengths of an optical signal passing through the optical circuit. And outputs the propagation signal and the result of the logical operation as an optical signal , and the first logic circuit corresponds to first and second light sources that output lights of different wavelengths. First and second optical gates for respectively controlling passage/cutoff of light from the first and second light sources according to one kind of input signal of the plurality of input signals of the bit to be 1. A wavelength multiplexer that multiplexes lights having different wavelengths output from the second optical gate, and a logic function circuit that outputs a result of a predetermined logic function of the same bits with respect to the plurality of input signals, Depending on the output of the logic function circuit, one of the propagation signal from the lower bit and the negation signal of the propagation signal and the output of the wavelength multiplexer is used as the propagation signal to the higher bit and the A second optical circuit for selectively outputting a negative signal of the propagation signal, wherein the second logic circuit demultiplexes the propagation signal from the lower bit and the negative signal of the propagation signal. And, according to the output of the logic function circuit, one of the propagation signal demultiplexed by the wavelength demultiplexer and the negative signal of the propagation signal is selectively used as a result of the logical operation for each bit. And a fourth optical gate for outputting to .

Further , one configuration example of the optical logic circuit of the present invention is characterized in that the wavelength of the light source used for each different bit is different.
Further, one configuration example of the optical logic circuit of the present invention corresponds to its own bit among the propagation signal from the lower bit and the negation signal of this propagation signal in bits other than the least significant bit and the most significant bit. WDM filter for extracting an optical signal of a wavelength as the propagation signal to its own bit and a negative signal of this propagation signal and inputting it to the wavelength demultiplexer, and inputting signals of other wavelengths to the third optical gate The first and second light sources of bits other than the most significant bit output light in which wavelengths having different numbers of higher bits than their own bits are multiplexed. is there.

Further, the optical logic circuit of the present invention, when performing a logical operation of a plurality of input signals of N bits (N is an integer of 2 or more), performs the logical operation according to the plurality of input signals of corresponding bits. A first logic circuit for each bit that outputs a propagation signal to the higher-order bit, and the logic for each bit according to the plurality of input signals of the corresponding bit and the propagation signal from the lower-order bit. A second logic circuit for each bit that outputs the result of the operation, and at least a part of the first and second logic circuits is an optical circuit, and the optical signals passing through the optical circuit have different wavelengths of 0. , 1 is assigned, and the propagation signal and the result of the logical operation are output as an optical signal, and the first logic circuit includes first and second light sources that output lights of different wavelengths. , Selectively outputting one of the light from the first light source and the light from the second light source in accordance with one kind of input signal of the plurality of input signals of corresponding bits. One optical gate, and in accordance with the plurality of input signals of corresponding bits, one of the propagation signal from the lower bits and the negation signal of the propagation signal, and the output of the first optical gate. A second optical gate selectively outputting the propagated signal to the higher-order bit and a negative signal of the propagated signal, the second logic circuit being responsive to the plurality of input signals of the corresponding bit. , A third optical gate for selectively outputting the propagated signal from the lower bit and a negated signal of the propagated signal to either one of the two output ports.

Further, the optical logic circuit of the present invention, when performing a logical operation of a plurality of input signals of N bits (N is an integer of 2 or more), performs the logical operation according to the plurality of input signals of corresponding bits. A first logic circuit for each bit that outputs a propagation signal to the higher-order bit, and the logic for each bit according to the plurality of input signals of the corresponding bit and the propagation signal from the lower-order bit. A second logic circuit for each bit that outputs the result of the operation, and at least a part of the first and second logic circuits is an optical circuit, and the optical signals passing through the optical circuit have different wavelengths of 0. , 1 is assigned, and the propagation signal and the result of the logical operation are output as an optical signal, and the first logic circuit includes first and second light sources that output lights of different wavelengths. , Selectively outputting one of the light from the first light source and the light from the second light source in accordance with one kind of input signal of the plurality of input signals of corresponding bits. One optical gate, and in accordance with the plurality of input signals of corresponding bits, one of the propagation signal from the lower bits and the negation signal of the propagation signal, and the output of the first optical gate. , The second optical circuit selectively outputting the propagated signal to the higher-order bit and a negative signal of the propagated signal, the second logic circuit including: A wavelength demultiplexer for demultiplexing a negative signal and one of two output ports for transmitting the propagation signal input from the wavelength demultiplexer to the first input port according to the plurality of input signals of corresponding bits. And a third optical gate for selectively outputting to the other of the two output ports a negative signal of the propagation signal input from the wavelength demultiplexer to the second input port. It is characterized by that.
Further, the optical logic circuit of the present invention, when performing a logical operation of a plurality of input signals of N bits (N is an integer of 2 or more), performs the logical operation according to the plurality of input signals of corresponding bits. , A first logic circuit for each bit that outputs a propagation signal to an upper bit and a negation signal of this propagation signal, the plurality of input signals of corresponding bits, the propagation signal from a lower bit, and the propagation A second logic circuit for each bit that outputs the result of the logic operation for each bit in response to a negative signal of the signal, and the first logic circuit includes at least a part of an optical circuit, The propagation signal from the bit and the negative signal of the propagation signal are input, and the propagation signal to the higher-order bit and the negative signal of the propagation signal are output with light of different wavelengths, and the second logic circuit is at least Part of the optical circuit is an optical circuit, and the result of the logical operation is output as an optical signal.

  According to the present invention, in accordance with a plurality of input signals of corresponding bits, a first logic circuit for each bit that outputs a propagation signal to an upper bit, which is necessary for a logical operation, and a plurality of input signals of corresponding bits, An optical logic circuit is configured from a second logic circuit for each bit that outputs the result of the logical operation for each bit according to the propagation signal from the lower bit. According to the present invention, simplification of the circuit configuration can be realized. Further, in the present invention, since the optical gates included in the first and second logic circuits can be opened and closed at once by the input signal, the propagation paths of the optical signals in the first and second logic circuits are determined. It is possible to significantly reduce the time until. Furthermore, since the number of serial connection stages in the first and second logic circuits can be significantly reduced, the operation time can be greatly reduced. The optical logic circuit provided by the present invention has a structure in which opticalization has been advanced to the transistor level, facilitating the fusion of the electric circuit and the optical circuit, and has a strong field of electric circuits (enhanced integration of a huge number of elements and parallel operation). It is possible to achieve both the high-throughput calculation by processing and the specialty of optical circuits (ultra-low latency calculation that completes the calculation at the propagation speed of light while propagating information at the speed of light), and the operating frequency peaks. It is possible to solve the problem of the electric circuit which is going into a state. Further, according to the present invention, by assigning values of 0 and 1 to different wavelengths of the optical signal, the propagation signal to the upper bit and its negation signal can be calculated independently, and the phase of the optical signal is calculated in the calculation process. Need not be strictly controlled. Further, in the present invention, it becomes possible to use a common circuit for the operation of the propagated signal to the upper bit and its negated signal, which simplifies the circuit and reduces the number of switches (optical gates).

  Further, according to the present invention, the first logic circuit is configured to output the first and second light sources which output lights of different wavelengths, and the first logic circuit according to the first input signal of the plurality of input signals of corresponding bits. A first optical gate that selectively outputs one of the light from the light source and the light from the second light source, and a propagation signal from a lower bit in accordance with a plurality of input signals of corresponding bits and It is composed of either a negative signal of this propagation signal or an output of the first optical gate, and a second optical gate which selectively outputs a propagation signal to the upper bit and a negative signal of this propagation signal. By doing so, the logic function circuit can be deleted from the first logic circuit, and the circuit can be simplified.

FIG. 3 is a block diagram showing the configuration of a cascaded-BDD type optical logic circuit. It is a block diagram which shows the structure which employ|adopted the phase modulation system to the optical logic circuit of a cascaded-BDD type. It is a block diagram which shows the structure of the optical logic circuit of this invention. FIG. 3 is a block diagram showing a configuration of one bit of a cascaded-BDD type optical logic circuit. It is a figure which shows the truth table of the structure for 1 bit of the cascaded-BDD type optical logic circuit. FIG. 3 is a block diagram showing a configuration of one bit of a cascaded-BDD type optical logic circuit. It is a block diagram which shows the structure for 1 bit of the optical logic circuit which employ|adopted the phase modulation system to the cascaded-BDD type optical logic circuit. FIG. 3 is a block diagram showing a configuration of one bit of the optical logic circuit according to the first exemplary embodiment of the present invention. It is a figure which shows the wavelength of the optical signal output from the light source in the optical logic circuit which concerns on the 1st Example of this invention. It is a figure explaining the process of the carry signal of the last digit in the 1st example of the present invention. It is a block diagram which shows the structure for 1 bit of the optical logic circuit which concerns on the 2nd Example of this invention. It is a figure explaining the signal which shows the addition result in the 2nd Example of this invention. It is a block diagram which shows the structure for 1 bit of the optical logic circuit which concerns on the 3rd Example of this invention. It is a figure explaining the process of the carry signal of the last digit in the 3rd Example of the present invention. It is a figure explaining the signal which shows the addition result in the 3rd Example of this invention. It is a figure which shows an example of the simulation result of the full adder which cascade-connected the optical logic circuit which concerns on the 3rd Example of this invention for 4 bits. It is a figure which shows the other example of the simulation result of the full adder which cascade-connected the optical logic circuit which concerns on the 3rd Example of this invention for 4 bits. It is a block diagram which shows the structure for 3 bits of the optical logic circuit which concerns on the 4th Example of this invention. It is a block diagram which shows the structure of the conventional BDD type full adder.

[Principle of the Invention]
As a method of simplifying a conventional BDD-based circuit, a method of adopting a Cascaded-BDD type optical logic circuit can be considered. The Cascaded-BDD type optical logic circuit is a circuit that uses an output signal from another BDD circuit as a signal for controlling a switch arranged at a node of the BDD circuit. FIG. 1 shows the configuration of a full adder as an example of a Cascaded-BDD type optical logic circuit. Similar to FIG. 19, 100a (100a0 to 100a2) and 100c (100c0 to 100c2) are demultiplexers, and 101a (101a0 to 101a2), 101b (101b0 to 101b2), 101c (101c0 to 101c2) are 2×2 optical switches. , 102a (102a0 to 102a2), 102b (102b0 to 102b2), 102c (102c0 to 102c2) are XOR (exclusive OR) circuits. In the configuration of FIG. 1, by adopting the XOR circuits 102a to 102c as another BDD circuit, the number of switches included in the carry operation path (C _{i to} C _i+1 ) is reduced by half.

Further, as a method for further simplifying the conventional BDD-based circuit, a phase modulation method can be considered. As shown in FIG. 2, the phase modulation method makes it possible to generate the negation signal bar C _i of the carry signal by phase inversion of the carry signal C _i , and the lower stage of FIG. 1 (XOR circuit 102c and 2×2). The negative operation of the carry operation in the optical switch 101c) is omitted.

The phase modulator 103ai (103a0 to 103a2) in FIG. 2 allows the optical signal from the light source (not shown) to pass through when the optical signal X _i (X _{0 to} X ₂ ) is “1”, and X _i is When it is “0”, the phase of the optical signal from the light source is shifted by π and output. The phase modulator 103bi (103b0 to 103b2) shifts the phase of the optical signal C _i (C _{0 to} C ₂ ) by π when the output of the XOR circuit 102bi (102b0 to 102b2) is “1”, and outputs the signal. When the output of the XOR circuit 102bi is "0", the optical signal C _i is passed as it is.

  As shown in FIG. 2, by combining the Cascaded-BDD and the phase modulation method, the circuit configuration can be simplified and the operation speed can be doubled. However, in the phase modulation method, it is necessary to separately set a strict waveguide length and separately incorporate a phase shifter in order to compensate for the phase rotation other than the phase modulation section incorporated in the switch.

  Therefore, the present invention proposes a simplified circuit configuration that does not require strict phase control. FIG. 3 shows the configuration of the optical logic circuit (full adder) of the present invention. The full adder of FIG. 3 includes a demultiplexer 200a (200a0 to 200aSR2), 2×2 optical switches 201a (201a0 to 201a2), 202a (202a0 to 202a2), 203b (203b0 to 203b2), and a wavelength multiplexer. And 204b (204b0 to 204b2). The 2×2 optical switches 201a and 202a form a first logic circuit, and the 2×2 optical switch 203b forms a second logic circuit.

The branching filter 200ai (i=0, 1, 2) branches the carry signal C _i (propagation signal) from the preceding stage and its negation signal bar C _i into two. The 2×2 optical switch 201ai selects and outputs the light of the wavelength λ _a corresponding to the signal “1” when the signal X _i is “1”, and when the signal X _i is “0”. , The light of wavelength λ _b corresponding to the signal “0” is selected and output.

The 2×2 optical switch 202ai selects the output of the 2×2 optical switch 201ai when the signal X _i and the signal Y _i are both “1” or both “0”, and is a carry signal to the next stage. C _i+1 , bar C _i+1 , and when _one of the signals X _i and Y _i is “1” and the other is “0”, the optical signal C _i , bar from the demultiplexer 200 ai C _i is selected and output as a carry signal C _i+1 and a bar C _i+1 to the next stage.

The 2×2 optical switch 203bi is the amount that is input to the first input port (the upper input port in FIG. 3) when the signal X _i and the signal Y _i are both “1” or both “0”. optical signal C _i from the filter 200Ai, and outputs the bar C _i to the second output port (the lower side of the output port in FIG. 3). At this time, the optical switch 203bi connects the second input port (the lower input port in FIG. 3) and the first output port (the upper output port in FIG. 3). However, the second input port has no input.

Further, the optical switch 203bi outputs the optical signal C from the demultiplexer 200ai to the first input port when one of the signals X _i and Y _i is “1” and the other is “0”. _i , and bar C _i are output to the first output port. At this time, the optical switch 203bi connects the second input port and the second output port. As described above, the second input port has no input.

In the example of FIG. 3, the wavelength multiplexer 204bi is provided for each bit in order to extract the optical signal S _i indicating the addition result of the signals X _i and Y _i of each bit. The wavelength multiplexer 204bi multiplexes optical signals with different wavelengths output from the optical switch 203bi.

In the present invention, the carry signal C _i+1 and its negation signal bar C _i+1 are calculated by wavelength multiplexing, and two kinds of calculations are executed by a common circuit. As a result, the circuit shown in FIG. 3 can realize the same function as in FIG. 2 without phase compensation.

[First Embodiment]
Next, a first embodiment of the present invention will be described. Here, first, the 1-bit configuration of each optical logic circuit of FIGS. 1 and 2 will be described, and then the 1-bit configuration of the optical logic circuit of the present embodiment will be described.

4 is a block diagram showing the configuration of one bit of the cascaded-BDD type optical logic circuit (full adder) shown in FIG. 1, and FIG. 5 is a diagram showing a truth table of the circuit of FIG. In addition, "-" in FIG. 5 indicates that either "0" or "1" may be used.
The logic circuits 301, 303, 307 are circuits that perform operations according to the logic functions f ₁ , f ₂ , and bar f ₂ , respectively. The truth table of the logical functions f ₁ , f ₂ and bar f ₂ is as shown in FIG.

The pass/block type optical gate 302 allows the optical signal from the light source 300 to pass when the output of the logic function f ₂ (logic circuit 303) is “1”, and the output of the logic function f ₂ is “0”. At some time, the light signal from the light source 300 is blocked. The pass/cross type optical gate 304 selects and outputs the optical signal C _i when the output of the logic function f ₁ (logic circuit 301) is “1”, and the output of the logic function f ₁ is “0”. Then, the output of the optical gate 302 is selected and output. The pass/cross type optical gate 305 selects and outputs the optical signal bar C _i when the output of the logical function f ₁ is “1”, and when the output of the logical function f ₁ is “0”. The optical signal C _i is selected and output.

The pass/block type optical gate 308 allows the optical signal from the light source 306 to pass when the output of the negation bar f ₂ (logic circuit 307) of the logic function f ₂ is “1”, and the output of the bar f ₂ is When it is “0”, the optical signal from the light source 306 is cut off. The pass/cross type optical gate 309 selects and outputs the optical signal bar C _i when the output of the logical function f ₁ is “1”, and when the output of the logical function f ₁ is “0”. The output of the optical gate 308 is selected and output.

FIG. 6 is a block diagram showing the configuration of one bit of the cascaded-BDD type optical logic circuit (full adder) shown in FIG. In the circuit of FIG. 6, in the circuit shown in FIG. 4, the operation of the logical function f ₁ (logical circuit 301) is an XOR operation, and instead of the output of the logical function f ₂ , bar f ₂ , X _i , bar X _i Is used as is.

FIG. 7 is a block diagram showing the configuration of one bit of the optical logic circuit (full adder) shown in FIG. The pass/π-shift type phase modulator 401 allows the optical signal from the light source 400 to pass as it is when the signal X _i is “1”, and outputs the light signal from the light source 400 when the signal X _i is “0”. The phase of the optical signal is shifted by π and output. The pass/cross type optical gate 403 selects and outputs the optical signal C _i when the output of the XOR circuit 402 to which the signals X _i and Y _i are input is “1”, and the output of the XOR circuit 402 is output. When it is “0”, the output of the optical gate 401 is selected and output.

Phase modulator 404, the phase of the optical signal C _i to output shifted by π when the output of the XOR circuit 402 is "1", the optical signal C _i when the output of the XOR circuit 402 is "0" Pass through.
That is, in the circuit of FIG. 7, by assigning phases of zero/π to the “0”/“1” signals in the circuit shown in FIG. 6, respectively, the lower circuits (306, 308, 309) in FIG. Omitted. However, as described above, it is necessary to exactly match the phase relationship between the phase of “1” of the light source 400 and Ci (=“0” or “1”).

  FIG. 8 is a block diagram showing the configuration of one bit of the optical logic circuit (full adder) according to this embodiment. In this embodiment and the following embodiments, the addition of input signals will be described as an example of the logical operation. The 1-bit optical logic circuit 1 of the present embodiment includes light sources 10 and 11, pass/block type optical gates 12 and 13, a wavelength multiplexer 14, a demultiplexer 15, and an XOR circuit 16 (logic). Functional circuit), a pass/cross type optical gate 17, a wavelength demultiplexer 18, and a pass/cross type optical gate 19. The light sources 10 and 11, the optical gates 12 and 13, the wavelength multiplexer 14, the XOR circuit 16, and the optical gate 17 constitute a first logic circuit, and the wavelength demultiplexer 18 and the optical gate 19 are the second logical circuit. Constitutes the logic circuit of.

The light source 10 outputs an optical signal of wavelength λ _a corresponding to the signal “1”. The light source 11 outputs an optical signal of wavelength λ _b corresponding to the signal “0”. FIG. 9 is a diagram showing the transmission characteristics of the wavelength multiplexer 14 and the wavelength demultiplexer 18. FIG. 9A is a diagram showing the wavelength characteristic of the upper port, and FIG. 9B is a diagram showing the wavelength characteristic of the lower port.

The pass/block type optical gate 12 allows the optical signal from the light source 10 to pass when the signal X _i (electrical signal) is “1” and transmits the optical signal from the light source 10 when the signal X _i is “0”. Block the optical signal. pass / block type optical gate 13 passes the optical signal from the light source 11 when a negative signal of the signal X _i bar X _i (electrical signal) is "1", the signal bar X _i is "0" At some time, the optical signal from the light source 11 is cut off. The wavelength multiplexer 14 multiplexes optical signals having different wavelengths output from the optical gates 12 and 13.

The branching filter 15 splits the carry signal C _i and bar C _i from the preceding stage into two. The XOR circuit 16 is an electric circuit that performs an XOR operation on the signal X _i (electrical signal) and the signal Y _i (electrical signal). The pass/cross type optical gate 17 selects the optical signal C _i and the bar C _i from the demultiplexer 15 when the output (electrical signal) of the XOR circuit 16 is “1”, and outputs the signal to the next stage. The carry signal C _i+1 and the bar C _i+1 are output, and when the output of the XOR circuit 16 is “0”, the output of the wavelength multiplexer 14 is selected and the carry signal C to the next stage is selected. Output as _i+1 and bar C _i+1 .

The branching ratio of the demultiplexer 15 may not be 1:1. Since the optical signal Si side indicates the addition result, it is sufficient that the light can be received by the optical receiver. On the other hand, the path on the C _i side, which is a carry signal, has an optical path continuous for the number of digits and is branched by the optical demultiplexer 15 at each digit, so that a high light intensity is required. Therefore, it is desirable to increase the branching ratio on the carry signal side. Further, the branching ratio may be changed for each digit. For example, since the carry signal becomes weaker in the later digits, the branching ratio may be gradually brought closer to 1:1.

On the other hand, the wavelength demultiplexer 18, an optical signal C _i, the bar C _i to the optical signal bar C _i and demultiplexed optical signals C _i and the wavelength lambda _b of the wavelength lambda _a from the demultiplexer 15, the optical signal C _i is input to the first input port (upper input port in FIG. 8) of the pass/cross type optical gate 19, and the optical signal bar C _i is input to the second input port (lower part in FIG. 8) of the optical gate 19. Input port). The optical gate 19 selects the optical signal bar C _i when the output of the XOR circuit 16 is “1” and outputs it as an optical signal S _i indicating the addition result of X _i and Y _i . When the output is “0”, the optical signal C _i is selected and output as the optical signal S _i .

When configuring the full adder, the carry signal C _i+1 and bar C _i+1 of the optical logic circuit 1 of FIG. 8 are input to the optical logic circuit 1 of the next stage, as in FIG. If the optical logic circuits 1 for N bits (N is an integer of 2 or more) are cascade-connected, an N-bit full adder can be realized.

Note that the last digit of the carry signal, the wavelength filter 20 as shown in provided 10, the optical signal C _{i + 1,} the optical signal bar C _{i + 1} side of the wavelength lambda _b of the bar C _{i + 1} It is necessary to generate a carry signal for the last digit by removing it with the wavelength filter 20.

  In this embodiment, like the phase modulation method, the circuits (306, 308, 309) in the lower stage of the cascaded-BDD type optical logic circuit of FIG. 6 can be omitted. Further, in the present embodiment, unlike the phase modulation method, since "0"/"1" is not assigned to the phase of the optical signal shown in FIG. 7, a strict phase like the phase modulation method shown in FIG. No need for control.

[Second Embodiment]
Next, a second embodiment of the present invention will be described. FIG. 11 is a block diagram showing the configuration of one bit of the optical logic circuit (full adder) according to this embodiment. The 1-bit optical logic circuit 2 of this embodiment includes light sources 21 and 22, a pass/cross type optical gate 23, a demultiplexer 24, and pass/cross type optical gates 25 and 26. It The light sources 21 and 22 and the optical gates 23 and 25 form a first logic circuit, and the optical gate 26 forms a second logic circuit.

The light source 21 outputs an optical signal of wavelength λ _a corresponding to the signal “1”. The light source 22 outputs an optical signal of wavelength λ _b corresponding to the signal “0”. The pass/cross type optical gate 23 selects and outputs the optical signal from the light source 21 when the signal X _i (electrical signal) is “1” and outputs the light signal when the signal X _i is “0”. The optical signal from 22 is selected and output.

The branching filter 24 branches the carry signal C _i and bar C _i from the preceding stage into two. The pass/cross type optical gate 25 selects the output of the optical gate 23 when both the signal X _i (electrical signal) and the signal Y _i (electrical signal) are “1” or both “0”, The carry signal C _i+1 and the bar C _i+1 to the next stage are output, and when _one of the signals X _i and Y _i is “1” and the other is “0”, the duplexer 24 outputs the signal. optical signal C _i, using the bar C _i, the carry signal C _{i + 1} of the next stage, and outputs it as a bar C _{i + 1.}

The pass/cross type optical gate 26 is input to the first input port (the upper input port in FIG. 11) when the signals X _i and Y _i are both “1” or both “0”. that the optical signal C _i from the demultiplexer 24, and outputs the bar C _i to the second output port (the lower side of the output port in FIG. 11). At this time, the optical gate 26 connects the second input port (the lower input port in FIG. 11) and the first output port (the upper output port in FIG. 11). However, in this embodiment, the second input port has no input.

The optical gate 26 receives the optical signal C from the demultiplexer 24 that is input to the first input port when one of the signals X _i and Y _i is “1” and the other is “0”. _i , and bar C _i are output to the first output port. At this time, the optical gate 26 connects the second input port and the second output port. As described above, the second input port has no input.

When the full adder is configured, the carry signal C _i+1 and the bar C _i+1 of the optical logic circuit 2 of FIG. 11 are input to the optical logic circuit 2 of the next stage as in the case of FIG. An N-bit full adder can be realized by connecting N-bit optical logic circuits 2 in cascade.

The last digit of the carry signal, a wavelength filter provided in the same manner as FIG. 10, removed by the optical signal C _{i + 1,} a wavelength filter optical signal bar C _{i + 1} side of the wavelength lambda _b of the bar C _{i + 1} Therefore, it is necessary to generate a carry signal for the last digit.

Further, in the present embodiment, it is necessary to provide the wavelength multiplexer 27 (wavelength filter) for each bit in order to extract the optical signal S _i indicating the addition result of the signals X _i and Y _i of each bit. The wavelength multiplexer 27 multiplexes optical signals with different wavelengths output from the optical gate 26.

Specifically, the wavelength multiplexer 27 does not pass the optical signal of wavelength λ _a among the optical signals output from the first output port (upper output port of FIG. 11) of the optical gate 26, and Pass the optical signal of λ _b . The wavelength multiplexer 27, without passing the optical signal of the wavelength lambda _b of the optical signal output from the second output port of the optical gate 26 (the lower side of the output port in FIG. 11), the wavelength lambda _a Pass the optical signal of. In this way, the optical signal S _i is generated. As shown in FIG. 12, the optical signal S _i of the present embodiment is a signal representing “0”/“1” in light intensity, and when the addition result of the signals X _i and Y _i is “0”, the light intensity is Zero level.

  The configuration of this embodiment is obtained by simplifying the circuit of the first embodiment by the following three methods (I) to (III).

(I) In FIG. 8, the switches where the optical gates 12 and 13 are controlled by the signals X _i and bars X _i are changed to pass/cross type optical gates 23 which operate according to the signals X _i . Thus, it is possible to omit the wavelength multiplexer 14, to shorten signal C _i, the path length of the bar C _i, it is possible to improve the calculation speed.

(II) From the method of inputting the signal to the pass/cross type optical gate 19 in FIG. 8 by dividing the signal into upper and lower ports by the wavelength demultiplexer 18, the wavelength at the output side of the pass/cross type optical gate 26 Change to the method of selective multiplexing. Considering the need to integrate the addition optical gate in the same chip as other switches, the wavelength demultiplexer 18 needs to be integrated in the chip in the configuration of FIG. On the other hand, in the configuration of FIG. 11, it is possible to perform the calculation using the wavelength multiplexer 27 (wavelength filter) arranged outside the chip, and it is possible to further simplify the manufacturing of the chip. Become.

(III) By changing the pass/cross type optical gates 304, 403, and 17 used in FIGS. 6, 7, and 8 to the optical gate 25 having two control inputs from one control input, for cascaded-BDD The XOR circuits 301, 402, and 16 are omitted. Application to Figure 7 of this approach, the signal C _i, result in the expansion phase shifter in the path of the bar C _i, is considered to be unsuitable in terms of operation speed. On the other hand, in the configuration of the present embodiment in which “0”/“1” is not assigned to the phase of the optical signal, it is not necessary to add a phase shifter, so that the high speed of the cascaded-BDD is maintained and the XOR circuit is omitted Is possible.

[Third Embodiment]
Next, a third embodiment of the present invention will be described. FIG. 13 is a block diagram showing the configuration of one bit of the optical logic circuit (full adder) according to this embodiment. As described above, in the second embodiment, the methods (I) to (III) are applied to the circuit of the first embodiment shown in FIG. 8, and this embodiment is the first embodiment. The method of (I) and (III) is applied to the circuit of. In this embodiment, a signal whose light intensity is not zero can be used as a signal representing "0" of the output S _i .

  The 1-bit optical logic circuit 3 of the present embodiment includes light sources 30 and 31, a pass/cross type optical gate 32, a demultiplexer 33, a pass/cross type optical gate 34, and a wavelength demultiplexer. 35 and a pass/cross type optical gate 36. The light sources 30 and 31 and the optical gates 32 and 34 form a first logic circuit, and the wavelength demultiplexer 35 and the optical gate 36 form a second logic circuit.

The light source 30 outputs an optical signal of wavelength λ _a corresponding to the signal “1”. The light source 31 outputs an optical signal of wavelength λ _b corresponding to the signal “0”. The pass/cross type optical gate 32 selects and outputs the optical signal from the light source 30 when the signal X _i (electrical signal) is “1” and outputs the light source when the signal X _i is “0”. The optical signal from 31 is selected and output.

The branching filter 33 branches the carry signal C _i and bar C _i from the preceding stage into two. The pass/cross type optical gate 34 selects the output of the optical gate 32 when both the signal X _i (electrical signal) and the signal Y _i (electrical signal) are “1” or both “0”, Output as carry signal C _i+1 and bar C _i+1 to the next stage, and when _one of signal X _i and signal Y _i is “1” and the other is “0”, branching filter 33 outputs optical signal C _i, using the bar C _i, the carry signal C _{i + 1} of the next stage, and outputs it as a bar C _{i + 1.}

Wavelength demultiplexer 35 the optical signal C _i, demultiplexed optical signal bar C _i of the bar C _i of wavelength lambda _a light signal C _i and the wavelength lambda _b from the demultiplexer 33, the optical signal C _i Is input to the first input port (upper input port in FIG. 13) of the pass/cross type optical gate 36, and the optical signal bar C _i is input to the second input port (lower side in FIG. 13) of the optical gate 36. Input port).

The pass/cross type optical gate 36 outputs the optical signal C _i input to the first input port to the second when the signal X _i and the signal Y _i are both “1” or both “0”. The optical signal bar C _i which is output to the output port (the lower output port in FIG. 13) and is input to the second input port is output to the first output port (the upper output port in FIG. 13). Further, the optical gate 36 outputs the optical signal C _i input to the first input port to the first output when one of the signals X _i and Y _i is “1” and the other is “0”. The optical signal bar C _i output to the port and input to the second input port is output to the second output port.

When the full adder is configured, the carry signal C _i+1 and bar C _i+1 of the optical logic circuit 3 of FIG. 13 are input to the optical logic circuit 3 of the next stage, as in FIG. An N-bit full adder can be realized by connecting N-bit optical logic circuits 3 in cascade.

For the carry signal of the final digit, it is necessary to provide a wavelength demultiplexer 40 (wavelength filter), photodiodes 41 and 42, and an adder/subtractor 43 as shown in FIG.
Wavelength demultiplexer 40, the carry signal C _{i + 1,} is branched into an optical signal C _{i + 1} bar C _{i 1} the wavelength lambda _{b +} optical signal bar C _{i + 1} and the wavelength lambda _a.

The photodiode 41 converts the optical signal bar C _i+1 into an electric signal. The photodiode 42 converts the optical signal C _i+1 into an electric signal. The adder/subtractor 43 adds the signal obtained by inverting the polarity of the output signal of the photodiode 41 and the output signal of the photodiode 42. In this way, it is possible to generate an electric signal in which the carry signal of the last digit is differentially received.

Further, in this embodiment, in order to take out light signals S _i indicating the addition result of the signals X _i and Y _i for each bit is converted into an electric signal, a photodiode 37, 38 and subtracter 39. Differential It is necessary to provide a detection type receiver for each bit.

  The photodiode 37 converts an optical signal output from the first output port (upper output port in FIG. 13) of the optical gate 36 into an electric signal. The photodiode 38 converts the optical signal output from the second output port (the lower output port in FIG. 13) of the optical gate 36 into an electric signal. The adder/subtractor 39 adds the signal obtained by inverting the polarity of the output signal of the photodiode 37 and the output signal of the photodiode 38.

Thus, by installing the differential detection type receiver for each bit, the difference in the intensity level of the "0"/"1" signals can be set to double, so that the signal detection accuracy can be improved. .. That is, in the signal obtained by converting the optical signal S _i of this embodiment into an electric signal, as shown in FIG. 15, the signal representing “1” has a positive polarity and the signal representing “0” has a negative polarity.

  The selection of (I) pass/block type, pass/cross type, (III) 1 control input type, 2 control input type, etc. may be selected depending on the performance and size of the switch.

FIG. 16 is a diagram showing a simulation result of a 4-bit full adder in which the optical logic circuit 3 shown in FIG. 13 is cascade-connected for 4 bits, and is a result of adding a 4-bit signal X _i and a 4-bit Y _i. FIG. Here, it is assumed that the input signals (X _i , Y _i ) are input in parallel to all the switches at intervals of 10 GHz, and the ON/OFF switching time of the switches is set to 5 ps. 16 shows an output signal S _i under the assumption of an ideal state in which the in-circuit optical propagation time per optical logic circuit 3 is zero, and out1 indicates the in-circuit optical propagation time of 2.5 ps (1 The output signal S _i when the element length per one optical logic circuit 3 is 250 μm) is shown.

In any of the light propagation times, the correct addition operation result S _i according to the input (X _i , Y _i ) is output. However, in the case where the optical propagation time in the circuit is not zero (out1), the timing of the electrical signal controlling the switch and the timing of the optical signal input to the switch are different, so a spike-like signal is output at the clock cycle of the electrical signal. Has been done.

A spike-like signal due to propagation delay causes a calculation error, so it is necessary to devise such as removing the spike during the time period when the signal is received. Alternatively, the light source may be cut off at this timing. For example, when the light source light supplied from the light sources 30 and 31 of FIG. 13 is not CW (Continuous Wave) light but RZ (Return to Zero) signal light matched to the clock of the electric signal, the output of the 4-bit full adder The signal S _i is shown in FIG. Here, the above-mentioned optical propagation time in the circuit is set to a larger value of 5 ps (corresponding to an element length of 500 μm per one optical logic circuit 3), but the spike-shaped signal is sufficiently removed.

  Further, the maximum value of the calculation delay per digit corresponds to this optical propagation time in the circuit, but considering that the calculation time per digit in the CMOS circuit is about 20 ps, even with the size of the device length of 500 μm. It has achieved a sufficiently high calculation speed. By using the nanophotonics technology capable of shortening the length to several tens of μm, it is possible to realize further speedup.

[Fourth Embodiment]
In the first embodiment, the wavelength of the light source used for each different bit may be different. FIG. 18 is a block diagram showing the configuration of N=3 bits of the optical logic circuit (full adder) according to this embodiment, where the lowest digit is i=1. The light source 50-1 in the optical logic circuit 4-1 of the first bit outputs an optical signal in which (N-1) different wavelengths λ ₂ ,..., λ _N corresponding to the signal “1” are multiplexed. Output. The light source 51-1 outputs an optical signal in which (N−1) different wavelengths λ ₂ ′,..., λ _N ′ corresponding to the signal “0” are multiplexed. The wavelengths λ ₂ ,..., λ _N correspond to the above-mentioned wavelength λ _a extended to (N−1) bits, and the wavelengths λ ₂ ′,..., λ _N ′ have the above-mentioned wavelength λ _b. Corresponds to an extension of (N-1) bits. These λ ₂ ,..., λ _N , λ ₂ ′,..., λ _N ′ are all different wavelengths.

  The operations of the pass/block type optical gates 12-1 and 13-1, the wavelength multiplexer 14-1, the XOR circuit 16-1, and the pass/cross type optical gate 17-1 are the same as those of the first embodiment. It is the same as the optical gates 12 and 13, the wavelength multiplexer 14, the XOR circuit 16, and the optical gate 17.

On the other hand, the light source 52-1 outputs the optical signal of wavelength lambda ₁ 'corresponding to the carry signal bar C _1. The wavelength lambda ₁ 'corresponds to the wavelength lambda _b. Here, the optical signal corresponding to C ₁ is not used. These settings mean that the carry signal to the least significant digit is zero.
The operations of the wavelength demultiplexer 18-1 and the pass/cross type optical gate 19-1 are the same as those of the wavelength demultiplexer 18 and the optical gate 19 of the first embodiment, respectively.

Next, in the light source 50-2 in the optical logic circuit 4-2 of the second bit, (N-2) different wavelengths λ ₃ ,..., λ _N corresponding to the signal “1” are multiplexed. Output an optical signal. The light source 51-2 outputs an optical signal in which (N-2) different wavelengths λ ₃ ′,..., λ _N ′ corresponding to the signal “0” are multiplexed. However, in this embodiment, N=3.

Here, the propagation signal output from the first bit of the optical gate 17-1 of the optical logic circuits 4-1, a plurality of wavelengths _{λ 2, ···, λ N,} λ 2 ', ···, λ N 'Is a multiplexed optical signal.
Therefore, the WDM (Wavelength Division Multiplexing) filter 53-2 in the second-bit optical logic circuit 4-2 corresponds to its own bit among the propagation signals output from the lower-order optical logic circuit 4-1. wavelength lambda _2, lambda light signal of ₂ ', the carry signal C ₂ from the lower bits, and inputted to the wavelength demultiplexer 18-2 taken out as a bar C _2, other wavelengths lambda _3, · · ·, lambda The optical signals of _N , λ ₃ ′,..., λ _N ′ are passed as they are and input to the optical gate 17-2.

  The operations of the pass/block type optical gates 12-2 and 13-2, the wavelength multiplexer 14-2, the XOR circuit 16-2, and the pass/cross type optical gate 17-2 are the same as those of the first embodiment. It is the same as the optical gates 12 and 13, the wavelength multiplexer 14, the XOR circuit 16, and the optical gate 17. The operations of the wavelength demultiplexer 18-2 and the pass/cross type optical gate 19-2 are the same as those of the wavelength demultiplexer 18 and the optical gate 19 of the first embodiment, respectively.

  Next, the operation of the XOR circuit 16-3 in the optical logic circuit 4-3 of the 3rd bit of the most significant bit is similar to that of the XOR circuit 16 of the first embodiment. In this most significant bit, the pass/cross type optical gate 17 is unnecessary.

The propagation signal output from the optical gate 17-2 of the second-bit optical logic circuit 4-2 has a plurality of wavelengths λ ₃ ,..., λ _N , λ ₃ ′,..., λ _N ′ multiplexed. It is the optical signal which was made. However, in this embodiment, since N=3, it is not necessary to use the WDM filter as in the second bit, and the optical signals of the wavelengths λ ₃ and λ ₃ ′ corresponding to the optical logic circuit 4-3 of the third bit are transmitted. , the carry signal C ₃ from the lower bits and is inputted as a bar C ₃ to wavelength demultiplexer 18-3.

  The operations of the wavelength demultiplexer 18-3 and the pass/cross type optical gate 19-3 are the same as those of the wavelength demultiplexer 18 and the optical gate 19 of the first embodiment, respectively.

In this way, a full adder similar to that of the first embodiment can be realized. In the optical logic circuit 4 of bits other than the most significant bit, the light source 50 has different wavelengths λ of the number M of bits higher than its own bit i (M is an integer of 1 or more and N or less, M=N−i). It is only necessary to output an optical signal in which _i ,..., λ _N are multiplexed, and the light source 51 may output an optical signal in which a number M of different wavelengths λ _i ′,..., λ _N ′ is multiplexed. Good.

In the optical logic circuit 4 for bits other than the least significant bit and the most significant bit, the WDM filter 53 is provided instead of the demultiplexer 15 of the first embodiment, and the own bit of the propagation signals from the lower bits is provided. The optical signals of the wavelengths λ _i and λ i'corresponding to _i are extracted as a carry signal from the lower bit (i-1) to its own bit i and input to the wavelength demultiplexer 18, and the optical signals of other wavelengths are output. The signal may be input to the optical gate 17.

In the optical logic circuit 4 of the least significant bit, the light source 52 for outputting the optical signal of the wavelength λ _i ′ corresponding to the carry signal C _i =“0” for the bit i of its own may be provided.
In the optical logic circuit 4 for the most significant bit, the carry signal from the least significant bit may be input to the wavelength demultiplexer 18 as it is. When the output S _i of the most significant bit is the final carry value, the inputs X _i and Y _i to the optical logic circuit 4 of the most significant bit are both zero. In this case, therefore, the optical logic circuit of the most significant bit is used. 4 may be replaced with the circuit of FIG.
According to the present embodiment, it is possible to reduce the power branch loss of the carry signal.

  INDUSTRIAL APPLICABILITY The present invention can be applied to logical operations performed in an optical circuit or a mixed circuit of an optical circuit and an electric circuit.

  1, 2, 3, 4,... Optical logic circuit, 10, 11, 12, 22, 30, 31, 50 to 52... Light source, 12, 13, 17, 19, 23, 25, 26, 32, 34, 36... Optical gate, 14, 27... Wavelength multiplexer, 15, 24, 33... Demultiplexer, 16... XOR circuit, 18, 35, 40... Wavelength demultiplexer, 20... Wavelength filter, 37, 38, 41, 42 ... Photodiodes, 39, 43... Adder/subtractor, 53... WDM filter.

Claims (6)

When a logical operation is performed on a plurality of input signals each having N bits (N is an integer of 2 or more), a propagation signal to an upper bit necessary for the logical operation according to the plurality of input signals of corresponding bits. A first logic circuit for each bit that outputs
A second logic circuit for each bit that outputs a result of the logical operation for each bit in response to the plurality of input signals of corresponding bits and the propagation signal from the lower bit,
At least a part of the first and second logic circuits is an optical circuit, and values of 0 and 1 are assigned to different wavelengths of an optical signal passing through the optical circuit, and the propagation signal and the result of the logical operation are assigned to each other. It outputs as an optical signal ,
The first logic circuit is
First and second light sources that output light of different wavelengths,
First and second optical gates that respectively control passage/cutoff of light from the first and second light sources according to one kind of input signal of the plurality of input signals of corresponding bits,
A wavelength multiplexer that multiplexes lights of different wavelengths output from the first and second optical gates,
A logic function circuit that outputs the result of a predetermined logic function of the same bits for the plurality of input signals;
Depending on the output of the logic function circuit, one of the propagation signal from the lower bit and the negation signal of the propagation signal and the output of the wavelength multiplexer is used as the propagation signal to the higher bit and the A third optical gate that selectively outputs a negative signal of the propagation signal,
The second logic circuit is
A wavelength demultiplexer that demultiplexes the propagation signal from the lower bit and a negative signal of this propagation signal,
Depending on the output of the logic function circuit, either one of the propagation signal demultiplexed by the wavelength demultiplexer and a negative signal of the propagation signal is selectively output as a result of the logical operation for each bit. And a fourth optical gate for controlling the optical logic circuit. The optical logic circuit according to claim 1 ,
An optical logic circuit, wherein the wavelength of the light source used for each different bit is different. The optical logic circuit according to claim 2 ,
In bits other than the least significant bit and the most significant bit, of the propagation signal from the lower bit and the negation signal of this propagation signal, the optical signal of the wavelength corresponding to its own bit is the propagation signal to its own bit. And a WDM filter that takes out as a negative signal of this propagation signal and inputs it to the wavelength demultiplexer, and inputs signals of other wavelengths to the third optical gate,
An optical logic circuit characterized in that the first and second light sources of bits other than the most significant bit output lights in which wavelengths having different numbers of higher bits than their own bits are multiplexed. When a logical operation is performed on a plurality of input signals each having N bits (N is an integer of 2 or more), a propagation signal to an upper bit necessary for the logical operation according to the plurality of input signals of corresponding bits. A first logic circuit for each bit that outputs
A second logic circuit for each bit that outputs a result of the logical operation for each bit in response to the plurality of input signals of corresponding bits and the propagation signal from the lower bit,
At least a part of the first and second logic circuits is an optical circuit, and values of 0 and 1 are assigned to different wavelengths of an optical signal passing through the optical circuit, and the propagation signal and the result of the logical operation are assigned to each other. It outputs as an optical signal,
The first logic circuit is
First and second light sources that output light of different wavelengths,
A first selectively outputting either one of the light from the first light source and the light from the second light source according to one kind of input signal of the plurality of input signals of corresponding bits; With the optical gate of
Depending on the plurality of input signals of corresponding bits, one of the propagation signal from the lower bit and the negative signal of the propagation signal and the output of the first optical gate is transferred to the higher bit. A propagation signal and a second optical gate that selectively outputs a negative signal of the propagation signal,
The second logic circuit is
A third optical gate for selectively outputting the propagation signal from the lower bit and a negative signal of the propagation signal to either one of the two output ports according to the plurality of input signals of corresponding bits. An optical logic circuit characterized by including. When a logical operation is performed on a plurality of input signals each having N bits (N is an integer of 2 or more), a propagation signal to an upper bit necessary for the logical operation according to the plurality of input signals of corresponding bits. A first logic circuit for each bit that outputs
A second logic circuit for each bit that outputs a result of the logical operation for each bit in response to the plurality of input signals of corresponding bits and the propagation signal from the lower bit,
At least a part of the first and second logic circuits is an optical circuit, and values of 0 and 1 are assigned to different wavelengths of an optical signal passing through the optical circuit, and the propagation signal and the result of the logical operation are assigned to each other. It outputs as an optical signal,
The first logic circuit is
First and second light sources that output light of different wavelengths,
A first selectively outputting either one of the light from the first light source and the light from the second light source according to one kind of input signal of the plurality of input signals of corresponding bits; With the optical gate of
Depending on the plurality of input signals of corresponding bits, one of the propagation signal from the lower bit and the negative signal of the propagation signal and the output of the first optical gate is transferred to the higher bit. A propagation signal and a second optical gate that selectively outputs a negative signal of the propagation signal,
The second logic circuit is
A wavelength demultiplexer for demultiplexing the propagation signal from the lower bit and a negative signal of this propagation signal,
The wavelength demultiplexer is configured to selectively output the propagation signal input from the wavelength demultiplexer to the first input port to one of two output ports in response to the plurality of input signals of corresponding bits. And a third optical gate for selectively outputting a negation signal of the propagation signal input to the second input port from the third optical gate to the other of the two output ports. When a logical operation is performed on a plurality of input signals each having N bits (N is an integer of 2 or more), a propagation signal to an upper bit necessary for the logical operation according to the plurality of input signals of corresponding bits. And a first logic circuit for each bit that outputs a negative signal of this propagation signal,
A second logic circuit for each bit that outputs the result of the logical operation for each bit in response to the plurality of input signals of corresponding bits, the propagation signal from the lower bit, and the negative signal of the propagation signal. Prepare,
At least a part of the first logic circuit is an optical circuit, and the propagation signal from the lower bit and a negative signal of this propagation signal are input, Output with different wavelengths of light,
An optical logic circuit, wherein at least a part of the second logic circuit is an optical circuit, and the result of the logical operation is output as an optical signal.