JP6536959B2 - Optical logic circuit and adder - Google Patents

Description

  The present invention relates to an optical logic circuit that performs logical operations with an optical circuit or a mixing circuit of an optical circuit and an electrical circuit, and an adder that is an example of the optical logic circuit.

  In order to improve the processing speed of the present electronic arithmetic circuit, it is devised to reduce the chip size and the element size to the limit. The reason is that the resistance (R) and the capacitance (C) in the circuit greatly limit the signal propagation, and the only way to increase the operation speed is to reduce the chip size and the element size. Therefore, devices are packed into logic blocks and cores with a small area, and multi-core (many-core) and many-core (many cores) etc. are devised, but the wiring for connecting those cores is a new "delay" Limits to speeding up operations.

  On the other hand, an optical wiring or an optical path gate used in optical communication can propagate an optical signal independently of C and R in the wiring path. In addition, with the development of nanophotonics, the energy consumption of the optical gate (optical path gate) is dramatically improved, and the energy cost [J / bit] is about the same as that of the CMOS gate. For this reason, various studies have been made to optimize communication within and between chips.

FIG. 13 is a diagram for explaining switching energy per bit (= energy cost [J / bit]). In the case of a CMOS gate, it is assumed to be 10 ⁻¹⁵ J / bit or less (including wires) (non- Patent Document 1). On the other hand, the energy cost of an optical gate of nanophotonics has been realized on the order of 10 ^-15 J / bit, and the energy cost is about the same as that of a CMOS gate (see Non-Patent Document 2). Moreover, the light gate of nano photonics is advantageous also in the aspect of shortening (refer nonpatent literature 5 and 6).

  An operation process in a configuration in which optical path gates are combined will be described. By connecting 2 × 1 light path gates in a tree, a circuit can be configured to reproduce a look up table (LUT) for an n-digit input as shown in FIG. 14 (FIG. 15A). . The example of FIG. 14 and FIG. 15 (A) represents the case of n = 3.

Reference numerals 11-1 to 11-7 in FIG. 15A denote optical path gates. Each of the optical path gates 11-1 to 11-7 selects one light path (the upper light path in the example of FIG. 15A) when the gate input is "1", and the gate input is "0". And select the other light path (lower light path). This path selection operation is the same in FIG. 3, FIG. 7, FIG. 8, FIG. 10 (FIG. 11 selects the opposite path). 1 stage optical pass gate 11-1 to 11-4 operates in response to the gate input C _i, the light pass gates 11 - 5 and 11 - 6 in the second stage is operated in response to the gate input X _i, 3-stage eye light pass gate 11-7 operates in response to the gate input Y _i. FIG. 15B shows an equivalent circuit of one optical pass gate.

  The logic block 10 shown in FIG. 15A is for outputting an optical signal of "0" or "1" for all combinations for n-digit input, and all operations for n-digit input. To do. The operation process in such a configuration has the following three stages.

The first step is the preparation of the answer. When a tree structure is configured using 2 × 1 optical path gates, 2 ^ n answers (1 bit of “0” or “1”) are prepared in advance for n inputs. In the electric circuit, this answer is stored in the memory, and in the case of the optical circuit, the light source 101 is placed at the answer of "1". For example, the logic block 10 in FIG. 15A is a circuit that performs the operation of C _{i +1} .

  The second stage is the construction of the output path. In the n-tiered tree structure, the same switch operation is performed simultaneously in all tiers in the same tier. In this way, the construction of the path does not depend on the number of switches, and is completed in the switching time of one switch.

For example, in the example of FIG. 15A, when the signal (C _i , X _i , Y _i ) = (1, 1, 0) is input, the optical pass gates 11-1 to 11-4 and 2 of the first stage are provided. The stage optical pass gates 11-5 and 11-6 are switched to the upper side, the third stage optical pass gate 11-7 is switched to the lower side, and a path indicated by 14 is constructed. The equivalent circuit of the output path at this time is shown as shown in FIG.

  The third step is the output of the answer. Output a 1-bit signal prepared in advance through the constructed path. In the case of an electric circuit, the operations of the first and second stages can be realized very easily. In other words, a huge memory switch may be used to store 2 ^ n answers, and a path may be constructed with a switching time of about 10 ps.

  However, in the case of an electrical circuit, the third stage process is very difficult. That is, as shown in FIG. 16, since C and R of n transistors 12 are connected, the response speed of the path is degraded by n ^ 2. Therefore, in the electric circuit, connections as shown in FIG. 16 are used only when n <4 to 6.

  There are several proposals for making such circuits optically, that is, combining optical path gates like CMOS gates to construct a logic block (see Patent Document 1, Non-Patent Document 3, and Non-Patent Document 4). .

JP-A-4-299733

Rodney S. Tucker and Kerry Hinton, "Energy Consumption and Energy Density in Optical and Electronic Signal Processing", IEEE Photonics Journal, Volume 3, Number 5, October 2011, pp. 821 Koji Takeda et al., “Few-fJ / bit data transmissions using directly modulated lambda-scale embedded active region photonic-crystal lasers”, Nature Photonics 7, pp. 569-575, 2013 James Hardy et al., "Optic inspired logic architecture", OPTICS EXPRESS, Vol. 15, No. 1, pp. 150-165, 2007 Qianfan Xu et al., “Reconfigurable optical directed-logic circuits using microresonator-based optical switches”, OPTICS EXPRESS, Vol. 19, No. 6, pp. 5244-5259, 2011 Noritsugu Yamamoto et al., "Photonic crystal directional coupler switch with small switching length and wide bandwidth", OPTICS EXPRESS, Vol. 14, No. 3, pp. 1223-1229, 2006 Kengo Nozaki et al., "All-optical switching for 10-Gb / s packet data by using an ultralow-power optical bistability of photonic-crystal nanocavities", OPTICS EXPRESS, Vol. 23, No. 23, pp. 30379-30392 , 2015

  In the prior art shown in the above-mentioned documents, there are proposed a technology for converting communication in a chip or between chips and a technology for converting a logic block. However, there has been a problem that there is no consideration to the operation path (critical path) which limits the operation time of the circuit, and the delay caused by the operation can not be solved.

  The present invention has been made to solve the above-mentioned problems, and the problem of delay occurring at the operation level is advanced not only within the chip and between the chips and between the chips, but also with finer particle sizes and progressing to the transistor level. It is an object of the present invention to provide an optical logic circuit and an adder that can solve the problem from the beginning. In the present invention, the calculation speed is dramatically improved by converting the critical path that limits the calculation in the electronic chip into an optical signal, rebuilding the path to a configuration suitable for the optical device, and shortening the path length. .

The optical logic circuit according to the present invention comprises: first operation means for outputting the result of desired logical operation of a plurality of bit signals X and a plurality of bit signals Y for each bit; and each bit in the first operation means And second control means for outputting the propagation signal to the upper bits for each bit, which is necessary for the logical operation of the second control bit, and control signals for controlling the first and second control means based on the signals X and Y A fourth operation means for outputting each time, and a fourth operation for inputting the result of the logical operation for each bit of the signals X and Y, which is different from the logical operation of the first operation means, to the second operation means And each of the second arithmetic means includes one optical path gate for each bit configuration, each optical path gate is connected in series, and each optical path gate is operated by the third arithmetic means. Lower bits according to the corresponding bit control signal It is characterized in that the propagating and selecting one of the transmission signal and the fourth of the corresponding bit of the operation result calculated by the calculating means from the light pass gate to the upper bits.

In one configuration example of the optical logic circuit of the present invention, the optical pass gate is a nano photonics optical gate.
In one configuration example of the optical logic circuit of the present invention, all of the first, second, third and fourth arithmetic means are optical circuits.
In one configuration example of the optical logic circuit according to the present invention, the first computing means comprises an electric circuit, and the second, third and fourth computing means comprise an optical circuit.
In one configuration example of the optical logic circuit of the present invention , the logical operation in the first operation means is addition of the signal X and the signal Y.

The adder according to the present invention further comprises: first operation means for outputting, for each bit, the result of addition of the signal X of a plurality of bits and the signal Y of a plurality of bits; and addition of each bit in the first operation means The second arithmetic means for outputting the carry signal, which is a propagation signal to the upper bits necessary for the second bit, for each bit, and the control signals for controlling the first and second arithmetic means exclude the signals X and Y as control signals. The XOR gate for outputting the result of the logical OR for each bit, and the AND gate for inputting the result of the bitwise AND of the signals X and Y to the second arithmetic means, the first and second The arithmetic means of each comprises one optical path gate for each bit configuration, each optical path gate constituting the second arithmetic means is connected in series, and the control signal for each bit calculated by the XOR gate corresponds Input to the optical path gate of Are, each light pass gates constituting said second calculating means in response to a control signal of the corresponding bit calculated by the XOR gates, the carry from the light pass gate of the lower bits of said second arithmetic means It is characterized in that any one of the result of the logical product of the signal and the corresponding bit operated by the AND gate is selected and propagated to the upper bit .
Further, in one configuration example of the adder according to the present invention, each of the optical path gates constituting the first arithmetic means includes a carry signal or its inverted signal according to the control signal for each bit calculated by the XOR gate. It is characterized in that either one is output.

  According to the present invention, the first operation means for outputting the result of the desired logical operation of the signal X of multiple bits and the signal Y of multiple bits for each bit, and the logical operation for each bit in the first operation means A second operation means for outputting the propagation signal to the upper bits for each bit, and a control signal for controlling the first and second operation means based on the signals X and Y for each bit. The third arithmetic means is provided, the configuration for each bit of the second arithmetic means is one light path gate, each optical path gate is connected in series, and the control signal for each bit calculated by the third arithmetic means is supported. Calculation path (critical path) that limits the operation time of the circuit can be reconstructed to a configuration suitable for optical elements, and the length of the critical path can be shortened. Light propagating in critical path It is possible to perform a logic operation on the propagation velocity.

  Further, according to the present invention, the first operation means for outputting the result of addition of the signal X of plural bits and the signal Y of plural bits for each bit, and the addition required for each bit in the first operation means The result of the exclusive OR of the signals X and Y is used as a control signal for controlling the first and second operation means, and the second operation means for outputting the carry signal, which is a propagation signal to the upper bits, for each bit. An XOR gate for outputting each bit and an AND gate for inputting the result of AND operation of each bit of the signals X and Y to the second arithmetic means are provided. The configuration of each bit of the first and second arithmetic means Each of the optical path gates constituting the second arithmetic means is connected in series as one optical path gate, and the bit-by-bit control signal calculated by the XOR gate is input to the optical path gate of the corresponding bit. Operation that limits the operation time of The path (critical path) can be reconstructed to a configuration suitable for optical elements, the length of the critical path can be shortened, and the addition of the signals X and Y is performed at the propagation speed of light propagating through the critical path It becomes possible.

It is a figure explaining the connection method of a logic block. It is a block diagram which shows the structure of the conventional adder. It is a block diagram which shows the detailed structure of the conventional adder. It is a figure explaining the critical path of the conventional adder. It is a figure explaining shortening of the critical path in this invention. It is a block diagram showing composition of an adder concerning a 1st embodiment of the present invention. It is a figure which shows the structure of the AND gate of the adder based on the 1st Embodiment of this invention. It is a figure which shows the structure of the XOR gate of the adder based on the 1st Embodiment of this invention. It is a block diagram which shows the structure of the adder which concerns on the 2nd Embodiment of this invention. It is a block diagram which shows the detailed structure of the adder based on the 2nd Embodiment of this invention. It is a figure which shows the structure of the SUM gate of the adder based on the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the adder which concerns on the 3rd Embodiment of this invention. FIG. 6 is a diagram showing switching energy per bit of an electronic device and an optical device. It is a figure which shows the truth table of a look-up table. 15 is a diagram showing the configuration of a logic block corresponding to the look-up table of FIG. 14 and an equivalent circuit diagram of an optical path gate. FIG. It is an equivalent circuit schematic of an output path.

First Embodiment
Hereinafter, embodiments of the present invention will be described with reference to the drawings. The present invention solves the problem of the third stage process in the electric circuit described in FIG. That is, the propagation of the optical signal utilizes a feature that is independent of neither the capacitor (C) nor the resistance (R) of the path. Such an optical conversion makes it possible to complete the calculation at the time when the optical signal propagates through the output path.

  In addition, the calculation path (critical path) that limits the calculation time of the circuit is reconstructed to a configuration suitable for the optical device by the method shown below, and the path length is shortened by miniaturizing the optical device by nanophotonics. By doing this, you can dramatically improve the computing speed.

  In the present invention, for the sake of convenience, a plurality of combinations of logic blocks are classified into two types shown in FIG. 1 (A) and FIG. 1 (B). Here, as shown in FIG. 1 (A), the serial connection is a connection in which the sources and drains of the transistors 12 of the logic blocks 10 of the front and rear stages are connected in series, and the cascade connection is as shown in FIG. It is defined as a connection in which a signal that has passed through the transistor 12 of the final stage of the logic block 10 of the previous stage is input to the gate of the transistor 12 of the first stage of the logic block 10 of the next stage.

For example, in the case of the adder (X + Y), it can be a combination of logical blocks of three inputs _{(X i, Y i, C} i). Here, X _i, Y _i is i-th digit of the value to be added, C _i is the value of the carry from i-1 digits. When a 3-input logic block is configured by a LUT, a carry operation can be realized by using the C _{i + 1} output array in FIG. 14 as the answer in FIG. 15A, and the answer in FIG. By using the output array of S _i in FIG. 14, addition of each digit can be realized.

The circuit configuration of the conventional adder is shown in FIG. Here, for the sake of simplicity, the combination of logic blocks 10 is represented using the equivalent circuit of FIG. Upper logic blocks 10-1 to 10-4 are logic blocks for calculating carry values C _{i +1} , C _{i +2} , C _{i +3} , and C _{i +4} , and lower logic blocks 10-5 to 10 -8 is a logic block which performs addition of each digit.

  When adding X consisting of a plurality of bits and Y consisting of a plurality of bits, logic blocks 10-5 to 10-8 perform addition for each digit, and logic blocks 10-1 to 10-4 perform high-order digits. Calculate the carry value to FIG. 3 is a block diagram showing a detailed configuration of the adder of FIG.

  In the circuit configuration as shown in FIGS. 2 and 3, the one that determines the operation time is the longest path (critical path). In the present invention, it is proposed to actively use the serial connection and to use this connection for the critical path of operation. The method will be described by giving a specific example.

  First, the critical path of the circuit of FIG. 2 and FIG. 3 is extracted. The structure which extracted the critical path of the adder shown to FIG. 2, FIG. 3 is shown in FIG. The path indicated by 15 in FIGS. 2 to 4 is a critical path. The construction is such that the logic block 10 of the next stage can not be operated if the path taken by the carry signal is the longest and the carry operation of the logic block 10 of the previous stage is not completed. In the case of an electrical circuit, the time taken for 32-bit addition is said to be about 1 ns.

  Next, minimize the critical path. The single digit operation in FIG. 4 is performed by three transistors 12 (optical path gates) serially connected on the critical path, but all of these operations are necessarily performed on the optical path gate existing on the critical path. It does not have to be done.

  For example, as shown in FIG. 5, using the results of operations performed by XOR (exclusive OR) gates 21-1 to 21-3 outside the critical path as gate input signals to the optical path gates 20-1 to 20-3, respectively. Thus, the number of optical path gates on the critical path can be reduced to a minimum (here, one).

Furthermore, the connection to the next block is changed from cascade to serial. It is possible to serially change the signals input in the cascade according to the condition of the operation. In the example of FIG. 5, the carry signal Ci _{+ 1} from the i digit is input to the optical pass gate 20-2 of the i + 1 digit, and the carry signal Ci _{+ 2} from the i + 1 digit is to the optical pass gate 20-3 with i + 2 digit It has a serial connection like input.

  As a result, construction of the path of the critical path can be performed simultaneously in each digit, and the construction time of the path becomes independent of the number (number of digits) of optical path gates on the critical path. Furthermore, since the carry operation is completed only by passing the optical signal through the constructed path, the operation time is equal to the light propagation time.

  Next, FIG. 6 shows a specific circuit configuration of the adder of the present embodiment. Here, a configuration in which 3-bit X and Y are added is described as an example. The adder according to this embodiment includes 1 × 1 optical pass gates 30-1 to 30-6, 2 × 1 optical pass gates 31-1 to 31-9, and AND (logical product) gates 32-1 to 32-3. And NAND (non-conjunction) gates 33-1 to 33-3 and XOR (exclusive OR) gates 34-1 to 34-3. Note that the present embodiment is an example of a configuration in which all signals and circuits are converted to light.

The AND gate 32-1 calculates the logical product of the X and Y values X ₁ and Y ₁ of the first digit, and the AND gate 32-2 calculates the X and Y values X ₂ and Y ₂ of the second digit. A logical product is calculated, and the AND gate 32-3 calculates a logical product of the X and Y values X ₃ and Y ₃ of the third digit.

  The output signal of the AND gate 32-1 is the gate input signal of the 1 × 1 optical path gate 30-1, and the output signal of the AND gate 32-2 is the gate input signal of the 1 × 1 optical path gate 30-2 The output signal 3 is the gate input signal of the 1 × 1 optical path gate 30-3.

The NAND gate 33-1 calculates the NAND of the X and Y values X ₁ and Y ₁ of the first digit, and the NAND gate 33-2 calculates the X and Y values X ₂ and Y ₂ of the second digit. The NAND gate 33-3 computes the NAND of the values X ₃ and Y ₃ of the third digit X and Y.

  The output signal of the NAND gate 33-1 becomes the gate input signal of the 1 × 1 optical path gate 30-4, and the output signal of the NAND gate 33-2 becomes the gate input signal of the 1 × 1 optical path gate 30-5. The output signal 3 is the gate input signal of the 1 × 1 optical path gate 30-6.

XOR gate 34-1, the first digit of the X, calculates the exclusive OR of the values X _1, Y ₁ of the Y, XOR gate 34-2, the second digit of X, the values of Y X _2, Y _The XOR gate 34-3 calculates the exclusive OR of the values X ₃ and Y ₃ of the third digit X and Y.

  The output signal (control signal) of the XOR gate 34-1 is the gate input signal of the 2 × 1 optical path gates 31-1, 31-4 and 31-7, and the output signal (control signal) of the XOR gate 34-2 is 2 × The gate input signal of the 1 optical path gate 31-2, 31-5, 31-8, and the output signal (control signal) of the XOR gate 34-3 is of 2 × 1 optical path gate 31-3, 31-6, 31-9. It becomes a gate input signal.

  FIG. 7 is a diagram showing the configuration of the AND gate 32-1. The AND gate 32-1 is constituted by the optical pass gates 320-322. Each of the optical path gates 320 to 322 selects one optical path (the upper optical path in the example of FIG. 7) when the gate input is “1”, and the other optical path when the gate input is “0” Select the lower light path).

1 stage optical pass gate 320 and 321 operate in response to gate input X _i, 2 stage optical pass gate 322 operates in response to the gate input Y _i. As in the case of the logic block described in FIG. 15A, it is necessary to prepare four answers in advance for two inputs X ₁ and Y ₁ . Therefore, the light source may be disposed at the answer of “1” and light may be input. The configuration of the AND gates 32-2 and 32-3 is the same as that of the AND gate 32-1.

FIG. 8 is a diagram showing the configuration of the XOR gate 34-1. The XOR gate 34-1 is configured by the optical pass gates 340-342. 1 stage optical pass gate 340 and 341 operate in response to gate input X _i, 2 stage optical pass gate 342 operates in response to the gate input Y _i.

As in the case of the AND gate 32-1, it is necessary to prepare four answers in advance for the two inputs of X ₁ and Y ₁ , and a light source is placed at the answer of “1” to Just enter The configuration of the XOR gates 34-2 and 34-3 is the same as that of the XOR gate 34-1.
The NAND gates 33-1 to 33-3 can be easily realized by a combination of optical path gates.

  The 1 × 1 optical path gates 30-1 to 30-3 are turned on when the gate inputs from the AND gates 32-1 to 32-3 are “1” to pass the optical signal from the input path, When the input is “0”, it turns off and blocks the light signal. Similarly, the 1 × 1 optical pass gates 30-4 to 30-6 are turned on when the gate input from the NAND gates 33-1 to 33-3 is "1", and when the gate input is "0". It will be off.

  The output signals of the 1 × 1 optical path gates 30-1 to 30-6 are input to 2 × 1 optical path gates 31-1 to 31-3 and 31-4 to 31-6. In addition, it is necessary to arrange a light source in the input path of each 1 × 1 light path gate 30-1 to 30-6 to input light.

The 2 × 1 optical path gates 31-1 to 31-3 select one of the optical paths (the carry signals C _{1 to} C ₃ ) when the gate input from the XOR gates 34-1 to 34-3 is "1". When the gate input is “0”, the other light path (the outputs of the 1 × 1 light path gates 30-1 to 30-3) is selected. The output signal of the 2 × 1 optical pass gate 31-1 to 31-3 become the carry signal C ₂ -C ₄ for the higher digit. For example carry signal C ₂ is input to the 2 × 1 optical pass gate 31-2,31-8, the carry signal C ₃ is inputted to the 2 × 1 optical pass gate 31-3,31-9.

When the gate inputs from the XOR gates 34-1 to 34-3 are "0", the 2 × 1 optical path gates 31-4 to 31-6 select one of the optical paths (1 × 1 optical path gates 30-4 to 30-. 6) and select the other light path (the carry signal bars C ₁ to C ₃ ) when the gate input is “1”.

The output signals of the 2 × 1 light path gates 31-4 to 31-6 become carry signals C _{2 to} C _{4 which} are complementary to the carry signals C ₂ to C ₄ . Carry signal bar C ₂ is input to the 2 × 1 optical pass gate 31-5,31-8, the carry signal bar C ₃ are input to the 2 × 1 optical pass gate 31-6,31-9.

2 × 1 optical pass gate 31-7～31-9 is one light path when the gate input from the XOR gate 34-1～34-3 is "1" (carry signal bar C ₁ ~ bar C ₃₎ Is selected, and when the gate input is “0”, the other light path (the carry signals C _{1 to} C ₃ ) is selected. The output of the 2 × 1 optical pass gate 31-7～31-9 is the output signal S ₁ to S _3, which shows the results of each digit of the summing.

Incidentally, since the carry signal C ₁ is used in the first digit of the operation is "0", it is necessary to enter a "1" At the as complementary carry signal bar C _1, 2 × 1 optical pass gates 31 the input of the bar C ₁ of -4,31-7 it is necessary to input light using a light source.

  The paths indicated by 15 and 16 in FIG. 6 are the critical paths of the adder. The configuration shown in FIG. 6 is equivalent to the configuration of FIG. 5, and the result of the XOR operation of X and Y executed outside the critical path is input to the optical path gate on the critical path 15. The lower critical path 16 is a path through which a carry signal complementary to the upper critical path 15 is propagated.

  In this embodiment, the carry calculation is completed only by propagating the light to the optical path gate serially connected on the critical path. Addition of each digit is computed using a branch signal from the critical path, and the computation does not affect other digits. That is, it is possible to perform the addition at the propagation speed of light propagating through the critical path.

Second Embodiment
Next, a second embodiment of the present invention will be described. FIG. 9 is a block diagram showing the configuration of the adder according to the present embodiment, and the same reference numerals as in FIG. 6 denote the same components. The adder according to this embodiment includes 1 × 1 optical pass gates 30-1 to 30-3, 2 × 1 optical pass gates 31-1 to 31-3, 31 to 7 to 31, and an AND gate 32-1. .About.32-3, XOR gates 34-1 to 34-3, and light / light gates 35-1 and 35-2.

In the first embodiment, the lower critical path 16 shown in FIG. 6 is used to generate inverted signals bar C ₂ and bar C ₃ of the carry signals C ₂ and C ₃ . Therefore, if a circuit having an inversion function is used, the circuits in the lower part of FIG. 6, that is, 1 × 1 optical pass gates 30-4 to 30-6, 2 × 1 optical pass gates 31-4 to 31-6, and NAND gate 33-1 It is possible to omit ~ 33-3.

In the example of this embodiment, the light-optical gate 35-1 produces an inverted signal bar C ₂ from the carry signal C ₂ which is output from the 2 × 1 optical pass gate 31-1, a carry signal C ₂ You input the inverted signal bar C ₂ to 2 × 1 optical pass gate 31-8.

Similarly, the light-optical gate 35-2, 2 × 1 optical pass gate generates an inverted signal bar C ₃ from the carry signal C ₃ outputted from 31-2, the carry signal C ₃ and the inverted signal bar C ₃ And are input to the 2 × 1 optical pass gate 31-9.
The other configuration is as described in the first embodiment.

FIG. 10 is a block diagram showing the detailed configuration of the adder of the present embodiment shown in FIG. In the example of FIG. 10, a configuration in which 4 bits of X and Y are added is shown.
The SUM gates 36-1 to 36-4 correspond to a configuration in which the 2 × 1 optical pass gates 31-7 to 31-9 and the optical / optical gates 35-1 and 35-2 shown in FIG. 6 are combined.

FIG. 11 is a diagram showing the configuration of the SUM gate 36-1. The SUM gate 36-1 includes a NOT gate 360 and an optical pass gate 361. NOT gate 360 generates an inverted signal bar C ₁ from the carry signal C _1. The optical pass gate 361 is the same as the 2 × 1 optical pass gate 31-7. The configuration of the SUM gates 36-2 to 36-4 is the same as that of the SUM gate 36-1.

Thus, in the present embodiment, the configuration can be simplified as compared with the first embodiment.
Incidentally, FIG. 9, in the example of FIG. 10, but omitting the circuit of the lower of FIG. 6, the carry signal bar C ₂ calculated in the circuit of the lower, the inverted signal C _2, C ₃ of the bar C ₃ By generating the light / light gate, the circuit in the upper part of FIG. 6, that is, 1 × 1 light path gate 30-1 to 30-3, 2 × 1 light path gate 31-1 to 31-3 and AND gate 32-1 32-3 may be omitted.

Third Embodiment
Next, a third embodiment of the present invention will be described. FIG. 12 is a block diagram showing the configuration of the adder according to the present embodiment, and the same reference numerals as in FIG. 6 denote the same components. The adder according to this embodiment includes: 1 × 1 optical path gates 30-1 to 30-3, 2 × 1 optical path gates 31-1 to 31-3, AND gates 32-1 to 32-3, and an XOR gate 34-1 to 34-3, electric switches 37-1 to 37-3, and OE converters 38-1 and 38-2.

  In the present invention, since the addition is completed for each digit and does not affect other digits, the middle stage circuit shown in FIG. 9, that is, 2 × 1 optical pass gates 31-7 to 31-9 and light -Even when the portions of the optical gates 35-1 and 35-2 are processed by the electric signal, it is possible to obtain an operation speed substantially equal to that of the case of using light.

Electrical switch 37-1～37-3 selects one of the electrical paths (the carry signal bar C ₁ ~ bar C ₃₎ when the gate input is "1" from XOR gate 34-1～34-3 When the gate input is “0”, the other electric path (the carry signals C _{1 to} C ₃ ) is selected. The output of the electric switch 37-1～37-3 becomes the output signal S ₁ to S _3, which shows the results of each digit of the summing. Since the carry signal C ₁ is "0", it is necessary to input an electrical signal corresponding to "1" as an inverted signal bar C ₁ to an electrical switch 37-1.

The OE converter 38-1 converts the carry signal C ₂ (optical signal) output from the 2 × 1 optical path gate 31-1 into an electric signal, and at the same time, the inverted signal bar C of the converted carry signal C ₂ It generates _two inputs and carry signal C ₂ and the inverted signal bar C ₂ to an electrical switch 37-2.

Similarly, the OE converter 38-2 converts the carry signal C ₃ (optical signal) output from the 2 × 1 optical path gate 31-2 into an electrical signal, and at the same time, inverts the converted carry signal C ₃ It generates a signal bar C _3, to enter the the carry signal C ₃ and the inverted signal bar C ₃ to an electrical switch 37-3.
The other configuration is as described in the first embodiment.

  Further, the upper gates shown in FIG. 9, that is, AND gates 32-1 to 32-3 and XOR gates 34-1 to 34-3 are used as electrical switches, and 1 × 1 optical pass gate 30-1 to 30. The combination of -3 and the light source associated therewith may be replaced with a light source which is turned on when the gate input from the AND gates 32-1 to 32-3 is "1". Since these parts exist outside the critical path, even if these parts are processed with electrical signals, it is possible to obtain approximately the same computing time as when using light. As in the present embodiment, even if only the path that constitutes the upper critical path 15 is replaced with light and the other circuits are electrically, it is possible to execute the calculation at the light propagation speed.

  The circuits described in the first to third embodiments have a configuration in which the opticalization has been advanced to the transistor level, and the fusion of the electronic circuit and the optical circuit is facilitated, and the field of expertise of the electronic circuit Both ultra-high-throughput, ultra-high-throughput computing) and optical circuit expertise (ultra-low-latency computing that completes computation at the propagation speed of light while propagating information at the speed of light) This makes it possible to solve the problem of the electronic circuit whose operating frequency is in a plateau.

In the first to third embodiments, only the configuration as an adder has been described. However, when the circuit has a critical path, (an operation completed for each digit and an operation affected by other digits are It goes without saying that in some cases, the present invention can be applied to circuits other than adders, in which operations affected by other digits become critical paths. For example, when the circuit configuration is changed as follows, it becomes a subtractor. Specifically, all signals of the input Y are input as the logical negation of Y, and a logical value 1 is input to the least significant digit C ₁ , that is, “1” is input as the signal C _1. If you do not enter the bar C _1. Thus, the configuration of the adder can be applied to various arithmetic circuits, and examples of the application include a multiplier, a divider, or a coincidence detection circuit that detects a matching bit string from one or more conditions. is there.

  Moreover, shortening = speeding-up can be achieved by using the optical gate (nonpatent literature 5, 6) of a nano photonics as an optical path gate.

  The path gates (31-1 to 31-6) on the critical path may be configured so that electrical path switching can be performed, and the gate does not have to be operated by an optical signal. This makes it possible to use conventional optical devices.

  The present invention can be applied to logical operations performed by an optical circuit or a mixed circuit of an optical circuit and an electrical circuit.

  30-1 to 30-6 ... 1 x 1 optical path gate, 31-1 to 31-9 ... 2 x 1 optical path gate, 32-1 to 32-3 ... AND gate, 33-1 to 33-3 ... NAND gate, 34-1 to 34-3 ... XOR gate, 35-1 and 35-2 ... light and optical gate, 36-2 to 36-4 ... SUM gate, 37-1 to 37-3 ... electric switch, 38-1, 38-2 ... OE converter, 320-322, 340-342, 361 ... light path gate, 360 ... NOT gate.

Claims (7)

First operation means for outputting, for each bit, the result of a desired logical operation of a plurality of bit signals X and a plurality of bit signals Y;
A second operation means for outputting, for each bit, a propagation signal to the upper bits necessary for the bitwise logical operation in the first operation means;
Third operation means for outputting a control signal for controlling the first and second operation means based on the signals X and Y for each bit ;
And fourth operation means for inputting the result of the logical operation for each bit of the signals X and Y, which is different from the logical operation in the first operation means, to the second operation means ,
In the second arithmetic means, the configuration of each bit consists of one optical path gate, and each optical path gate is connected in series,
Each of the optical path gates includes the propagation signal from the optical path gate of the lower bit and the corresponding bit operated by the fourth operation means in accordance with the control signal of the corresponding bit operated by the third operation means. An optical logic circuit characterized in that any one of the operation results is selected and propagated to the upper bits . In the optical logic circuit according to claim 1,
An optical logic circuit characterized in that the optical pass gate is a nano photonics optical gate. In the optical logic circuit according to claim 1 or 2,
An optical logic circuit, wherein all of the first, second, third and fourth arithmetic means are optical circuits. In the optical logic circuit according to claim 1 or 2,
The first computing means comprises an electric circuit,
An optical logic circuit characterized in that the second, third and fourth calculation means comprise an optical circuit. The optical logic circuit according to any one of claims 1 to 4.
An optical logic circuit characterized in that the logical operation in the first operation means is the addition of a signal X and a signal Y. First operation means for outputting the result of addition of the plurality of bit signals X and the plurality of bit signals Y for each bit;
A second operation means for outputting, for each bit, a carry signal as a propagation signal to the upper bits necessary for the addition for each bit in the first operation means;
An XOR gate which outputs the result of the exclusive OR of the signals X and Y as a control signal for controlling the first and second arithmetic means, bit by bit;
And an AND gate for inputting the result of the bitwise AND operation of the signals X and Y to the second operation means,
Each of the first and second operation means has a configuration for each bit consisting of one optical path gate, each optical path gate constituting the second operation means is connected in series, and the bit operated by the XOR gate Each control signal is input to the optical path gate of the corresponding bit ,
Each of the optical path gates constituting the second arithmetic operation means receives the carry signal from the optical path gate of the lower bit of the second arithmetic operation means according to the control signal of the corresponding bit operated by the XOR gate An adder characterized in that any one of the results of the logical product of corresponding bits operated by the AND gate is selected and propagated to the upper bits . In the adder according to claim 6,
Wherein each light pass gates constituting the first calculating means, adder and outputting either the carry signal or the inverted signal in response to the control signal for each of the bits calculated by the XOR gates.