JP2017158041A - Optical logic circuit and accumulator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To resolve a problem of a delay occurred at a calculation level.SOLUTION: An accumulator comprises: optical pass gates 31-7 to 31-9 which output a signal X of a plurality of bits and a result of an addition of Y in each pit; optical pass gates 31-1 to 31-3 which output a carry signal required for the addition of each bit in the optical pass gates 31-7 to 31-9 in each bit; XOR gates 34-1 to 34-3 which output a result of an exclusive OR of the signals X and Y as a control signal controlling 2×1 optical pass gates 31-1 to 31-3 and 31-7 to 31-9; and AND gates 32-1 to 32-3 which input a result of logical AND in each bit of the signals X and Y to the 2×1 optical pass gates 31-1 to 31-3.SELECTED DRAWING: Figure 6

Description

  The present invention relates to an optical logic circuit that performs a logical operation in an optical circuit or a mixed circuit of an optical circuit and an electric circuit, and an adder that is an example of the optical logic circuit.

  In order to improve the processing speed of the current electronic arithmetic circuit, a device for reducing the chip size and the element size to the limit is devised. The reason is that the resistance (R) and capacitance (C) in the circuit greatly limit the propagation of signals, and the only way to increase the calculation speed is to reduce the chip size and element size. For this reason, devices such as multi-cores and many-cores have been devised, such as packing elements into narrow-area logic blocks and cores, but the wiring to connect these cores has a new “delay”. The limits to the speeding up of computation are beginning to appear.

  On the other hand, an optical wiring or an optical pass gate used in optical communication or the like can propagate an optical signal independent of C and R in the wiring path. In addition, with the progress of nanophotonics, the energy consumption of the optical gate (optical pass gate) has been dramatically improved, and the energy cost [J / bit] is about the same level as the CMOS gate and light. For this reason, various studies have been made to opticalize communication within and between chips.

FIG. 13 is a diagram for explaining switching energy per bit (= energy cost [J / bit]). In the case of a CMOS gate, it is assumed that it becomes 10 ⁻¹⁵ J / bit or less when wiring (wire) is included (non-cost). Patent Document 1). On the other hand, the energy cost of the optical gate of nanophotonics has been realized at about 10 ⁻¹⁵ J / bit, and the energy cost is about the same as that of the CMOS gate (see Non-Patent Document 2). Nanophotonic optical gates are also advantageous in terms of shortening the length (see Non-Patent Documents 5 and 6).

  An arithmetic process in a configuration in which an optical pass gate is combined will be described. When 2 × 1 optical pass gates are connected in a tree shape, a circuit that reproduces a look-up table (LUT) for an n-digit input as shown in FIG. 14 can be configured (FIG. 15A). . In the examples of FIGS. 14 and 15A, the case of n = 3 is shown.

11A to 11-7 in FIG. 15A are optical pass gates. Each of the optical path gates 11-1 to 11-7 selects one optical path (the upper optical path in the example of FIG. 15A) when the gate input is “1”, and the gate input is “0”. Is selected, the other optical path (lower optical path) is selected. This route selection operation is the same in FIG. 3, FIG. 7, FIG. 8, FIG. 10 (FIG. 11 selects the opposite route). The first-stage optical pass gates 11-1 to 11-4 operate according to the gate input C _i , and the second-stage optical pass gates 11-5 and 11-6 operate according to the gate input X _i. The optical pass gate 11-7 of the eye operates in response to the gate input Y _i . FIG. 15B is a diagram showing an equivalent circuit of one optical pass gate.

  The logic block 10 shown in FIG. 15A outputs an optical signal of “0” or “1” for all combinations for n-digit inputs, and performs all operations for n-digit inputs. Is to execute. The arithmetic process in such a configuration has the following three stages.

The first step is preparing the answer. When a tree structure is configured using 2 × 1 optical pass gates, 2 ^ n answers (1 bit of “0” or “1”) are prepared in advance for n inputs. In the electric circuit, this answer is stored in the memory, and in the case of the optical circuit, the light source 101 is arranged at the answer of “1”. For example, the logic block 10 in FIG. 15A is a circuit that performs an operation of C _{i + 1} .

  The second stage is the construction of the output path. In an n-stage tree structure, the same switch operation is performed simultaneously in all stages in the same stage. As a result, the path construction does not depend on the number of switches, and is completed in the switching time of one switch.

For example, in the example of FIG. 15A, when the signal (C _i , X _i , Y _i ) = (1, 1, 0) is input, the first-stage optical pass gates 11-1 to 11-4 and 2 The optical path gates 11-5 and 11-6 of the stage are switched to the upper side, the optical path gate 11-7 of the third stage is switched to the lower side, and a path indicated by 14 is constructed. An equivalent circuit of the output path at this time is shown as in FIG.

  The third stage is answer output. A 1-bit signal prepared in advance is output through the constructed path. In the case of an electric circuit, the first-stage and second-stage operations can be realized very easily. In other words, it is only necessary to store 2 ^ n answers using a huge memory switch and construct a path with a switching time of about 10 ps.

  However, in the case of an electric circuit, the third stage process is very difficult. That is, as shown in FIG. 16, since C and R of n transistors 12 are connected, the response speed of the path deteriorates at n ^ 2. Therefore, in the electric circuit, the connection as shown in FIG. 16 is used only when n <4-6.

  There are some proposals for a method of opticalizing such a circuit, that is, combining a light pass gate like a CMOS gate to form a logic block (see Patent Document 1, Non-Patent Document 3, and Non-Patent Document 4). .

JP-A-4-299733

Rodney S. Tucker and Kerry Hinton, “Energy Consumption and Energy Density in Optical and Electronic Signal Processing”, IEEE Photonics Journal, Volume 3, Number 5, October 2011, pp.821 Koji Takeda et al., “Few-fJ / bit data transmissions using directly modulated lambda-scale embedded active region photonic-crystal lasers”, Nature Photonics 7, pp. 569-575, 2013. James Hardy et al., “Optic inspired logic architecture”, OPTICS EXPRESS, Vol.15, No.1, pp.150-165, 2007 Qianfan Xu et al., “Reconfigurable optical directed-logic circuits using microresonator-based optical switches”, OPTICS EXPRESS, Vol.19, No.6, pp.5244-5259, 2011 Noritsugu Yamamoto et al., “Photonic crystal directional coupler switch with small switching length and wide bandwidth”, OPTICS EXPRESS, Vol.14, No.3, pp.1223-1229, 2006 Kengo Nozaki et al., “All-optical switching for 10-Gb / s packet data by using an ultralow-power optical bistability of photonic-crystal nanocavities”, OPTICS EXPRESS, Vol.23, No.23, pp.30379-30392 , 2015

  In the prior art shown in the above documents, a technique for opticalizing communication within a chip or between chips and a technique for opticalizing a logic block have been proposed. However, there is a problem in that there is no consideration for a computation path (critical path) that limits the computation time of the circuit, and a delay caused by the computation cannot be solved.

  The present invention has been made in order to solve the above-described problems. In addition to optical wiring and optical gates within and between chips, the present invention further advances the photonization to a transistor level with finer granularity, and causes a delay problem occurring at the calculation level. An object of the present invention is to provide an optical logic circuit and an adder that can solve the above problem fundamentally. In the present invention, the critical path that controls the calculation in the electronic chip is opticalized, the path is reconstructed into a configuration suitable for the optical element, and the path length is shortened, thereby dramatically improving the calculation speed. .

  The optical logic circuit of the present invention includes a first arithmetic unit that outputs a result of a desired logical operation of a multi-bit signal X and a multi-bit signal Y for each bit, and for each bit in the first arithmetic unit. A second arithmetic means for outputting a signal propagated to the upper bits necessary for the logical operation of each bit, and a control signal for controlling the first and second arithmetic means based on the signals X and Y. A third computing means for outputting each time, and the second computing means comprises a single optical pass gate for each bit, and each optical pass gate is connected in series, and the third computing means The calculated control signal for each bit is input to the optical pass gate of the corresponding bit.

In one configuration example of the optical logic circuit of the present invention, the optical pass gate is a nanophotonics optical gate.
In one configuration example of the optical logic circuit of the present invention, all of the first, second, and third arithmetic means are optical circuits.
In one configuration example of the optical logic circuit according to the present invention, the first arithmetic means is an electric circuit, and the second and third arithmetic means are optical circuits.
In one configuration example of the optical logic circuit of the present invention, the logical operation is addition of the signal X and the signal Y.

Further, the adder of the present invention includes a first calculation means for outputting a result of addition of the multi-bit signal X and the multi-bit signal Y for each bit, and addition for each bit by the first calculation means. Required for the second operation means for outputting a carry signal, which is a signal propagated to the higher bits, for each bit, and the signals X and Y are exclusively used as control signals for controlling the first and second operation means. An XOR gate for outputting a logical OR result for each bit; and an AND gate for inputting a logical product for each bit of the signals X and Y to the second arithmetic means. The calculation means of each bit is composed of one optical pass gate, each optical pass gate constituting the second calculation means is connected in series, and the control signal for each bit calculated by the XOR gate corresponds. Input to optical pass gate of bit It is characterized in that the.
Further, in one configuration example of the adder of the present invention, each optical pass gate constituting the first calculation means has a carry signal or its inverted signal in accordance with the control signal for each bit calculated by the XOR gate. Each of the optical pass gates constituting the second calculation means outputs either a carry signal or an output signal of the AND gate according to the control signal for each bit calculated by the XOR gate. It is characterized by doing.

  According to the present invention, the first arithmetic means for outputting the result of a desired logical operation of the multi-bit signal X and the multi-bit signal Y for each bit, and the logical operation for each bit in the first arithmetic means And second control means for outputting a propagation signal to the upper bits necessary for each bit and a control signal for controlling the first and second calculation means based on the signals X and Y for each bit. 3 arithmetic means, the configuration of each bit of the second arithmetic means is one optical pass gate, each optical pass gate is connected in series, and the control signal for each bit calculated by the third arithmetic means is supported. By inputting to the optical path gate of the bit to be reconstructed, the operation path (critical path) that controls the operation time of the circuit can be reconstructed into a configuration suitable for the optical element, and the length of the critical path can be shortened. Light traveling along the critical path It is possible to perform a logic operation on the propagation velocity.

  In the present invention, the first calculation means for outputting the result of the addition of the multi-bit signal X and the multi-bit signal Y for each bit, and the addition required for each bit in the first calculation means, A second arithmetic means for outputting a carry signal, which is a propagation signal to the upper bits, for each bit, and a result of exclusive OR of signals X and Y as a control signal for controlling the first and second arithmetic means. An XOR gate that outputs each bit and an AND gate that inputs the result of the logical product of the signals X and Y to the second arithmetic means are provided, and the configuration of the first and second arithmetic means for each bit is provided. By adding each optical pass gate constituting each of the second arithmetic means in series and inputting the control signal for each bit calculated by the XOR gate to the corresponding optical pass gate for each bit, an adder is provided. To limit the calculation time The path (critical path) can be reconstructed into a configuration suitable for the optical element, the length of the critical path can be shortened, and the signals X and Y are added at the propagation speed of the light propagating through the critical path. It becomes possible.

It is a figure explaining the connection method of a logic block. It is a block diagram which shows the structure of the conventional adder. It is a block diagram which shows the detailed structure of the conventional adder. It is a figure explaining the critical path of the conventional adder. It is a figure explaining shortening of the critical path in this invention. It is a block diagram which shows the structure of the adder which concerns on the 1st Embodiment of this invention. It is a figure which shows the structure of the AND gate of the adder which concerns on the 1st Embodiment of this invention. It is a figure which shows the structure of the XOR gate of the adder which concerns on the 1st Embodiment of this invention. It is a block diagram which shows the structure of the adder which concerns on the 2nd Embodiment of this invention. It is a block diagram which shows the detailed structure of the adder which concerns on the 2nd Embodiment of this invention. It is a figure which shows the structure of the SUM gate of the adder which concerns on the 2nd Embodiment of this invention. It is a block diagram which shows the structure of the adder which concerns on the 3rd Embodiment of this invention. It is a figure which shows the switching energy per bit of an electronic device and an optical device. It is a figure which shows the truth table of a lookup table. FIG. 15 is a diagram illustrating a configuration of a logic block corresponding to the lookup table of FIG. 14 and an equivalent circuit diagram of an optical pass gate. It is an equivalent circuit diagram of an output path.

[First Embodiment]
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the present invention, the problem of the third stage process in the electric circuit described in FIG. 16 is solved by photonization. That is, the characteristic that the propagation of the optical signal is independent of the capacitor (C) and the resistance (R) of the path is used. Such opticalization makes it possible to complete the calculation in the time required for the optical signal to propagate through the output path.

  In addition, the following method is used to reconstruct the computation path (critical path) that controls the computation time of the circuit into a configuration suitable for optical elements, and the path length is shortened by miniaturization of optical elements by nanophotonics. By doing so, the calculation speed is dramatically improved.

  In the present invention, for the sake of convenience, a plurality of combinations of logic blocks are classified into two types shown in FIGS. 1 (A) and 1 (B). Here, as shown in FIG. 1A, the serial connection is a connection in which the source and drain of the transistor 12 of the logic block 10 in the preceding stage and the subsequent stage are connected in series, and the cascade connection is as shown in FIG. 1B. The signal that has passed through the final stage transistor 12 of the preceding logic block 10 is defined as a connection that is input to the gate of the first stage transistor 12 of the next stage logic block 10.

For example, in the case of an adder (X + Y), it can be constituted by a combination of logic blocks of three inputs (X _i , Y _i , C _i ). Here, X _i and Y _i are the i- _th value to be added, and C _i is the carry value from the i−1 digit. When a 3-input logical block is configured by an LUT, a carry operation can be realized by using the output array of C _{i + 1} in FIG. 14 for the answer in FIG. 15A, and the answer in FIG. If the output array of S _i in FIG. 14 is used, summation of each digit can be realized.

The circuit configuration of the conventional adder is shown in FIG. Here, for the sake of simplicity, combinations of the logic blocks 10 are represented using the equivalent circuit notation shown in FIG. The upper logical blocks 10-1 to 10-4 are the logical blocks for calculating the carry values C _{i + 1} , C _{i + 2} , C _{i + 3} , C _{i + 4} , and the lower logical blocks 10-5 to 10-10. -8 is a logic block that performs addition of each digit.

  When X consisting of a plurality of bits and Y consisting of a plurality of bits are added, addition is performed for each digit in the logic blocks 10-5 to 10-8, and the upper digit is added in the logic blocks 10-1 to 10-4. Calculates the carry value to. FIG. 3 is a block diagram showing a detailed configuration of the adder of FIG.

  In the circuit configuration as shown in FIGS. 2 and 3, the longest path (critical path) determines the calculation time. In the present invention, it is proposed that the serial connection is positively used and this connection is used for a critical path of calculation. The method will be described with a specific example.

  First, the critical paths of the circuits of FIGS. 2 and 3 are extracted. FIG. 4 shows a configuration in which the critical path of the adder shown in FIGS. 2 and 3 is extracted. The route indicated by 15 in FIGS. 2 to 4 is a critical path. The path through which the carry signal passes is the longest, and if the carry operation of the preceding logic block 10 is not completed, the operation of the next logic block 10 cannot be performed. In the case of an electric circuit, the time required for adding 32 bits is said to be about 1 ns.

  Next, the critical path is minimized. The one-digit operation in FIG. 4 is executed by three transistors 12 (optical pass gates) serially connected on the critical path, but all of these operations are necessarily executed by the optical pass gate existing on the critical path. It does not have to be done.

  For example, as shown in FIG. 5, the results calculated by XOR (exclusive OR) gates 21-1 to 21-3 outside the critical path are used as gate input signals to the optical path gates 20-1 to 20-3, respectively. Thus, the number of optical path gates on the critical path can be reduced to a minimum (here, one).

Furthermore, the connection to the next block is changed from cascade to serial. The signal input to the cascade can be changed serially depending on the calculation conditions. In the example of FIG. 5, carry signal C _{i + 1} from i digit is input to i + 1 digit optical pass gate 20-2, and carry signal C _{i + 2} from i + 1 digit is inputted to i + 2 digit optical pass gate 20-3. It is connected serially as input.

  As a result, the path construction of the critical path can be performed simultaneously in each digit, and the path construction time becomes independent of the number of optical path gates (digits) on the critical path. Furthermore, since the carry calculation is completed simply by passing the optical signal through the constructed path, the calculation time becomes equal to the light propagation time.

  Next, FIG. 6 shows a specific circuit configuration of the adder of the present embodiment. Here, a configuration in which 3 bits of X and Y are added will be described as an example. The adder of the present embodiment includes 1 × 1 optical pass gates 30-1 to 30-6, 2 × 1 optical pass gates 31-1 to 31-9, and AND (logical product) gates 32-1 to 32-3. And NAND (Negative AND) gates 33-1 to 33-3 and XOR (Exclusive OR) gates 34-1 to 34-3. Note that this embodiment is an example of a configuration in which all signals and circuits are opticalized.

The AND gate 32-1 calculates the logical product of the X and Y values X ₁ and Y ₁ of the first digit, and the AND gate 32-2 calculates the X and Y values X ₂ and Y ₂ of the second digit. The AND gate 32-3 calculates the logical product of the X and Y values X ₃ and Y ₃ of the third digit.

  The output signal of the AND gate 32-1 becomes the gate input signal of the 1 × 1 optical pass gate 30-1, the output signal of the AND gate 32-2 becomes the gate input signal of the 1 × 1 optical pass gate 30-2, and the AND gate 32- The output signal 3 becomes the gate input signal of the 1 × 1 optical pass gate 30-3.

The NAND gate 33-1 calculates the negative logical product of the X and Y values X ₁ and Y ₁ of the first digit, and the NAND gate 33-2 calculates the X and Y values X ₂ and Y ₂ of the second digit. The NAND gate 33-3 calculates the negative logical product of the X and Y values X ₃ and Y ₃ of the third digit.

  The output signal of the NAND gate 33-1 becomes the gate input signal of the 1 × 1 optical pass gate 30-4, the output signal of the NAND gate 33-2 becomes the gate input signal of the 1 × 1 optical pass gate 30-5, and the NAND gate 33− The output signal 3 becomes the gate input signal of the 1 × 1 optical pass gate 30-6.

The XOR gate 34-1 calculates the exclusive OR of the X and Y values X ₁ and Y ₁ of the first digit, and the XOR gate 34-2 calculates the X and Y values X ₂ and Y of the second digit. _The XOR gate 34-3 calculates the exclusive OR of the X and Y values X ₃ and Y ₃ of the third digit.

  The output signal (control signal) of the XOR gate 34-1 becomes the gate input signal of the 2 × 1 optical pass gates 31-1, 31-4, 31-7, and the output signal (control signal) of the XOR gate 34-2 is 2 ×. It becomes the gate input signal of the 1 optical pass gates 31-2, 31-5, 31-8, and the output signal (control signal) of the XOR gate 34-3 is the 2 × 1 optical pass gates 31-3, 31-6, 31-9. This is a gate input signal.

  FIG. 7 is a diagram showing the configuration of the AND gate 32-1. The AND gate 32-1 includes optical pass gates 320 to 322. Each of the optical path gates 320 to 322 selects one optical path (upper optical path in the example of FIG. 7) when the gate input is “1”, and the other optical path (when the gate input is “0”). Select the lower light path.

The first-stage optical pass gates 320 and 321 operate according to the gate input X _i , and the second-stage optical pass gate 322 operates according to the gate input Y _i . As in the case of the logic block described with reference to FIG. 15A, it is necessary to prepare four answers in advance for the two inputs X ₁ and Y ₁ . Therefore, a light source may be arranged at the answer of “1” to input light. The configuration of the AND gates 32-2 and 32-3 is the same as that of the AND gate 32-1.

FIG. 8 is a diagram showing the configuration of the XOR gate 34-1. The XOR gate 34-1 includes optical pass gates 340 to 342. The first-stage optical pass gates 340 and 341 operate according to the gate input X _i , and the second-stage optical pass gate 342 operates according to the gate input Y _i .

As in the case of the AND gate 32-1, it is necessary to prepare four answers for the two inputs X ₁ and Y ₁ in advance. You can enter. The configuration of the XOR gates 34-2 and 34-3 is the same as that of the XOR gate 34-1.
The NAND gates 33-1 to 33-3 can also be easily realized by a combination of optical pass gates.

  The 1 × 1 optical pass gates 30-1 to 30-3 are turned on when the gate input from the AND gates 32-1 to 32-3 is “1”, and pass the optical signal from the input path. When the input is “0”, the optical signal is cut off by turning off. Similarly, the 1 × 1 optical pass gates 30-4 to 30-6 are turned on when the gate input from the NAND gates 33-1 to 33-3 is “1”, and when the gate input is “0”. Turns off.

  Output signals of the 1 × 1 optical pass gates 30-1 to 30-6 are input to the 2 × 1 optical pass gates 31-1 to 31-3 and 31-4 to 31-6. In addition, it is necessary to arrange a light source in the input path of each 1 × 1 optical pass gate 30-1 to 30-6 and input light.

The 2 × 1 optical pass gates 31-1 to 31-3 select _one optical path (carry signals C _{1 to} C ₃ ) when the gate input from the XOR gates 34-1 to 34-3 is “1”. When the gate input is “0”, the other optical path (outputs of the 1 × 1 optical pass gates 30-1 to 30-3) is selected. The output signals of the 2 × 1 optical pass gates 31-1 to 31-3 become carry signals C _{2 to} C ₄ for higher digits. For example, the carry signal C ₂ is input to the 2 × 1 optical pass gates 31-2 and 31-8, and the carry signal C ₃ is input to the 2 × 1 optical pass gates 31-3 and 31-9.

The 2 × 1 optical pass gates 31-4 to 31-6 have one optical path (1 × 1 optical pass gates 30-4 to 30− when the gate input from the XOR gates 34-1 to 34-3 is “0”. 6 output) is selected, and when the gate input is “1”, the other optical path (carry signal bars C ₁ to C ₃ ) is selected.

The output signal of the 2 × 1 optical pass gate 31-4～31-6 becomes carry complementary signals bar C ₂ ~ bar C ₄ relative to the carry signal C ₂ -C _4. Carry signal bar C ₂ is input to the 2 × 1 optical pass gate 31-5,31-8, the carry signal bar C ₃ are input to the 2 × 1 optical pass gate 31-6,31-9.

The 2 × 1 optical pass gates 31-7 to 31-9 have one optical path (carrying signal bars C ₁ to C ₃ ) when the gate input from the XOR gates 34-1 to 34-3 is “1”. When the gate input is “0”, the other optical path (carry signals C _{1 to} C ₃ ) is selected. The outputs of the 2 × 1 optical pass gates 31-7 to 31-9 become output signals S _{1 to} S ₃ indicating the result of the addition of each digit.

Since the carry signal C ₁ used in the first digit calculation is “0”, it is necessary to input “1” as the carry signal bar C ₁ complementary to this, and the 2 × 1 optical pass gate 31. It is necessary to place a light source and input light at the input of the bar C ₁ of −4, 31-7.

  The paths indicated by 15 and 16 in FIG. 6 are the critical paths of the adder. The configuration shown in FIG. 6 is equivalent to the configuration shown in FIG. 5, and the XOR calculation result of X and Y executed outside the critical path is input to the optical path gate on the critical path 15. The lower critical path 16 is a path through which a carry signal complementary to the upper critical path 15 propagates.

  In this embodiment, the carry calculation is completed only by propagating light to the optical path gate connected serially on the critical path. The sum of each digit is calculated using a branch signal from the critical path, and the calculation does not affect the other digits. That is, the summation can be executed at the propagation speed of light propagating through the critical path.

[Second Embodiment]
Next, a second embodiment of the present invention will be described. FIG. 9 is a block diagram showing the configuration of the adder according to the present embodiment. The same components as those in FIG. 6 are denoted by the same reference numerals. The adder of the present embodiment includes 1 × 1 optical pass gates 30-1 to 30-3, 2 × 1 optical pass gates 31-1 to 31-3, 31-7 to 31-9, and an AND gate 32-1. 32-3, XOR gates 34-1 to 34-3, and optical / optical gates 35-1 and 35-2.

In the first embodiment, the lower the critical path 16 shown in FIG. 6 is used to make the inverted signal bar C ₂ carry signal C _2, C _3, the bars C _3. Therefore, if a circuit having an inversion function is used, the lower circuit of FIG. 6, that is, 1 × 1 optical pass gates 30-4 to 30-6, 2 × 1 optical pass gates 31-4 to 31-6, and NAND gate 33-1 ~ 33-3 can be omitted.

In the example of the present embodiment, the optical / optical gate 35-1 generates the inverted signal bar C ₂ from the carry signal C ₂ output from the 2 × 1 optical pass gate 31-1, and the carry signal C ₂ You input the inverted signal bar C ₂ to 2 × 1 optical pass gate 31-8.

Similarly, the optical / optical gate 35-2 generates an inverted signal bar C ₃ from the carry signal C ₃ output from the 2 × 1 optical pass gate 31-2, and carries the carry signal C ₃ and the inverted signal bar C _3. Are input to the 2 × 1 optical pass gate 31-9.
Other configurations are the same as those described in the first embodiment.

FIG. 10 is a block diagram showing a detailed configuration of the adder of the present embodiment shown in FIG. Note that the example of FIG. 10 shows a configuration in which 4-bit X and Y are added.
The SUM gates 36-1 to 36-4 correspond to a configuration in which the 2 × 1 optical pass gates 31-7 to 31-9 and the optical / optical gates 35-1 and 35-2 in FIG. 6 are combined.

FIG. 11 is a diagram showing the configuration of the SUM gate 36-1. The SUM gate 36-1 includes a NOT gate 360 and an optical pass gate 361. The NOT gate 360 generates an inverted signal bar C ₁ from the carry signal C ₁ . The optical pass gate 361 is the same as the 2 × 1 optical pass gate 31-7. The configuration of the SUM gates 36-2 to 36-4 is the same as that of the SUM gate 36-1.

Thus, in this embodiment, the configuration can be simplified as compared with the first embodiment.
In the example of FIGS. 9 and 10, the lower circuit shown in FIG. 6 is omitted, but the inverted signals C ₂ and C ₃ of the carry signals C ₂ and C ₃ calculated by the lower circuit are used. 6 is generated by the optical / optical gate, that is, the 1 × 1 optical pass gates 30-1 to 30-3, the 2 × 1 optical pass gates 31-1 to 31-3, and the AND gates 32-1 to 32-1. 32-3 may be omitted.

[Third Embodiment]
Next, a third embodiment of the present invention will be described. FIG. 12 is a block diagram showing the configuration of the adder of the present embodiment. The same components as those in FIG. 6 are denoted by the same reference numerals. The adder of the present embodiment includes 1 × 1 optical pass gates 30-1 to 30-3, 2 × 1 optical pass gates 31-1 to 31-3, AND gates 32-1 to 32-3, and an XOR gate. 34-1 to 34-3, electrical switches 37-1 to 37-3, and OE converters 38-1 and 38-2.

  In the present invention, the summation is completed for each digit and does not affect other digits. Therefore, the middle stage circuit shown in FIG. 9, that is, the 2 × 1 optical pass gates 31-7 to 31-9 and the light Even if the portions with the optical gates 35-1 and 35-2 are processed with electrical signals, the calculation speed can be almost the same as when light is used.

Electrical switch 37-1～37-3 selects one of the electrical paths (the carry signal bar C ₁ ~ bar C ₃₎ when the gate input is "1" from XOR gate 34-1～34-3 When the gate input is “0”, the other electrical path (carry signals C _{1 to} C ₃ ) is selected. The output of the electric switch 37-1～37-3 becomes the output signal S ₁ to S _3, which shows the results of each digit of the summing. Since the carry signal C ₁ is “0”, it is necessary to input an electric signal corresponding to “1” to the electric switch 37-1 as the inverted signal bar C ₁ .

The OE converter 38-1 converts the carry signal C ₂ (optical signal) output from the 2 × 1 optical pass gate 31-1 into an electrical signal, and at the same time, the inverted signal bar C of the converted carry signal C _{2. 2} and the carry signal C ₂ and the inverted signal bar C ₂ are input to the electric switch 37-2.

Similarly, the OE converter 38-2 converts the carry signal C ₃ (optical signal) output from the 2 × 1 optical pass gate 31-2 into an electric signal, and at the same time, inverts the converted carry signal C ₃ . The signal bar C ₃ is generated, and the carry signal C ₃ and the inverted signal bar C ₃ are input to the electric switch 37-3.
Other configurations are the same as those described in the first embodiment.

  Furthermore, the upper gates shown in FIG. 9, that is, AND gates 32-1 to 32-3 and XOR gates 34-1 to 34-3 are used as electrical switches, and 1 × 1 optical pass gates 30-1 to 30 are used. -3 and the light source associated therewith may be replaced with a light source that turns ON when the gate input from the AND gates 32-1 to 32-3 is "1". Since these portions exist outside the critical path, even if these portions are processed with an electric signal, it is possible to obtain almost the same computation time as when light is used. As in the present embodiment, even if only the path constituting the upper critical path 15 is replaced with light and the other circuits are configured electrically, it is possible to perform computation at the light propagation speed.

  The circuits described in the first to third embodiments are configured to be opticalized up to the transistor level, facilitating the fusion of electronic circuits and optical circuits, It is possible to achieve both ultra-high-throughput computation using ultra-high integration and parallel processing) and optical circuit expertise (ultra-low latency computation that completes computation at the speed of light propagation while propagating information at the speed of light). Thus, it is possible to solve the problem of the electronic circuit whose operating frequency is reaching its peak.

In the first to third embodiments, only the configuration as the adder has been described. However, when the circuit has a critical path, (the operation that is completed for each digit and the operation that is affected by other digits are not performed. In some cases, the operation affected by other digits becomes a critical path. Needless to say, the present invention can be applied to circuits other than adders. For example, if the circuit configuration is changed as follows, it becomes a subtracter. Specifically, all signals of input Y are input as logical negation of Y, and logical value 1 is input to C ₁ of the least significant digit, that is, “1” is input as signal C ₁ , If you do not enter the bar C _1. In this way, the configuration of the adder can be applied to various arithmetic circuits. Examples of the application include a multiplier, a divider, or a coincidence detection circuit that detects a bit string that coincides with one or more conditions. is there.

  Further, by using a nanophotonics optical gate (Non-Patent Documents 5 and 6) as the optical pass gate, it is possible to reduce the length and speed.

  In addition, it is possible to use a configuration in which electrical paths can be switched as the pass gates (31-1 to 31-6) on the critical path, and the gate does not have to be operated with an optical signal. Thereby, a conventional optical element can be used.

  The present invention can be applied to a logical operation performed in an optical circuit or a mixed circuit of an optical circuit and an electric circuit.

  30-1 to 30-6 ... 1x1 optical pass gate, 31-1 to 31-9 ... 2x1 optical pass gate, 32-1 to 32-3 ... AND gate, 33-1 to 33-3 ... NAND gate, 34-1 to 34-3: XOR gate, 35-1, 35-2 ... optical / optical gate, 36-2 to 36-4 ... SUM gate, 37-1 to 37-3 ... electrical switch, 38-1, 38-2 ... OE converter, 320-322, 340-342, 361 ... optical pass gate, 360 ... NOT gate.

Claims (7)

First arithmetic means for outputting a result of a desired logical operation of the multi-bit signal X and the multi-bit signal Y for each bit;
Second arithmetic means for outputting a propagation signal to the upper bits necessary for each bit in the first arithmetic means;
A third arithmetic means for outputting a control signal for controlling each of the first and second arithmetic means based on the signals X and Y for each bit;
Each of the second calculation means is composed of one optical pass gate for each bit, each optical pass gate is connected in series, and the control signal for each bit calculated by the third calculation means An optical logic circuit that is input to an optical pass gate. The optical logic circuit according to claim 1,
An optical logic circuit, wherein the optical pass gate is a nanophotonics optical gate. The optical logic circuit according to claim 1 or 2,
An optical logic circuit characterized in that all of the first, second and third arithmetic means are optical circuits. The optical logic circuit according to claim 1 or 2,
The first computing means comprises an electric circuit,
The optical logic circuit, wherein the second and third arithmetic means are optical circuits. 5. The optical logic circuit according to claim 1, wherein:
An optical logic circuit characterized in that the logical operation is addition of a signal X and a signal Y. First arithmetic means for outputting a result of addition of the multi-bit signal X and the multi-bit signal Y for each bit;
A second computing means for outputting a carry signal, which is a signal propagated to the upper bits, necessary for the addition for each bit in the first computing means;
An XOR gate that outputs the result of exclusive OR of the signals X and Y as a control signal for controlling the first and second arithmetic means;
An AND gate that inputs a logical product of each bit of the signals X and Y to the second arithmetic means;
Each of the first and second arithmetic means is composed of one optical pass gate, and each optical pass gate constituting the second arithmetic means is connected in series, and the bit calculated by the XOR gate. An adder characterized in that each control signal is input to an optical pass gate of a corresponding bit. The adder according to claim 6, wherein
Each optical pass gate constituting the first calculation means outputs either a carry signal or its inverted signal according to a bit-by-bit control signal calculated by the XOR gate,
Each optical pass gate constituting the second calculation means outputs either a carry signal or an output signal of the AND gate according to a bit-by-bit control signal calculated by the XOR gate. Adder.