JPH04299733A - Addition system and its circuit - Google Patents

Abstract

PURPOSE:To increase the adding speed of two numbers by processing previously the carry signals which are continuously propagated in order to eliminate the carry propagation and also to simplify the hardware configuration by applying frequently a simple logical arithmetic for each bit. CONSTITUTION:When two numbers A and B are added together, the carry processing is previously applied to a part where the carry signals are continuously propagated. Then the value given in such a form that causes no carry propagation is deformed so as to increases the adding speed of the two numbers. An AND X and an OR Y of numbers A and B are obtained by an AND circuit 1 and an OR circuit 2. A carry range detecting circuit 3 obtains the value M showing a carry occurrence range from the values of X and Y. Then an EX-OR circuit 4 applies the batch carry processing to Y, and an EX-OR circuit 5 performs the addition for each bit to obtain a sum S.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for increasing the speed of an adder in a digital arithmetic unit.

0002

2. Description of the Related Art Conventionally, a carry look-ahead method has been known as a method for performing high-speed addition. This method performs addition based on the following principle. 2 numbers A of n bits to be added,
The value of each bit of B is an-1, an-2,...
a1, a0 and bn-1, bn-2,...b1
, b0, the sums sn-1, sn-2,
...s1, s0 and carry cn-1, cn-2
,...c1, c0 are calculated using the following equations (1) and (2).

0003

This equation can be transformed into equations (5) and (6) by introducing the following two functions (3) and (4).

[0005]

As can be seen from equation (5), if the carry ci can be used simultaneously for all bits, the sum si can be calculated in parallel. Using formula (6), carry ci becomes c
0 = g0 + c-1・p0

(7) c1 = g1 + c0 ・p
1 =g1 +g0 ・p1 +c-1・p0 ・
p1
(8) c2 = g2 + c1 ・p2
=g2 +g1 ・p2 +g0 ・p1 ・p2
+c-1・p0 ・p1 ・p2 (9)
c3 =g3 +c2 ・p3 =g3 +g2 ・p3 +g1 ・p2 ・p3
+g0 ・p1 ・p2 ・p3 +c-1・p0
・p1 ・p2 ・p3

(10) . . . Therefore, by using these carry signals and pi, the sum can be obtained from equation (5).

FIG. 9 shows an example of the configuration of a 4-bit adder using this method. The carry generation propagation circuit 81 is (3), (
4) This is the part that calculates the formula, the carry look ahead circuit 82 calculates the carry signal by calculating the formulas (7) to (10), and the sum generation circuit 83 calculates the sum according to the formula (5). This is the circuit you are looking for. The signal names in the figure correspond one-to-one with the signal names in equations (1) to (10).

[0008]

[Problem to be solved by the invention] The carry look-ahead circuit described above is easy to implement in hardware when the word length of the number to be added is short, but when the word length becomes long, the overall word length is shortened. This method requires measures such as performing calculations in sections, which has drawbacks such as requiring changes to the hardware configuration and slowing down calculation time.

An object of the present invention is to eliminate the drawbacks of the conventional method and provide a method for performing addition at high speed using a similar hardware configuration with an arbitrary addition word length.

0010

[Means for Solving the Problems] The present invention extracts the range of digits where carry propagation occurs or the range of digits where carry propagation does not occur from the logical sum and logical product of addition terms and augend terms, It is characterized by performing carry processing for each bit at a time and then calculating the sum.

[0011]

[Operation] In the present invention, when performing addition of two numbers, carry processing is performed in advance on the part where carry signals are propagated continuously, and the given value is transformed into a form in which carry propagation does not occur. This achieves faster speeds. Furthermore, most of the processing of each functional block can be done by simple logical operations for each bit, which simplifies the hardware configuration.

0012

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the principle and embodiments of the present invention will be described with reference to FIGS. 1 to 4.

Let the augend and addition term with a word length of n bits be A and B, and the values of each bit are an-1 and an-2.
,...a1, a0, and bn-1, bn-2
,... b1, b0. For these A and B, logical product X and logical sum Y are calculated. In other words, for each bit xi = ai ・bi

(11) yi = ai + bi

(12
). By this operation, if the values of both ai and bi are 1, xi and yi will both become 0, and if one is 1 and the other is 0, yi will become 1 and xi will become 0,
If both are 1, xi and yi are both 1. This means that the 1's in ai and bi are repacked in the order of yi and xi, so finding the sum of A and B can be converted into finding the sum of X and Y. If yi is 0, xi is also 0, so the carry does not propagate beyond this digit i. Therefore, when considering carry propagation, 1 in Y
You can consider each continuous part independently.

FIG. 2 shows changes in numerical values after each calculation process. Assume that bits l to k of Y are 1 as shown in this figure. However, it is assumed that l is higher than k. Now, among the bits whose value is 1 between bits 1 and k in X, the least significant bit is defined as q bit. In this example, k+1 becomes q. At this time, carry propagation starts from q bits and continues to l+1 bits. Let M be a value indicating the range of this carry. In this example, M is determined such that the bits mq+1 to ml+1 to which the carry is transmitted are set to 1, and the other bits are set to 0. The carry process is completed by inverting the values from yq+1 to yl+1, which are the range in which the carry is transmitted, that is, by calculating the exclusive OR of Y and M shown in the following equation (13).

[0015]

Let this value be Z. Zi indicates the value of the i bit of Z. FIG. 2 shows Z in this example. After this processing, no carry occurs at all, so the sum S can be obtained by taking the exclusive OR of z and X shown in the following equation (14).

[0017]

si is the value of the i bit of S. This sum S is equal to the sum of the initial A and B.

FIG. 1 is a block diagram of hardware that implements this addition method. AND circuit 1 and OR circuit 2 are blocks that realize equations (1) and (2), respectively. The carry range detection circuit 3 determines a value M indicating the range in which carry occurs from the values of X and Y. In the first EX-OR circuit 4 (
13) Carry out the carry process of the expression for Y and convert it to the second EX
-OR circuit 5 performs addition for each bit as shown in equation (14). As a result, the sum S of A and B is obtained.

When adding two numbers, a carry signal from the lower bits may be added. In this case, if one bit is added below the least significant bit and this bit is set to -1 digit, it is sufficient to give a carry signal to x-1 and a 1 to y-1.

Next, an embodiment of the carry detection circuit 3 will be described with reference to FIGS. 3 and 4.

FIG. 3 is a cell layout diagram for realizing the carry detection circuit 3. A set of Y signal lines 21 and M signal lines 22 arranged in parallel in the vertical direction is arranged for necessary bits. The figure shown is an 8-bit example. On the other hand, the X signal line 23 is arranged diagonally from the lower level to the upper level. A basic cell 24 is placed at the intersection of these signal lines.

FIG. 4 shows an embodiment of a basic cell using an optical logic circuit. The optical blocker 32 transmits light when the signal yi is 1, and blocks it when the signal yi is 0. xj is 1 and 0 for the presence or absence of light.
When there is an optical signal, the optical splitter 31 distributes the optical signal to the optical interrupter and the signal line mi+1. The signal transmitted from above through the mi+1 signal line is transmitted downward as is. With this configuration, the carry range signal M can be obtained from the X and Y signals. Optical interrupter 32
Alternatively, it is possible to implement electrical signals by replacing the transfer gate with a gate that sends a signal to mi+1 using the xj signal instead of the optical divider.

Another embodiment of the present invention will be explained using FIGS. 5 and 6.

In FIG. 2, the value of sq is always 0, so the q bits of the value M indicating the range of carry are also determined to be 1, and in parallel with determining Z in the same way as in equation (13). x
If the value of q is forcibly set to 0, the sum S can be obtained even if the exclusive OR in equation (14) is changed to an ordinary OR.

FIG. 5 shows changes in signals in this method. M' is a carry range signal when the carry range is defined so that the q-th bit is also 1. X' is a signal that forcibly sets the k-th bit of the X signal to 0, X' i = Xi ・M' i-1

(15) is the required signal. Z' is a signal obtained by replacing M in equation (13) with M'. By taking the exclusive OR of X' and Z', the sum S can be obtained.

FIG. 6 shows a block diagram of a circuit according to this method. A carry range detection circuit 51 outputs a signal M' indicating a carry range from the X and Y signals. 2nd AN
The D circuit 52 executes equation (15) and outputs X'. An EX-OR circuit 4 obtains Z' from M' and Y. X'
and Z' are logically summed by the second OR circuit 53 to obtain the sum S.

Next, another embodiment of the present invention will be described using FIGS. 7 and 8. This is an example using a signal within a range in which carry does not occur.

[0029] Instead of M, find a range in which no carry occurs, that is, find M'' where k to q are 1 and the others are 0, and do the exclusive OR of M'' and X. In parallel, the signal Y is converted to Y' with only the l+1th bit set to 1 and all other bits set to 0, and M'' and Y'
The sum S can also be obtained by taking the logical sum of . However, at this time, if there is no bit of X that becomes 1 between digits k and l, y' l+1 needs to remain 0.

FIG. 7 shows signal changes in this case. M'
' is a signal indicating the range in which carry does not occur, that is, from the kth bit where a series of 1s starts on Y to the k+1st bit where 1 appears for the first time on X is 1, and the rest are all 0s. It is a range signal. Let Y' be a signal in which only yl+1 is 1 and all other bits are 0. Also, Z
'' is a signal obtained from the exclusive OR of M'' and X. This signal is generated by using the carry range signals M and Y used in the first embodiment.

[0031]

##EQU1## The sum S is obtained from the logical sum of Y' and Z''.

FIG. 8 shows a block diagram of a circuit according to this method. A signal M'' is obtained by a non-carry range detection circuit 71. EX-OR circuit 72 performs the exclusive OR of M'' and X.
to obtain Z'. In parallel, from the output Y of the first OR circuit and the output of the carry range detection circuit 3,
Using the OT circuit 73 and the second AND circuit 74 (16
) to obtain the signal of Y'. These signals Z
By taking the logical sum of ' and Y' in the OR circuit 75, the sum S
seek.

[0034]

[Effects of the Invention] As described above, if the present invention is applied, carry propagation can be eliminated by pre-processing continuously propagating carry signals, and two numbers can be added at high speed. . Furthermore, simple logical operations for each bit can be used frequently, and the hardware configuration can be simplified.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a diagram illustrating signal changes after passing through each block.

FIG. 3 is a diagram showing an embodiment of a carry range detection circuit of the present invention.

FIG. 4 is a circuit diagram of a basic cell of a carry range detection circuit.

FIG. 5 is a block diagram showing another embodiment of the invention.

FIG. 6 is a diagram illustrating changes in a signal after passing through each block.

FIG. 7 is a diagram showing yet another embodiment of the present invention.

FIG. 8 is a diagram illustrating changes in a signal after passing through each block.

FIG. 9 is a circuit diagram of a conventional adder.

[Explanation of symbols]

1 AND circuit 2 OR circuit 3 Carry range detection circuit 4 EX-OR circuit 5 EX-OR circuit 21 Y signal line 22 M signal line 23 X signal line 24 Basic cell 31 Optical distributor 32 Optical interrupter 51 Carry range detection circuit 52 AND circuit 53 OR circuit 71 Non-carry range detection circuit 72 EX-OR circuit 73 NOT circuit 74 AND circuit 75 OR circuit 81 Carry generation propagation circuit 82 Carry look ahead circuit 83 Sum generation circuit

Claims (4)

[Claims] [Claim 1] Extract the range of digits in which carry propagation occurs or the range of digits in which carry propagation does not occur from the logical sum and logical product of the addition term and the augend term, and carry out each bit at a time. An addition method characterized by calculating the sum after processing. [Claim 2] A that receives the augend signal and the addition signal as inputs.
an ND circuit, an OR circuit whose inputs are the augend signal and the addition signal, a carry range detection circuit whose inputs are the outputs of the AND circuit and the OR circuit, and the carry range detection circuit and the OR circuit. The first EX-O whose input is the output of
R circuit, the carry detection circuit, and the first EX-OR
An adder circuit comprising a second EX-OR circuit that receives the output of the circuit as an input. 3. A first AND circuit that receives the augend signal and the addition signal as inputs, a first OR circuit that receives the addend signal and the addition signal as inputs, and the first AND circuit and the first a carry range detection circuit whose input is the output of the first OR circuit; a second AND circuit whose inputs are the output of the first AND circuit and the output of the carry range detection circuit; and the first OR circuit. an EX-OR circuit whose inputs are the output of the circuit and the output of the carry range detection circuit; and a second OR circuit whose inputs are the output of the second AND circuit and the output of the EX-OR circuit.
An adder circuit comprising an R circuit. 4. A first AND circuit that receives the augend signal and the addition signal as inputs, a first OR circuit that receives the augend signal and the addition signal as inputs, and the first AND circuit and the first a non-carry range detection circuit whose input is the output of the first OR circuit; a carry range detection circuit whose input is the output of the first AND circuit and the first OR circuit; and the non-carry range detection circuit. an EX-OR circuit whose inputs are the output of the circuit and the output of the first AND circuit; a NOT circuit whose inputs are the output of the first OR circuit; and the output of the carry range detection circuit and the NOT circuit. a second AND whose input is the output of
and a second OR circuit whose inputs are the outputs of the EX-OR circuit and the second AND circuit.