JP6468607B2 - Optical computing unit - Google Patents

Description

  The present invention relates to an optical arithmetic unit that performs a logical operation in an optical circuit or a mixed circuit of an optical circuit and an electric circuit.

  The present electronic arithmetic circuit is devised to reduce the chip size and element size to the limit in order to improve the processing speed. This is because the resistance (R) and capacitance (C) in the circuit greatly limit the propagation of signals, and the only way to increase the calculation speed is to reduce the chip size and element size.

  For this reason, devices such as multi-core and many-core are devised by packing elements in a logic block or core having a small area. However, the wiring for connecting them creates a new “delay”, and there is a limit to speeding up the calculation.

  On the other hand, an optical wiring or an optical pass gate used in optical communication or the like can propagate an optical signal independent of C and R in the wiring path. In addition, with the progress of nanophotonics, the energy consumption of the optical pass gate has been dramatically improved, and the energy cost [J / bit] is about the same level as that of the CMOS gate and light. For this reason, various studies have been made to opticalize communication within and between chips.

  An arithmetic process in an arithmetic circuit combining pass gates will be described with reference to FIG. When the 2 × 1 (two-branch) pass gates 101 are connected in a tree shape, an arithmetic circuit 100 that reproduces a truth table (Look up table (LUT): see FIG. 12) for an n-digit control input can be configured. The arithmetic circuit 100 outputs a signal of “0” or “1” for all combinations of n-digit control inputs, and executes all 1-bit output operations for n-digit control inputs.

  In this arithmetic circuit 100, in the arithmetic circuit 100A using a pass gate 101A such as a CMOS gate as the pass gate 101, as shown in FIG. 13, n gates C and R are connected, so that the response speed of the path is n ^. Deteriorates at 2. Therefore, in such an arithmetic circuit 100A (electric circuit), the digit n of the control input can be used only when n <4-6.

FIG. 14 shows an example in which an optical pass gate 101B is used as the pass gate 101 and the light source 102 is arranged at a signal input port corresponding to a leaf of a tree structure. In this arithmetic circuit 100 (100B), by driving the optical pass gate 101B, one optical signal (one output result) corresponding to a combination of 2 ⁿ control inputs from the output port corresponding to the trunk of the tree structure. Can be obtained.

  In the arithmetic circuit 100B, the optical path gate 101B includes two optical paths (optical switches) SW1 and SW2 that block or transmit an optical signal, and between the plurality of light sources 102 and the plurality of optical path gates 101B. The optical pass gates 101B are connected by an optical circuit 103.

  This arithmetic circuit 100B has a feature that the setting of the type of calculation can be freely changed because the contents of the truth table (LUT) can be changed by the arrangement of the light source 102. In addition, since the propagation of light does not depend on the electrical CR, a logical operation that is not limited by the CR can be performed, thereby eliminating the latency bottleneck of the electrical circuit. In this arithmetic circuit 100B, if the control input is an electric signal, a logical operation is performed by a mixed circuit of the optical circuit and the electric circuit. If the control input is an optical signal, the logical operation is performed only by the optical circuit. Will be done.

A. Tetsuya, “Photonic-Crystal Logic Devices Based on the Binary Decision Diagram,” IEICE, Electronics (1), 386 (2000) S. Lin, “Demonstration of optical computing logics based on binary decision diagram,” OPTICS EXPRESS 20, 1378 (2012)

  However, in the configuration as shown in FIG. 14, the number of optical switches (optical elements) increases exponentially with the increase in the number of control inputs, and an enormous number of optical elements are required. For this reason, a method of reducing the number of optical elements and simplifying the circuit by a technique called BDD (Binary Decision Diagram) has been proposed (for example, see Non-Patent Documents 1 and 2). However, in this method, only a specific-purpose operation can be handled, and the feature that the setting of the operation type can be freely changed is impaired.

  The present invention has been made to solve such problems, and its purpose is to greatly reduce the number of optical elements without losing the feature that the setting of the type of calculation can be freely changed. An object of the present invention is to provide an optical computing unit that can be driven with low power consumption.

  In order to achieve such an object, the present invention includes a plurality of light sources (102), a plurality of optical switches (SW1, SW2), a plurality of light sources (102), and a plurality of optical switches (SW1, SW2). And an optical circuit (103) for connecting between the optical switches (SW1, SW2), and driving the optical switches (SW1, SW2) in accordance with the combination of control inputs (103 In the optical computing unit that outputs one output result through the optical switch (SW1 (SWA), SW2 (SWB)), a plurality of paths related to one control input are bundled to block or pass the optical signal. It is characterized by performing.

  In the present invention, the optical switches (SWA, SWB) block or pass an optical signal by bundling a plurality of paths related to one control input. Accordingly, when the control input is n digits, the number of optical switches can be reduced to 2 × n. It is also possible to reduce the number of optical switches to n by using a delay circuit. In this way, the present invention can greatly reduce the number of optical switches (optical elements) and can be driven with low power consumption without impairing the feature that the setting of the type of calculation can be freely changed. become.

  In the above description, as an example, constituent elements on the drawing corresponding to the constituent elements of the invention are indicated by reference numerals with parentheses.

  As described above, according to the present invention, since a plurality of paths related to one control input are bundled and an optical signal is blocked or passed by one optical switch, the type of calculation can be freely set. Thus, the effect that the number of optical elements can be greatly reduced and the apparatus can be driven with low power consumption can be obtained without impairing the feature of being able to be changed.

FIG. 1 is a diagram in which two optical paths (optical switches) of a 2 × 1 (two-branch) optical path gate constituting a tree circuit are represented by marks. FIG. 2 is a diagram showing the relationship between the control input (“0”, “1”) and the passage / cutoff of two optical switches. FIG. 3 is a diagram illustrating an example using an optical switch that blocks or passes light by bundling a plurality of paths related to one control input (case of n = 3 stages). FIG. 4 is a diagram showing a case of n = 4 stages. FIG. 5 is a diagram showing an example in which the recombination of signal paths and the function of bundling / distributing signals are realized by a matrix switch. 6 is a diagram illustrating an example of an optical switch used in the arithmetic circuit illustrated in FIG. FIG. 7 is a diagram illustrating another example of the optical switch used in the arithmetic circuit illustrated in FIG. FIG. 8 is a diagram showing a configuration when using a multiplexer / demultiplexer in which input / output ports for multiplexing / demultiplexing using wavelengths are arranged in order of wavelength. FIG. 9 is a diagram illustrating a configuration using a delay circuit. FIG. 10 is a diagram illustrating a specific delay amount. FIG. 11 is a diagram illustrating an arithmetic circuit using a pass gate. FIG. 12 is a diagram illustrating a truth table for an n-digit control input. FIG. 13 is a diagram for explaining the deterioration of the response speed of the path when a CMOS gate or the like is used as the pass gate. FIG. 14 is a diagram illustrating an arithmetic circuit using an optical pass gate as the pass gate.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. First, the outline of the present invention will be described before the description of the embodiments.

[Summary of the Invention]
FIG. 1 shows a diagram in which two optical paths (optical switches) of a 2 × 1 (two-branch) optical path gate 101B constituting a tree circuit are represented by marks. In this figure, the optical switch SW1 is represented by “◯”, and the optical switch SW2 is represented by “☆”. Further, in “O” and “☆”, “O” and “☆” mean passing, and “●” and “★” mean blocking.

  In this example, when the control input In [i] is “1”, the optical switch SW1 / SW2 is “◯” / “★”, and when the control input In [i] is “0”, the optical switch SW1 / SW2 is assumed to be “●” / “☆” (see FIG. 2).

In such a tree circuit having n control inputs, 2 ⁿ +2 ^n-1 +... +2 ¹ optical switches are required. In the example of FIG. 1, since n = 3, optical switches SW1 and SW2 are used, and 2 ³ +2 ² +2 ¹ = 14 optical switches are required.

  In this tree circuit 1, if the optical switches SW1 and SW2 can process a plurality of signals collectively (blocking or passing an optical signal by bundling a plurality of paths related to one control input). If possible, the number of optical switches SW1 and SW2 can be reduced to 2 × n (see FIG. 3).

That is, the tree circuit 1 shown in FIG. 1 requires 2 ³ +2 ² +2 ¹ = 14 optical switches, whereas the arithmetic circuit 2 shown in FIG. 3 has 2 × 3 = 6 light switches. It can be a switch. As a result, the number of optical switches (optical elements) can be greatly reduced and driving can be performed with low power consumption without losing the feature that the setting of the type of calculation can be freely changed.

  In order to distinguish from the optical switches SW1 and SW2 in the tree circuit 1, the optical switches SW1 and SW2 used in the arithmetic circuit 2 are SWA and SWB. In FIG. 3, the optical switch SWA is represented by “◯”, the optical switch SWB is represented by “☆”, “○”, “☆” means passing, “●”, “★” are blocking. What is meant is the same as the optical switches SW1 and SW2.

  The arithmetic circuit 2 can be realized by combining an element that rearranges the path before the optical switches SWA and SWB, an element that bundles signals, and an element that distributes signals at the subsequent stage. In the arithmetic circuit 2 shown in FIG. 3, the functional block BL1 is provided between the light source 102 and the first-stage optical switches SWA and SWB, and the first-stage optical switches SWA and SWB and the second-stage optical switches SWA and SWA are provided. A functional block BL2 is provided between SWB and SWB, and a functional block BL3 is provided between optical switches SWA and SWB at the second stage and optical switches SWA and SWB at the third stage.

  In the arithmetic circuit 2 shown in FIG. 3, each functional block BL has a function of distributing signals (a function of rearranging paths) and a function of bundling signals. FIG. 4 shows a case of n = 4 stages. In each functional block BL, when the bundled signals are distributed, the spatial order is the same before and after the bundle. By doing in this way, the same signal distribution method (port exchange) can be used between the respective stages.

  The recombination of signal paths and the function of bundling / distributing signals in FIG. 4 can be realized by the configuration shown in FIG. Specifically, recombination of the path can be configured by a matrix switch MS, and signals can be transmitted / blocked without changing the spatial order of signals by allowing the optical switches SWA and SWB to propagate signals without spatially overlapping them. Control can be performed. However, since the matrix switch MS does not need to be dynamically switched once the appropriate route is set, it may be formed by optical wiring. In the case of optical wiring, since crossing occurs, it is preferable to use a three-dimensional wiring or a directional coupler.

[Embodiment 1]
FIG. 6 shows an example of the optical switches SWA and SWB used in the arithmetic circuit 2 shown in FIG. In this example, it is assumed that one switch having the areas of optical switches SWA and SWB (having the areas of “◯” and “☆”) is inserted, and in the areas of “◯” and “☆” of this one switch. Each of these routes is collectively passed / blocked. Thereby, since the number of switches can be reduced, control becomes simple.

[Embodiment 2]
FIG. 7 shows another example of the optical switches SWA and SWB used in the arithmetic circuit 2 shown in FIG. In this example, by using the lens LN, the optical signal of the path related to the areas of the optical switches SWA and SWB ("◯" and "☆" areas) is collected at one point, and the collected optical signal is collected. It is made to pass or block by a shielding wall (not shown). By condensing light at one point, it becomes possible to reduce the size of the switch, resulting in low power consumption.

  The switch arranged in the condensing part may be an absorber that absorbs light or a diffuser plate or a mirror that scatters in a direction different from the incident angle. Since each signal travels in a different direction after passing through the switch, it is easy to separate them. Moreover, each signal can be made parallel by inserting a lens once again.

  In this example, it is assumed that the light is focused on one point by the lens. However, it is not always necessary to focus the light on one point, and the light passes through a local area to the extent that the passage blocking can be controlled collectively by a small switch. You should do it.

[Embodiment 3]
In the third embodiment, wavelength multiplexing is used to bundle a plurality of signals and pass through the optical switches SWA and SWB, thereby reducing the size and operating power of the switch. FIG. 8 shows a configuration when a multiplexer / demultiplexer in which input / output ports for multiplexing / demultiplexing using wavelengths are arranged in order of wavelength is used.

  In this configuration, the plurality of light sources 102 are light sources having different wavelengths. The optical circuit 103 multiplexes optical signals from a plurality of paths and then sends them to the optical switches SWA and SWB, and demultiplexing the optical signals passing through the optical switches SWA and SWB for each wavelength. Including This multiplexer and duplexer are provided in each functional block BL.

  In this case, since the signal distribution method (port exchange) differs among the stages, the setting of the matrix switch MS in FIG. 5 is changed. In this case as well, a route may be created by optical wiring without using a switch. In addition, as a multiplexer and a duplexer, an arrayed-waveguide grating (AWG) may be used.

[Embodiment 4]
In the configuration shown in FIG. 8, the functions of the optical switches SWA and SWB can be combined into one by further shifting the timing and propagating the signal to the path.

  For example, as shown in FIG. 9, the delay circuit DL (DL0 (delay circuit 0) to DL3 (delay circuit 3)) is used. In this configuration, one optical switch SWC is disposed between adjacent delay circuits DL. The optical switch SWC operates to pass / cut off a signal that precedes / delays when the input is “1” and to block / pass the signal that precedes / delays when the input is “0”.

  The delay circuits DL0, DL1, DL2, and DL3 are input signals (control inputs) corresponding to the position of “0” in In [0], In [1], In [2], and In [3] in the truth table. Delays one or more bits of the optical signal of a plurality of paths related to “0” with respect to the input signal corresponding to the position of “1” (the optical signals of the plurality of paths related to the control input “1”) A specific delay amount is shown in Fig. 10. In Fig. 10, a double circle indicates a time delay line for one bit, and a single circle compensates for the delay of the double circle. is there.

  Thus, for example, when the inputs to In [0], In [1], In [2], In [3] are “0”, “0”, “1”, “1”, as shown in FIG. As described above, the signal that can pass through all the switches SWC is only the fourth signal from the top to the delay circuit DL0. The relationship between the control input and the signal output corresponds to the type of calculation, and can be changed by the light source arrangement for the control input, that is, the circuit can change the type of calculation by the light source arrangement. . In addition, the number of optical switches can be reduced to n.

  The above circuit reduces the number of elements by a completely different method from the electrical circuit, and the type of calculation can be freely changed by the light source arrangement for control input, and the calculation is completed only by the propagation of light. In this case, it is possible to solve the problem of an electronic circuit whose operating frequency is reaching a peak state by providing an extremely low latency operation that is difficult to perform.

[Extension of the embodiment]
The present invention has been described above with reference to the embodiment. However, the present invention is not limited to the above embodiment. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the technical idea of the present invention.

  2 ... arithmetic circuit, SWA, SWB, SWC ... optical switch (optical element), BL (BL1 to BL4) ... functional block, MS ... matrix switch, DL (DL0-DL3) ... delay circuit. 101 (101B): optical pass gate, 102: light source, 103: optical circuit, LUT: truth table.

Claims (5)

A plurality of light sources, a plurality of optical switches, and an optical circuit connecting between the plurality of light sources and the plurality of optical switches and between the plurality of optical switches, the plurality of light sources depending on a combination of control inputs In an optical computing unit that outputs one output result through the optical circuit by driving an optical switch,
The optical switch is
An optical computing unit characterized in that a plurality of paths related to one control input are bundled to block or pass an optical signal. The optical computing unit according to claim 1,
The optical switch is
Condensing means for condensing optical signals coming from the plurality of paths at one point;
Means for passing or blocking the optical signal collected by the light collecting means. The optical computing unit according to claim 1,
The plurality of light sources are
Light sources with different wavelengths,
The optical circuit is
A multiplexer that multiplexes optical signals from the plurality of paths and then sends them to the optical switch;
A demultiplexer that demultiplexes the optical signal that has passed through the optical switch for each wavelength. In the optical arithmetic unit according to claim 3,
The optical circuit is
A delay circuit for delaying optical signals of a plurality of paths related to one control input;
The optical switch is
An optical computing unit comprising means for passing or blocking a signal depending on whether or not the optical signal that has passed through the optical circuit is delayed. In the optical arithmetic unit according to claim 3 or 4,
The multiplexer and the duplexer are:
An optical computing unit using an arrayed waveguide diffraction grating.