JP6707752B2 - Optical multiplier and optical multiplication method - Google Patents

Description

The present invention relates to an optical multiplier using an optical circuit for multiplication and an optical multiplication method.

Current electronic arithmetic circuits have been devised to reduce the chip size and element size to the utmost in order to improve the arithmetic processing speed. This is because the resistance (R) and the capacitance (C) in the circuit largely control the propagation of signals, and therefore the only way to increase the operation speed is to reduce the chip size and element size. For this reason, devices such as multi-core/many-core have been devised by packing elements in narrow-area logic blocks and cores, but the wiring to connect them creates a new "delay" and limits the speed of calculation. I can see it.

On the other hand, an optical wiring or an optical pass gate used in optical communication or the like can propagate an optical signal independent of C and R in the wiring path. Further, with the progress of nanophotonics, the energy consumption of the optical gate has been dramatically improved, and the energy cost [J/bit] is about the same level for the CMOS gate and the optical pass gate. For this reason, various studies have been made on opticalizing communication inside and between chips.

Here, a connection form in which a signal is input from the electric control port side of the optical gate is defined as a cascade connection, and a form in which the light propagation paths of the switches are continuously connected is defined as a serial connection. For example, assuming an optoelectronic circuit in which serial connection and cascade connection are mixed, the portion of the cascade connection is the boundary between light and electricity. At this boundary, the optical signal propagating through the circuit is once converted into electricity (OE conversion). Since this conversion is rate-controlled by an electric circuit, a circuit that is frequently used for OE conversion has little merit in using light. Therefore, the boundary between light and electricity, that is, the arrangement location and the number of cascade connections are important points in the circuit configuration. In the following, we consider this problem for multipliers.

First, consider an optical multiplier having a configuration in which OE conversion is not arranged in the optical propagation path. Non-Patent Document 1 shows that an arbitrary logical function can be realized only by serial connection by using a 2×2 optical pass gate. By using the "Direct Logic" proposed in Non-Patent Document 1, it is possible to calculate an arbitrary logical function at the propagation speed of light (Non-Patent Document 2). However, some complex logic functions require the number of elements in the order of exponential function with respect to the number of inputs, and multiplication is included in the example.

Non-Patent Document 3 proposes a circuit configuration based on a binary decision diagram as a circuit architecture suitable for an optical pass gate. Even with this method, any logical function can be realized only by serial connection. However, as in the case of “Direct Logic”, the required number of elements is an exponential order in a logical function using multiplication or the like. Therefore, it can be said that it is not realistic to configure the multiplier by the “Direct Logic” or the binary decision graph without the OE conversion.

Next, consider the circuit configuration of the multiplier on the assumption that OE conversion is used. The multiplier is an arithmetic circuit that inputs two data represented by a binary number and outputs a product of these as binary number data. FIG. 14 shows a calculation process of multiplication for 4-bit integers x ₃ x ₂ x ₁ x ₀ and y ₃ y ₂ y ₁ y ₀ . p _ij is called a partial product, and this partial product is obtained by the logical product of x _i and y _j . By adding the partial products p _ij for each digit as shown in FIG. 14, the multiplication results s ₆ , s ₅ ,..., S ₀ can be obtained. The parallel multiplier is a multiplication circuit that realizes the above process in one clock cycle.

A general parallel multiplier is composed of a partial product generator and a partial product adder. The partial product generation unit is realized by using a logical product operation (hereinafter, AND) gate. On the other hand, the partial product addition unit has configurations such as an array type and a Wallis tree type. The partial product adder of the array type multiplier connects a large number of full adders (FA) in an array as shown in FIG. Since there is a signal path that passes through a maximum of 2(N-1) full adders, the operation time is rate-controlled in this addition process.

As shown in FIG. 16, the partial product addition unit of the Wallis tree type multiplier parallelizes the addition within the same digit, thereby reducing the number of FA stages and increasing the speed. In addition, a carry lookahead adder (CLA) is used at the end to process the carry of each digit.

Here, an example in which the full adder is realized by an optical pass gate will be described with reference to FIG. 17 (Non-Patent Document 4). This full adder includes light sources 501 and 502 that output an optical signal whose intensity information is “1”, pass/block type optical gates 503 and 504, pass/cross type optical gates 505 to 507, and OE conversion. And vessels 508-510.

The OE converters 508 and 509 convert the optical signal x _i into an electric signal. The OE converter 510 converts the optical signal y _i into an electric signal. The optical signal y _i may be input to the OE converter 508 instead of x _i .
Optical gate 503 passes the optical signal from the light source 501 when the electric signal x _i is "1", the electrical signal x _i blocks the optical signal from the light source 501 when it is "0". The optical gate 504 blocks the optical signal from the light source 502 when the electrical signal x _i is “1”, and passes the optical signal from the light source 502 when the electrical signal x _i is “0”. The electrical signal y _i may be used as the electrical control input of the optical gates 503 and 504 instead of x _i .

The optical gate 505 selects and outputs the output of the optical gate 503 when the electric signals x _i and y _i are both “1” or both “0”, and the electric signal x _i is “1” and the electric signal y is y. _{When i} is “0” or the electric signal x _i is “0” and the electric signal y _i is “1”, the optical signal C _i is selected and output. The optical gate 506 selects and outputs the optical signal C _i when the electrical signals x _i and y _i are both “1” or both “0”, and the electrical signal x _i is “1” and the electrical signal y _{i is selected.} Is "0", or the electrical signal x _i is "0" and the electrical signal y _i is "1", the optical signal bar C _i is selected and output. The optical gate 507 selects and outputs the output of the optical gate 504 when the electrical signals x _i and y _i are both “1” or both “0”, and the electrical signal x _i is “1” and the electrical signal y is _{When i} is “0”, or the electric signal x _i is “0” and the electric signal y _i is “1”, the optical signal bar C _i is selected and output.

J. Hardy et al., "Optics inspired logic architecture", Optics Express, vol. 15, no. 1, pp. 150-165, 2007. Q. Xu et al., "Reconfigurable optical directed-logic circuits using microresonator-based optical switches", Optics Express, vol. 19, no. 6, pp. 5244-5259, 2011. Tetsuya Asai et al., “Photonic crystal integrated device based on binary decision graph”, Proc. of the 2000 IEICE General Conference, 386-387, 2000. Toru Ishihara et al., “Proposal of Parallel Adder Circuit Based on Optical Pass Gate Logic and Operation Verification by Photoelectric Mixed Circuit Simulator”, IEICE Tech., vol.

In the above-described full adder, since it is necessary to perform OE conversion on the optical signals x _i and y _i , the number of times of OE conversion corresponding to the number of FA is required. The number of times depends on the number of digits of the input, and the OE conversion time is several times to several tens of times of the propagation delay time in the optical pass gate. Therefore, the delay time required for the OE conversion is dominant as the number of input digits increases. Therefore, high-speed arithmetic processing cannot be performed. From the above reason, it can be said that the configurations of the array-type multiplier and the Wallis tree-type multiplier are not suitable as the configuration of the faster optical parallel multiplier. The above-described full adder is used to calculate the partial product addition by a binary number, which causes the calculation speed of multiplication to be limited by the OE conversion.

The present invention has been made to solve the above problems, and an object thereof is to enable optical multiplication at a higher speed.

An optical multiplier according to the present invention includes a partial product generation unit that generates N×N partial products of an N-bit (N is an integer of 2 or more) first digital signal and an N-bit second digital signal. An adding section that adds the partial products while integrating them into digits to generate an added value, a conversion section that analog-digital converts the added value to generate a digital value, and a digital adding section that digitally adds the digital values.

In the above-mentioned optical multiplier, the partial product generation unit and the addition unit correspond to the generation of partial products with lights of different wavelengths, and simultaneously perform generation of partial products and generation of addition values by wavelength multiplexing.

In the above optical multiplier, the partial product generating unit generates a partial product by the second-order Booth method.

An optical multiplication method according to the present invention includes a first step of generating N×N partial products of an N-bit (N is an integer of 2 or more) first digital signal and an N-bit second digital signal. The method further comprises a second step of adding the partial products while integrating the digits and generating an added value, a third step of analog-digital converting the added value to generate a digital value, and a fourth step of digitally adding the digital value. ..

As described above, according to the present invention, an excellent effect that optical multiplication can be performed at higher speed can be obtained.

FIG. 1 is a configuration diagram showing a configuration of an optical multiplier according to an embodiment of the present invention. FIG. 2 is a flowchart for explaining the optical multiplication method according to the embodiment of the present invention. FIG. 3 is an explanatory diagram for explaining the concept of the present invention. FIG. 4 is a configuration diagram illustrating a configuration example of the partial product generation unit 101. FIG. 5 is an explanatory diagram for explaining a process of converting z _i into a binary number in 4-bit multiplication. FIG. 6A is an explanatory diagram showing a conversion step of z _i into a binary number in 16-bit multiplication when digit unification is not performed. FIG. 6B is an explanatory diagram showing a process of converting z _i into a binary number in 16-bit multiplication when digit integration is performed. FIG. 7A is a configuration diagram illustrating a circuit configuring the adder 102. FIG. 7B is a configuration diagram showing a configuration example of the directional coupler 201. FIG. 8A is a configuration diagram showing a configuration example of the conversion unit 103. FIG. 8B is a configuration diagram showing a configuration example of the encoder 203. FIG. 9 is a configuration diagram showing a configuration example of wavelength division multiplexing in the partial product generation unit 101 and the addition unit 102. FIG. 10 is an explanatory diagram for explaining multiplication of 16 bits×16 bits. FIG. 11 is a configuration diagram showing a configuration example of an encoding circuit according to the method of the secondary Booth. FIG. 12 is a configuration diagram showing a configuration example in which the secondary booth method and wavelength multiplexing are used together. FIG. 13 is an explanatory diagram for explaining a state in which wavelength multiplexing and secondary Booth encoding are performed in the case of 16 bits×16 bits. FIG. 14 is an explanatory diagram showing a calculation process of multiplication for 4-bit integers x ₃ x ₂ x ₁ x ₀ and y ₃ y ₂ y ₁ y ₀ . FIG. 15 is a configuration diagram showing the configuration of the partial product addition unit of the array type multiplier. FIG. 16 is a configuration diagram showing the configuration of the partial product addition unit of the Wallis tree multiplier. FIG. 17 is a configuration diagram showing the configuration of a full adder realized by an optical pass gate.

The optical multiplier according to the embodiment of the present invention will be described below with reference to FIG. This optical multiplier includes a partial product generation unit 101, an addition unit 102, a conversion unit 103, and a digital addition unit 104.

The partial product generation unit 101 generates N×N partial products of the N-bit (N is an integer of 2 or more) first digital signal and the N-bit second digital signal. The adding unit 102 adds the generated N×N partial products while integrating the digits to generate an added value. The conversion unit 103 analog-digital converts the added value generated by the addition unit 102 to generate a digital value. The digital adder 104 digitally adds the digital values generated by the converter 103.

Here, as will be described later, the partial product generation unit 101 and the addition unit 102 associate the generation of partial products with lights of different wavelengths, and simultaneously generate partial products and generation of addition values by wavelength multiplexing. By processing, it becomes possible to perform higher-speed calculation. Further, as will be described later, the partial product generation unit 101 may generate a partial product by the secondary Booth method.

Next, the optical multiplication method of the present invention will be described with reference to the flowchart of FIG. First, in a first step S101, the partial product generation unit 101 generates N×N partial products of an N-bit (N is an integer of 2 or more) first digital signal and an N-bit second digital signal. To do.

Next, in a second step S102, the adding unit 102 adds the generated partial products while integrating the digits to generate an added value. Next, in a third step S103, the conversion unit 103 analog-digital converts the generated added value to generate a digital value. Next, in a fourth step S104, the digital adding unit 104 digitally adds the generated digital values.

As described above, the present invention is characterized in that the addition of partial products after the partial products are generated by the partial product generation unit 101 is not limited to the binary arithmetic. In the present invention, after the partial product generation unit 101 generates a partial product (S101), as shown in FIG. 3, the addition unit 102 generates an addition value by analog addition accompanied by digit integration (S102) and outputs it. The converted analog data is AD-converted by the conversion unit 103 (S103), and carried by the digital addition unit 104 (S104) to obtain a multiplication result.

With the above-described configuration, analog addition can be realized by adding the electric fields of light, and thus can be performed using light interference. This eliminates the need for conversion into electricity (OE conversion) during analog addition. In addition, the digit integration is performed to reduce the number of digital additions and the number of OE conversions required at this time.

As described above, according to the present invention, the number of times of OE conversion is overwhelmingly reduced as compared with the conventional multiplier, and the calculation time can be shortened.

The details will be described below. First, the partial product generator 101 will be described in more detail. As illustrated in FIG. 4, the partial product generation unit 101 may include a light source 111, a 1×1 optical pass gate 112, and a 1×1 optical pass gate 113. The 1×1 optical pass gate 112 and the 1×1 optical pass gate 113 are serially connected. The electrical control input to the 1×1 optical pass gate 112 is x _i, and the electrical control input to the 1×1 optical pass gate 113 is y _i . If the signal is set to be transmitted only when the electrical control input is 1, a combination of electrical signals in which both the 1×1 optical pass gate 112 and the 1×1 optical pass gate 113 are in a transmissive state, that is, x _i y _j = Only in the case of 1, light is output. This realizes a partial product.

Next, the adding section 102 will be described in more detail. First, the digit integration in the adding unit 102 will be described. For example, in the multiplication calculation process described using FIG. 14, p _ij is a partial product of x _i and y _j . Here, the sum (analog sum) of partial products within the same digit is defined as z _i . For example, z ₂ =p ₂₀ +p ₁₁ +p ₀₂ . In the case of multiplication of N bits×N bits (N is an integer of 2 or more), z _i takes a value up to N because it is obtained by the sum of N partial products. In order to obtain the binary multiplication result S _i from this value, it is necessary to convert z _i into a multi-bit binary number and carry it out using a digital adder.

FIG. 5 shows a process of converting z _i into a binary number in 4-bit multiplication. 6A and 6B show a process of converting z _i into a binary number in 16-bit multiplication. First, the processing steps when digit unification is not performed will be described with reference to FIG. 5A and FIG. 6A. In this case, in each digit, each number in the circle, square, triangle, hexagon, gray circle, gray rectangle, and gray hexagon is the maximum integer that the digit can take, which means that It is shown that log ₂ (N) times of digital addition occurs in bit multiplication after AD conversion. The number of digital additions after AD conversion is 2 times (addition for 3 rows) if 4 bits×4 bits, and 4 times (addition for 5 rows) if 16 bits×16 bits.

Next, the processing when the digit integration is performed will be described with reference to FIGS. 5B and 6B. Here, in the multiplication of 4 bits×4 bits [(a) of FIG. 5] and 16 bits×16 bits [FIG. 6B], k-digit integration is performed with k=2 and 4, respectively. As a result, the number of digital additions that occur after AD conversion can be reduced to one (addition for two rows).

For example, as shown in (b) of FIG. 5, eight pieces of z ₇ ,..., Z ₀ , which are sums of partial products, are each divided into two pieces, and divided into a total of four sets. For each set, the DA conversion is performed by regarding the two partial product addition results as one analog amount. Here, this operation is called two-digit unit integration. For example, the integrated z _{0, 1} of 2 orders of magnitude of z ₀ and z _1, is to determine the analog value 2z ₁ + z _0. In general, when the addition results of partial products are integrated by k digits and DA conversion is performed, the integrated z _{n, n+k-1 in} k digit units for the n-th set counting from the least significant side is given by the following equation. ..

Next, the series z _{n and n+k−1} obtained by the integration are converted into binary numbers by AD conversion. Here, the binary sequence obtained by AD conversion can be grouped into constant rows (here, two rows). Lastly, the final multiplication result is obtained by digitally adding the binary sequences collected in the constant row.

Next, addition (analog addition) in the addition unit 102 will be described with reference to FIGS. 7A and 7B. FIG. 7A shows a configuration in which the partial product addition z _n within the same digit described with reference to FIG. 3 and the k-digit unit integrated z _{n, n+k−1} are circuitized. It is composed of a container 201 and an attenuator 202. As shown in FIG. 7B, the directional coupler 201 is composed of two optical waveguides, one optical waveguide is provided with a phase shifter 201a, and takes the sum of electric fields of two optical signals by interference. By connecting the directional couplers 201 in a tree shape, it is possible to perform analog addition of partial products within the same digit and calculation of digit integration.

For integration in units of two digits, the signal intensity of the lower bit z _i (electric field intensity of the light) becomes half of the signal intensity of the higher bit z _i+1 (electric field intensity of the light) by the attenuator 202 such as a splitter. That is, the signal strength of the lower bits z _i is attenuated so that z _i =z _i+1 /2 holds, and then the directional coupler 201 combines the two-digit light.

Next, the conversion unit 103 will be described in more detail. Since the results z _i,j obtained by the partial product generation unit 101 and the addition unit 102 are analog values, they are converted into a binary series by AD conversion. The relationship of the N-bit digital value of the analog value is, for example, as shown in Table 1 below, and the digital values of out ₀ , out ₁ , and out ₂ periodically change with respect to the analog value.

Such a periodical change can be easily obtained as a digital optical signal by controlling the phase of the interferometer with an analog value and thresholding the intensity of the output optical signal. The functions of these conversion units 103 can be realized by using optical nonlinear processing or OE conversion. The conversion unit 103 can be composed of, for example, three encoders 203 and three threshold value processors 204 as shown in FIG. 8A. The encoder 203 can be composed of a well-known Mach-Zehnder interferometer 205, as shown in FIG. 8B. An input signal is input to the heating unit 206 provided on one arm of the Mach-Zehnder interferometer 205.

Next, the digital adder 104 will be described in more detail. A binary output of the multiplication result is obtained by executing digital addition of 2N-bit binary constant rows on the digital value generated by the conversion unit 103. In the case of digital addition for two rows, a parallel adder based on the optical pass gate logic proposed in Non-Patent Document 4 can be used to perform high-speed calculation.

For example, first, C _i and C _{i + 1,} complement and C _{i + 1's} complement of C _i full adder described with reference to FIG. 17, a full adder to be continuously connected to the serial The connected optical parallel adder is used. By inputting each of the two digital values in the carry process (S104) by digital addition described in FIG. 3 to the x side and the y side of the full adder in the optical parallel adder configured as described above, carry is performed. The process is executed to obtain the binary multiplication value S _i . Digital addition of three or more rows can be realized by connecting the above-mentioned optical parallel adders in multiple stages.

Next, wavelength multiplexing in the partial product generation unit 101 and the addition unit 102 will be described. OE conversion is not included in the process of carry and addition in the adding unit 102 described above. Therefore, as shown in FIG. 9A, a plurality of different multiplications are performed by using the partial product generation part by the 1×1 optical pass gate 112 and the 1×1 optical pass gate 113, the ring resonator 207, and the attenuator 202. By allocating different wavelengths to the generation of the partial product in (3), it is possible to simultaneously process the arithmetic processes of the optical multiplier in the embodiments in different multiplications by wavelength multiplexing. It should be noted that FIG. 9A shows the configuration of the portion that performs the processing within the frame 301 of FIG. 9B.

Next, generation of a partial product by the secondary Booth method in the partial product generation unit 101 will be described. In the process of analog addition and digit integration in the adder 102 described above, if the maximum value of the values after k-digit integration increases due to an increase in the number of digits N, a problem may occur in AD conversion in the subsequent stage. For example, when k=4, the maximum value of z after integration is 229, and it is necessary to perform conversion on the values of 0 to 229 in the subsequent AD conversion, and the linearity of AD conversion may not be guaranteed.

As a mitigation plan for this problem, it is possible to use the method of the second booth. The second-order Booth's method changes the addition amount and the subtraction amount of the multiplicand according to the values of the adjacent 3-bits of the multiplier when calculating the partial product. This method can effectively reduce the number of partial product additions in many cases, as compared with the simple partial product addition described with reference to FIG. The secondary Booth method uses the encoding rules shown in Table 2 below.

When calculating the partial product, 0, ±X, and ±2X are used as the partial product according to the values of the adjacent 3 bits of the multiplier. As a result, in the 16-bit×16-bit multiplication as shown in FIG. 10, it is possible to reduce the addition of partial products from 16 rows to 9 rows, and as a result, digit integration is k=4 (FIG. 6B). To k=3, and the maximum value of z after integration can be reduced from 229 to 58.

FIG. 11 shows an encoding circuit according to the second-order Booth method. The encoding circuit uses the directional coupler 201. The multiplicand X is input as an optical signal, and the multiplier Y is input as an electric signal. However, since the encoding is for one partial product, this circuit is actually required for the number of partial products. For example, in the case of 16 bits×16 bits, 16×9 encoding circuits are required.

Next, a method of reducing the number of booth encoding circuits by using the secondary Booth method and wavelength multiplexing together will be described. FIG. 12 shows a circuit configuration using both the secondary booth method and wavelength multiplexing. In this circuit, a directional coupler 201, a ring resonator 207, 1 is a pass, 0 is a pass/block gate 208 of a block, 0 is a pass, and 1 is a pass of a block. /Block gate 209.

The operations of the partial products 0, X, -X, 2X, -2X shown in Table 2 will be described below.

When the partial product is X, for each bit of the multiplicand X, that is, x _N-1 , x _N-2 ,..., X ₀ , λ _N-1 , λ _N-2 ,..., λ, respectively. A wavelength of ₀ is assigned and wavelength multiplexing is performed. The electric signals x _N-1 , x _N-2 ,..., X ₀ are input to the pass/block gate 208 to control ON/OFF of light of each wavelength.

When the partial product is 2X, the wavelength may be shifted to the left by 1 bit as compared with the case of X. This corresponds to taking twice the value of X.

When the partial product is -X, the complement of X may be used. That is, the pass/block gate 209 may be used. In this case, it is necessary to extend the code up to 2N-1 digits. When the partial product is -2X, the wavelength may be shifted left by 1 bit as compared with the case where -X is used. This corresponds to taking twice the value of -X.

By the above wavelength multiplexing operation, in the case of 16 bits×16 bits, the number of booth encoding circuits can be reduced from 16×9 to 9 to 1/16.

FIG. 13 shows the results of wavelength multiplexing and secondary Booth encoding in the case of 16 bits×16 bits. When the partial product addition after Booth encoding is performed, it is possible to perform the partial product addition of each digit by extracting a specific wavelength from the wavelength-multiplexed signal. In this case, partial product addition is addition of optical signals having different wavelengths. Addition of optical signals of different wavelengths can be realized by multiplexing optical signals of different wavelengths and converting the combined optical signal into a current by a photodiode. However, in this case, since the number of Booth encoding circuits is reduced by wavelength multiplexing, the effect of speeding up the operation by simultaneously processing a plurality of multiplications using wavelength multiplexing cannot be obtained.

As described above, according to the present invention, partial products are integrated while adding digits to generate an added value, the added value is analog-digital converted to generate a digital value, and the digital value is digitally added. By doing so, optical multiplication can be performed at a higher speed.

The present invention is not limited to the embodiments described above, and many modifications and combinations can be implemented by a person having ordinary knowledge in the field within the technical idea of the present invention. That is clear.

101... Partial product generation section, 102... Addition section, 103... Conversion section, 104... Digital addition section.

Claims (4)

A partial product generation unit for generating N×N partial products by the N-bit (N is an integer of 2 or more) first digital signal and the N-bit second digital signal;
An adding unit that adds the partial products while integrating the digits to generate an added value;
A conversion unit that generates a digital value by analog-digital converting the added value;
And a digital adder that digitally adds the digital values. The optical multiplier according to claim 1, wherein
The partial product generation unit and the addition unit correspond to the light of different wavelengths to the generation of the partial product, and simultaneously process the generation of the partial product and the generation of the addition value by wavelength multiplexing. And an optical multiplier. The optical multiplier according to claim 1, wherein
The optical multiplier, wherein the partial product generation unit generates the partial product by a second-order Booth method. A first step of generating N×N partial products of the N-bit (N is an integer of 2 or more) first digital signal and the N-bit second digital signal;
A second step of adding the partial products while integrating the digits to generate an added value;
A third step of analog-to-digital converting the added value to generate a digital value,
And a fourth step of digitally adding the digital values.