JP6698186B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a power semiconductor module widely adopted in inverter circuits and the like.

  For example, Patent Documents 1 and 2 each disclose a semiconductor device including an island such as a die pad and a semiconductor chip arranged on the island. The semiconductor chip is bonded to the island using molten solder.

JP, 2011-155286, A JP-A-6-37122

Conventionally, joining of semiconductor chips has been achieved by crushing molten plate-shaped solder or solder paste with the semiconductor chips and spreading them widely in the space between the semiconductor chips and the islands. However, the conventional methods involve problems of solder leakage and solder shrinkage.
Solder leakage is a phenomenon in which molten solder leaks to the outside of the semiconductor chip. The leaked solder rides on the surface of the semiconductor chip, and this shortens the distance between the end of the back contact to the semiconductor chip and the surface of the semiconductor chip, and the withstand voltage of the semiconductor chip is the Reduce to less than withstand voltage.

  On the other hand, solder shrinkage is a phenomenon in which a space in which solder does not exist (a defective region) is generated between a semiconductor chip and an island. Since the defective region is finally filled with a resin having a low thermal conductivity or remains as a void in the empty region, the heat dissipation of the semiconductor chip may be deteriorated. Further, since a structure in which a part of the semiconductor chip is not supported by the solder and the part of the semiconductor chip is projected to the outside of the solder is formed, stress is likely to be concentrated on the root portion of the structure. Therefore, there is a possibility that cracks are likely to occur due to a thermal cycle in which high temperature and low temperature are repeated.

Therefore, there is a demand to solve both such solder leakage and solder shrinkage at low cost.
An object of the present invention is to provide a semiconductor device that can prevent solder shrinkage at a low cost and can suppress a decrease in breakdown voltage even if solder leakage occurs.

The semiconductor device of the present invention has a semiconductor chip having a pad on the surface, a conductive member supporting the semiconductor chip, a bonding material provided between the conductive member and the semiconductor chip, and one end on the pad. A contact block arranged, a recess formed on the surface of the conductive member and spaced apart from a region immediately below the semiconductor chip, and a resin package sealing the semiconductor chip, the conductive member, and the contact block. Including, the bonding material has a leaking portion leaked to the outside of the semiconductor chip , and from the region immediately below the semiconductor chip to the recess, extending to the region on the conductive member, The depth of the recess is 1/100 to 1/10 of the thickness of the contact block.

FIG. 1 is a schematic plan view of a power semiconductor module showing an embodiment of the present invention. FIG. 2 is a cross-sectional view that appears when the power semiconductor module of FIG. 1 is cut along the II-II cutting line. FIG. 3 is a cross-sectional view that appears when the power semiconductor module of FIG. 1 is cut along a III-III cutting line. FIG. 4 is a cross-sectional view that appears when the power semiconductor module of FIG. 1 is cut along the line IV-IV. FIG. 5 is an enlarged view of a region surrounded by a broken line V in FIG. FIG. 6 is a line graph showing the relationship between the load on the semiconductor chip and the amount of solder leakage. FIG. 7 is a line graph showing the relationship between the load on the semiconductor chip and the amount of shrinkage of solder. FIG. 8 is a contour line graph showing the distribution of the amount of solder leakage when the load on the semiconductor chip and the chip area/solder area are changed. FIG. 9 is a contour line graph showing the distribution of the amount of solder shrinkage when the load on the semiconductor chip and the chip area/solder area are changed. 10A and 10B are views showing a part of the manufacturing process of the power semiconductor module of FIG. 1, in which FIG. 10A is a plan view and FIG. 10B is a sectional view. 11A and 11B are views showing the next step of FIGS. 10A and 10B, where FIG. 11A is a plan view and FIG. 11B is a sectional view. 12A and 12B are views showing the next step of FIGS. 11A and 11B, wherein FIG. 12A is a plan view and FIG. 12B is a sectional view. 13A and 13B are views showing the next step of FIGS. 12A and 12B, wherein FIG. 13A is a plan view and FIG. 13B is a sectional view. 14A and 14B are views showing the next step of FIGS. 13A and 13B, wherein FIG. 14A is a plan view and FIG. 14B is a sectional view.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
<Configuration of Module According to Embodiment of Present Invention>
FIG. 1 is a schematic plan view of a power semiconductor module 1 showing an embodiment of the present invention. FIG. 2 is a cross-sectional view that appears when the power semiconductor module 1 of FIG. 1 is cut along the II-II cutting line. FIG. 3 is a cross-sectional view that appears when the power semiconductor module 1 of FIG. 1 is cut along the III-III cutting line. FIG. 4 is a cross-sectional view that appears when the power semiconductor module 1 of FIG. 1 is cut along the IV-IV cutting line. FIG. 5 is an enlarged view of a region surrounded by a broken line V in FIG.

The power semiconductor module 1 includes a high side assembly 2, a low side assembly 3, a relay terminal 4, and a resin package 5. As shown in FIGS. 1 and 2, the high side assembly 2 and the low side assembly 3 are arranged adjacent to each other with a gap 62 therebetween.
The high-side assembly 2 includes a high-side heat dissipation block 6, a high-side IGBT 7 (IGBT: Insulated Gate Bipolar Transistor) and a high-side FRD 8 (FRD: Fast Recovery Diode), a high-side contact block 9, and a high-side emitter terminal 10. , And the high side gate terminal 11. Hereinafter, the high-side IGBT 7 and the high-side FRD 8 may be simply referred to as the chip 7 and the chip 8 (the same applies to the low-side IGBT 30 and the low-side FRD 31 described later).

The high side heat dissipation block 6 is made of, for example, copper (Cu). In this embodiment, the high-side heat dissipation block 6 is formed in a slightly flat rectangular parallelepiped shape (rectangular shape in plan view).
A plurality of escape grooves 13 are formed on the surface 12 of the high-side heat dissipation block 6. Here, the escape groove 13 is shallowly formed in a region (surface portion) near the surface 12 of the high side heat dissipation block 6. In other words, in the high side heat dissipation block 6, a thick metal portion remains below the relatively shallow escape groove 13. This structure prevents the high side heat dissipation block 6 from bending at the escape groove 13 as a boundary due to heat or stress. For example, when the high-side heat dissipation block 6 has a thickness of 1 mm to 20 mm, the escape groove 13 may have a depth of about 0.01 mm to 2 mm.

In this embodiment, each of the escape grooves 13 extends along a pair of short sides of the high-side heat dissipation block 6 so as to connect the pair of long-side end surfaces 14 of the high-side heat dissipation block 6 as shown in FIG. 1. Has been formed. As a result, one end and the other end of each escape groove 13 are opened at the end face 14 of the high side heat dissipation block 6, respectively.
A step structure 15 is formed on the side surface of each escape groove 13. In this embodiment, the step structure 15 is a structure formed by dividing the escape groove 13 into two steps in the depth direction, as shown in FIG. Thus, the step structure 15 includes the first groove 16 and the second groove 17 which is formed by further recessing the bottom of the first groove 16 and is narrower than the first groove 16. As shown in FIG. 1, the step structure 15 is formed continuously along the longitudinal direction of the escape groove 13 from one end surface 14 of the high side heat dissipation block 6 to the other end surface 14.

  Note that the number of steps of the step structure 15 is not limited to two, and may be three, four, or more. Further, the depths of the plurality of grooves (the first and second grooves 16 and 17 in this embodiment) may be the same or different from each other. Further, the step structure 15 may be selectively formed in the longitudinal direction of the escape groove 13. For example, a plurality of second grooves 17 may be formed at intervals along the longitudinal direction of the escape groove 13. Furthermore, the step structure 15 may not be formed.

  Since the escape grooves 13 are formed along the long sides of the high-side heat dissipation block 6 at intervals, the surface 12 of the high-side heat dissipation block 6 is divided into a plurality of regions. In this embodiment, as shown in FIG. 1, four escape grooves 13 are formed in parallel with each other. As a result, on the surface 12 of the high-side heat dissipation block 6, three chip regions 18 having a quadrangular shape in plan view, which are sandwiched by the escape grooves 13 adjacent to each other, are formed.

  One high side IGBT 7 and one high side FRD 8 are arranged in each chip region 18. Specifically, the high-side IGBT 7 and the high-side FRD 8 are arranged along the escape groove 13 in this order from the side distant from the low-side assembly 3 in this order. A predetermined space is provided between the high side IGBT 7 and the high side FRD 8 and the escape groove 13.

The high-side IGBT 7 has an emitter pad 19 and a gate pad 20 on its upper surface and a collector pad 21 on its back surface. On the other hand, the high side FRD8 has an anode pad 22 on its upper surface and a cathode pad (not shown) on its back surface.
The high-side IGBT 7 and the high-side FRD 8 are joined to the high-side heat dissipation block 6 on the back surface by using the solder material 23, respectively. Thus, the collector of the high side IGBT 7 and the cathode of the high side FRD 8 are electrically connected to the high side heat dissipation block 6, respectively. 2 and 3, the emitter pad 19, the gate pad 20, and the collector pad 21 are not shown for clarity.

The solder material 23 is provided between the high side IGBT 7 and the high side FRD 8 and the high side heat dissipation block 6. In addition, the solder material 23 may have a portion 26 that leaks outward from the peripheral edges of the high side IGBT 7 and the high side FRD 8. The leak-out portion 26 may enter the escape groove 13 as shown by a broken line in FIG. 5, for example.
Further, a P (Positive) terminal 25 is integrally connected to the high side heat dissipation block 6. The P terminal 25 is connected to the positive side (Positive side) of the circuit power supply. The power supply voltage supplied from the P terminal 25 is applied to the collector of the high side IGBT 7 and the cathode of the high side FRD 8 via the high side heat dissipation block 6. In this embodiment, the P terminal 25 has the same thickness as the high-side heat dissipation block 6 as shown in FIG. 3, and protrudes from the end face 24 of the short side of the high-side heat dissipation block 6 so as to straddle the inside and outside of the resin package 5. ing. That is, the P terminal 25 is connected to the end surface 24 different from the end surface 14 where the escape groove 13 of the high side heat dissipation block 6 is open. A through hole 54 is formed in the exposed portion of the P terminal 25.

  The high side contact block 9 is made of, for example, copper (Cu). The high-side contact blocks 9 are arranged one by one on the emitter pad 19 of the high-side IGBT 7 and the anode pad 22 of the high-side FRD 8 using the solder material 27. As a result, the high-side contact block 9 is electrically connected to the emitter pad 19 of the high-side IGBT 7 and the anode pad 22 of the high-side FRD8.

  The high-side emitter terminal 10 and the high-side gate terminal 11 are arranged on the opposite side of the low-side assembly 3 with respect to the high-side heat dissipation block 6 and extend inside and outside the resin package 5. The high side emitter terminal 10 and the high side gate terminal 11 are electrically connected to the emitter pad 19 and the gate pad 20, respectively, using a bonding wire 28.

  The low-side assembly 3 includes a low-side heat dissipation block 29, a low-side IGBT 30 and a low-side FRD 31, a low-side contact block 32, a low-side emitter terminal 33, a low-side gate terminal 34, and an N (Negative) terminal 50.

  The low side heat dissipation block 29 is made of, for example, copper (Cu). In this embodiment, the low-side heat dissipation block 29 is formed in the same flattened rectangular parallelepiped shape (rectangular shape in plan view) as the high-side heat dissipation block 6. The high-side heat dissipation block 6 and the low-side heat dissipation block 29 are arranged adjacent to each other such that their long side end faces 14 and 37 face each other.

  A plurality of escape grooves 36 are formed on the surface 35 of the low-side heat dissipation block 29. Here, the escape groove 36 is shallowly formed in a region (surface portion) near the surface 35 of the low-side heat dissipation block 29. In other words, in the low-side heat dissipation block 29, a thick metal portion remains below the relatively shallow escape groove 36. This structure prevents the low-side heat dissipation block 29 from bending around the escape groove 36 due to heat or stress. For example, when the low-side heat dissipation block 29 has a thickness of 1 mm to 20 mm, the escape groove 36 may have a depth of about 0.01 mm to 2 mm.

In this embodiment, each escape groove 36 is formed along a pair of short sides of the low side heat dissipation block 29 so as to connect the pair of long side end faces 37 of the low side heat dissipation block 29, as shown in FIG. 1. ing. As a result, one end and the other end of each escape groove 36 are open at the end surface 37 of the low-side heat dissipation block 29.
A step structure 38 is formed on the side surface of each escape groove 36. In this embodiment, the step structure 38 is a structure formed by dividing the escape groove 36 into two steps in the depth direction, like the step structure 15 of FIG. That is, the step structure 38 includes a first groove and a second groove (both not shown) having the same structure as the first groove 16 and the second groove 17 in FIG. As shown in FIG. 1, the step structure 38 is continuously formed along the longitudinal direction of the escape groove 36 from one end surface 37 of the low side heat dissipation block 29 to the other end surface 37.

  The escape grooves 36 are formed at intervals along the long sides of the low-side heat dissipation block 29, so that the surface 35 of the low-side heat dissipation block 29 is divided into a plurality of regions. In this embodiment, four escape grooves 36 are formed in parallel with each other. As a result, on the surface 35 of the low-side heat dissipation block 29, three chip regions 41 having a quadrangular shape in plan view, which are sandwiched by the escape grooves 36 adjacent to each other, are formed. The escape groove 36 may be formed along the longitudinal direction of the escape groove 13 of the high side heat dissipation block 6 as shown in FIG. 1, or along the direction orthogonal to the longitudinal direction of the escape groove 13. It may be formed.

  One low side IGBT 30 and one low side FRD 31 are arranged in each chip region 41. Specifically, the low-side IGBT 30 and the low-side FRD 31 are arranged along the escape groove 36 at intervals in this order from the side distant from the high-side assembly 2. A predetermined space is provided between the low side IGBT 30 and the low side FRD 31 and the escape groove 36.

  The low-side IGBT 30 has an emitter pad 42 and a gate pad 43 on its upper surface and a collector pad (not shown) on its back surface. On the other hand, the low side FRD 31 has an anode pad 44 on its upper surface and a cathode pad (not shown) on its back surface. The low-side IGBT 30 and the low-side FRD 31 are joined to the low-side heat dissipation block 29 on the back surface using a solder material 45, respectively. As a result, the collector of the low-side IGBT 30 and the cathode of the low-side FRD 31 are electrically connected to the low-side heat dissipation block 29, respectively.

  The solder material 45 is provided between the low-side IGBT 30 and the low-side FRD 31 and the low-side heat dissipation block 29. Like the solder material 23, the solder material 45 may have a portion 39 that leaks outward from the peripheral edges of the low-side IGBT 30 and the low-side FRD 31. The leak-out portion 39 may be in the escape groove 36 like the leak-out portion 26 of FIG.

  The output terminal 46 is integrally connected to the low-side heat dissipation block 29. The output terminal 46 is connected to the load of the circuit. In this embodiment, the output terminal 46 has the same thickness as the low-side heat dissipation block 29, as shown in FIG. 4, and protrudes from the end surface 47 of the short side of the low-side heat dissipation block 29 so as to extend over the inside and outside of the resin package 5. . That is, the output terminal 46 is connected to the end surface 47 different from the end surface 37 where the escape groove 36 of the low-side heat dissipation block 29 is open. Further, in this embodiment, the end face 47 to which the output terminal 46 is connected is the end face 47 opposite to the end face 47 adjacent to the P terminal 25. As a result, the output terminal 46 extends in the direction opposite to the P terminal 25. A through hole 55 is formed in the exposed portion of the output terminal 46.

  The low side contact block 32 is made of, for example, copper (Cu). The low-side contact blocks 32 are arranged one by one on the emitter pad 42 of the low-side IGBT 30 and the anode pad 44 of the low-side FRD 31 using the solder material 45. As a result, the low-side contact block 32 is electrically connected to the emitter pad 42 of the low-side IGBT 30 and the anode pad 44 of the low-side FRD 31.

  The low-side emitter terminal 33 and the low-side gate terminal 34 are arranged on the opposite side of the high-side assembly 2 with respect to the low-side heat dissipation block 29, and extend inside and outside the resin package 5. The low side emitter terminal 33 and the low side gate terminal 34 are electrically connected to the emitter pad 42 and the gate pad 43, respectively, using a bonding wire 49.

The N terminal 50 is made of, for example, copper (Cu), and is formed in a block shape having the same thickness as the high-side heat dissipation block 6 and the low-side heat dissipation block 29. The N terminal 50 is collectively joined to the low side contact block 32 on the low side IGBT 30 and the low side FRD 31 using a solder material 51.
Specifically, the N terminal 50 extends along the long side of the low-side heat dissipation block 29 so as to cross the plurality of chip regions 41 in a plan view. The laying region of the N terminal 50 in the longitudinal direction extends from one end surface 47 of the low-side heat dissipation block 29 to the outside of the resin package 5, for example. As a result, the N terminal 50 projects from the resin package 5 and defines a space 52 between the N-side terminal 50 and the low-side heat dissipation block 29 inside the resin package 5. A through hole 56 is formed in the exposed portion of the N terminal 50. In this embodiment, the protruding direction of the N terminal 50 is the same as the protruding direction of the P terminal 25, that is, the protruding direction of the output terminal 46 included in the same low-side assembly 3 is opposite. As a result, the N terminal 50 and the output terminal 46 do not overlap with each other and do not interfere with each other.

On the other hand, in the width direction, the N terminal 50 is formed narrower than the low-side heat dissipation block 29. The difference in width between the two allows the low-side heat dissipation block 29 to have a contact region 53 formed laterally from the N terminal 50 and formed of a part of the chip region 41.
The N terminal 50 is connected to the negative side (Negative side) of the circuit power supply. The power supply voltage supplied from the N terminal 50 is applied to the emitter of the low side IGBT 30 and the anode of the low side FRD 31 via the low side contact block 32.

  The relay terminal 4 is made of copper (Cu), for example, and is formed with the same thickness as the high-side heat dissipation block 6 and the low-side heat dissipation block 29. The relay terminal 4 is arranged above the high-side heat dissipation block 6 and the low-side heat dissipation block 29, straddling them. As a result, the relay terminal 4 defines a space 57 between the high-side heat dissipation block 6 and the low-side heat dissipation block 29. Specifically, the relay terminal 4 extends along the long sides of the high-side heat dissipation block 6 and the low-side heat dissipation block 29 so as to cross the plurality of chip regions 18 and 41 in a plan view. The laying region of the relay terminal 4 in the longitudinal direction extends from one end surface 24, 47 of each heat dissipation block 6, 29 to the other end surface 24, 47, for example.

In the high side assembly 2, the relay terminals 4 are collectively joined to the high side contact blocks 9 on the high side IGBT 7 and the high side FRD 8 using the solder material 58. On the other hand, the relay terminal 4 is joined to the low-side heat dissipation block 29 using the relay block 59 in the low-side assembly 3.
The relay blocks 59 are arranged one by one in each contact region 53 of the low-side heat dissipation block 29 with the solder material 60 interposed therebetween. Further, the solder material 61 is also provided between each relay block 59 and the relay terminal 4.

As shown in FIG. 2, the current from the emitter of the high-side IGBT 7 and the anode of the high-side FRD 8 passes through the relay terminal 4, the relay block 59, and the low-side heat dissipation block 29 in order, and flows to the collector of the low-side IGBT 30 and the cathode of the low-side FRD 31. ..
The resin package 5 is made of, for example, an epoxy resin. The resin package 5 covers the high side assembly 2, the low side assembly 3, the relay terminal 4, and the like so that the back surfaces 63 and 64 of the high side heat dissipation block 6 and the low side heat dissipation block 29 are exposed. The heat generated in each of the chips 7, 8, 30, 31 is dissipated from the back surfaces 63, 64 of the high side heat dissipation block 6 and the low side heat dissipation block 29. Further, in this embodiment, a part of the resin package 5 enters the spaces 52 and 57. As a result, the part of the resin package 5 is held by being sandwiched between the lower conductive member (the high side heat dissipation block 6 and the low side heat dissipation block 29) and the upper conductive member (the relay terminal 4 and the N terminal 50). To be done. As a result, the adhesion of the resin package 5 to the high side assembly 2, the low side assembly 3, the relay terminal 4, etc. can be improved.
<Pre-evaluation until the present invention>
The present inventors evaluated the relationship between the solder leak amount (solder shrinkage amount) and the load on the semiconductor chip (IGBT) by experiments in order to investigate the causes of solder leak and solder shrinkage at the time of joining the semiconductor chips. The results are shown in FIGS. 6 and 7 are line graphs showing the relationship between the load on the semiconductor chip and the amount of solder leakage (solder shrinkage). Here, the amount of solder leakage to the semiconductor chip (the amount of solder shrinkage) is considered, and the escape groove described later is not considered. 8 and 9 are contour line graphs showing the distribution of the amount of solder leakage (solder shrinkage amount) when the load on the semiconductor chip and the chip area/solder area are changed. Contour lines were drawn for the range in which the experiment was conducted. Note that in FIGS. 8 and 9, the numerical values attached to the respective lead lines indicate the solder leak amount (mm ³ ) and the solder shrinkage amount (mm ² ) in the regions indicated by the lead lines, respectively.

According to FIGS. 6 to 9, it has been found that the solder leakage amount can be suppressed substantially as the load is reduced, regardless of the size of the chip area/the solder area. However, regarding the amount of solder shrinkage, it was conventionally thought that the load on the semiconductor chip was insufficient and the amount of solder was insufficient. For example, according to the data of FIG. 7 (IGBT), despite the increased load from 40g to 160 g, the solder shrinkage amount is increased from about 1.6 mm ² to about 2.2 mm ^2. That is, conventionally, it has been considered that the solder leakage and the solder shrinkage have a trade-off relationship, but it has been found from FIGS. 6 to 9 that this trade-off is not always correct.

Therefore, the inventors of the present application form the escape grooves 13 and 36 whose both ends are open in the high-side heat dissipation block 6 and the low-side heat dissipation block 29 as described above, and the chip area/solder area in the manufacturing process in an appropriate range. Found to set. As a result, it has been found that it is possible to provide a semiconductor device that can prevent solder shrinkage and can suppress a decrease in breakdown voltage even if solder leakage occurs at low cost.
<Process of Manufacturing Module According to Embodiment of Present Invention>
Below, as a result of verifying FIG. 6 to FIG. 9, the above-mentioned high side assembly 2 will be taken as an example of what kind of form should be specifically joined in the manufacturing process of the semiconductor device. Explain.

  10(a), (b) to 14(a), (b) are views showing a part of the manufacturing process of the power semiconductor module 1 of FIG. 1 (manufacturing process of the high side assembly 2) in process order. 10A is a plan view corresponding to FIG. 1, and FIG. 10B is a cross-sectional view corresponding to FIG. 10(a)(b) to 14(a)(b), the reference numerals shown in FIGS. 1 and 5 may be omitted for clarity.

In order to manufacture the high side assembly 2, first, as shown in FIGS. 10A and 10B, the high side heat dissipation block 6 in which the escape groove 13 is formed is prepared. The escape groove 13 can be formed, for example, by molding the high side heat dissipation block 6 with a mold and then pressing the surface 12.
Next, as shown in FIGS. 11A and 11B, the plate-shaped solder 65 is arranged at a predetermined position in the chip area 18. The size of the plate-shaped solder 65 is set such that the ratio (chip area/solder area) to the chip size (area) of the high side IGBT 7 and the high side FRD 8 is 1 or less. In this embodiment, the plate-like solder 65 having a size smaller than that of each of the chips 7 and 8 is used within the above range. A solder paste may be used instead of the plate-shaped solder 65.

Next, as shown in FIGS. 12A and 12B, the high-side IGBT 7 and the high-side FRD 8 are arranged on the respective plate-shaped solders 65.
Next, as shown in FIGS. 13A and 13B, a jig 66 for applying a load is installed on the high side heat dissipation block 6.
The jig 66 has a plurality of openings 67 according to the arrangement pattern of the high side IGBT 7 and the high side FRD 8. Each of the openings 67 has a smaller area than the high side IGBT 7 and the high side FRD8. Further, the jig 66 has a guide portion 69 that is selectively raised from the peripheral edge 68 of the opening 67 in a portion facing the escape groove 13. The guide portion 69 may be formed in a stripe shape like the escape groove 13 or may be selectively formed around the opening 67.

  Then, the jig 66 aligns the openings 67 with the chips 7 and 8, and is installed so that the peripheral edges 68 of the openings 67 contact the peripheral edges of the chips 7 and 8. From this state, the plate-shaped solder 70 and the high side contact block 9 are further placed on the chips 7 and 8 exposed from the opening 67.

  Next, as shown in FIGS. 14A and 14B, a load is applied to the high side contact block 9 and the jig 66 together with heating. As a result, the melted plate-shaped solder 65 is crushed and spread by the chips 7 and 8 to form the solder material 23. Further, the plate-shaped solder 70 is also melted to form the solder material 27. At this time, since the peripheral edges of the chips 7 and 8 are pressed by the opening peripheral edge 68 of the jig 66, the chips 7 and 8 can be evenly loaded. As a result, it is possible to prevent the molten solder from leaking out in a specific direction. Thereby, the amount of leakage when the solder material 23 leaks can be dispersed along the peripheral edges of the chips 7 and 8. Through the above steps, the high side assembly 2 is obtained.

Then, in order to manufacture the power semiconductor module 1, after the low side assembly 3 is manufactured by the same method as the high side assembly 2, both the assemblies 2 and 3 are connected by the relay terminal 4, and then these are connected by the resin package 5. It may be sealed.
According to the above manufacturing method, the area ratio (chip area/solder area) between the chips 7 and 8 and the plate-like solder 65 is set to 1 or less when joining the high side IGBT 7 and the high side FRD 8. As a result, solder shrinkage can be suppressed regardless of the magnitude of the load applied to the high side IGBT 7 and the high side FRD 8. In particular, if the area ratio is 0.8 or less and a large amount of solder is used, solder shrinkage can be prevented.

  On the other hand, since the area of the plate-like solder 65 is relatively large with respect to the area of the chips 7 and 8, solder leakage to the chips 7 and 8 may occur as shown in FIG. However, even if the solder leaks out, the solder can be guided to the escape groove 13. Particularly, in this embodiment, the escape grooves 13 are formed on both sides of each chip region 18, and the guide portions 69 are formed on the jig 66. Therefore, the leaked solder can be guided to the escape groove 13. That is, here, when considering a new solder leak to the outside of the region including the escape groove 13 (solder leak outside the region), the area ratio is 1 or less and the outside solder leak can be set to 0 (zero). it can. As a result, it is possible to prevent a part of the solder material 23 from riding on the surfaces of the chips 7 and 8, and thus it is possible to suppress a decrease in withstand voltage. On the other hand, if the area ratio is less than 0.6, excess solder overflows from the open end of the escape groove 13, so the area ratio is preferably 0.6 or more.

  Further, one end and the other end of each escape groove 13 are open at the end face 14 of the high side heat dissipation block 6, respectively. Therefore, for example, when the escape groove 13 is formed by pressing the high-side heat dissipation block 6, excess copper material that is extruded can escape to the open end of the escape groove 13. As a result, it is possible to prevent the extruded copper material from remaining as a raised object in the vicinity of the escape groove 13, so that a working operation for removing the raised object is not necessary after pressing. As a result, the cost increase required to form the escape groove 13 can be suppressed to a relatively low level. Moreover, in this embodiment, the escape groove 13 is formed along the short side of the high side heat dissipation block 6. Therefore, as compared with the case where the escape groove 13 is formed along the long side, the processing size of the high side heat dissipation block 6 for forming the escape groove 13 can be shortened. As a result, the cost increase due to the formation of the escape groove 13 can be further suppressed.

  Then, once the solder enters the escape groove 13, it can be guided to the second groove 17 located at a relatively deep position by its own weight. Therefore, if the amount of solder leakage is about the volume of the second groove 17, all the leaked solder can be retained in the deep region (second groove 17) of the escape groove 13. As a result, it is possible to suppress the backflow of the solder in the escape groove 13, and it is possible to improve the withstand voltage reliability of the power semiconductor module 1.

Although the embodiments of the present invention have been described above, the present invention can be implemented in other forms.
For example, the above-described embodiment shows an example in which the escape grooves 13 and 36 are formed in the high-side heat dissipation block 6 and the low-side heat dissipation block 29 used as heat sinks. However, the structure such as the escape grooves 13 and 36 can be formed in, for example, the island of the lead frame.

Further, the high-side heat dissipation block 6 and the low-side heat dissipation block 29 do not have to be rectangular in plan view. For example, in a plan view, it may be another polygon (for example, a triangle, a pentagon, etc.), a circle, or the like.
Further, the escape grooves 13 and 36 do not have to be formed in a stripe shape, and may be formed in a meandering shape, for example.

Further, the present invention can be applied not only to power semiconductor modules, but also to other module products, discrete products and the like.
In addition, various design changes can be made within the scope of the matters described in the claims.
In addition to the inventions described in the claims, the following features can be extracted from the contents of the above-described embodiments.

  For example, a semiconductor chip, a conductive member supporting the semiconductor chip, a bonding material provided between the conductive member and the semiconductor chip, and one end and the other end are respectively connected to the peripheral end of the conductive member. An escape groove formed on the surface of the conductive member, disposed apart from the semiconductor chip, for releasing the bonding material leaking from between the semiconductor chip and the conductive member in a direction away from the semiconductor chip. And the area ratio of the semiconductor chip and the bonding material (chip area/bonding material area) is 1.0 or less.

  This semiconductor device is a conductive member having a relief groove formed on its surface, and a conductive member in which a predetermined chip area is defined by connecting one end and the other end of the relief groove to the peripheral end of the conductive member is prepared. A step of disposing a bonding material in the chip area, a step of disposing a semiconductor chip on the bonding material, and applying a load to the semiconductor chip while melting the bonding material to form the semiconductor chip. Including a step of bonding to the conductive member, the escape groove is a groove for allowing the bonding material leaked from between the semiconductor chip and the conductive member to escape in a direction away from the semiconductor chip, It can be manufactured by a method of manufacturing a semiconductor device, in which an area ratio between the semiconductor chip and the bonding material (chip area/bonding material area) is 1.0 or less.

  According to this method, even if the chip area/bonding material area is 1.0 or less, the solder shrinkage can be prevented regardless of the load applied to the semiconductor chip. Since the area of the bonding material is relatively large with respect to the area of the semiconductor chip, solder leakage may occur. However, even if the solder leaks out, the solder can be guided to the escape groove. As a result, it is possible to prevent the solder from riding on the surface of the semiconductor chip, and to prevent the breakdown voltage from decreasing.

  In addition, one end and the other end of the escape groove are connected to the peripheral end of the conductive member, respectively. That is, one end and the other end of the escape groove are open at the peripheral end of the conductive member. Therefore, for example, when the conductive member is pressed to form the escape groove, excess conductive material extruded can escape to the open end of the escape groove. As a result, it is possible to prevent the extruded conductive material from remaining as a raised object in the vicinity of the escape groove, so that a working operation for removing the raised object is not necessary after press working. As a result, the cost increase required for forming the escape groove can be suppressed to a relatively low level.

In the method for manufacturing a semiconductor device, the area ratio (chip area/bonding material area) between the semiconductor chip and the bonding material may be 0.6 to 0.8. Further, in the semiconductor device, part of the bonding material may or may not enter the escape groove.
In the semiconductor device, a plurality of the escape grooves may be formed on the surface of the conductive member, and the semiconductor chip may be arranged in a chip region sandwiched by the escape grooves.

In this configuration, even if the bonding material leaks to the left or right of the semiconductor chip, the escape groove is always formed in the vicinity thereof, so that the solder can be reliably prevented from running on the surface of the semiconductor chip.
In the semiconductor device, the plurality of escape grooves may be formed in stripes parallel to each other.

The semiconductor device may further include a step structure formed on a side surface of the escape groove.
With this configuration, it is possible to prevent the bonding material once entering the escape groove from flowing back.
Therefore, the breakdown voltage reliability of the semiconductor device can be improved.
In the semiconductor device, the step structure is a structure formed by dividing the escape groove into a plurality of steps in the depth direction, and may be formed from the one end to the other end of the escape groove. ..

In the semiconductor device, the conductive member may have an end face forming a peripheral end thereof, and the one end and the other end of the escape groove may be open at the end face.
In the semiconductor device, the surface of the conductive member may be formed in a rectangular shape, and the escape groove may be formed along a pair of short sides of the rectangular conductive member.

With this configuration, the processing dimension of the conductive member for forming the escape groove can be shortened as compared with the case where the escape groove is formed along the pair of long sides. As a result, the cost increase associated with the formation of the escape groove can be further suppressed.
The semiconductor device is disposed on the semiconductor chip, and the semiconductor device is inserted into a space between the second conductive member and a second conductive member that faces the conductive member with a space therebetween. It may further include a chip, a resin package that seals the conductive member, and the second conductive member.

In this configuration, a part of the resin package is held by sandwiching the part with the conductive member and the second conductive member. As a result, the adhesion of the resin package to the semiconductor chip, the conductive member and the second conductive member can be improved.
In the semiconductor device, the conductive member may have a back surface exposed from the resin package and may function as a heat sink.

  The semiconductor device includes a high side base member serving as the conductive member, a high side assembly including a high side switching element serving as the semiconductor chip, and a high side assembly disposed apart from the high side assembly. A low-side base member as a member, and a low-side assembly including a low-side switching element as the semiconductor chip disposed on the low-side assembly, and a resin package for sealing the high-side assembly and the low-side assembly, a power semiconductor module, It may be.

In the semiconductor device, the back surfaces of the high-side base member and the low-side base member may be exposed from the resin package, and may serve as heat sinks.
The semiconductor device is arranged on the high-side terminal integrally formed with the high-side base member so as to protrude from the resin package, and on the low-side switching element so as to protrude from the resin package, with a space therebetween. And a low side terminal facing the low side base member.

The semiconductor device may further include a relay member disposed on the high-side switching element and electrically connected to the low-side base member.
In the method for manufacturing a semiconductor device, a step of installing a jig in which an opening having a plane area smaller than that of the semiconductor chip is formed so that a peripheral edge of the opening is in contact with a peripheral edge of the semiconductor chip; The method further includes a step of disposing a second bonding material on the upper surface of the semiconductor chip and a step of disposing a conductive block on the second bonding material, wherein the bonding step applies a load to the peripheral edge of the semiconductor chip by the jig. It may include a step of applying.

In this method, the load can be evenly applied to the semiconductor chip, so that it is possible to prevent the bonding material from leaking unevenly in a specific direction. With this, the amount of leakage when the bonding material leaks can be dispersed along the peripheral edge of the semiconductor chip, so that it is possible to better prevent the solder from running onto the surface of the semiconductor chip.
In the method of manufacturing a semiconductor device, the jig may be formed by selectively raising a part of a back surface of the jig with respect to a ground plane for the semiconductor chip, and may have a guide portion surrounding the semiconductor chip. Good.

  According to this method, even if a large amount of the bonding material leaks, the bonding material can be reliably guided to the escape groove by the guide portion of the jig.

1 Power semiconductor module 2 High side assembly 3 Low side assembly 4 Relay terminal 5 Resin package 6 High side heat dissipation block 7 High side IGBT
8 high side FRD
9 High-side contact block 12 (High-side heat dissipation block) surface 13 Escape groove 14 (Long side of high-side heat dissipation block) End face 15 Step structure 16 First groove 17 Second groove 18 Chip area 23 Solder material 24 (High side) Short side of heat dissipation block) End face 25 P terminal 26 Leakage portion 27 Solder material 29 Low side heat dissipation block 30 Low side IGBT
31 Low Side FRD
32 low side contact block 35 (low side heat dissipation block) surface 36 escape groove 37 (long side of low side heat dissipation block) end face 38 step structure 39 leakage part 41 chip area 45 solder material 46 output terminal 47 (short side of low side heat dissipation block) end face 50 N terminal 51 Solder material 52 Space 53 Contact area 57 Space 59 Relay block 63 (High side heat dissipation block) Back surface 64 (Low side heat dissipation block) Back surface 65 Plate-shaped solder 66 Jig 67 (Jig) opening 68 (Jig opening) ) Edge 69 Guide 70 Plate solder

Claims (19)

A semiconductor chip having a pad on the surface;
A conductive member supporting the semiconductor chip,
A bonding material provided between the conductive member and the semiconductor chip,
A contact block having one end disposed on the pad,
A concave portion formed on the surface of the conductive member, the concave portion being arranged apart from the region directly below the semiconductor chip,
A resin package for sealing the semiconductor chip, the conductive member and the contact block,
The bonding material has a leaking portion that has leaked to the outside of the semiconductor chip, and from the region immediately below the semiconductor chip to the recess, extending to the region on the conductive member,
The semiconductor device, wherein the depth of the recess is 1/100 to 1/10 of the thickness of the contact block. The semiconductor device according to claim 1, wherein an area ratio (chip area/bonding material area) between the semiconductor chip and the bonding material is 1.0 or less. The semiconductor device according to claim 2 , wherein an area ratio between the semiconductor chip and the bonding material (chip area/bonding material area) is 0.6 to 0.8. The semiconductor device according to claim 1, wherein the contact block is made of copper. It said recess has one end and at least one of the other end is connected to the peripheral edge of the conductive member, a semiconductor device according to any one of claims 1-4. The semiconductor chip includes a power semiconductor chip, the semiconductor device according to any one of claims 1 to 5. A plurality of the recesses are formed on the surface of the conductive member,
The semiconductor chip, the plurality of which are arranged in the chip region between the recess, the semiconductor device according to any one of claims 1 to 6. Further comprising the formed step structure on the side surface of the recess, the semiconductor device according to any one of claims 1 to 7. The semiconductor device according to claim 8 , wherein the step structure is a structure formed by dividing the recess into a plurality of steps in the depth direction, and is formed over the entire side surface of the recess. Further comprising a second conductive member disposed on the semiconductor chip and facing the conductive member at a distance.
The resin package seals the semiconductor chip, the conductive member, the contact block, and the second conductive member so as to enter the space between the conductive member and the second conductive member. The semiconductor device according to any one of 1 to 9 . The conductive member, the rear surface is not exposed from the resin package, and plays a role of a heat sink, the semiconductor device according to any one of claims 1 to 10. The semiconductor device is
A second semiconductor chip,
A third conductive member that supports the second semiconductor chip and is arranged apart from the conductive member;
Wherein disposed on the other end of the contact block, the third further comprising a conductive member and electrically connected to the relay board, a semiconductor device according to any one of claims 1 to 11. The semiconductor device is
A high side base member as the conductive member, and a high side assembly including a high side switching element as the semiconductor chip arranged thereon,
A low-side assembly that is arranged apart from the high-side assembly and that includes a low-side base member as the conductive member, and a low-side switching element as the semiconductor chip arranged on the low-side base member;
The semiconductor device according to any one of claims 1 to 9 , which is a power semiconductor module including a resin package that seals the high side assembly and the low side assembly. 14. The semiconductor device according to claim 13 , wherein the high-side base member and the low-side base member each have a back surface exposed from the resin package and serve as a heat sink. A high-side terminal integrally formed with the high-side base member so as to project from the resin package;
The semiconductor device according to claim 13 , further comprising: a low-side terminal that is disposed on the low-side switching element so as to project from the resin package and that faces the low-side base member with a space therebetween. 16. The semiconductor device according to claim 13 , further comprising a relay member arranged on the high side switching element and electrically connected to the low side base member. The step structure includes a first recess, the bottom of the first recess is formed by further recessed, and a the narrow second concave portion than the first recess, according to claim 8 Semiconductor device. The semiconductor device according to claim 17 , wherein a difference in width between the first recess and the second recess is smaller than a width of the second recess. The leakage out portion, before SL has a surface opposite to the surface of the conductive member formed on the outside of the concave portion, the semiconductor device according to any one of claims 1 to 18.

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