JP6693081B2 - Integrated circuit and integrated circuit test method - Google Patents

Description

  The present invention relates to an integrated circuit and a test method for the integrated circuit.

There is a fail bit map (FBM) test as a method of acquiring fail bit information of all addresses of RAM (Random Access Memory) in an integrated circuit. In the FBM test, for example, a self-test (Built In Self Test, BIST) circuit is incorporated in an integrated circuit and a RAM test in the integrated circuit is executed.

JP, 2009-26372, A JP, 2010-40085, A

By the way, according to the conventional technology, the fail bit information and the fail address information are stored in a storage circuit that operates with a clock slower than the clock of the self-test circuit. For this reason, the conventional technique adopts a method of temporarily ending the test by the self-test circuit in order to obtain an error result such as fail address information. Therefore, it is not possible to acquire error result data such as a plurality of pieces of fail address information by executing the test by the self-test circuit once, resulting in a drawback that the number of times the test is repeated increases.

  Therefore, the present invention acquires a plurality of error results and a plurality of test target addresses in which an error has occurred in the test by the test circuit in the integrated circuit, reduces the repetition of the test by the test circuit in the integrated circuit, and uses the high-speed clock. An object of the present invention is to provide an integrated circuit capable of efficiently executing a test and a method of testing the integrated circuit.

  One aspect of the disclosed technology is exemplified by the following integrated circuit. The integrated circuit includes a storage unit, an address generation unit, a test execution unit, a plurality of result data storage units, and a plurality of address storage units, and a storage unit, an address generation unit, a test execution unit, a plurality of result data storage units, It has a first clock circuit that supplies a first clock to a plurality of address storage units. The integrated circuit further includes an external output unit and a second clock circuit that supplies the external output unit with a second clock that is slower than the first clock.

  The address generation unit generates a test target address in the storage unit. The test execution unit generates test result data at each test target address in the storage unit. The plurality of result data storage units sequentially store error result data when the test result is an error. The plurality of address storage units respectively store a plurality of test target addresses corresponding to the error result data held in the plurality of result data storage units. The external output unit stores the error result data in each of the plurality of result data storage units, stores the test target address in each of the plurality of address storage units, and then stores the error stored in each of the plurality of result data storage units. The result data and the test target address stored in each of the plurality of address storage units are output to the external device.

According to the present integrated circuit, a plurality of error results and a plurality of test target addresses in which an error has occurred are acquired by the test by the test circuit in the integrated circuit, the repetition of the test by the test circuit in the integrated circuit is reduced, and the high-speed clock is reduced. The test by can be efficiently performed.

6 is a flowchart illustrating a processing procedure of an FBM test according to the first embodiment. FIG. 3 is a circuit block diagram of the integrated circuit of the first embodiment and a diagram illustrating a configuration of an LSI tester that activates an FBM test in the present integrated circuit. This is an example of a fail bit pattern. It is an example of data held by a memory circuit when a fail bit pattern occurs. 6 is a flowchart illustrating a processing procedure of a high-speed FBM test executed by the integrated circuit of the first embodiment. 6 is a configuration diagram illustrating a configuration of an integrated circuit according to a second embodiment. FIG. 9 is a flowchart illustrating a processing procedure of a high-speed FBM test in the integrated circuit of the second embodiment. It is a figure which illustrates the structure of the memory circuit which memorize | stores 3 sets of fail bit information and fail address information. It is a figure which illustrates the timing of execution of a BIST test, data transfer, the restart / continuation of a BIST test, fail bit information, and fail address information. It is a figure which illustrates the data transferred to an LSI tester after a BIST test. It is a figure which illustrates the change of the value of each part when an error is detected in an integrated circuit. It is a figure which illustrates the change of the value of each part when an error is detected in an integrated circuit.

  Hereinafter, an integrated circuit according to an embodiment will be described with reference to the drawings. The configurations of the following embodiments are examples, and the present integrated circuit is not limited to the configurations of the embodiments.

[Embodiment 1]
An integrated circuit according to the first embodiment will be described with reference to FIGS. 1 to 5. This integrated circuit includes a memory, a BIST circuit that executes a BIST test of the memory, and a scan shift circuit that performs initial setting for the BIST test in the BIST circuit and reads the test result after the BIST test is completed. The scan shift circuit is connected to an LSI (Large Scale Integration) tester outside the integrated circuit. This integrated circuit executes the high-speed FBM test using the BIST circuit by the following procedure according to the command from the LSI tester. That is,
(1) This integrated circuit performs pass / fail determination at the test target address by the BIST test.
(2) Then, this integrated circuit provides the first specific address, which is the test target address when the first failure occurs during the BIST test, and the information of the first fail bit pattern indicating the error bit detected in the BIST test. Remember. Further, when the first fail bit pattern appears consecutively, the present integrated circuit stores during the BIST test the number of consecutive occurrences of the same fail bit pattern for the first fail bit pattern.
(3) Furthermore, when the second fail bit pattern different from the first fail bit pattern appears, the present integrated circuit causes the second specific address and the second fail bit where the second fail bit pattern appears. Memorize the pattern information. Further, when the second fail bit pattern appears consecutively, the present integrated circuit stores the number of consecutive occurrences of the same fail bit pattern for the second fail bit pattern during the BIST test.
(4) Then, this integrated circuit determines the last specified address so that the pass / fail judgment of the next BIST test starts at the address next to the last specified address at which the last fail bit information was obtained during the BIST test. Holds the address and prepares for the next BIST test.

In this integrated circuit, in (2) and (3) above, the fail bit pattern, the address where the fail bit pattern first appears, and the number of consecutive occurrences of the fail bit pattern are stored as a test result and a series of BIST After the test, it has a plurality of sets of storage units that can output the stored test results to an external LSI tester by scan shift.

The items (2) and (3) above store the fail address information during the BIST test, and the item (4) sets the test target address of the next BIST test without the BIST control circuit. This integrated circuit repeats this procedure up to the end of the test target address to reduce the time of the high-speed FBM test. The integrated circuit achieves the following effects.
(Effect 1) By executing the above items (2) and (3), this integrated circuit can skip storing fail bit information when the same fail bit pattern continues. Further, this integrated circuit can skip transfer of fail bit information when the same fail bit pattern continues.
(Effect 2) By executing the above items (2) and (3), this integrated circuit can transfer a plurality of fail bit information in one BIST test. That is, this integrated circuit has a circuit configuration capable of increasing fail bit information and fail address information that can be stored in one BIST test.

  FIG. 1 is a flowchart illustrating the processing procedure of the FBM test. This integrated circuit starts the BIST test according to the settings from the LSI tester (G1).

The integrated circuit sequentially accesses the test target address and executes the BIST test (G2). Then, when the same fail bit pattern appears in two test addresses before and after, the present integrated circuit stores the same fail bit pattern consecutive number of times and skips the address. Further, when the test result of the test target address is normal, that is, when it is determined that the test result is pass, the present integrated circuit skips the address. In this way, in the BIST test, this integrated circuit displays (a) different fail bit pattern information, (b) different fail address pattern generated fail address information, and (c) the same fail bit pattern consecutive number of times. Remember.

Then, the integrated circuit determines whether or not the data is stored in all the storage circuits or the test of the address in the predetermined range is completed (G3). When the data is not stored in all the storage circuits and the test of the predetermined address is not completed, the integrated circuit returns to the process of G2. On the other hand, when either the data is stored in the memory circuit in the predetermined range or the test of the address in the predetermined range is completed, this integrated circuit ends the BIST test (G4). .. Here, the address in the predetermined range is an address in the test range that can be continuously executed when the fail bit information does not occur. The predetermined range of addresses may be, for example, the entire range of RAM.

Then, the integrated circuit switches the clock from the high speed CLK to the low speed CLK. Then, the integrated circuit transfers the test result to the external LSI tester by scan shift (G6). Further, the LSI tester determines whether or not the test results of all addresses have been acquired (G7). The LSI tester activates the next BIST test in this integrated circuit when the test results for all addresses are not acquired. Then, the integrated circuit starts determination of the BIST test from the address next to the last stored fail address (G8). On the other hand, if the LSI tester acquires test results for all addresses,
Finish the high-speed FBM test.

FIG. 2 is a circuit block diagram of the present integrated circuit and a diagram exemplifying a configuration of an LSI tester that activates an FBM test in the present integrated circuit. In FIG. 2, this integrated circuit is exemplified by an LSI. This integrated circuit consists of a phase locked loop (PLL) circuit 3-22, a frequency divider circuit 3-23, a pattern generator (PG) 3-1, a memory (RAM) 3-3, a mask circuit 3-7a, 3-7b, 3-7m and fail bit memory circuit
3-8a, 3-8b, 3-8m, comparison circuits 3-18a, 3-18b, mask circuits 3-21a, 3-21b, same fail consecutive number counter 3-20a, 3-20b, test Address counter 3-10 and mask circuit 3-12a, 3-12b,
3-12m, fail address storage circuits 3-11a, 3-11b, 3-11m, and a mask signal generation circuit 3-19.

The memory (RAM) 3-3 is an example of a storage unit. The pattern generator (PG) 3-1 is an example of a data generation unit that generates test data to be written at the test target address in the storage unit. The mask circuit 3-7a stores the next error result data in the first result data storage unit when the error result data is stored in the first result data storage unit among the plurality of result data storage units. It is an example of the 1st interruption circuit which interrupts. The mask circuit 3-7b stores the first error result data in the second result data storage unit after the first error result data is stored in the first result data storage unit among the plurality of result data storage units. Is an example of a second cutoff circuit that cuts off the storage of the next error result data in the second result data storage unit when different second error result data is stored. The fail bit storage circuits 3-8a, 3-8b, 3-8m are examples of a plurality of result data storage units that sequentially store error result data when the test result is an error. The fail bit storage circuit 3-8a is also an example of the first result data storage unit. The fail bit storage circuit 3-8b is also an example of the second result data storage unit. The test address counter 3-10 is an example of an address generation unit that generates a test target address in the storage unit. The test address counter 3-10 is also an example of the first counter included in the address generator. The fail address storage circuits 3-11a, 3-11b, 3-11m are examples of an address storage unit that stores a plurality of test target addresses corresponding to the error result data held in the plurality of result data storage units, respectively. fail address memory circuit
3-11a, 3-11b, 3-11m are also examples of the second counter driven by the same clock as the clock that drives the first counter. The mask circuits 3-12a, 3-12b, 3-12m correspond to the result data storage unit in which the error result data is stored when the error result data is stored in any of the plurality of result data storage units. It is an example of a shutoff circuit for shutting off a clock to the second counter of the address storage unit. The same failure consecutive number counter 3-20a is an example of a third counter that counts the number of repetitions when the same error result data is repeated a plurality of times consecutively. The same fail consecutive number counter 3-20b is an example of a fourth counter. The phase-locked loop (PLL) circuit 3-22 is an example of a first clock circuit that supplies a first clock to a storage unit, an address generation unit, a test execution unit, a plurality of result data storage units, and a plurality of address storage units. Is. The frequency divider circuit 3-23 is an example of a second clock circuit that supplies a second clock, which is slower than the first clock, to the external output unit.

The PLL circuit 3-22 is supplied with the tester clock from the LSI tester. The PLL circuit 3-22 generates a high frequency clock synchronized with the tester clock. The high frequency clock is supplied to the pattern generator 3-1, the memory 3-3, and each storage circuit in this integrated circuit.

The frequency divider circuit 3-23 divides the high frequency clock from the PLL circuit 3-22 to generate a low frequency clock. The low frequency clock is supplied to the pattern generator 3-1, the memory 3-3, and each memory circuit in this integrated circuit, and is used for initial setting by scan shift and reading of test results.

The pattern generator 3-1 has a scan input (SI) terminal and a scan output (SO) terminal. The pattern generator 3-1 receives an initial value setting from the LSI tester by scan shift from the scan chain circuit through the SI terminal. Then, the pattern generator 3-1 generates a test pattern in accordance with the high frequency clock from the PLL circuit 3-22, and supplies the generated test pattern to the memory 3-3 and the like.

The test address counter 3-10 generates an address to be tested according to the high frequency clock from the PLL circuit 3-22. The memory 3-3 writes the test pattern generated by the pattern generator 3-1 to the test target address and reads the data written to the test target address. The data read from the test target address in the memory 3-3 is compared with the test pattern (expected value) generated by the pattern generator 3-1. In FIG. 2, the comparator for comparing the data read from the memory 3-3 with the expected value is omitted.

fail bit The memory circuits 3-8a, 3-8b, 3-8m are the bit pattern of the error when an error occurs as a result of the comparison between the data read from the memory 3-3 and the expected value. Store the bit pattern (pf_info_a, pf_info_b, pf_info_m). The fail bit pattern (pf_info_a, pf_info_b, pf_info_m) is an example of error result data. However, in the present embodiment, as a result of the comparison, if an error occurs and the fail bit patterns at the test target addresses tested before and after are different from each other, different fail bit patterns fail. It is stored in the bit memory circuits 3-8a, 3-8b, 3-8m.

On the other hand, as a result of comparing the data read from the memory 3-3 with the expected value, if no error occurs, the test result pattern is the fail bit storage circuit 3-8a, 3-8b, 3-8m. I can't remember. Further, if the same fail bit pattern appears at the test target addresses tested before and after, the subsequent fail bit pattern is not stored. Therefore, mask circuits 3-7a, 3-7b, 3-7m are provided. In the mask circuits 3-7a, 3-7b, 3-7m, an error occurs as a result of the comparison between the data read from the memory 3-3 and the expected value, and the test target is tested before and after. When different fail bit patterns appear at the addresses, mask signals for sequentially storing different fail bit patterns in the fail bit storage circuits 3-8a, 3-8b, 3-8m are supplied.

For example, in the initial state, the mask circuits 3-7a, 3-7b, 3-7m are set to have no mask. The settings of mask circuits 3-7a, 3-7b, 3-7m are maintained until a fail bit pattern appears.
Therefore, until the first fail bit pattern appears, the result of comparing the data read from the memory 3-3 with the expected value is overwritten in the fail bit storage circuits 3-8a, 3-8b, 3-8m, respectively. It Then, when the first fail bit pattern appears and is written in the fail bit storage circuits 3-8a, 3-8b, 3-8m, first, the mask circuit 3-7a is set to mask the input signal, and the mask signal is set. Circuits 3-7b and 3-7m remain unmasked. This mask signal is generated by the mask signal generation circuit 3-19 from the first fail bit pattern.

Then, the result of the comparison between the data read from the memory 3-3 and the expected value, which is the test result at the next test target address, is not written to the fail bit storage circuit 3-8a. As a result, the first fail bit pattern is held in the fail bit memory circuit 3-8a. If the result of comparison between the data read from the memory 3-3 and the expected value is normal (pass) or the same error as the first fail bit pattern, the mask circuit 3-7b, 3 At -7m, the maskless setting is maintained. As a result, as long as the result of comparison between the data read from memory 3-3 and the expected value is normal (pass) or the same error as the first fail bit pattern continues, the data is read from memory 3-3. The result of comparison between the generated data and the expected value is overwritten and stored in the fail bit storage circuits 3-8b and 3-8m.

When a second fail bit pattern different from the first fail bit pattern is generated, the mask signal generation circuit 3-19 masks the mask circuit 3-7b and masks the mask circuit 3-7m without masking. To generate. At this time, the mask of the mask circuit 3-7a is still maintained. Then, the result of comparison between the data read from the memory 3-3 and the expected value, which is the test result at the next test target address, is not written to the fail bit storage circuit 3-8b. As a result, the second fail bit pattern is held in the fail bit storage circuit 3-8b. Mask circuit
The operation of 3-7m is similar to the operation of mask circuits 3-7a and 3-7b. In this way, the fail bit storage circuits 3-8a, 3-8b, 3-8m hold different fail bit patterns (pf_info_a, pf_info_b, pf_info_m). The fail bit storage circuits 3-8a and 3-8b have SI terminals and SO terminals. The fail bit storage circuits 3-8a and 3-8b receive the initial value setting from the LSI tester by scan shift from the scan chain circuit through the SI terminal. Further, the fail bit storage circuits 3-8a and 3-8b transfer the stored fail bit pattern to the LSI tester by scan shift through the scan chain circuit connected to the SO terminal.

The comparison circuit 3-18a compares the storage data of the fail bit storage circuit 3-8a with the storage data of the fail bit storage circuit 3-8b, and transmits the comparison result to the mask signal generation circuit 3-19. Also, the comparison circuit 3-18b compares the storage data of the fail bit storage circuit 3-8b with the storage data of the fail bit storage circuit 3-8m, and transmits the comparison result to the mask signal generation circuit 3-19. When the mask signal generation circuit 3-19 detects that a different fail bit pattern is generated according to the comparison result of the comparison circuits 3-18a and 3-18b, it masks the mask circuits 3-7b and 3-7m sequentially. Generate a signal. Also, the comparison circuit
The comparison results of 3-18a and 3-18b are supplied to the same fail consecutive number counters 3-20a and 3-20b through mask circuits 3-21a and 3-21b, respectively.

When the first fail bit pattern appears in the mask circuit 3-21a and the stored data (pf_info_a) of the fail bit storage circuit 3-8a and the stored data (pf_info_b) of the fail bit storage circuit 3-8b are the same. Then, according to the mask signal of the mask signal generation circuit 3-19, the state without masking is set.
When the storage data (pf_info_a) of the fail bit storage circuit 3-8a and the storage data (pf_info_b) of the fail bit storage circuit 3-8b are different data, the mask circuit 3-21a causes the mask signal generation circuit 3 -The mask state is entered according to the mask signal of -19.

That is, as long as the first fail bit pattern continues, the mask signal generation circuit 3-19 sets the mask circuit 3-21a to be unmasked and generates a mask signal for masking the mask circuit 3-21b. Then, when a second fail bit pattern different from the first fail bit pattern is generated, the mask signal generation circuit 3-19 generates a signal for masking the mask 3-21a from the comparison result of the comparison circuit 3-18a. .. Therefore, the same fail consecutive number counter 3-20a counts the number of consecutive appearances (Ca2) of the first fail bit pattern according to the presence / absence of masking in the mask circuit 3-21a.

Similarly, in the mask circuit 3-21b, the second fail bit pattern appears, and the storage data (pf_info_b) of the fail bit storage circuit 3-8b and the storage data (pf_info_m) of the fail bit storage circuit 3-8m are generated. If they are the same, the mask signal is generated in accordance with the mask signal of the mask signal generation circuit 3-19. When the storage data (pf_info_b) of the fail bit storage circuit 3-8b and the storage data of the fail bit storage circuit 3-8m (pf_info_m) become different data, the mask circuit 3-21b causes the mask signal generation circuit 3 -The mask state is entered according to the mask signal of -19.

That is, as long as the second fail bit pattern continues, the mask signal generation circuit 3-19 generates a mask signal for masking the mask circuit 3-21b. Then, when the next fail bit pattern different from the second fail bit pattern is generated, the mask signal generation circuit 3-19 generates a signal for masking the mask 3-21b from the comparison result of the comparison circuit 3-18b. .. Therefore, the same fail consecutive number counter 3-20b counts the number of consecutive appearances (Cb2) of the second fail bit pattern according to the presence / absence of masking in the mask circuit 3-21b. The number of consecutive occurrences of fail bit pattern (Ca2, Cb2) is an example of the number of repetitions counted by the third counter.

The same fail consecutive number counters 3-20b and 3-20b have SI terminals and SO terminals. The same failure consecutive number counters 3-20b and 3-20b receive the initial value setting from the LSI tester by the scan shift from the SI terminal through the scan chain circuit. Further, the same fail consecutive number counters 3-20b and 3-20b transfer the consecutive appearance numbers (Ca2, Cb2) of the fail bit pattern to the LSI tester by scan shift through the scan chain circuit connected to the SO terminal.

The fail address storage circuits 3-11a, 3-11b, 3-11m are the first fail bit pattern and the second, respectively.
The test target addresses (Ca1, Cb1, Cm1) where the fail bit pattern and the third fail bit pattern appear are stored. The test target addresses (Ca1, Cb1, Cm1) where the first fail bit pattern, the second fail bit pattern, and the third fail bit pattern appear correspond to the error result data stored in multiple result data storage units. It is an example of a plurality of test target addresses. Therefore, the mask circuits 3-12a, 3-12b, and 3-12m are set to the maskless state in the initial state. Then, when the first fail bit pattern appears and is stored in the fail bit memory circuit 3-8a, and the test target address is set in the fail address memory circuits 3-11a, 3-11b, 3-11m, first, the mask The circuit 3-12a is masked, while the mask circuits 3-12b and 3-12m are kept masked. As a result, even if the test target moves to the next test target address, the value (Ca1) of the test target address of the fail address storage circuit 3-11a is retained.

Similarly, when the second fail bit pattern appears and is stored in the fail bit storage circuit 3-8b, the mask circuit 3-12b is masked and the mask circuit 3-12c remains unmasked. As a result, even if the test target moves to the next test target address, the value (Cb1) of the test target address of the fail address storage circuit 3-11b is retained. The operation of the fail address storage circuit 3-11c and the mask circuit 3-12c is the same as the operation of the fail address storage circuit 3-11a and the mask circuit 3-12a, and the operation of the fail address storage circuit 3-11b and the mask circuit 3-12b. Is.

The fail address storage circuits 3-11a, 3-11b, 3-11m have SI terminals and SO terminals. The fail address storage circuits 3-11a, 3-11b, 3-11m receive initial values from the LSI tester by scan shift through the SI terminal from the scan chain circuit. Further, the fail address storage circuits 3-11a, 3-11b, 3-11m transfer the fail address information to the LSI tester by scan shift through the scan chain circuit connected to the SO terminal.

  When the first fail bit pattern appears and the first fail address is set in the fail address storage circuit 3-11a, the mask signal generation circuit 3-19 masks the mask circuit 3-12a and the mask circuit 3-12b. , 3-12c with no mask is generated. Similarly, when the second fail bit pattern appears and the second fail address is set in the fail address storage circuit 3-11b, the mask signal generation circuit 3-19 masks the mask circuit 3-12b, A signal for not masking the mask circuit 3-12c is generated. Further, similarly, when the third fail bit pattern appears and the third fail address is set in the fail address storage circuit 3-11c, the mask signal generation circuit 3-19 masks the mask circuit 3-12c. To generate the signal.

FIG. 3 is an example of the fail bit pattern at the test target addresses ad 0 to ad 7. In this example, an error appears in bit 1 at each of the test target addresses ad 1, ad 2, ad 5. Also, at the test target address ad 6, an error occurs in bit 1 and bit 2. In addition, at the test target address ad 7, an error has occurred in bit 2. In this case, the address ad 1 at which the first fail bit pattern appears and the fail pattern 0010 at that time are held in the memory circuit a. Here, the memory circuit a is, for example, the fail address memory circuit 3-11a and the fail bit memory circuit 3-8a in FIG.

In addition, even if the same fail pattern 0010 as the address ad 1 appears at the address ad 5 after the normal state continues at the addresses ad 3 and ad 4, the address ad 5 at which the fail bit pattern appears and the The fail pattern 0010 is held in the memory circuit b. Here, the memory circuit b is, for example, the fail address memory circuit 3-11b and the fail bit memory circuit 3-8b in FIG.

  Further, even when a fail pattern 0011 different from the address ad 5 appears at the address ad 6, the address ad 6 at which the fail bit pattern appears and the fail pattern 0011 at that time are held in the memory circuit m. Here, the memory circuit m is, for example, the fail address memory circuit 3-11m and the fail bit memory circuit 3-8m in FIG.

In FIG. 3, a fail pattern 0010 appears at the address ad7, which is different from the address ad6. However, since all the memory circuits have already stored error result data, the address ad7 at which the fail bit pattern appears at the address ad7. 7 and the fail pattern 0010 at that time cannot be stored in the integrated circuit of FIG. Therefore, this integrated circuit temporarily ends the BIST test while holding the last tested address ad 6 in the fail address storage circuit 3-11m and outputs the test results of the storage circuits a, b, m to the LSI tester. To do. Then, the integrated circuit restarts the BIST test from the address next to the last tested address ad 6.

FIG. 4 is an example of data held in the memory circuits a, b, and m when the fail bit pattern of FIG. 3 occurs. As described with reference to FIG. 3, the memory circuit a holds 0010 as the information of the fail bit pattern (hereinafter, fail bit information), and uses ad1 as the test target address (hereinafter, fail address) at which the fail bit pattern appears. Hold. Also, the number of consecutive same failures is 2. Further, the memory circuit b holds 0010 as fail bit information and ad5 as a fail address. Also, the number of consecutive same failures is one. Further, the memory circuit m holds 0110 as fail bit information and ad6 as fail address. In the circuit of FIG. 2, the same fail consecutive number is not counted for the third fail bit pattern.

FIG. 5 is a flowchart illustrating the processing procedure of the high-speed FBM test executed by the integrated circuit in the present embodiment. FIG. 5 embodies the procedure of FIG. 1, particularly the processing of G2, according to the configuration of FIG.

As described with reference to FIG. 1, the present integrated circuit starts the BIST test according to the setting from the LSI tester (S101). That is, the present integrated circuit advances the test target address sequentially and executes the BIST test at the test target address (S102). Then, the present integrated circuit determines whether or not a fail bit pattern has appeared as a result of the comparison between the data read from the memory 3-3 and the expected value (S103). When the fail bit pattern does not appear in the determination of S103, the integrated circuit returns to the process of S102.

  On the other hand, if a fail bit pattern appears in the determination of S103, this integrated circuit stores fail bit information and fail address information (S104). Then, the present integrated circuit sequentially advances the test target address and executes the BIST test at the next test target address (S105).

Then, the present integrated circuit determines whether or not a fail bit pattern has appeared as a result of the comparison between the data read from the memory 3-3 and the expected value (S106). When the fail bit pattern does not appear in the determination of S106, the integrated circuit advances the test target address until the fail bit pattern appears by the processes of S107 and S108. Then, when the fail bit pattern appears, the integrated circuit proceeds to the processing of S111.

  On the other hand, if a fail bit pattern appears in the determination of S106, this integrated circuit determines whether the appearing fail bit information is the same as the fail bit information that appeared before it (S109). If it is determined in S109 that the fail bit information that appears is the same as the fail bit information that appears before that, this integrated circuit skips the storage of the fail bit information and counts up the same fail count. (S110). Then, the integrated circuit returns to the processing of S105.

The process of sequentially advancing the test target address in S102, S105, and S107 is an example of generating the test target address of the storage unit. The processing of S102, S103, S105, S106, S107, and S108 is an example of generating test result data at each test target address in the storage unit.

On the other hand, if different fail bit patterns appear in the judgment of S109, this integrated circuit determines the same fail bit.
The number of times is stored (S111). Then, the integrated circuit sets the storage destination of each data to the next storage circuit (S112). Then, the integrated circuit stores the newly appeared fail bit information and fail address (S113). In the above, the processes of S104 and S113 are an example of the process of sequentially storing the error result data when the test result is an error in the plurality of result data storage units. In addition, S104, S113
The above process is an example of a process of storing a plurality of test target addresses corresponding to the error result data respectively held in the plurality of result data storage units in a plurality of address storage units.

  Then, the integrated circuit determines whether or not the data is stored in all the storage circuits or the test of the addresses in the predetermined range is completed (S114). The predetermined range is held in a predetermined register in the integrated circuit. The predetermined range may be, for example, all addresses of the memory in the integrated circuit.

  The integrated circuit returns to the processing of S105 when the data is not stored in all the storage circuits and when the test of the address in the predetermined range is not completed. On the other hand, when either the data is stored in all the storage circuits or the test of the address in the predetermined range is completed, this integrated circuit ends the BIST test (S115).

Then, the integrated circuit switches the clock from the high speed clock to the low speed clock (S116). Then, the integrated circuit transfers the test result to the external LSI tester by the scan shift (S117). The processing of S117 is performed in accordance with the second clock that is slower than the first clock, and the error result data stored in each of the plurality of result data storage units and the test target addresses stored in each of the plurality of address storage units. 5 is an example of a process of outputting and to an external device.

Further, according to the control of the LSI tester, the present integrated circuit determines whether or not the test results of all addresses have been acquired (S118). More specifically, the LSI tester determines whether the end of the test address output by the scan shift matches the end of all addresses. If the end of the test address output by scan shift matches the end of all addresses, the LSI
The tester does not continue the test. As a result, the integrated circuit ends the high-speed FBM test when the test results of all addresses are acquired. On the other hand, if the LSI tester has not obtained the test results for all addresses, it instructs this integrated circuit to continue the BIST test. Then, the present integrated circuit starts the determination of the next BIST test from the last stored fail address (S119).

  If all the test target addresses have not been tested after the processing of S118 and S119 has been output to the external device, the last test target address among the plurality of test target addresses stored in the plurality of address storage units It is an example of a process of starting the determination of the next test from the address next to.

  As described above, this integrated circuit can store a plurality of sets of fail bit information and fail address information during the BIST test. Therefore, instead of the process of suspending the BIST test and storing the fail address information in the low-speed clock operation as in the past, a predetermined number of sets of fail bit information and fail address information are set during the BIST test that operates in the high-speed clock. Can be remembered. Therefore, the integrated circuit can store the fail bit information and the fail address information without interrupting the BIST test until all the predetermined number of storage circuits are stored. In addition, this integrated circuit can reduce the number of BIST tests and shorten the test time by collectively transferring a plurality of sets of fail bit information and fail address information in one BIST test.

Further, since this integrated circuit skips the fail bit information when the same fail bit pattern continues, the processing time can be shortened. In addition, the present integrated circuit stores a plurality of fail bit information and also stores the number of consecutive identical fail bit patterns by comparing the stored plurality of fail bit information.
Therefore, this integrated circuit simultaneously obtains a plurality of different fail bit information in one BIST test while suppressing an increase in the number of circuit points, and skips the transfer of fail bit information when consecutive identical fail bit patterns appear. .. In this case, the present integrated circuit can obtain the same information from the BIST test by storing the number of appearances of the same fail bit pattern, as in the case of storing the continuous same fail bit pattern. Therefore, ultimately, the present integrated circuit can extend the range of test target addresses that can be processed in one BIST test, and reduce the number of BIST repetitions.

  Furthermore, the present integrated circuit counts the number of times of the same fail bit pattern and shortens the time, and also skips the fail bit information in the case of a normal test result, that is, pass, thereby shortening the processing time. Therefore, ultimately, the present integrated circuit can extend the range of test target addresses that can be processed in one BIST test, and reduce the number of BIST repetitions.

In the above embodiment, the present integrated circuit has three mask circuits 3-7a, 3-7b, 3-7m, three fail bit memory circuits 3-8a, 3-8b, 3-8m, and three mask circuits. 3-12a, 3-12b, 3-12m, and three fail address storage circuits 3-11a, 3-11b, 3-11m. However, the fail bit storage circuit and the fail address storage circuit are not limited to three each. For example, two of these circuits may be provided, or four or more of these circuits may be provided.

[Embodiment 2]
Hereinafter, the integrated circuit according to the second embodiment will be described with reference to FIGS. In the first embodiment, mask circuits 3-7a, 3-7b, 3-7m, fail bit memory circuits 3-8a, 3-8b, 3-8m, mask circuits 3-12a, 3-12b, 3-12m, Also, the integrated circuit for storing a plurality of fail bit information and fail address information by the fail address storage circuits 3-11a, 3-11b, 3-11m has been described. In this embodiment, a circuit that generates a mask signal in an integrated circuit that stores a plurality of pieces of fail bit information and fail address information will be described more specifically.

FIG. 6 is a configuration diagram illustrating the configuration of the integrated circuit of the second embodiment. This integrated circuit (LSI) includes a PLL circuit 2-22, a frequency dividing circuit 2-23, a scan chain input section 2-24, a scan chain output section 2-25, a pattern generator 2-1 and a scan latch. It has 2-2, 2-4, 2-5 and a memory 2-3. This integrated circuit also includes a comparator 2-6 for generating fail bit information, mask circuits 2-7a, 2-7b for holding the generated fail bit information, and data receivers 2-8a, 2 -8b. In addition, the present integrated circuit has a counter 2-10 that generates a test target address. Further, the present integrated circuit has counters 2-11a and 2-11b and mask circuits 2-12a and 2-12b for holding the fail address information. Further, this integrated circuit has a counter 2-20 for counting the number of consecutive occurrences of the same fail bit information. Further, the present integrated circuit includes an OR gate 2-9a, 2-9b, a comparator 2-16, a register 2-17, a mask circuit 2-18, and an AND gate 2-19 for generating a mask signal. It has comparators 2-13a and 2-13b, a register 2-15, and OR gates 2-14a and 2-14b.

The memory 2-3 is an example of a storage unit. The pattern generator 2-1 is an example of a data generator. The mask circuit 2-7a stores the next error result data in the first result data storage unit when the error result data is stored in the first result data storage unit among the plurality of result data storage units. It is an example of the 1st interruption circuit which interrupts. The mask circuit 2-7b stores the first error result data in the second result data storage unit after storing the first error result data in the first result data storage unit among the plurality of result data storage units. Is an example of a second cutoff circuit that cuts off the storage of the next error result data in the second result data storage unit when different second error result data is stored. The data receiver 2-8a is an example of a first result data storage unit. The data receiver 2-8b is an example of a second result data storage section. The data receivers 2-8a and 2-8b are also examples of the result data storage unit. The counter 2-10 is an example of an address generation unit. The counter 2-10 is an example of the first counter. The counters 2-11a and 2-11b are examples of address storage units. The counters 2-11a and 2-11b are also examples of the second counter. The scan chain output section 2-25 and the circuit connected to the scan chain output section 2-25 are examples of the external output section. The mask circuits 2-12a and 2-12b are examples of cutoff circuits. Counter 2-20 is an example of the third counter. The PLL circuit 2-22 is an example of the first clock circuit. The frequency divider circuit 1-23 is an example of the second clock circuit.

Hereinafter, the circuit operation of FIG. 6 will be described. First, all the comparison circuits in FIG. 6 are set to "0" if the two inputs match, and set to "1" if they do not match, and all the mask circuits are circuits masked by the control signal input of "1". Suppose there is.

This integrated circuit repeatedly executes the BIST test while sequentially changing the test target address. At the start of the BIST test, this integrated circuit executes the scan shift operation with the low frequency clock output from the frequency dividing circuit 2-23, and captures the output of the LSI tester through the scan chain input unit 2-24. As shown in FIG. 6, the pattern generator 2-1 and the data receiver 2-8a
, 2-8b and counters 2-10, 2-11a, 2-11b, 2-20 and registers 2-15, 2-17 respectively have SI terminals and SO terminals. By the scan shift operation, the pattern generator 2-1 and the data receivers 2-8a and 2-8b and the counters 2-10, 2-11a, 2-11b and 2-20 and the register 2-15
, 2-17 initial value is set from each SI pin.

After that, the integrated circuit executes the BIST test with the high frequency clock generated by the PLL circuit 2-22. At the end of the BIST test, this integrated circuit executes the scan shift operation with the low frequency clock, and the SO receiver of each element, the scan chain circuit, and the scan chain output unit 2-25 are used to detect the data receiver 2-8a. Outputs the value (pf_info1), 2-8b value (pf_info2), counter 2-11a value (Ca1), counter 2-11b value (Cb), and counter 2-20 value (Ca2) to the LSI tester. .. The value of counter 2-11a (Ca1) and the value of counter 2-11b (Cb) are examples of error result data. The value (Ca2) of the counter 2-20 is an example of the number of times the error result data is repeatedly generated. At this time, if the value (Cb) of the counter 2-11b output to the LSI tester matches the last tested address of the memory 2-3, the LSI tester ends the repetition of the BIST test.

  As described above, the pattern generator 2-1 receives the initial value setting from the LSI tester by scan shift through the scan chain input unit 2-22 and the scan chain circuit.

After setting the initial value, the pattern generator 2-1 generates test data in accordance with, for example, a high frequency clock, and stores the test data in the scan latch 2-2 and the scan latch 2-5. The memory 2-3 writes the test data input from the scan latch 2-2 to the test target address designated by the counter 2-10 according to the high frequency clock. Further, the memory 2-3 reads data from the test target address designated by the counter 2-10 according to the high frequency clock and stores it in the scan latch 2-4. The data stored in the scan latch 2-4 is called RD. The test data stored in the scan latch 2-5 is called an expected value (mean). The comparator 2-6 compares the data RD stored in the scan latch 2-4 with the expected value (mean) of the scan latch 2-5 according to the high-speed clock, and generates a test result. The scan latches 2-2, 2-4, 2-5 and the comparator 2-6 are examples of the test execution unit.

In the first BIST test, this integrated circuit sets the data receivers 2-8a, 2-8b and counters 2-10, 2-11a, 2-11b, 2-20 and registers 2-15, 2-17 to 0. To do. The roles of each data receiver and counter are as follows.

The data receiver 2-8a stores the first fail bit information (pf_info1), and 2-8b stores the second fail b information.
Store it information (pf_info2). The counter 2-10 indicates the test target address (C) currently being tested. The counter 2-11a stores the address (Ca1) where the first fail bit information was obtained, and the counter 2-11b stores the address (Cb) where the second fail bit information was obtained. The counter 2-20 stores the number of times (Ca2) that the first fail bit pattern appears consecutively.

The fail bit information (pf_info1, pf_info2) is an example of error result data. The addresses (Ca1, Cb) from which the fail bit information is obtained are an example of a plurality of test target addresses corresponding to the error result data held in the plurality of result data storage units. The number of times the fail bit pattern appears consecutively (Ca2) is an example of the number of repetitions counted by the third counter when the same error result data is repeated a plurality of times.

  This integrated circuit stores the comparison result between the read data (RD) of the scan latch 2-4 and the expected value (mean) of the scan latch 2-5 in the data receivers 2-8a and 2-8b. However, depending on the presence / absence of the mask signal of the mask circuits 2-7a and 2-7b, the data receivers 2-8a and 2-8b store the new comparison result between the read data and the expected value or the current value (previous value). Either the operation of holding the comparison result of 1) is selected.

If the value of data receiver 2-8a (comparison result) indicates fail, the output of OR gate 2-9a is 1
Then, the mask signal (Ia) is given to the mask circuits 2-7a and 2-12a. The influence of the mask signal (Ia) is as follows.

By the mask signal (Ia), the present integrated circuit holds the value of the data receiver 2-8a until the next BIST test. Further, the mask signal (Ia) causes the present integrated circuit to stop updating the counter 2-11a at the address currently under test. Once the update is stopped, the output (IIa) of the comparator 2-13a that compares the value (C) of the counter 2-10 with the value (Ca1) of the counter 2-11a becomes 1. As a result, this integrated circuit holds the value of the counter 2-11a until the next BIST test.

After the data receiver 2-8a is masked by the mask circuit 2-7a, the mask signal (Ib) changes depending on the pass / fail result of the data receiver 2-8b and the comparison result of the data receivers 2-8a and 2-8b. .. The mask signal (Ib) is given as follows.

When the comparison result of the data receiver 2-8a and the data receiver 2-8b is different, or when pass is detected and then fail again, the mask signal (Ib) becomes 1 and the output of the comparator 2-16 is ORed. The output of the gate 2-9b is combined with the AND gate 2-19 to output a logical value. That is, when the data receiver 2-8b fails and the comparison result of the data receiver 2-8a and the data receiver 2-8b is different, the output of the comparator 2-16 = 1 and the output of the OR gate 2-9b = It becomes 1. Just before the data receiver 2-8b fails, and the comparison result of the data receiver 2-8a and the data receiver 2-8b is different, both the data receivers 2-8a and 2-8b are fail, and the mask It is assumed that the mask signal (Ia) = 1 is given to the circuits 2-7a and 2-12a. Therefore, the output of the OR gate 2-9b is 1, and 1 is held in the register 2-17. As a result, the mask circuit 2-18 is controlled without a mask. Therefore, the output of the AND gate 2-19 = mask signal (Ib) = 1. That is, when both the data receiver 2-8a and the data receiver 2-8b have failed and the comparison results are different, the mask signal (Ib) is given to 1.

Furthermore, when the data receiver 2-8b passes, 0 is entered in the register 2-17, so the register 2-17 masks the mask 2-18 at the timing of the next test. In addition, the data receiver 2-8a, 2-8b
The comparison result of is disagreement = 1. In this state, when the data receiver 2-8b shows fail at the timing of the next test, the mask 2-18 maintains the previous value and outputs 1, so the output of the AND gate 2-19 = Mask signal ( Ib) = 1.

Further, in the circuit of FIG. 6, when the pass is detected in the data receiver 2-8b and the same fail bit pattern as in the data receiver 2-8a appears in the next test, the mask signal (Ib) becomes 1.
That is, the present integrated circuit sets the signal (Ib) to 1 by providing the register 2-17 and holding the comparison result when the pass is performed until the next address. Therefore, it can be understood that when the data receiver 2-8b changes from fail to pass, the data receiver 2-8a is masked regardless of the comparison result, and the comparison result = 1 in the pass state is output.

  The influence of the mask signal (Ib) is as follows.

  By the mask signal (Ib), this integrated circuit holds the value of the data receiver 2-8b until the next BIST test. Further, the mask signal (Ib) causes the present integrated circuit to stop updating the counter 2-11b during the test of the current address. The output (IIb) of the comparator 2-13b that compares the counters 2-10 and 2-11b becomes 1 by stopping the update once, and this integrated circuit holds the value of the counter 2-11b until the next BIST test.

A counter 2-20 that counts the number of times (fail) of consecutive fail bit patterns (Ca2) is controlled by a mask circuit 2-21, and the mask circuits 2-21 are supplied with the following mask signals (1) to (3). The mask signals (1) to (3) are OR logic and control the presence / absence of a mask in the mask circuit 2-21.
(1) A signal to be masked when the comparison results of the data receivers 2-8a and 2-8b are different.
(2) Signal to mask when data receiver 2-8b is pass.
(3) Mask signal (Ib). Even if the fail bit pattern is held in the data receiver 2-8a and then the same fail bit pattern as in the data receiver 2-8a appears after detecting pass, this integrated circuit uses the mask circuit 2-21. Mask counters 2-20. Therefore, the Mask signal (Ib) of (3) is given to the mask circuit 2-21. When the mask circuit 2-21 is not masked by the mask signals (1) to (3), the counter 2-20 counts the number of consecutive fail bit patterns (Ca2).

When the BIST test is completed, this integrated circuit transfers the values of the data receivers 2-8a, 2-8b and the counters 2-11a, 2-11b, 2-20 to the LSI tester by scan shift. If the value of the counter 2-11b does not match the number of addresses of the memory 2-3, the LSI tester activates the next BIST test, and this integrated circuit continues the BIST test.

When continuing the BIST test, this integrated circuit sets the values of the data receivers 2-8a and 2-8b and the counter 2-20 to 0 by the scan shift from the LSI tester. On the other hand, this integrated circuit holds the values obtained in the previous BIST test for the counters 2-11a and 2-11b.

When this integrated circuit restarts and continues the BIST test after data transfer by scan shift, this integrated circuit continues to operate the data receivers 2-8a and 2-8b until the counter 2-10 value matches the counter 2-11b. The mask signal (IIIb) becomes 1. That is, in the current BIST test, the addresses held by the counter 2-11b have been completed. Therefore, in the next BIST test, this integrated circuit is
Mask the data receiver 2-8b up to the address held by. This integrated circuit outputs the signal (IIIb)
The timing to turn on is the next cycle when the value of the counter 2-10 matches the value of the counter 2-11b.
Therefore, a register 2-15 is provided to set the mask signal (IIIb) to 1 until the next cycle. After the mask signal (IIIb) becomes 0, this integrated circuit operates similarly to the first BIST test. The mask signal (IIIb) is given the mask signal (IIIb) by the OR gate 2-14a. Therefore, the effect of setting the mask signal (IIIb) to 1 until the next cycle by the register 2-15 extends to the mask signal (IIIa). That is, in the next BIST test, this integrated circuit is
Data receiver 2-8a up to the latter address among the addresses held by counter 2-11b
To mask. As illustrated above, the integrated circuit in FIG. 6 holds the values obtained in the previous BIST test for the counters 2-11a and 2-11b by saying that “the test is performed after the output to the external device by the external output unit. Of the test result data generated by the execution unit, the storage of error result data at the test target address before the last test target address is blocked. ”

Note that each mask circuit, unlike a counter and a register, does not operate in clock synchronization. Therefore, the timing is designed so that the mask signal arrives before the input of the mask circuit. The mask signals (I) and (II) are required to reach the mask circuits before the next test address is tested.

  The mask signals (IIIa) and (IIIb) are registered in the register 2-15 and the OR gate 2-by the path delay from the scan latch 2-4 to the mask circuits 2-7a and 2-7b via the comparison circuit 2-6. Design so that the path delay to the mask circuit via 14b and OR gate 2-14a is small. Normally, a comparison circuit that compares several tens of bits has a large delay, and thus it is easy to satisfy this design requirement.

FIG. 7 illustrates a processing procedure of a high-speed FBM test in the integrated circuit of the second embodiment illustrated in FIG. The integrated circuit of FIG. 6 has two storage circuits for fail bit information and two storage circuits for fail address information, such as two data receivers 2-8a, 2-8b and counters 2-11a, 11b. Therefore, it is not necessary to perform the process of determining that the data is stored in all the storage circuits (S114 of FIG. 5) and the process of setting the storage target of each data to the next storage circuit (S112 of FIG. 5) as in the first embodiment. is there. Therefore, in the process procedure of FIG. 7, the processes of S112 and S114 are omitted as compared with FIG. On the other hand, the processes corresponding to the processes other than the processes of S112 and S114 are similarly executed in FIG. Therefore, in FIG. 7, in the symbols in FIG.
Changed from 2 to 2 and given, and the description thereof is omitted. That is, the process S2NN of FIG. 7 corresponds to the process S1NN of FIG. Here, NN is an integer.

In the second embodiment, like the two data receivers 2-8a and 2-8b and the counters 2-11a and 11b, the number of systems of the fail bit information storage circuit and the fail address information storage circuit is two. The circuit is illustrated. However, the structure of the integrated circuit is not limited to the structure shown in FIG. FIG. 8 illustrates a configuration of a storage circuit that stores three or more sets of fail bit information and fail address information. That is, FIG. 8 is a modification example in which FIG. 6 is expanded, and the suffixes of the reference numerals are increased to a, b, and m. Further, among the constituent elements illustrated in FIG. 8, those corresponding to the constituent elements in FIG. 6 are illustrated by changing the reference numeral “2-nn” in FIG. 6 to a reference numeral “1-nn”. For example, in FIG. 6, two data receivers 2-8a, 2-8b are provided, but in FIG. 8, three data receivers 1-8a, 1-8b, 1-8m are provided. Has been. Further, for example, the one provided like the counter 2-20 in FIG. 6 is provided as two like the data receivers 1-20a and 1-20b in FIG. Further, like the PLL circuit 1-22 and the scan chain output circuit 1-23 in FIG. 8, those whose number of components is the same as those in FIG. 6 are the same as those in FIG. Is changed to "1-", which is illustrated in FIG.

  That is, the integrated circuit (LSI) of FIG. 8 includes a PLL circuit 1-22, a frequency dividing circuit 1-23, a scan chain input unit 1-24, a scan chain output unit 1-25, and a pattern generator 1-1. , Scan latches 1-2, 1-4, 1-5, memories 1-3, and comparators 1-6 for generating fail bit information.

  Further, this integrated circuit has data receivers 1-8a, 1-8b, 1-8m which are storage circuits for storing fail bit information. The integrated circuit also has mask circuits 1-7a, 1-7b, 1-7m for masking the data receivers 1-8a, 1-8b, 1-8m. Furthermore, this integrated circuit consists of comparators 1-18a, 1-18b, OR gates 1-9a, 19b, 1-9m, registers 1-17a, 1-17b, mask circuits 1-18a, 1-18b, AND gates. It has 1-19a, 1-19b, counters 1-20a, 1-20b and mask circuits 1-21a, 1-21b.

Furthermore, this integrated circuit includes counters 1-11a, 1-11b, 1-11m, comparators 1-13a, 1-13b, 1-13m, registers 1-15, mask circuits 1-12a, 1-12b, 1 -12m and OR gates 1-14a, 1-14b, 1-14m. Further, the present integrated circuit holds a test target address (C) generation counter 1-10 and a register 1-15 holding a value reg1 for generating the mask signal IIIm.

With the above configuration, the integrated circuit of FIG. 8 has three types of fail bit information (pf_info1, pf_info2,
pf_info3) Holds the number of times two types of fail bit information have successively appeared (Ca2, Cb2) and three types of fail address information (Ca1, Cb1, Cm1). The integrated circuit of FIG. 8 has three systems of storage circuits with the branch numbers of the codes being a, b, and m, and holds three types of fail bit information and fail address information.
However, the configuration of this integrated circuit is not limited to that shown in FIG. That is, the number of storage circuit systems may be four or more.

FIG. 9 is a diagram exemplifying execution timing of the BIST test, data transfer, and restart / continuation of the BIST test by the integrated circuit of FIG. 6, fail bit information, and fail address information. The integrated circuit of FIG. 6 is provided with two storage circuits for storing fail bit information and one circuit (counter 2-20) for storing the number of consecutive same pattern failures.

In the present embodiment, the test data is written in the memory 2-3 at cycle 1, for example. Writing is sequentially executed from addresses ad 0 to ad 7.

Next, in cycle 2, the test data written in the memory 2-3 is read. Reading is sequentially executed from the address ad0. In the example of FIG. 9, the fail bit is detected by reading the addresses ad 1, ad 2 and ad 5. Fail bit at addresses ad 1, ad 2 and ad 5
Are all bit 1. Therefore, the same fail bit information is continuously detected in ad 1 and 2. In addition, since all the memory circuits (data receivers 1-8a, 1-8b, 1-8m) are stored by detecting the fail bit at the address ad 5, this integrated circuit uses the memory circuits (data receivers 1-8a, 1-8a). , 1-8b, 1-8m) remains masked until the next BIST test. Then, this integrated circuit transfers data to the LSI tester at the end of cycle 2 of the BIST test. After the data transfer is completed, this integrated circuit restarts and continues the BIST test in cycle 3. Already in cycle 2, address ad
Since the BIST test has been completed up to 5, in cycle 3, this integrated circuit does not store the comparison result between the read data and the expected value from address ad 0 to ad 5, and the counter 1-11a, 1-11b , 1-11m etc. are counted. Then, the present integrated circuit restarts the judgment of whether or not the fail bit is included in the comparison result of the data read from the memory 2-3 and the expected value at the addresses ad6 and 7. In the example of FIG. 9, in cycle 3, bits 1 and 2 are detected as fail bits in ad 6, and fail in ad 7
bit 2 is detected as bit.

FIG. 10 illustrates data transferred to the LSI tester after the BIST test in cycle 2 and cycle 3 by the integrated circuit in FIG. In cycle 2, in the data receiver 1-8a (value pf_Finfo1), which is the first storage circuit, consecutive fail bit information (fail of bit 1) is detected from ad 1 at address ad 2, and the same pattern fail consecutive number of times Is exemplified as 1. In the example of FIG. 10, the same pattern fail consecutive number = 0 indicates 1 time, and the same pattern fail consecutive number = 1 indicates 2 times. Also, at address ad 5, fail bit information (fail of bit 1) is detected.

Similarly, in cycle 3, in the second memory circuit (pf_info2), the address ad 6
In, the failure bit information (fail of bits 1 and 2) is detected, and it is illustrated that the same pattern fail consecutive number is 0. Also, at address ad 7, fail bit information (fail of bit 2) is detected.

FIG. 11A and FIG. 11B are diagrams illustrating the change in the value of each part when an error is detected in each cycle illustrated in FIG. 10 in the integrated circuit of FIG. 6. That is, in FIG. 10, the test data is written in the memory 2-3 in cycle 1 and read in cycles 2 and 3. Further, in FIG. 10, pass indicates no error bit (normal), and fail indicates error bit detection.

First, when the value C of the counter 2-10 is C = 1, the data at the address ad 0 is read by pass (normal).
The value of each mask circuit (Ia, Ib, IIa, IIb, IIIa, IIIb), the comparison result of the comparator 2-16 (cmp 1), the output of the mask circuit 2-18 (cmp 2), the register 2-15 The outputs (reg 1, reg 2) of 2 and 17 are 0.
On the other hand, the counting results (Ca1, Cb) of the counters 2-11a and 2-11b are 1, which is the same as the counting result (C) of the counter 2-10. Further, the counting result (Ca2) of the counter 2-20, which is the number of consecutive same pattern failures, is 0.

When the value C of the counter 2-10 is C = 2, the data at the address ad 1 is read by fail. As a result, the data receiver 2-8a (value pf_info1) and the counter 2-11a (value Ca1) are masked. Further, when the value C of the counter 2-10 is C = 3, the data of ad 2 is read by fail. As a result, the value Ca of the counter 2-20 that counts the number of consecutive same pattern failures becomes Ca = 1. Furthermore, with the value C = 4 of the counter 2-10, ad
The data of 3 is read by pass. As a result, since the failure due to the same pattern is interrupted, the counter 2-20 (value Ca) is masked.

After that, with the value C = 6 of the counter 2-10, the data of ad 5 is read by fail. As a result, the data receiver 2-8b (value pf_info1) and the counter 2-11b (value Cb) are masked. At this point, all memory circuits hold the fail bit information and fail address information, so the BIST test cannot continue any further. The present integrated circuit masks the data receiver 2-8a and the counters 2-11a, 2-11b in which the test results are stored, and advances the counting of the counter 2-10. As a result, the present integrated circuit holds the test target address for which the test is completed in the counter 2-11b, advances the counter 2-10 to the value C = 7,8, and ends the cycle 2. After the end of Cycle 2, this integrated circuit scan scan shifts data receiver 2-8a (value pf_info1, first fail bit information), data receiver 2-8b (value pf_info2, value pf_info2,
2nd fail bit information), counter 2-11a (value Ca1, 1st fail address), counter 2-20 (
The value Ca2, the number of consecutive same pattern failures) and the counter 2-11b (value Cb, the second fail address) are transferred to the LSI tester. The fail addresses held by the counters 2-11a and 2-11b are values 1 to 8 for the addresses ad 0 to 7, respectively.

  Hereinafter, the description will be continued with reference to FIG. 11B. After the data transfer, the data receiver 2-8b (value pf_info2, second fail bit information) and the counter 2-20 (value Ca2, the same pattern fail consecutive count) are cleared. On the other hand, the counter 2-11a (value Ca1, the first fail address) and the counter 2-11b (value Cb, the second fail address) are held as BIST test completed addresses.

Then, when the value C of the counter 2-10 is incremented and matches the counter 2-11b (value Cb, the second fail address), the mask IIIb and IIIa are released and the data receivers 2-8a and 2-8b are released. Data writing, comparison with expected value, etc. are restarted. In the example of FIG. 11B, when the value C of the counter 2-10 is C = 7, the data of the address ad 6 is read by fail (fail bit 1,2). As a result, the data receiver 2-8a (value pf_info1) and the counter 2-11a (value Ca1) are masked. Further, when the value C of the counter 2-10 is C = 8, the data at the address ad 7 is read by fail (fail bit 2). As a result, the data receiver 2-8b (value pf_info2) and the counter 2-11b (value Cb) are masked. Then, after the end of cycle 3, the data is transferred to the LSI tester by scan shift.

As described above, the present integrated circuit fails during the BIST test, like the integrated circuit of the first embodiment.
Multiple sets of bit information and fail address information can be stored. That is, this integrated circuit can store the fail bit information and the fail address information without interrupting the BIST test until all the predetermined number of storage circuits are stored. Therefore, this integrated circuit can output a plurality of sets of fail bit information and fail address information to the LSI tester by scan shift in one BIST test.

In addition, this integrated circuit has a storage circuit (a plurality of sets of fail bit information and fail address information).
If the data is stored in all of the data receivers 2-8a, 2-8 etc. and the counters 2-11a, 2-11b etc.), the data receiver 2-8a, counter 2-11a, Mask 2-11b etc. and advance the test address until the end of each cycle. Then, this integrated circuit holds the fail address at which the fail bit was finally detected in the memory circuit (for example, the counter 2-11b in FIG. 6 and the counter 2-11m in FIG. 8), and performs the test in the next BIST test. The storage of test results in the data receivers 2-8a, 2-8b, etc. is stopped until the counter 2-10 of the target address reaches the fail address. Therefore, this integrated circuit temporarily holds the BIST test results in multiple memory circuits, transfers the BIST test results in the scan shift with the low-speed clock, and starts from the address next to the previous fail address in the next BIST test. The test can be restarted and continued efficiently with less resources and without waste.

Further, this integrated circuit generates test data by the pattern generators 1-1 and 2-1.
Store in scan latch 2-2 and scan latch 2-5. The memory 2-3 writes the test data input from the scan latch 2-2 to the test target address designated by the counter 2-10 according to the high frequency clock generated by the PLL circuit 2-22. Further, the memory 2-3 reads data from the test target address designated by the counter 2-10 according to the high frequency clock and stores it in the scan latch 2-4. Then, the comparator 2-6 compares the data RD stored in the scan latch 2-4 with the expected value (mean) of the scan latch 2-5 according to the high-speed clock, and generates a test result. As described above, this integrated circuit can execute the BIST test according to the high frequency clock generated by the PLL circuit 2-22.

The integrated circuit has data receivers 2-8a and 2-8b and mask circuits 2-7a and 2-7b as shown in FIG. When the fail bit information is stored in the data receiver 2-8a, the mask signal Ia is generated by the OR gate 2-9a, and the mask circuit 2-7a writes new fail bit information to the data receiver 2-8a. Cut off. As a result, the data receiver 2-8a can hold the fail bit information generated first. When fail bit information different from that of the data receiver 2-8a is stored in the data receiver 2-8b, the mask signal Ib is generated by the comparator 2-16 and the AND gate 2-19, and the mask circuit 2-7b outputs the data. Block writing of new fail bit information to receiver 2-8b. Such an operation is the same even when the storage circuit illustrated in FIG. 8 has a three-system configuration or the storage circuit has three or more systems. Therefore, according to this embodiment, different pieces of fail bit information acquired in the RAMs 1-3 and 2-3 can be selected and stored in plural.

Further, this integrated circuit has counters 2-11a and 2-11b driven by the same clock as the counter 2-10 and data receivers 2-8a and 2-8b as shown in FIG. When the fail bit information is stored in the data receivers 2-8a, 2-8b, the mask signals Ia, Ib are generated in the integrated circuit, and the counters 2-corresponding to the data receivers 2-8a, 2-8b are used. The clocks to 11a, 2-11b are blocked by the mask circuits 2-12a, 2-12b. Therefore, this integrated circuit can accurately detect the test target address in which the fail bit information appears. The detection of the test target address is similarly performed by the counters 1-11a, 1-11b, 1-11m and the data receivers 1-8a, 1-8b, 1-8m shown in FIG.

Further, like the integrated circuit of the first embodiment, this integrated circuit skips without storing fail bit information when the same fail bit pattern continues, so that the processing time can be shortened. Further, the present integrated circuit counts the number of repetitions when the same fail bit information is repeatedly repeated a plurality of times by the counter 2-20 of FIG. 6 and the counters 1-20a and 1-20b of FIG. Therefore, the present integrated circuit can detect the number of appearances even if the same fail bit information is skipped without being stored.

Further, in the present integrated circuit, when one fail bit information (first fail bit information) is continuously repeated a plurality of times and then the second fail bit information appears, the data receiver 2-8a is 1 fa
The il bit information is held, and the data receiver 2-8b holds the second fail bit information. Further, the counter 2-11a holds the first fail address information which is the test target address where the first fail bit information appears, and the counter 2-11b is the test target address where the second fail bit information appears. Holds the second fail address information. Therefore, this integrated circuit can hold a plurality of fail bit information and a plurality of fail address information with one activation of the BIST test. Therefore, the present integrated circuit can suppress the number of repetitions of the BIST test and efficiently execute the FBM test.

  Furthermore, this integrated circuit shortens the processing time by skipping the acquisition of the test result when the BIST test result is pass. Furthermore, in the present integrated circuit, after the first fail bit information appears, the BIST test result becomes pass, and when the second fail bit information that appears next appears repeatedly multiple times, It has a counter 2-20 for counting the number of repetitions of fail bit information. Therefore, this integrated circuit skips the acquisition of the test result when the BIST test result is pass, and the efficiency is the same as the first fail bit information for the subsequent second fail bit information. Can be processed as desired.

  Further, as described above, this integrated circuit has the fail bit information held in the data receivers 1-8a, 1-8b, 1-8m, 2-8a, 2-8b, the counters 1-11a, 1-11b, 1 -11m, 2-11a, 2-11b, the fail address information, the number of repetitions of the same fail bit information held in the counters 1-20a, 1-20b, etc. can be collectively transferred to the LSI tester.

1-1,2-1,3-1 pattern generator
1-3,2-3,3-3 memory
1-8a, 1-8b, 1-8m data receiver
1-10,1-11a, 1-11b, 1-11m, 1-20,1-20a, 1-20b counter
1-13,1-13b, 1-13c, 1-18a, 1-18b Comparator
3-8a, 3-8b, 3-8m fail bit memory circuit
3-11a, 3-11b, 3-11c fail address storage circuit
3-18a, 3-18b Comparison circuit
3-19 Mask signal generation circuit
3-20a, 3-20b Same fail continuous counter

Claims (8)

Storage part,
An address generation unit that generates a test target address of the storage unit by a first counter according to a first clock;
A test execution unit that generates test result data at each test target address of the storage unit;
A plurality of result data storage units for sequentially storing error result data when the test result is an error,
A plurality of address storage units respectively storing a plurality of test target addresses corresponding to the error result data held in the plurality of result data storage unit,
The error result data is stored in each of the plurality of result data storage units, the test target address is stored in each of the plurality of address storage units, and the error result data stored in each of the plurality of result data storage units and An external output unit that outputs the test target address stored in each of the plurality of address storage units to an external device,
A first clock circuit that supplies the first clock to the storage unit, the address generation unit, the test execution unit, the plurality of result data storage units, and the plurality of address storage units;
A second clock circuit that supplies a second clock, which is slower than the first clock, to the external output unit;
Equipped with
Each of the plurality of address storage units,
A second counter that is driven by the same clock as the first clock that drives the first counter and that counts the test target address;
When error result data is stored in any of the plurality of result data storage units, the clock to the second counter of the address storage unit corresponding to the result data storage unit storing the error result data is shut off. and the cut-off circuit, and possess,
The address storage unit that holds the last test target address among the test target addresses in which the plurality of error result data appear is a test generated by the test execution unit after the output to the external device by the external output unit. Of the result data, the integrated circuit that blocks the storage of the error result data at the test target address before the last test target address . A first block of storing the next error result data in the first result data storage unit when the error result data is stored in the first result data storage unit of the plurality of result data storage units. A cutoff circuit,
A second error different from the first error result data is stored in the second result data storage unit after the first error result data is stored in the first result data storage unit of the plurality of result data storage units. The integrated circuit according to claim 1, further comprising a second shutoff circuit that shuts off the storage of the next error result data in the second result data storage unit when the result data is stored.   The integrated circuit according to claim 1, further comprising a third counter that counts the number of repetitions when the same error result data is repeated a plurality of times in succession.   When the second error result data different from the first error result data is generated after the first error result data is continuously repeated a plurality of times, the first error result data of the plurality of result data storage units is stored. The first result data storage unit holds the first error result data, the second result data storage unit holds the second error result data, and the first address of the plurality of address storage units. 4. The storage unit holds a test target address in which the first error result data appears, and the second address storage unit holds a test target address in which the second error result data appears. An integrated circuit according to item.   The number of repetitions of the second error result data when the normal error result data is generated after the first error result data is continuously repeated a plurality of times and then the second error result data is repeatedly generated. The integrated circuit according to claim 1, further comprising a fourth counter that counts.   The external output unit outputs error result data stored in a plurality of result data storage units, the number of repetitions of the error result data repeatedly, and a test target address at which the error result data is detected to an external device. The integrated circuit according to any one of claims 1 to 5. Further comprising a data generation unit that generates test data to be written in the test target address of the storage unit,
The test execution unit stores the test data as an expected value, writes the test data to the test target address, compares the data read from the test target address in which the test data is written with the expected value. The integrated circuit according to any one of claims 1 to 6 , which generates test result data. In accordance with the first clock, the first counter generates a test target address in the storage unit, generates test result data at each test target address in the storage unit, and outputs error result data when the test result is an error. Are sequentially stored in a plurality of result data storage units, and a plurality of test target addresses corresponding to the error result data respectively held in the plurality of result data storage units are repeatedly stored in a plurality of address storage units.
The error result data is stored in each of the plurality of result data storage units, and the test target address is stored in each of the plurality of address storage units. Outputting the error result data respectively stored in the result data storage section and the test target addresses respectively stored in the plurality of address storage sections to an external device,
Each of the plurality of address storage units,
A second counter that is driven by the same clock as a first clock that drives a first counter that generates a test target address of the storage unit and that counts the test target address;
When an error result data is stored in one of said plurality of result data storage unit, shut off the clock to the second counter address storage unit corresponding to said error result result data storage unit that stores data ,
The address storage unit that holds the last test target address among the test target addresses in which the plurality of error result data appear is the last test among the test result data that is further generated after the output to the external device. A test method for an integrated circuit that blocks storage of error result data at a test target address before the target address .

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