JP6690162B2 - Key matrix circuit - Google Patents

Description

  The present invention relates to a key matrix circuit.

  A key matrix circuit is generally used for operation keys (for example, a numeric keypad) of electronic devices such as mobile phones and car navigations that have become widespread in recent years. The operation of devices using such a key matrix circuit has become complicated as the functions have improved, and it is possible to achieve all of the multiple functions that the devices have by just using the key alone as in the past. It has become difficult to respond.

  For this reason, it is hoped that not only will keys be used alone, but multiple keys will be pressed at the same time to enable key operations that support more functions without increasing the number of keys. It is rare. However, in the key matrix circuit, when three or more keys are pressed at the same time, it may not be possible to distinguish from a case where another key that has not been pressed is pressed, and there is a problem that accurate detection cannot be performed.

  In order to solve such a problem, conventionally, for example, in Patent Document 1, by using a key switch with resistance for all the key switches, even if three or more keys are pressed at the same time, There is described a configuration capable of detecting a key that has been pressed.

JP, 2009-32203, A

  However, the key switch with resistance is expensive because it is a special component, and if the configuration described in Patent Document 1 is adopted, it is difficult to keep the cost low. On the other hand, if an external resistor is added to a normal key switch to realize the same function as that of the key switch with resistance, the cost can be reduced. Therefore, if all the key switches with resistance described in Patent Document 1 are replaced with a configuration in which a normal key switch and an external resistor are combined, the cost can be kept low.

  However, in many cases, it is not allowed to occupy a large mounting space for an operation key or the like that uses a key matrix circuit. Therefore, if a configuration in which a normal key switch and an external resistor are combined is newly added, There is a problem in securing the required mounting space for the external resistor.

  The present invention has been made in view of the above circumstances, and a key matrix circuit capable of accurately detecting a pressed key switch even when three or more key switches are simultaneously pressed, An object of the present invention is to suppress an increase in mounting space while realizing the structure using an ordinary key switch and an external resistor that can reduce cost.

In order to solve the above problems, the present invention is understood by the following configurations.
(1) The key matrix circuit of the present invention is a key matrix circuit, in which a power supply voltage is applied via a first key scan output signal line, a second key scan output signal line, and a pull-up resistor. A plurality of key return input signal lines, a plurality of key switches that are a first key switch group that electrically connect the first key scan signal line and each of the key return signal lines, and A plurality of key switches, which is a second key switch group electrically connecting between two key scan signal lines and each of the key return signal lines, and the first key scan signal line on which the first key switches are connected. A plurality of first connection points to which a plurality of key switches, which are a first key switch group, are connected to the key scan signal line of the second key scan signal line, and the second key scan signal line on the second key scan signal line. A plurality of second connection points to which a plurality of key switches, which are a second key switch group, are respectively connected to the signal line, and a position between the adjacent first connection points is defined as a certain first position, When the position between the second connection points is set to the second position, the signal is controlled to either the first position or the second position connected to the same key return input signal line via the key switch. A resistance is provided, and the resistance values of the first signal control resistors provided at the plurality of first positions are different from the resistance values of the second signal control resistors provided at the plurality of second positions.

  (2) In addition to the configuration of (1) above, a third key scan output signal line is arranged and electrically connects between the third key scan signal line and each of the key return signal lines. A plurality of key switches, which is a third key switch group, and a plurality of key switches, which are a third key switch group and are connected to the third key scan signal line, respectively. And a third signal control resistor is provided at every other third position when the position between the adjacent third connection points is defined as a third position. The resistance value of the third signal control resistor is different from both the resistance value of the first signal control resistor and the resistance value of the second signal control resistor.

  (3) In addition to the configuration of (2) above, a fourth key scan output signal line is arranged and electrically connects between the fourth key scan signal line and each of the key return signal lines. A plurality of key switches that are a group of four key switches, and a plurality of key switches that are a group of a fourth key switch that are connected to the fourth key scan signal line on the fourth key scan signal line. And a fourth connection point of, and when the position between the adjacent fourth connection points is set to the fourth position, the third position is connected to the same key return input signal line via the key switch. When the signal control resistor is not provided, the signal control resistor is provided at the fourth position, and the resistance value of the fourth signal control resistor is the resistance value of the first signal control resistor and the second signal control resistor. Resistance value and Different than either of the resistance value of the resistor.

(4) In the configuration of (3) above, two key switches connected to the same key return input signal line in the third key switch group and the fourth key switch group and the same key return input. A key switch connected to another key return input signal line which is not adjacent to the signal line and is connected to a key scan output signal line to which the two key switches are connected, and one of the other key switch The key switch of, and a sneak route that passes through, and a normal route that passes only the other key switch, the resistance value of the entire sneak route and the resistance value of the entire normal route differ from each other. The resistance values of the third signal control resistor and the fourth signal control resistor located on the sneak route and the normal route are selected so that It has been.

  According to the present invention, even when three or more key switches are simultaneously pressed, a key matrix circuit capable of accurately detecting the pressed key switches is provided, and the cost can be reduced to a normal key matrix circuit. It is possible to provide a key matrix circuit that realizes a configuration using a switch and an external resistor while suppressing an increase in mounting space.

It is a figure which shows the structure of the key matrix circuit of 1st Embodiment of this invention. (A) is a diagram for explaining the operation of the first embodiment, and (b) is a diagram showing an equivalent circuit of (a). (A) is a diagram for explaining the operation of the first embodiment, and (b) is a diagram showing an equivalent circuit of (a). (A) is a diagram for explaining the operation of the first embodiment, and (b) is a diagram showing an equivalent circuit of (a). (A) is a diagram for explaining the operation of the first embodiment, and (b) is a diagram showing an equivalent circuit of (a). (A) is a diagram for explaining the operation of the first embodiment, and (b) is a diagram showing an equivalent circuit of (a). (A) is a diagram for explaining the operation of the first embodiment, and (b) is a diagram showing an equivalent circuit of (a). (A) is a diagram for explaining the operation of the first embodiment, and (b) is a diagram showing an equivalent circuit of (a). (A) is a diagram for explaining the operation of the first embodiment, and (b) is a diagram showing an equivalent circuit of (a). (A) is a figure of operation | movement description of the 1st modification of 1st Embodiment, (b) is a figure which showed the equivalent circuit of (a). (A) is a figure of operation | movement description of the 1st modification of 1st Embodiment, (b) is a figure which showed the equivalent circuit of (a). (A) is a figure of operation | movement description of the 1st modification of 1st Embodiment, (b) is a figure which showed the equivalent circuit of (a). (A) is a figure of operation | movement description of the 1st modification of 1st Embodiment, (b) is a figure which showed the equivalent circuit of (a). (A) is a figure of operation | movement description of the 1st modification of 1st Embodiment, (b) is a figure which showed the equivalent circuit of (a). (A) is a figure of operation | movement description of the 1st modification of 1st Embodiment, (b) is a figure which showed the equivalent circuit of (a). (A) is a figure of operation | movement description of the 1st modification of 1st Embodiment, (b) is a figure which showed the equivalent circuit of (a). (A) is a figure of operation | movement description of the 1st modification of 1st Embodiment, (b) is a figure which showed the equivalent circuit of (a). It is a figure which shows the 2nd modification of 1st Embodiment. It is a figure which shows the 3rd modification of 1st Embodiment. It is a figure which shows the 4th modification of 1st Embodiment. (A) is a figure explaining operation of the 3rd modification of a 1st embodiment, and (b) is a figure showing the equivalent circuit of (a). (A) is a figure explaining operation of the 3rd modification of a 1st embodiment, and (b) is a figure showing the equivalent circuit of (a). (A) is a figure explaining operation of the 3rd modification of a 1st embodiment, and (b) is a figure showing the equivalent circuit of (a). (A) is a figure explaining operation of the 3rd modification of a 1st embodiment, and (b) is a figure showing the equivalent circuit of (a). (A) is a figure explaining operation of the 3rd modification of a 1st embodiment, and (b) is a figure showing the equivalent circuit of (a). (A) is a figure explaining operation of the 3rd modification of a 1st embodiment, and (b) is a figure showing the equivalent circuit of (a). (A) is a figure explaining operation of the 3rd modification of a 1st embodiment, and (b) is a figure showing the equivalent circuit of (a). (A) is a figure explaining operation of the 3rd modification of a 1st embodiment, and (b) is a figure showing the equivalent circuit of (a). (A) is a figure explaining operation of the 3rd modification of a 1st embodiment, and (b) is a figure showing the equivalent circuit of (a). (A) is a figure explaining operation of the 3rd modification of a 1st embodiment, and (b) is a figure showing the equivalent circuit of (a). (A) is a figure explaining operation of the 3rd modification of a 1st embodiment, and (b) is a figure showing the equivalent circuit of (a). (A) is a figure explaining operation of the 3rd modification of a 1st embodiment, and (b) is a figure showing the equivalent circuit of (a). (A) is a figure explaining operation of the 3rd modification of a 1st embodiment, and (b) is a figure showing the equivalent circuit of (a). (A) is a figure explaining operation of the 3rd modification of a 1st embodiment, and (b) is a figure showing the equivalent circuit of (a). (A) is a figure explaining operation of the 3rd modification of a 1st embodiment, and (b) is a figure showing the equivalent circuit of (a). (A) is a figure explaining operation of the 3rd modification of a 1st embodiment, and (b) is a figure showing the equivalent circuit of (a). (A) is a figure explaining operation of the 3rd modification of a 1st embodiment, and (b) is a figure showing the equivalent circuit of (a). (A) is a figure explaining operation of the 3rd modification of a 1st embodiment, and (b) is a figure showing the equivalent circuit of (a). (A) is a figure explaining operation of the 3rd modification of a 1st embodiment, and (b) is a figure showing the equivalent circuit of (a). (A) is a figure explaining operation of the 3rd modification of a 1st embodiment, and (b) is a figure showing the equivalent circuit of (a). (A) is a figure explaining operation of the 3rd modification of a 1st embodiment, and (b) is a figure showing the equivalent circuit of (a). (A) is a figure explaining operation of the 3rd modification of a 1st embodiment, and (b) is a figure showing the equivalent circuit of (a). (A) is a figure explaining operation of the 3rd modification of a 1st embodiment, and (b) is a figure showing the equivalent circuit of (a). (A) is a figure explaining operation of the 3rd modification of a 1st embodiment, and (b) is a figure showing the equivalent circuit of (a). (A) is a figure explaining operation of the 3rd modification of a 1st embodiment, and (b) is a figure showing the equivalent circuit of (a). (A) is a figure explaining operation of the 3rd modification of a 1st embodiment, and (b) is a figure showing the equivalent circuit of (a). (A) is a figure explaining operation of the 3rd modification of a 1st embodiment, and (b) is a figure showing the equivalent circuit of (a). (A) is a figure explaining operation of the 3rd modification of a 1st embodiment, and (b) is a figure showing the equivalent circuit of (a). (A) is a figure of operation explanation explaining a problem at the time of expanding the 3rd modification of a 1st embodiment, and (b) is a figure showing an equivalent circuit of (a). (A) is a figure explaining operation | movement of 2nd Embodiment, (b) is a figure which showed the equivalent circuit of (a). (A) is a figure explaining operation | movement of 2nd Embodiment, (b) is a figure which showed the equivalent circuit of (a). (A) is a figure explaining operation | movement of 2nd Embodiment, (b) is a figure which showed the equivalent circuit of (a).

Embodiment of the invention

  Hereinafter, a mode for carrying out the present invention (hereinafter referred to as the present embodiment) will be described in detail with reference to the accompanying drawings. The same elements are denoted by the same numbers throughout the description of this embodiment.

(Configuration of the first embodiment)
FIG. 1 shows the configuration of the key matrix circuit 10 of this embodiment. As shown in FIG. 1, the key matrix circuit 10 of the present embodiment includes a key matrix unit 11 and a control unit 12.

The key matrix unit 11 has two key scan output signal lines (scan line KS_A and scan line KS_B).
For simplicity of description, the scan line KS_A will be referred to as a first key scan output signal line, and the scan line KS_B will be referred to as a second key scan output signal line, unless otherwise specified. However, when the scan line KS_B is the first key scan output signal line, the scan line KS_A is the second key scan output signal line.

  Further, hereinafter, the scan line KS_A and the scan line KS_B will be referred to as a first key scan output signal line and a second key scan output signal line, respectively, and accordingly, the portions related to these will also be referred to as “first , "And" second ", the scan line KS_B is replaced with the first key scan output signal line and the scan line KS_A is replaced with the second key scan output signal line. The case should be construed to interchange the terms “first” and “second” given with respect to parts related to these.

  As shown in FIG. 1, in the key matrix section 11, a first key scan output signal line (scan line KS_A) and a second key scan output signal line (scan line KS_B) are wired.

  Then, for the first key scan output signal line (scan line KS_A) and the second key scan output signal line (scan line KS_B), a plurality of key return input signal lines (return lines KR1, KR2, KR3, KR4, KR5, KR6) are wired.

Further, the key matrix unit 11 has the first key scan output signal line (scan line KS_A) and the respective key return input signal lines (return lines KR1, KR2, KR3, KR4, KR5, KR6) when pressed. It is provided with key switches (A_SW1, A_SW2, A_SW3, A_SW4, A_SW5, A_SW6) that electrically connect the two.
In addition, when collectively calling these key switches electrically connected to the first key scan output signal line (scan line KS_A), they are referred to as a first key switch group. .

  Specifically, the respective key switches (A_SW1, A_SW2, A_SW3, A_SW4, A_SW5, A_SW6) of the first key switch group correspond to the respective key switches (A_SW1, A_SW2, A_SW3, A_SW4) of the first key switch group. , A_SW5, A_SW6) and a first key scan output signal line (scan line KS_A) and a key return input signal line (return lines KR1, KR2, KR3, KR4, KR5, KR6) are electrically connected by a wiring L. It is connected to the.

  Then, between the connection point P between the wiring L from the key switch (A_SW1, A_SW2, A_SW3, A_SW4, A_SW5, A_SW6) of the first key switch group and the first key scan output signal line (scan line KS_A). Signal control resistors (RA1, RA2, RA3, RA4, RA5, RA6) are provided at the plurality of first positions in.

  The signal control resistors (RA1, RA2, RA3, RA4, RA5, RA6) provided at the first position on the first key scan output signal line (scan line KS_A) are referred to as first signal control resistors. Unless otherwise specified, the description will proceed assuming that the first signal control resistors have the same resistance value.

  Specifically, at the first position between the connection points P between the wiring L from the key switch (A_SW2) and the first key scan output signal line (scan line KS_A), the first signal control resistor ( RA2) is provided, and the first signal is provided at the first position between the connection points P between the wiring L from the key switch (A_SW3) and the first key scan output signal line (scan line KS_A). A control resistor (RA3) is provided, and sequentially for the key switches (A_SW4, A_SW5, A_SW6), the wiring L from the key switches (A_SW3, A_SW4, A_SW5, A_SW6) and the first key scan output signal line are also provided. The first signal control resistors (RA4, RA5, RA6) are respectively provided at the first positions between the connection points P with the (scan line KS_A). It has been kicked. The first signal control resistor RA1 does not have to be arranged because the resistor is provided at the starting point of the normal output port KS_A.

Also, the key matrix unit 11 has a second key scan output signal line (scan line KS_B) and each key return input signal line (return lines KR1, KR2, KR3, KR4, KR5, KR6) when pressed. Key switches (B_SW1, B_SW2, B_SW3, B_SW4, B_SW5, B_SW6) for electrically connecting the two are provided.
In addition, when collectively calling these key switches electrically connected to the second key scan output signal line (scan line KS_B), they are referred to as a second key switch group. .

  Specifically, the respective key switches (B_SW1, B_SW2, B_SW3, B_SW4, B_SW5, B_SW6) of the second key switch group are the respective key switches (B_SW1, B_SW2, B_SW3, B_SW4) of the second key switch group. , B_SW5, B_SW6) and a second key scan output signal line (scan line KS_B) and a key return input signal line (return lines KR1, KR2, KR3, KR4, KR5, KR6) electrically by a wiring L. It is connected to the.

  On the other hand, in this example, the connection point between the wiring L from the key switch (B_SW1, B_SW2, B_SW3, B_SW4, B_SW5, B_SW6) of the second key switch group and the second key scan output signal line (scan line KS_B). No signal control resistor is provided at the second position between Ps.

  As shown in FIG. 1, pull-up resistors (R1, R2, R3, R4, R5, R6) are respectively connected to the respective key return input signal lines (return lines KR1, KR2, KR3, KR4, KR5, KR6). The power supply voltage VDD is applied.

(Basic operation of key matrix circuit)
In the following, a basic operation will be briefly described with respect to how the pressed state (key switch ON state) and non-pressed state (key switch OFF state) of the key switch are detected in the above configuration. .

  First, each key return input signal line (return line KR1, KR2, KR3, KR4, KR5, KR6) receives a power supply voltage VDD via a pull-up resistor (R1, R2, R3, R4, R5, R6). Always applied.

A microcomputer having six A / D (Analog / Digital) input ports (not shown) is mounted in the control unit 12, and each key return input signal line (return line KR1, return line KR1, KR2, KR3, KR4, KR5, KR6) are connected.
Therefore, when all the key switches are OFF, that is, when the key switches are not pressed, the voltage value (potential difference) corresponding to the applied power supply voltage VDD, that is, the voltage value is High at each input port. The condition is detected.

  On the other hand, in the two key scan output signal lines (scan line KS_A and scan line KS_B), the voltage value of the key scan output signal line to be scanned is set to Low, and the voltage value of the other key scan output signal line is set to High. . This operation is switched at regular time intervals.

  That is, the voltage value of the first key scan output signal line (scan line KS_A) is low and the voltage value of the second key scan output signal line (scan line KS_B) is high for a certain period of time. The performed key scan output signal line is the first key scan output signal line (scan line KS_A).

After a lapse of a fixed time, the voltage value of the first key scan output signal line (scan line KS_A) is High and the voltage value of the second key scan output signal line (Scan line KS_B) is Low. At this time, the key scan output signal line which is scanning is the second key scan output signal line (scan line KS_B).
In this way, the scan of the key scan output signal line is alternately repeated at a certain time interval.

Here, a case where the key scan output signal line which is performing the scan is the first key scan output signal line (scan line KS_A) will be described below.
In this case, any of the key switches A_SW1, A_SW2, A_SW3, A_SW4, A_SW5, and A_SW6 is OFF, that is, when not pressed, the voltage value corresponding to the applied power supply voltage VDD is still applied to each input port. (Potential difference), that is, a state in which the voltage value is High is detected.

On the other hand, for example, when the key switch A_SW2 is turned on, that is, pressed, the first key scan output signal line (scan line KS_A) and the key return input signal line of the return line KR2 are electrically connected via the key switch A_SW2. Will be done.
Therefore, upon receiving the voltage value Low of the first key scan output signal line (scan line KS_A), the voltage value of the key return input signal line of the return line KR2 also becomes Low.

  The key return input signal line of the return line KR2 is connected to the key switches of A_SW2 and B_SW2, and the key scan output signal line during scanning is the first key scan output signal line (scan line KS_A). Therefore, the key switch corresponding to this is A_SW2.

Therefore, when the voltage value (potential difference) of the key return input signal line of the return line KR2 changes while scanning the first key scan output signal line (scan line KS_A), the key switch A_SW2 is turned on, that is, pressed. Is detected.
Similarly, when only the key switch A_SW1 is ON, that is, when it is pressed, it is basically detected that the key switch A_SW1 is pressed by the same operation as the operation of the key switch A_SW2. .

  Even when the other key switch is pressed, the basic operation, that is, the change in the voltage value (potential difference) of which key return input signal line is detected when scanning which key scan output signal line. Which key switch is ON, that is, the key switch is pressed.

(Operation when multiple key switches are pressed simultaneously)
The basic operation of the present invention is as described above, and the case where a plurality of key switches are simultaneously turned on, that is, pressed, will be described below.

2A shows a circuit diagram basically the same as FIG. 1, but in order to make the signal flow easy to see, the key scan output signal lines (scan lines KS_A, KS_B) and the key return input signal line ( The return line KR1, KR2, KR3, KR4, KR5, KR6) is mainly shown, and the control unit 12 and pull-up resistors (R1, R2, R3, R4) are omitted.
It should be noted that, also in the subsequent drawings, the control unit 12, the pull-up resistors (R1, R2, R3, R4) and the like are omitted, as in FIG. 2A.

  First, the operation when a plurality (three) of the four adjacent key switches A_SW1, A_SW2, B_SW1, and B_SW2 are simultaneously pressed will be described.

First, a description will be given assuming a situation where the diagonally hatched key switches A_SW1, A_SW2, and B_SW1 in FIG. 2A are simultaneously pressed.
In the basic operation of the key matrix circuit described above, the voltage value changes. However, for simplicity of description, the expression "scan signal" is used to describe the signal flow.
Also, in the following figures, diagonally hatching is provided for key switches that are being pressed, and hatching is not provided for key switches that are not.

  Although not shown in FIG. 2, when the scan line KS_A is scanned, that is, when a scan signal is output to the scan line KS_A, the flow of the scan signal (the flow of change in voltage) is the key switch. The signal is input to the key return input signal lines (return lines KR1 and KR2) via A_SW1 and the key switch A_SW2, respectively.

  In this case, while scanning the scan line KS_A, the scan signal is input to the key return input signal lines (return lines KR1 and KR2) corresponding to the pressed key switches A_SW1 and A_SW2 (voltage value ( Change) is detected), and it is determined that the key switches A_SW1 and A_SW2 are pressed. This is a correct determination state, so there is no problem.

  On the other hand, as shown in FIG. 2A, when a scan signal is output from the scan line KS_B to scan the scan line KS_B (voltage value Low of the scan line KS_B), the return line KR2 of the key return input signal line is output. There are two possible routes for the scan signal to be input into the case where only one B_SW2 is pressed and when three of A_SW1, A_SW2 and B_SW1 are simultaneously pressed. Each case will be described in detail below.

First, when one normal key switch is pressed, the scan signal is input to the return line KR2 when it passes through the solid line path shown in FIG. 2A, that is, the key switch B_SW2 is pressed. That is the case.
Since it is more common to press one key switch, the path of the scan signal in this case will be referred to as a normal path hereinafter.

On the other hand, as can be seen from FIG. 2A, when these three key switches (A_SW1, A_SW2, B_SW1) are simultaneously pressed, the scan signal is input to the return line KR2 via the route indicated by the dotted line. To be done.
Note that, hereinafter, the path of the scan signal that passes through such a plurality of key switches will be referred to as a sneak path.

  Actually, the key switches (A_SW1, A_SW2, B_SW1) are actually pressed, but the key switch B_SW2 has the same circuit as that being pressed, and the key switches A_SW1, A_SW2, and B_SW1 are not simultaneously pressed. Therefore, it cannot be determined (undetectable) whether or not only one of B_SW2 is pressed.

The operation of this configuration when there are two routes that may be undetectable as described above will be further described below.
FIG. 2B shows an equivalent circuit in which the path of the scan signal is linearly shown, and the pull-up resistor R1 and the control unit 12 are omitted in FIG. 2B as well.
Note that, in the following figures, the diagram shown as (b) is a diagram showing an equivalent circuit of the same diagram (a) unless otherwise specified.

The left side of FIG. 2B shows an equivalent circuit in the case of the normal route, while the right side of FIG. 2B shows an equivalent circuit of the detour route.
As shown in FIG. 2B, in the configuration of the present invention, the signal control resistor does not exist in the normal route, while the first signal control resistor RA2 exists in the detour route.
Therefore, the scan signal input to the return line KR2 is detected as a different voltage value (potential difference) in the normal route and the sneak route because it is affected by the presence or absence of the signal control resistor.

  The key switches A_SW1, A_SW2, B_SW1, and B_SW2 that can be pressed when scanning the scan line KS_B are B_SW1 and B_SW2. Therefore, depending on the difference in voltage value (potential difference), Since it is possible to determine which key switch is pressed, it is possible to avoid undetectability.

  Here, the principle by which simultaneous pressing of the key switches A_SW1, A_SW2, and B_SW1 can be detected will be described with reference to FIG. First, when the key switch A_SW1 is pressed, the Low signal output from the KS_A line is input to KR_1 via the resistor RA1 and the key switch A_SW1, and KR_1 is divided by the pull-up resistor and the resistor RA1 that are pulled up by the power supply voltage VDD (not shown). It is detected by the fact that it becomes a pressure potential. When the key switch A_SW2 is pressed, the Low signal output from the KS_A line is input to KR_2 via the resistor RA2 and the key switch A_SW2, and KR_2 is divided by a pull-up resistor and a resistor RA2 that are pulled up by a power supply voltage VDD (not shown). It is detected by the fact that it becomes a pressure potential. Further, the depression of the key switch B_SW1 is detected when the Low signal output from the KS_B line is input to the KR_2 via the key switch B_SW1 and the KR_1 becomes the Low level. The Low signals output from the KS_A line and the KS_B line have different output timings.

Next, let us consider a case in which the diagonally hatched key switches A_SW1, A_SW2, and B_SW2 in FIG. 3A are simultaneously pressed.
Also here, although not shown, when scanning the scan line KS_A, the same result as that described above is obtained, so the determination state is correct, and there is no problem.
On the other hand, in the case of scanning the scan line KS_B, as shown in FIG. 3A, as the route to be input to the key return input signal line (return line KR1), two routes, that is, a normal line indicated by a solid line, are used. There are a route and a wraparound route indicated by a dotted line.

However, in the configuration of the present invention, as shown in FIG. 3B, in the case of the normal route (left side of the figure), there is no signal control resistance, while in the case of the detour route (right side of the figure), There is one signal control resistor RA2.
Therefore, since the scan signal input to the key return input signal line (return line KR1) has different voltage values (potential difference) detected between the normal route and the sneak route, this voltage value (potential difference) causes It is possible to determine which key switch is being pressed, and avoid undetectability.

Next, similar to the above, among the four adjacent key switches A_SW1, A_SW2, B_SW1, B_SW2, the key switches B_SW1 and B_SW2 are pressed, and any one of the key switches A_SW1 or A_SW2 is pressed (3 The operation when two key switches are simultaneously pressed will be described.
In this case, conversely to the above, when scanning the scan line KS_B, a sneak route that causes undetectability does not occur, so the problem is on the scan line KS_A side.

FIG. 4 shows the case where the key switches A_SW2, B_SW1, and B_SW2 are simultaneously pressed. As in the previous case, FIG. 4 (a) shows the normal route and the detour route, and FIG. 4 (b) the normal route and the detour route. The equivalent circuit of is shown.
In this case, as can be seen from FIG. 4B, only the first signal control resistor RA1 is present in the normal route, while the first signal control resistors RA1 and RA2 are present in the sneak route. It is possible to avoid undetectability.

  Similarly, FIG. 5 shows a case where the key switches A_SW1, B_SW1, and B_SW2 are simultaneously pressed, but even in this case, the first signal control resistors RA1 and RA2 are present in the normal route, whereas the sneak route is Since only the first signal control resistor RA1 is provided, it is possible to avoid undetectability.

Although the case where three key switches of the key switches A_SW1, A_SW2, B_SW1, and B_SW2 are simultaneously pressed has been described above, the same applies to the case of the key switches A_SW2, A_SW3, B_SW2, and B_SW3. Since the resistance state is different between the normal route and the sneak route, it is possible to avoid undetectability.

  That is, in the key switches A_SW2, A_SW3, B_SW2, and B_SW3, when the key switches A_SW2 and A_SW3 are pressed, and when any one of the key switches B_SW2 and B_SW3 is pressed, the scan line KS_B wraps around. Although a route occurs, when the key switch B_SW2 is pressed, the signal control resistor does not exist in the normal route (route that passes only the key switch B_SW3), while the first signal control resistor RA3 exists in the detour route. Will be done.

  On the contrary, when the key switch B_SW3 is pressed and the key switch B_SW2 is not pressed, the signal control resistor does not exist in the normal route (route that passes only the key switch B_SW2), while the first signal is used in the sneak route. The control resistor RA3 will be present.

  Similarly, in the key switches A_SW2, A_SW3, B_SW2, and B_SW3, when the key switches B_SW2 and B_SW3 are pressed, and when any one of the key switches A_SW2 and A_SW3 is pressed, the scan line KS_A is scanned. Although a sneak route is generated, in this case as well, the number of intervening first signal control resistors is different between the normal route and the sneak route, so that detection failure can be avoided.

  Specifically, when the key switches B_SW2 and B_SW3 are pressed, and when the key switch B_SW2 is pressed, the first signal control resistors RA1, RA2, RA3 are taken in the normal route (route passing only the key switch A_SW3). However, only the first signal control resistors RA1 and RA2 are present in the loop route.

  When the key switches B_SW2 and B_SW3 are pressed and the key switch B_SW3 is pressed, only the first signal control resistors RA1 and RA2 are present in the normal route (route passing only the key switch A_SW2). The first signal control resistors RA1, RA2, RA3 are present in the loop route.

  Further, since a similar phenomenon occurs between four adjacent upper and lower key switches (for example, between the key switches A_SW3, A_SW4, B_SW3 and B_SW4 and between the key switches A_SW4, A_SW5, B_SW4 and B_SW5), detection is performed. It is possible to avoid the impossibility.

Next, let's look at the simultaneous pressing of three key switches at remote positions.
6 and 7, in the key switches A_SW1, A_SW3, B_SW1, and B_SW3, wraparound occurs when the scan line KS_B that presses the key switches A_SW1 and A_SW3 and presses either one of the key switches B_SW1 and B_SW3 is scanned. It is a diagram showing a case where the signal control resistance does not exist in the normal route even in this case, while the first signal control resistances RA2 and RA3 exist in the sneak route, and it is possible to avoid undetectability. Is.

  Note that even if the key switches are further apart, for example, between the key switches A_SW1, A_SW4, B_SW1, and B_SW4, when the key switches A_SW1 and A_SW4 are pressed, either one of the key switches B_SW1 and B_SW4 is pressed. In the same way as above, there is no signal control resistance in the normal route when scanning the scan line KS_B in which the sneak occurs, and the first signal control resistance exists in the sneak route, so undetectable. It is possible to avoid, and this state is the same between the key switches that are far apart (for example, between the key switches A_SW1, A_SW5, B_SW1, and B_SW5 and between the key switches A_SW1, A_SW6, B_SW1, and B_SW6). Yes, it is possible to avoid undetectable It has become.

  On the other hand, in FIGS. 8 and 9, in the key switches A_SW1, A_SW3, B_SW1, and B_SW3, when the key switches B_SW1 and B_SW3 are pressed, and when the scan line KS_A that presses either one of the key switches A_SW1 and A_SW3 is scanned, it wraps around. FIG. 6 is a diagram showing a case in which, however, in this case as well, the number of the first signal control resistors that exist in the normal route and the sneak route are different, and thus it is possible to avoid undetectability.

  In addition, even if the key switch is farther away, for example, between the key switches A_SW1, A_SW4, B_SW1, and B_SW4, when the key switches B_SW1 and B_SW4 are pressed, and either one of the key switches A_SW1 and A_SW4 is pressed. In the same manner as above, since the number of the first signal control resistors that exist in the normal route and the sneak route when scanning the scan line KS_A in which the sneak occurs is different, it is possible to avoid undetectability. It is possible.

  2 to 9, the wiring L from the key switches (A_SW1, A_SW2, A_SW3, A_SW4, A_SW5, A_SW6) of the first key switch group and the first key scan output signal line (scan line KS_A) Signal control resistors (RA1, RA2, RA3, RA4, RA5, RA6) at a plurality of first positions on the first key scan output signal line (scan line KS_A) before the connection point P (on the output port side). I've seen about the case.

  However, when the key scan output signal lines of the first embodiment are two key scan output signal lines (scan line KS_A and scan line KS_B), the arrangement of the signal control resistors is the first key scan output signal line. It is not limited to the first position on the (scan line KS_A).

  Any one of the above-mentioned first signal control resistors (RA1, RA2, RA3, RA4, RA5, RA6) is omitted (for example, RA4, RA5, RA6), and instead, as shown in FIG. Before the connection point P (on the output port side) between the wiring L from the key switch (B_SW1, B_SW2, B_SW3, B_SW4, B_SW5, B_SW6) of the key switch group and the second key scan output signal line (scan line KS_B). A first signal control resistor is provided at a plurality of second positions on the second key scan output signal line (scan line KS_B) and at first positions corresponding to the same key return input signal lines (KR4, KR5, KR6). A first position is provided at a second position that is not provided, that is, a second position corresponding to the first signal control resistors (RA4, RA5, RA6) that are omitted and no longer exist. No. control resistor (RA1, RA2, RA3) and a second signal control resistor of different resistance value (RB4, RB5, RB6) it is sufficient so provided.

In the following, concretely, regarding the first modified example in which the arrangement of the signal control resistors shown in FIG.
First, as shown in FIG. 10, the first signal control resistors RA4, RA5, RA6 are omitted and the same key corresponding to the first position where the first signal control resistors RA4, RA5, RA6 are provided. The wiring L from the second position (key switch (B_SW4, B_SW5, B_SW6) of the second key switch group) corresponding to the return input signal line (KR4, KR5, KR6) and the second key scan output signal line (scan line) KS_B) will be described with respect to the case where the signal control resistors RB4, RB5, and RB6 are provided before (the position on the output port side) the connection point P with KS_B).
The signal control resistor provided on the second key scan output signal line will be referred to as a second signal control resistor.

  FIG. 10 to FIG. 13 show a case where three key switches out of four adjacent two key switches are pressed at the same time, and a case where a sneak route occurs when scanning the scan line KS_B will be described. Shows.

  As for the key switches A_SW1, A_SW2, A_SW3, B_SW1, B_SW2, and B_SW3, there is no change so far. Therefore, in the case of the right side, the group of four adjacent upper and lower key switches is shifted. It shows the case.

As shown in FIG. 10 to FIG. 13, it can be seen that in any case, the resistance state is different between the normal route and the sneak route, and the undetectability can be avoided.
Further, even if a group of four adjacent upper and lower key switches is shifted to the right side, similarly, the state of resistance remains different between the normal route and the sneak route.

Next, in the same arrangement of the signal control resistors as in FIG. 10 to FIG. 13, when the three key switches of the two adjacent upper and lower two key switches are simultaneously pressed, the sneak route is set when scanning the scan line KS_A. As in the case of FIG. 10 to FIG. 13, a case where the groups of four adjacent upper and lower key switches are shifted is shown in FIG. 14 to FIG. It can be seen that the undetectable state can be avoided because the resistance state is different between the wraparound route and the wraparound route.
Further, even if a group of four adjacent upper and lower key switches is shifted to the right side, similarly, the state of resistance remains different between the normal route and the sneak route.

Although illustration is omitted, it is confirmed that the resistance state is different between the normal route and the sneaking route even when the three key switches are simultaneously pressed at the separated positions described with reference to FIGS. 6 to 9. Therefore, it is possible to avoid undetectability.
Further, also in the arrangement of the signal control resistors (first signal control resistor and second signal control resistor) shown in FIG. 18 (second modification), FIG. 19 (third modification), and FIG. 20 (fourth modification). In the same way, in both the case where two key switches adjacent to each other are pressed vertically, and when the three key switches are simultaneously pressed at distant positions, the resistance state is different between the normal route and the sneak route. It has been confirmed and it is possible to avoid undetectability.

For example, in the case of the arrangement of the signal control resistors in FIG. 19 (third modified example), it will be shown just in case that undetectability can be avoided.
The arrangement of the signal control resistors of the third modification shown in FIG. 19 is the wiring L from the key switches (A_SW1, A_SW2, A_SW3, A_SW4, A_SW5, A_SW6) of the first key switch group and the first key scan output. A plurality of first positions on the first key scan output signal line (scan line KS_A) before the connection point P with the signal line (scan line KS_A) (on the output port side) are connected to the first signal control resistor (RA1, The first position having RA3 and RA5) and the first position not having the first signal control resistor appear alternately.

  Then, before the connection point P between the wiring L from the key switch (B_SW1, B_SW2, B_SW3, B_SW4, B_SW5, B_SW6) of the second key switch group and the second key scan output signal line (scan line KS_B) ( A plurality of second positions on the second key scan output signal line (scan line KS_B) of the output port side) and corresponding to the same key return input signal lines (KR1, KR2, KR3, KR4, KR5, KR6). At the second position where the first signal control resistor is not provided at the first position, that is, at the second position corresponding to the key return input signal line (KR2, KR4, KR6), a resistance value different from that of the first signal control resistor is provided. Second signal control resistors (RB2, RB4, RB6) are provided.

  With such an arrangement of the signal control resistors, it is possible that the three key switches in the group of four adjacent two upper and lower key switches are simultaneously pressed, and three remote key switches are simultaneously pressed. For all of these patterns, a diagram showing a signal path and an equivalent circuit diagram are shown, and it is shown below that undetectability can be avoided.

  21 to 26 show a case where a sneak route occurs when scanning the scan line KS_B in the case of a group of four adjacent upper and lower key switches, and the left side key switches (A_SW1, B_SW1) are shown. Even if the group of four key switches is further shifted to the right from the side, a series of patterns up to the state where the same state as that shown so far is repeated is shown.

  Similarly, FIGS. 27 to 32 show the same state as that shown so far even if the group of four key switches is further shifted to the right in the case where the sneak route occurs when scanning the scan line KS_A. It shows a series of patterns up to a repeating state.

  Further, FIGS. 33 to 40 show a case where three key switches are simultaneously pressed at distant positions, and show a series of key switch patterns in which a sneak route occurs when scanning the scan line KS_B. 41 to 48 similarly show a series of patterns of key switches in which a sneak route occurs when the scan line KS_A is scanned.

  As can be seen from FIGS. 21 to 48, since the first signal control resistors (RA1, RA3, RA5) and the second signal control resistors (RB2, RB4, RB6) have different resistance values, they are basically Since the resistance values (combined resistance) of the normal route and the sneaking route are different, it is possible to avoid undetectability.

  Since there are rare cases as shown in FIG. 37, the second signal control resistances (RB2, RB4, RB6) are ½ based on the resistance value BR of the first signal control resistances (RA1, RA3, RA5). It is preferable that the resistance value is different from the resistance value of the first signal control resistor except for the double and double resistance values ((1/2) × BR, 2 × BR).

(Second embodiment)
In the first embodiment, the case of two key scan output signal lines (scan line KS_A, scan line KS_B) has been described, but in the second embodiment, there are four key scan output signal lines (scan line KS_A, A method of expanding the scan line KS_B, the scan line KS_C, and the scan line KS_D will be described.

  For example, as shown in FIG. 49, the number of scan line KS_A and scan line KS_B in the case of FIG. When KS_C and scan line KS_D), as shown in FIG. 49, the normal route and the sneak route may have the same resistance value, which causes undetectability.

  Therefore, as shown in FIG. 50, in the added two key scan output signal lines (scan line KS_C and scan line KS_D), the signal control resistor is not located on the key scan output signal line but the key switch and the key scan output signal line. A signal control resistor is provided so as to be inserted in a wiring that connects the (scan line KS_C, scan line KS_D) and the key return input signal lines (KR1, KR2, KR3, KR4, KR5, KR6).

  When the key switch is used as a reference, the wiring connecting the key switch and the key scan output signal line (scan line KS_C, scan line KS_D) and the key return input signal line (KR1, KR2, KR3, KR4, KR5, KR6) is , A wiring L extending from the key switch to the key scan output signal line (scan line KS_C, scan line KS_D) and a wiring L extending from the key switch to the key return input signal line (KR1, KR2, KR3, KR4, KR5, KR6). However, the signal control resistor to be inserted may be provided on either side of the wiring.

Specifically, in FIG. 50, the third key scan output signal line (scan line KS_C) is provided so as to be arranged next to the second key scan output signal line (scan line KS_B), and is pressed. Key switches (C_SW1, C_SW2, C_SW3) electrically connecting the third key scan output signal line (scan line KS_C) to each key return input signal line (KR1, KR2, KR3, KR4, KR5, KR6). (C_SW4, C_SW5, C_SW6) are provided.
In addition, when collectively calling these key switches electrically connected to the third key scan output signal line (scan line KS_C), they are referred to as a third key switch group.

  However, in FIG. 50, the third key scan output signal line (scan line KS_C) is provided so as to be arranged next to the second key scan output signal line (scan line KS_B). A third key scan output signal line (scan line KS_C) may be provided so as to be arranged next to the scan output signal line (scan line KS_A).

Further, a fourth key scan output signal line (scan line KS_D) is provided so as to be arranged next to the third key scan output signal line (scan line KS_C), and the fourth key scan output is provided by being pressed. Key switches (D_SW1, D_SW2, D_SW3, D_SW4, D_SW5, D_SW6) for electrically connecting the signal line (scan line KS_D) and each key return input signal line (KR1, KR2, KR3, KR4, KR5, KR6) I am trying to provide it.
When collectively referred to as these key switches electrically connected to the fourth key scan output signal line (scan line KS_D), they are referred to as a fourth key switch group.

  Then, the key switches (C_SW1, C_SW2, C_SW3, C_SW4, C_SW5, C_SW6) of the third key switch group, the third key scan output signal line (scan line KS_C) and the key return input signal line (KR1, KR2). , KR3, KR4, KR5, KR6), the wiring in which the third signal control resistances (RC1, RC3, RC5) are inserted and the wiring in which the third signal control resistance is not inserted alternate. It is designed to be installed in.

Also, the key switches (C_SW1, C_SW2, C_SW3, C_SW4, C_SW5, C_SW6) of the third key switch group, the third key scan output signal line (scan line KS_C), and the key return input signal line (KR1, KR2, KR3). , KR4, KR5, KR6), a key return input in which the key switch (C_SW2, C_SW4, C_SW6) of the third key switch group is connected by a wire in which the third signal control resistor is not provided in the wire L that connects The key switches (D_SW2, D_SW4, D_SW6) of the fourth key switch group corresponding to the signal lines (KR2, KR4, KR6), the fourth key scan output signal line (scan line KS_D), and the key return input signal line (KR2). , KR4, KR6), the fourth signal control Resistance (RD2, RD4, RD6) is inserted wiring is so provided.
By doing so, it becomes possible to avoid the undetectability shown in FIG. 49, as shown in FIG.

  By the way, in the case of the arrangement of the signal control resistors shown in FIG. 50, when three key switches as shown in FIG. 51 are simultaneously pressed, the third signal control resistor (RC1) exists in the normal route, and the sneak route There is a second signal control resistor (RB2) in, but if these signal control resistors have the same resistance value, undetectability will occur.

In order to prevent such a case from occurring, the third signal control resistors (RC1, RC3, RC5) are connected to the first signal control resistors (RA1, RA3, RA5) and the second signal control resistors (RB2, RB4). , RB6).
Similarly, regarding the fourth signal control resistors (RD2, RD4, RD5), the first signal control resistors (RA1, RA3, RA5), the second signal control resistors (RB2, RB4, RB6) and the third signal control resistors ( It has a resistance value different from RC1, RC3, RC5).

  Also, as shown in FIG. 52, among the third key switch group (C_SW1, C_SW2, C_SW3, C_SW4, C_SW5, C_SW6) and the fourth key switch group (D_SW1, D_SW2, D_SW3, D_SW4, D_SW5, D_SW6). , Two key switches (C_SW4, D_SW4) connected to the same key return input signal line (KR4) and another key return input signal line (KR2) not adjacent to the same key return input signal line (KR4) One of the key switches (A_SW2, B_SW2, C_SW2, D_SW2) connected to the key scan output signal line (scan line KS_C, scan line KS_D) to which the previous two key switches (C_SW4, D_SW4) are connected. And the other key switch (C_ One of the key switches (C_SW2) of W2 and D_SW2) and the normal route that passes only the other key switch (D_SW2), and one fourth signal control on the bypass route. Since the resistance (RD4) exists and only one fourth signal control resistance (RD2) exists in the normal route, the resistance of the entire sneak route and the resistance of the entire normal route have the same resistance value. Will result in undetectability.

  In this example, both the sneak route and the normal route have only one fourth signal control resistor. However, for example, when C_SW3, D_SW3, and D_SW5 are simultaneously pressed, the third key scan is performed. When the output signal line (scan line KS_C) is scanned, only one third signal control resistor is present in the sneak route (route through C_SW3 → D_SW3 → D_SW5) and the normal route (C_SW5), and detection is performed. It will cause the impossible.

  In such a peculiar place, the third signal control resistor and the third signal control resistor located on the sneak route and the normal route are set so that the resistance of the sneak route and the resistance value of the normal route are different from each other. The resistance value of the 4-signal control resistor may be selected.

As described above in detail, based on the embodiment, by arranging the external resistors (signal control resistors) as described above, it is possible to avoid detection failure when a plurality of key switches are simultaneously pressed. At the same time, it is possible to reduce the number of required signal control resistors to almost half the number of key switches.
Therefore, it is possible to significantly suppress an increase in mounting space, while having a configuration using an ordinary switch and an external resistor, which enables cost reduction.
In addition, since the number of types of signal control resistors (signal control resistors having different resistance values) necessary for avoiding undetectability can be significantly reduced, cost reduction can be facilitated also from this point.

The preferred embodiments of the present invention have been described above in detail, but it goes without saying that the technical scope of the present invention is not limited to the scope described in the above embodiments.
For example, in the mode shown in FIG. 50, a third signal control resistor (RC1, RC3, RC5) is provided at a key switch C_SW1, C_SW3, C_SW5 of the third key switch group, and a fourth key switch group is provided. Although the fourth signal control resistors (RD2, RD4, RD6) are provided at the key switches D_SW2, D_SW4, D_SW6 of the above, the relationship may be reversed.

  That is, the third signal control resistors (RC2, RC4, RC6) are provided at the key switches C_SW2, C_SW4, C_SW6 of the third key switch group, and the key switches D_SW1, D_SW3 of the fourth key switch group are provided. , D_SW5, the fourth signal control resistors (RD1, RD3, RD5) may be provided.

  Furthermore, in the second embodiment described above, the case where the number of key scan output signal lines is expanded to four has been described, but the fourth key scan output signal line (scan line KS_D) is omitted, and only three scan output signal lines are provided. It may be in the state of.

  As described above, the present invention is not limited to the above-described embodiment, and it is obvious to those skilled in the art that various modifications and improvements can be made, and such modifications and improvements are added. It is clear from the description of the claims that the forms can be included in the technical scope of the present invention.

  10 ... Key matrix circuit, 11 ... Key matrix section, 12 ... Control section, KS_A, KS_B, KS_C, KS_D ... Scan lines (first to fourth key scan output signal lines), KR1 to KR6 ... Return lines (key return input) Signal line), A_SW1, A_SW2, A_SW3, A_SW4, A_SW5, A_SW6 ... key switch (first key switch group), B_SW1, B_SW2, B_SW3, B_SW4, B_SW5, B_SW6 ... key switch (second key switch group), C_SW1, C_SW2, C_SW3, C_SW4, C_SW5, C_SW6 ... Key switch (third key switch group), D_SW1, D_SW2, D_SW3, D_SW4, D_SW5, D_SW6 ... Key switch (fourth key switch group), RA1, RA , RA3, RA4, RA5, RA6, RB2, RB3, RB4, RB5, RB6, RC1, RC3, RC5, RD2, RD4, RD5 ... Signal control resistors (first to fourth signal control resistors), P ... Connection point, L … Wiring (wiring that connects the key scan signal line or key return signal line to the switch)

Claims (4)

A key matrix circuit,
A first key scan output signal line,
A second key scan output signal line,
A plurality of key return input signal lines to which power supply voltage is applied via pull-up resistors,
A plurality of key switches, which is a first key switch group, electrically connecting the first key scan output signal line and each of the key return input signal lines;
A plurality of key switches which is a second key switch group for electrically connecting the second key scan output signal line and each of the key return input signal lines;
On the first key scan output signal line, a plurality of first connection points to which a plurality of key switches of a first key switch group are respectively connected to the first key scan output signal line;
The on the second key scan output signal lines and a plurality of second connection point in which a plurality of key switches are respectively connected a second key switch group on the second key scan output signal line,
When the position between the adjacent first connection points is a certain first position and the position between the adjacent second connection points is a second position, the same key return input signal line is connected via the key switch. A signal control resistor is provided at any one of the first position and the second position, and the resistance value of the first signal control resistors provided at the plurality of first positions and the plurality of second positions. A key matrix circuit, wherein a resistance value of a second signal control resistor provided at a position is different. Further, a third key scan output signal line is arranged in addition to the first key scan output signal line and the second key scan output signal line,
A plurality of key switches, which is a third key switch group, electrically connecting the third key scan output signal line and each of the key return input signal lines;
The on said third key scan output signal lines and a plurality of third connection point in which a plurality of key switches are respectively connected to a third key switch group on the third key scan output signal line,
When wiring from the previous SL third connection point and the third connection point is arranged through the third key switch has a third position the position between the points connecting with said key return input signal line , Every other third signal control resistor is provided at the third position, and the resistance value of the third signal control resistor is the resistance value of the first signal control resistor and the resistance value of the second signal control resistor. The key matrix circuit according to claim 1, wherein the key matrix circuit is different from any of the values. Further, a fourth key scan output signal line is arranged in addition to the first key scan output signal line, the second key scan output signal line, and the third key scan output signal line,
A plurality of key switches which is a fourth key switch group for electrically connecting the fourth key scan output signal line and each of the key return input signal lines;
The on said fourth key scan output signal lines and a plurality of fourth connection point in which a plurality of key switches are respectively connected to a fourth key switch group on the fourth key scan output signal line,
When wiring before Symbol the fourth connection point and the fourth connection point is disposed through the fourth key switch has a fourth position located between the points connecting with said key return input signal line A fourth signal control resistor is provided at the fourth position when the third signal control resistor is not provided at the third position connected to the same key return input signal line via the key switch, and The resistance value of the fourth signal control resistor is different from any of the resistance value of the first signal control resistor, the resistance value of the second signal control resistor, and the resistance value of the third resistor. 2. The key matrix circuit described in 2.   Of the third key switch group and the fourth key switch group, two key switches connected to the same key return input signal line and another key return input signal not adjacent to the same key return input signal line A key switch connected to a line, and a wrap-around route via one of the key switches connected to the key scan output signal line to which the two key switches are connected and one of the other key switches, And, in the normal route passing only through the other key switch, on the sneak route and the normal route such that the resistance value of the entire sneak route and the resistance value of the entire normal route have different resistance values. The resistance values of the third signal control resistor and the fourth signal control resistor located above are selected. Key matrix circuit according to.

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