JP2017058959A - Key matrix circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a matrix circuit with a configuration using cost-reducible ordinary switches and external resistors, while suppressing an increase in a mounting space, with which it is possible to detect an accurately depressed key even when three or more keys are depressed simultaneously.SOLUTION: The present invention comprises a first and a second output signal line, a plurality of input signal lines, a first key switch group connecting the first output signal line and each input signal line, and a second key switch group connecting the second output signal line and each input signal line. A first signal control resistor is provided at one or more first positions out of a plurality of first positions preceding a connection point P of a key switch of the first key switch group and the first output signal line, and a second signal control resistor different from the first signal control resistor is provided at a second position out of a plurality of second positions preceding the connection point P of a key switch of the second key switch group and the second output signal line where no first signal control resistor corresponding to the same input signal line is provided at the first position.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a key matrix circuit.

  A key matrix circuit is generally used for operation keys (for example, a numeric keypad) of electronic devices such as mobile phones and car navigations that have become widespread in recent years. Devices that use such a key matrix circuit have become more complicated to operate as their functions improve, and using only a conventional key alone has all of the functions of the devices. It has become difficult to respond.

  For this reason, it is hoped that key operations corresponding to more functions can be performed without increasing the number of keys by adding a method of pressing multiple keys at the same time as well as using the keys alone. It is rare. However, in the key matrix circuit, when three or more keys are simultaneously pressed, there is a case where it cannot be distinguished from the case where other keys that are not pressed are pressed, and there is a problem that accurate detection cannot be performed.

  In order to solve such a problem, for example, in Patent Document 1, for example, by using key switches with resistors for all the key switches, even if three or more keys are simultaneously pressed, it is accurate. A configuration capable of detecting a key pressed is described.

JP 2009-32203 A

  However, a key switch with a resistor is a special part and is expensive. When the configuration described in Patent Document 1 is adopted, there is a problem that it is difficult to keep the cost low. On the other hand, if an external resistor is added to a normal key switch to realize a function similar to that of a key switch with a resistor, it can be constructed at low cost. For this reason, if all the key switches with resistors described in Patent Document 1 are replaced with a configuration in which normal key switches and external resistors are combined, the cost can be kept low.

  However, operation keys that use a key matrix circuit are often not allowed to occupy a large mounting space. For this reason, if a configuration combining a normal key switch and an external resistor is used, it will be newly added. Problems arise in securing the required mounting space for external resistors.

  The present invention has been made in view of such circumstances, and a key matrix circuit capable of accurately detecting a key switch being pressed even when three or more key switches are simultaneously pressed, An object is to suppress an increase in mounting space while realizing a configuration using a normal key switch and an external resistor capable of reducing the cost.

In order to solve the above-described problems, the present invention is grasped by the following configuration.
(1) The key matrix circuit of the present invention is a key matrix circuit, and a power supply voltage is applied via a first key scan output signal line, a second key scan output signal line, and a pull-up resistor. A plurality of key return input signal lines; a plurality of key switches which are a first key switch group electrically connecting the first key scan signal line and each of the key return signal lines; A plurality of key switches which are a second key switch group electrically connecting between the two key scan signal lines and each of the key return signal lines, and the first key scan signal line has the first key switch on the first key scan signal line. A plurality of first connection points to which a plurality of key switches, which are a first key switch group, are respectively connected to the key scan signal line, and the second key scan signal line on the second key scan signal line. A plurality of second connection points to which a plurality of key switches that are a second key switch group are respectively connected to the line, and a position between the adjacent first connection points is a first position, and the adjacent When the position between the second connection points is the second position, the signal is controlled to one of the first position and the second position connected to the same key return input signal line via the key switch. A resistance is provided, and a resistance value of the first signal control resistor provided at the plurality of first positions is different from a resistance value of the second signal control resistor provided at the plurality of second positions.

  (2) In addition to the configuration of (1) above, a third key scan output signal line is arranged, and the third key scan signal line is electrically connected between each key return signal line. A plurality of key switches that are three key switch groups, and a plurality of key switches that are third key switch groups connected to the third key scan signal lines on the third key scan signal lines, respectively. A third signal control resistor is provided in every third position, and when the position between the adjacent third connection points is a third position, and The resistance value of the third signal control resistor is different from both the resistance value of the first signal control resistor and the resistance value of the second signal control resistor.

  (3) In addition to the configuration of (2) above, a fourth key scan output signal line is arranged, and the fourth key scan signal line is electrically connected between each of the key return signal lines. A plurality of key switches that are four key switch groups, and a plurality of key switches that are fourth key switch groups connected to the fourth key scan signal lines on the fourth key scan signal lines, respectively. The fourth connection point, and when the position between the adjacent fourth connection points is the fourth position, the third connection point connected to the same key return input signal line via the key switch When no signal control resistor is provided, a signal control resistor is provided at the fourth position, and the resistance value of the fourth signal control resistor is the resistance value of the first signal control resistor, the second signal control resistor Resistance value and the first Different than either of the resistance value of the resistor.

(4) In the configuration of (3) above, two key switches connected to the same key return input signal line in the third key switch group and the fourth key switch group, and the same key return input One of one key switch connected to another key return input signal line not adjacent to the signal line and connected to the key scan output signal line to which the two key switches are connected and the other key switch And the normal route via only the other key switch, the resistance value of the entire wraparound route is different from the resistance value of the entire normal route. The resistance values of the third signal control resistor and the fourth signal control resistor located on the wraparound route and the normal route are selected as follows. It has been.

  According to the present invention, even when three or more key switches are pressed at the same time, a key matrix circuit capable of accurately detecting the key switches that are pressed down is a normal key that can reduce the cost. It is possible to provide a key matrix circuit that realizes a configuration using a switch and an external resistor while suppressing an increase in mounting space.

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DETAILED DESCRIPTION OF THE INVENTION

  DESCRIPTION OF EMBODIMENTS Hereinafter, a mode for carrying out the present invention (hereinafter referred to as this embodiment) will be described in detail with reference to the accompanying drawings. Note that the same numbers are assigned to the same elements throughout the description of the present embodiment.

(Configuration of the first embodiment)
FIG. 1 shows the configuration of the key matrix circuit 10 of the present embodiment. As shown in FIG. 1, the key matrix circuit 10 of the present embodiment includes a key matrix unit 11 and a control unit 12.

The key matrix unit 11 has two key scan output signal lines (scan line KS_A, scan line KS_B).
Hereinafter, for simplification of description, unless otherwise specified, the scan line KS_A is referred to as a first key scan output signal line, and the scan line KS_B is referred to as a second key scan output signal line. However, when the scan line KS_B is the first key scan output signal line, the scan line KS_A is the second key scan output signal line.

  Further, hereinafter, the scan line KS_A and the scan line KS_B will be referred to as the first key scan output signal line and the second key scan output signal line, respectively. In this case, the scan line KS_B is replaced with the first key scan output signal line, and the scan line KS_A is replaced with the second key scan output signal line. The case should be construed so as to replace the expressions “first” and “second” given for the parts related to these.

  As shown in FIG. 1, in the key matrix unit 11, a first key scan output signal line (scan line KS_A) and a second key scan output signal line (scan line KS_B) are wired.

  The first key scan output signal line (scan line KS_A) and the second key scan output signal line (scan line KS_B) have a plurality of key return input signal lines (return lines KR1, KR2, KR3, KR4, KR5, KR6) are wired.

Further, the key matrix unit 11 is pressed to connect the first key scan output signal line (scan line KS_A) and each key return input signal line (return lines KR1, KR2, KR3, KR4, KR5, KR6). Key switches (A_SW 1, A_SW 2, A_SW 3, A_SW 4, A_SW 5, A_SW 6) that electrically connect them are provided.
Note that when these key switches that are electrically connected to the first key scan output signal line (scan line KS_A) are collectively referred to as a first key switch group. .

  Specifically, the key switches (A_SW1, A_SW2, A_SW3, A_SW4, A_SW5, A_SW6) of the first key switch group are respectively the key switches (A_SW1, A_SW2, A_SW3, A_SW4) of the first key switch group. , A_SW5, A_SW6) and the first key scan output signal line (scan line KS_A) and the key return input signal line (return lines KR1, KR2, KR3, KR4, KR5, KR6) electrically It is connected to the.

  Between the connection points P between the wiring L from the key switches (A_SW1, A_SW2, A_SW3, A_SW4, A_SW5, A_SW6) of the first key switch group and the first key scan output signal line (scan line KS_A). Signal control resistors (RA1, RA2, RA3, RA4, RA5, RA6) are provided at a plurality of first positions.

  The signal control resistors (RA1, RA2, RA3, RA4, RA5, RA6) provided at the first position on the first key scan output signal line (scan line KS_A) are referred to as first signal control resistors. Unless otherwise specified, the description will proceed assuming that all the first signal control resistors have the same resistance value.

  More specifically, the first signal control resistor (the first signal control resistor (A_SW2)) is connected to the connection point P between the wiring L from the key switch (A_SW2) and the first key scan output signal line (scan line KS_A). RA2) is provided, and a first signal is present at a first position between the connection points P of the wiring L from the key switch (A_SW3) and the first key scan output signal line (scan line KS_A). A control resistor (RA3) is provided, and for the key switches (A_SW4, A_SW5, A_SW6), the wiring L and the first key scan output signal line from the key switches (A_SW3, A_SW4, A_SW5, A_SW6), respectively, sequentially. First signal control resistors (RA4, RA5, RA6) are respectively provided at first positions between the connection points P with (scan line KS_A). It has been kicked. The first signal control resistor RA1 need not be disposed because a resistor is provided at the starting point of the normal output port KS_A.

Further, the key matrix unit 11 is pressed to connect the second key scan output signal line (scan line KS_B) and each key return input signal line (return lines KR1, KR2, KR3, KR4, KR5, KR6). Key switches (B_SW 1, B_SW 2, B_SW 3, B_SW 4, B_SW 5, B_SW 6) that electrically connect them are provided.
When these key switches that are electrically connected to the second key scan output signal line (scan line KS_B) are collectively referred to as a second key switch group. .

  Specifically, the key switches (B_SW1, B_SW2, B_SW3, B_SW4, B_SW5, B_SW6) of the second key switch group are the key switches (B_SW1, B_SW2, B_SW3, B_SW4) of the second key switch group. , B_SW5, B_SW6) are electrically connected to the second key scan output signal line (scan line KS_B) and the key return input signal line (return lines KR1, KR2, KR3, KR4, KR5, KR6). It is connected to the.

  On the other hand, in this example, the connection point between the wiring L from the key switch (B_SW1, B_SW2, B_SW3, B_SW4, B_SW5, B_SW6) of the second key switch group and the second key scan output signal line (scan line KS_B). No signal control resistor is provided at the second position between Ps.

  As shown in FIG. 1, each key return input signal line (return lines KR1, KR2, KR3, KR4, KR5, KR6) is respectively connected via a pull-up resistor (R1, R2, R3, R4, R5, R6). The power supply voltage VDD is applied.

(Basic operation of key matrix circuit)
In the following, the basic operation of how the key switch is pressed (the key switch is turned on) and the non-pressed state (the key switch is turned off) is detected simply in the above configuration. .

  First, each key return input signal line (return lines KR1, KR2, KR3, KR4, KR5, KR6) is supplied with a power supply voltage VDD via a pull-up resistor (R1, R2, R3, R4, R5, R6). Always applied.

The control unit 12 includes a microcomputer having six A / D (Analog / Digital) input ports (not shown), and each key return input signal line (return line KR1, KR2, KR3, KR4, KR5, KR6) are connected.
Therefore, when none of the key switches is turned off, that is, when not pressed, the voltage value (potential difference) corresponding to the applied power supply voltage VDD, that is, the voltage value is High at each input port. A state is detected.

  On the other hand, in the two key scan output signal lines (scan line KS_A, scan line KS_B), the voltage value of the key scan output signal line to be scanned is set to Low, and the voltage value of the other key scan output signal line is set to High. . This operation is switched at regular time intervals.

  That is, the voltage value of the first key scan output signal line (scan line KS_A) is low and the voltage value of the second key scan output signal line (scan line KS_B) is high for a certain time. The key scan output signal line being performed is the first key scan output signal line (scan line KS_A).

After a certain period of time, the voltage value of the first key scan output signal line (scan line KS_A) is set to High and the voltage value of the second key scan output signal line (scan line KS_B) is set to Low. At this time, the key scan output signal line that is scanning is the second key scan output signal line (scan line KS_B).
Thus, the scan of the key scan output signal line is repeated alternately at a certain time interval.

Here, the case where the key scan output signal line that performs scanning is the first key scan output signal line (scan line KS_A) will be described below.
In this case, when any of the key switches A_SW1, A_SW2, A_SW3, A_SW4, A_SW5, and A_SW6 is OFF, that is, when not pressed, the voltage value corresponding to the applied power supply voltage VDD is also applied to each input port. (Potential difference), that is, a state where the voltage value is high is detected.

On the other hand, for example, when the key switch A_SW2 is turned on, that is, pressed, the first key scan output signal line (scan line KS_A) and the key return input signal line of the return line KR2 are electrically connected via the key switch A_SW2. Will do.
Therefore, in response to the voltage value Low of the first key scan output signal line (scan line KS_A), the voltage value of the key return input signal line of the return line KR2 also becomes Low.

  A key switch of A_SW2 and B_SW2 is connected to the key return input signal line of the return line KR2, but the key scan output signal line during scanning is the first key scan output signal line (scan line KS_A). Therefore, the key switch corresponding to this is A_SW2.

Therefore, when the voltage value (potential difference) of the key return input signal line of the return line KR2 changes while scanning the first key scan output signal line (scan line KS_A), the key switch A_SW2 is turned on, that is, pressed. Is detected.
Similarly, even when only the key switch A_SW1 is ON, that is, when it is pressed, it is detected that the key switch A_SW1 is pressed basically by the same operation as the operation of the key switch A_SW2. .

  Even when other key switches are pressed, the basic operation, that is, the change in the voltage value (potential difference) of which key return input signal line is detected when which key scan output signal line is being scanned. It is determined which key switch is turned on, that is, pressed.

(Operation when multiple key switches are pressed simultaneously)
The basic operation of the present invention is as described above. Hereinafter, a case where a plurality of key switches are simultaneously turned on, that is, pressed will be described.

FIG. 2A shows a circuit diagram that is basically the same as FIG. 1, but in order to make the signal flow easier to see, key scan output signal lines (scan lines KS_A, KS_B) and key return input signal lines ( Only the portions of the return lines KR1, KR2, KR3, KR4, KR5, and KR6) are mainly shown, and the controller 12 and the pull-up resistors (R1, R2, R3, and R4) are omitted.
In the subsequent drawings, similarly to FIG. 2A, the controller 12 and the pull-up resistors (R1, R2, R3, R4) are omitted for illustration.

  First, the operation when a plurality of (three) key switches among the four adjacent key switches A_SW1, A_SW2, B_SW1, and B_SW2 are simultaneously pressed will be described.

First, the description will be made on the assumption that the key switches A_SW1, A_SW2, and B_SW1 that are diagonally hatched in FIG.
In the basic operation of the key matrix circuit described above, the voltage value has been described as changing. However, for the sake of simplification, the description will be given as the signal flow using the expression scan signal.
In the following drawings, it is assumed that the key switch that is pressed is provided with diagonal hatching, and the key switch that is not provided is not provided with hatching.

  Although not shown in FIG. 2, when the scan line KS_A is scanned, that is, when a scan signal is output to the scan line KS_A, the flow of the scan signal (voltage change flow) is a key switch. The signals are input to the key return input signal lines (return lines KR1 and KR2) via A_SW1 and key switch A_SW2, respectively.

  In this case, when scanning the scan line KS_A, the scan signal is input to the key return input signal lines (return lines KR1, KR2) corresponding to the pressed key switches A_SW1, A_SW2 (voltage value ( It is determined that the key switches A_SW1 and A_SW2 are pressed. Since this is a correct determination state, there is no problem.

  On the other hand, as shown in FIG. 2A, when a scan signal is output from the scan line KS_B (voltage value Low of the scan line KS_B) in order to scan the scan line KS_B, the return line KR2 of the key return input signal line. There are two possible paths for the scan signal to be input when one B_SW2 is pressed and when three A_SW1, A_SW2, and B_SW1 are pressed simultaneously. Each case will be described in detail below.

First, when one normal key switch is pressed, the scan signal is input to the return line KR2 when the route passes through the solid line shown in FIG. 2A, that is, the key switch B_SW2 is pressed. It is the case.
Since it is more common to press one key switch, hereinafter, the path of the scan signal in this case is referred to as a normal route.

On the other hand, as can be seen from FIG. 2A, when the three key switches (A_SW1, A_SW2, B_SW1) are simultaneously pressed, the scan signal is input to the return line KR2 via the path indicated by the dotted line. Is done.
Hereinafter, such a path of the scan signal passing through the plurality of key switches is referred to as a wraparound route.

  Currently, the key switches (A_SW1, A_SW2, B_SW1) are actually pressed, but the key switch B_SW2 is the same circuit as that being pressed, and the key switches A_SW1, A_SW2, B_SW1 are simultaneously pressed. Therefore, it cannot be determined whether only one pressing of B_SW2 is performed (detection is impossible).

In the following, the operation of this configuration when there are two routes that may be undetectable as described above will be further described.
FIG. 2B shows an equivalent circuit in which the path of the scan signal is shown linearly, and FIG. 2B also shows the pull-up resistor R1, the control unit 12 and the like omitted.
In the following drawings, a diagram shown as (b) is a diagram showing an equivalent circuit of FIG.

The left side of FIG. 2B shows an equivalent circuit in the case of a normal route, while the right side of FIG. 2B shows an equivalent circuit of a wraparound route.
As shown in FIG. 2B, in the configuration of the present invention, there is no signal control resistor in the normal route, while there is a first signal control resistor RA2 in the wraparound route.
Therefore, the scan signal input to the return line KR2 is detected as a different voltage value (potential difference) in the normal route and the sneak route because it is affected by the presence or absence of the signal control resistor.

  In the key switches A_SW1, A_SW2, B_SW1, and B_SW2, the key switches that may be pressed when scanning the scan line KS_B are B_SW1 and B_SW2, and therefore, due to the difference in voltage value (potential difference), Since it is possible to determine which key switch is pressed, it is possible to avoid detection failure.

  Here, the principle that the simultaneous pressing of the key switches A_SW1, A_SW2, and B_SW1 can be detected will be described with reference to FIG. First, when the key switch A_SW1 is pressed, the Low signal output from the KS_A line is input to the KR_1 via the resistor RA1 and the key switch A_SW1, and KR_1 is divided by the pull-up resistor and the resistor RA1 that are pulled up by the power supply voltage VDD (not shown). It is detected by becoming a pressed potential. When the key switch A_SW2 is pressed, the Low signal output from the KS_A line is input to the KR_2 via the resistor RA2 and the key switch A_SW2, and the KR_2 is divided by the pull-up resistor and the resistor RA2 that are pulled up by the power supply voltage VDD (not shown). It is detected by becoming a pressed potential. Further, pressing of the key switch B_SW1 is detected when the Low signal output from the KS_B line is input to the KR_2 via the key switch B_SW1, and the KR_1 becomes the Low level. The Low signal output from the KS_A line and the KS_B line has different output timings.

Next, let us consider a case where it is assumed that the key switches A_SW1, A_SW2, and B_SW2 that are obliquely hatched in FIG.
Although not shown here, when the scan line KS_A is scanned, the same result as described above is obtained, so that the determination state is correct and there is no problem.
On the other hand, in the case of scanning the scan line KS_B, as shown in FIG. 3A, the two routes that are input to the key return input signal line (return line KR1), that is, the normal line indicated by a solid line are also used. There are a route and a wraparound route indicated by a dotted line.

However, in the configuration of the present invention, as shown in FIG. 3B, there is no signal control resistance in the case of the normal route (the left side in the drawing), while in the case of the wraparound route (the right side in the drawing) There is a one-signal control resistor RA2.
Accordingly, the scan signal input to the key return input signal line (return line KR1) detects different voltage values (potential differences) between the normal route and the wraparound route. Therefore, it is possible to determine which key switch is pressed, and to avoid detection failure.

Next, in the same manner as described above, in the four adjacent key switches A_SW1, A_SW2, B_SW1, and B_SW2, the key switches B_SW1 and B_SW2 are pressed, and any one of the key switches A_SW1 or A_SW2 is pressed (3 The operation when the two key switches are simultaneously pressed will be described.
In this case, contrary to the previous case, when the scan line KS_B is scanned, there is no wraparound route that causes detection failure, so the problem is on the scan line KS_A side.

FIG. 4 shows a case where the key switches A_SW2, B_SW1, and B_SW2 are simultaneously pressed. As in the previous case, FIG. 4A shows the normal route and the wraparound route, and FIG. 4B shows the normal route and the wraparound route. The equivalent circuit is shown.
In this case, as can be seen from FIG. 4B, only the first signal control resistor RA1 exists in the normal route, whereas the first signal control resistors RA1 and RA2 exist in the sneak route. It is possible to avoid detection failure.

  Similarly, FIG. 5 shows a case in which the key switches A_SW1, B_SW1, and B_SW2 are simultaneously pressed. Even in this case, the first signal control resistors RA1 and RA2 exist in the normal route, but in the sneak route. Since only the first signal control resistor RA1 is provided, it is possible to avoid detection failure.

In the above, the case where three key switches among the key switches A_SW1, A_SW2, B_SW1, and B_SW2 are simultaneously pressed has been described. However, the same applies to the case of the key switches A_SW2, A_SW3, B_SW2, and B_SW3. Since the resistance state differs between the normal route and the sneak route, it is possible to avoid detection failure.

  In other words, when the key switches A_SW2, A_SW3, B_SW2, and B_SW3 are pressed down and any one of the key switches B_SW2 and B_SW3 is pressed down, the scan line KS_B is sneak in. When a route is generated but the key switch B_SW2 is pressed, the normal route (route passing only through the key switch B_SW3) does not have a signal control resistor, but the sneak route has a first signal control resistor RA3. Will do.

  On the other hand, when the key switch B_SW3 is pressed and the key switch B_SW2 is not pressed, there is no signal control resistance in the normal route (route passing only through the key switch B_SW2), whereas the first signal in the sneak route There will be a control resistor RA3.

  Similarly, in the case where the key switch A_SW2, A_SW3, B_SW2, B_SW3 is pressed, and when one of the key switches A_SW2 and A_SW3 is pressed, the scan line KS_A is scanned. Although a sneak route is generated, in this case as well, the normal route and the sneak route differ in the number of intervening first signal control resistors, so that the detection failure can be avoided.

  Specifically, when the key switches B_SW2 and B_SW3 are pressed and the key switch B_SW2 is pressed, the first signal control resistors RA1, RA2, and RA3 in the normal route (route that passes only through the key switch A_SW3). On the other hand, only the first signal control resistors RA1 and RA2 exist in the sneak route.

  When the key switches B_SW2 and B_SW3 are pressed and the key switch B_SW3 is pressed, only the first signal control resistors RA1 and RA2 exist in the normal route (route passing only through the key switch A_SW2). In the wraparound route, the first signal control resistors RA1, RA2, and RA3 exist.

  Furthermore, the same thing happens between two adjacent upper and lower four key switches (for example, between key switches A_SW3, A_SW4, B_SW3, B_SW4, and between key switches A_SW4, A_SW5, B_SW4, B_SW5, etc.). It is possible to avoid the impossibility.

Next, let us look at the simultaneous pressing of the three key switches at different positions.
6 and 7 show that when the key switches A_SW1, A_SW3, B_SW1, and B_SW3 are pressed, the wraparound occurs when the scan line KS_B that presses the key switches A_SW1 and A_SW3 and presses either the key switch B_SW1 or B_SW3 is scanned. However, even in this case, there is no signal control resistor in the normal route, while the first signal control resistors RA2 and RA3 are present in the sneak route, and it is possible to avoid the detection failure. It is.

  Even when the key switches A_SW1, A_SW4, B_SW1, and B_SW4 are pressed further apart, for example, the key switches A_SW1 and A_SW4 are pressed and one of the key switches B_SW1 and B_SW4 is pressed. In the same manner as described above, there is no signal control resistor in the normal route when scanning the scan line KS_B in which the wraparound occurs, and the first signal control resistor exists in the wraparound route. This state can be avoided, and this state is also similar between remote key switches (for example, between key switches A_SW1, A_SW5, B_SW1, B_SW5, and between key switches A_SW1, A_SW6, B_SW1, B_SW6). Yes, it is possible to avoid undetectable It has become.

  On the other hand, FIG. 8 and FIG. 9 wrap around when scanning the scan line KS_A for pressing the key switches B_SW1 and B_SW3 and pressing one of the key switches A_SW1 and A_SW3 in the key switches A_SW1, A_SW3, B_SW1, and B_SW3. However, even in this case, since the number of first signal control resistors that are present differs between the normal route and the sneak route, it is possible to avoid detection failure.

  Note that even when the key switches are more distant, for example, between the key switches A_SW1, A_SW4, B_SW1, and B_SW4, the key switches B_SW1 and B_SW4 are pressed and one of the key switches A_SW1 and A_SW4 is pressed As described above, since the number of first signal control resistors existing in the normal route and the wraparound route when scanning the scan line KS_A in which the wraparound occurs is different, it is possible to avoid undetectableness. Is possible.

  With reference to FIGS. 2 to 9, the wiring L from the key switches (A_SW1, A_SW2, A_SW3, A_SW4, A_SW5, A_SW6) of the first key switch group and the first key scan output signal line (scan line KS_A) Signal control resistors (RA1, RA2, RA3, RA4, RA5, RA6) at a plurality of first positions on the first key scan output signal line (scan line KS_A) before the connection point P to (output port side) I have seen about the case of providing.

  However, when the key scan output signal lines of the first embodiment are two key scan output signal lines (scan line KS_A, scan line KS_B), the arrangement of the signal control resistors is the first key scan output signal line. It is not limited to the first position on (scan line KS_A).

  Any one of the first signal control resistors (RA1, RA2, RA3, RA4, RA5, RA6) is omitted (for example, RA4, RA5, RA6) and, instead, as shown in FIG. Before the connection point P (on the output port side) of the wiring L from the key switch (B_SW1, B_SW2, B_SW3, B_SW4, B_SW5, B_SW6) of the key switch group and the second key scan output signal line (scan line KS_B). A first signal control resistor is provided at a plurality of second positions on the second key scan output signal line (scan line KS_B) corresponding to the same key return input signal line (KR4, KR5, KR6). The first position is the second position that is not provided, that is, the second position corresponding to the first signal control resistor (RA4, RA5, RA6) that is omitted and no longer exists. No. control resistor (RA1, RA2, RA3) and a second signal control resistor of different resistance value (RB4, RB5, RB6) it is sufficient so provided.

Hereinafter, specifically, it will be seen that the detection failure can be avoided in the first modified example in which the arrangement of the signal control resistors shown in FIG. 10 is changed.
First, as shown in FIG. 10, the first signal control resistors RA4, RA5, RA6 are omitted, and the same key corresponding to the first position where the first signal control resistors RA4, RA5, RA6 were provided. The wiring L and the second key scan output signal line (scan line) from the second position (key switch (B_SW4, B_SW5, B_SW6) of the second key switch group) corresponding to the return input signal line (KR4, KR5, KR6) The case where the signal control resistors RB4, RB5, and RB6 are provided in front of the connection point P to (KS_B) (position on the output port side) will be described.
The signal control resistor provided on the second key scan output signal line is referred to as a second signal control resistor.

  FIGS. 10 to 13 show a case where three key switches among the four adjacent upper and lower key switches are simultaneously pressed, and a case where a wraparound route occurs when scanning the scan line KS_B. Show.

  Since there is no change in the parts of the key switches A_SW1, A_SW2, A_SW3, B_SW1, B_SW2, and B_SW3, the groups of four adjacent upper and lower key switches that are sequentially pressed are shifted from there. Shows the case.

As shown in FIGS. 10 to 13, it can be understood that in any case, the resistance state is different between the normal route and the sneak route, and the detection failure can be avoided.
Further, even when the group of four adjacent upper and lower key switches is shifted to the right side, the resistance state continues to be different between the normal route and the sneak route.

Next, in the same signal control resistor arrangement as in FIGS. 10 to 13, when the scan line KS_A is scanned when three key switches among the upper and lower two adjacent key switches are simultaneously pressed, As shown in FIGS. 10 to 13, the case where the two adjacent upper and lower key switch groups are shifted is shown in FIGS. 14 to 17. It can be seen that the state of resistance is different between the sneak path and the wraparound route, so that the detection failure can be avoided.
Further, even when the group of four adjacent upper and lower key switches is shifted to the right side, the resistance state continues to be different between the normal route and the sneak route.

Although illustration is omitted, it is confirmed that the resistance state is different between the normal route and the sneak route even when the three key switches are simultaneously pressed at the distant positions described with reference to FIGS. Therefore, it is possible to avoid detection failure.
Further, in the arrangement of the signal control resistors (first signal control resistor and second signal control resistor) shown in FIG. 18 (second modification), FIG. 19 (third modification), and FIG. 20 (fourth modification). Similarly, in both the upper and lower groups of four adjacent key switches, and in the case of simultaneous pressing of three key switches at remote positions, the resistance state differs between the normal route and the sneak route. It has been confirmed that it is possible to avoid detection failure.

For example, in the case of the arrangement of the signal control resistors in FIG. 19 (third modified example), it will be shown just in case that it is possible to avoid undetectability.
The arrangement of the signal control resistors of the third modified example shown in FIG. 19 is the wiring L and the first key scan output from the key switches (A_SW1, A_SW2, A_SW3, A_SW4, A_SW5, A_SW6) of the first key switch group. A plurality of first positions on the first key scan output signal line (scan line KS_A) before the connection point P to the signal line (scan line KS_A) (on the output port side) are the first signal control resistors (RA1,. The first position having RA3, RA5) and the first position not having the first signal control resistor appear alternately.

  Then, before the connection point P between the wiring L from the key switch (B_SW1, B_SW2, B_SW3, B_SW4, B_SW5, B_SW6) of the second key switch group and the second key scan output signal line (scan line KS_B) ( Corresponding to the same key return input signal line (KR1, KR2, KR3, KR4, KR5, KR6) at a plurality of second positions on the second key scan output signal line (scan line KS_B) on the output port side) The second position where the first signal control resistor is not provided at the first position, that is, the second position corresponding to the key return input signal line (KR2, KR4, KR6) has a resistance value different from that of the first signal control resistor. Second signal control resistors (RB2, RB4, RB6) are provided.

  In the case of such an arrangement of signal control resistors, there is basically a possibility of simultaneous pressing of three key switches in a group of two adjacent upper and lower key switches and simultaneous pressing of three separated key switches. For all of these patterns, a diagram showing a signal path and an equivalent circuit diagram are shown, and it will be shown below that the detection failure can be avoided.

  FIG. 21 to FIG. 26 show a case where a sneak route occurs when scanning the scan line KS_B in the case of two adjacent upper and lower key switch groups, and the left key switches (A_SW1, B_SW1). Even if a group of four more key switches from the side is shifted to the right side, a series of patterns up to a state where the same state as described above is repeated is shown.

  Similarly, FIGS. 27 to 32 show that when a sneak route occurs when scanning the scan line KS_A, even if a group of four more key switches is shifted to the right side, the same state as shown so far is obtained. It shows a series of patterns up to the repeated state.

  Further, FIG. 33 to FIG. 40 show a case where three key switches are simultaneously pressed at separate positions, and show a series of key switch patterns in which a sneak route is generated when scanning the scan line KS_B. FIG. 41 to FIG. 48 show a series of key switch patterns in which a wraparound route is generated when the scan line KS_A is similarly scanned.

  As can be seen from FIGS. 21 to 48, the first signal control resistors (RA1, RA3, RA5) and the second signal control resistors (RB2, RB4, RB6) have different resistance values. The resistance value (synthetic resistance) is different between the normal route and the wraparound route, and it is possible to avoid detection failure.

  Since the case shown in FIG. 37 is rare, the second signal control resistors (RB2, RB4, RB6) are 1/2 based on the resistance value BR of the first signal control resistors (RA1, RA3, RA5). It is desirable that the resistance value is different from the first signal control resistance except for the double and double resistance values ((1/2) × BR, 2 × BR).

(Second Embodiment)
In the first embodiment, the case of two key scan output signal lines (scan line KS_A, scan line KS_B) has been described. However, in the second embodiment, the case of four key scan output signal lines (scan line KS_A, A method of extending to the scan line KS_B, the scan line KS_C, and the scan line KS_D) will be described.

  For example, the number of scan lines KS_A and scan line KS_B in the case of FIG. 19 shown in detail is increased by another set, and as shown in FIG. 49, four key scan output signal lines (scan line KS_A, scan line KS_B, scan line) In the case of KS_C and scan line KS_D), as shown in FIG. 49, the normal route and the sneak route may have the same resistance value, so that detection becomes impossible.

  Therefore, as shown in FIG. 50, in the two added key scan output signal lines (scan line KS_C, scan line KS_D), the signal control resistance is not on the key scan output signal line but on the key switch and the key scan output signal line. A signal control resistor is inserted in a wiring connecting (scan line KS_C, scan line KS_D) and key return input signal lines (KR1, KR2, KR3, KR4, KR5, KR6).

  When the key switch is used as a reference, the wiring connecting the key switch to the key scan output signal lines (scan line KS_C, scan line KS_D) and key return input signal lines (KR1, KR2, KR3, KR4, KR5, KR6) , A wiring L going from the key switch to the key scan output signal line (scan line KS_C, scan line KS_D) and a wiring L going from the key switch to the key return input signal line (KR1, KR2, KR3, KR4, KR5, KR6). However, the signal control resistor to be inserted may be provided on either side of the wiring.

Specifically, in FIG. 50, the third key scan output signal line (scan line KS_C) is provided so as to be arranged next to the second key scan output signal line (scan line KS_B), and pressed. The key switches (C_SW1, C_SW2, C_SW3) electrically connecting the third key scan output signal line (scan line KS_C) and the key return input signal lines (KR1, KR2, KR3, KR4, KR5, KR6) C_SW4, C_SW5, C_SW6) are provided.
When these key switches that are electrically connected to the third key scan output signal line (scan line KS_C) are collectively referred to, they are referred to as a third key switch group.

  However, in FIG. 50, the third key scan output signal line (scan line KS_C) is provided so as to be arranged next to the second key scan output signal line (scan line KS_B). A third key scan output signal line (scan line KS_C) may be provided so as to be arranged next to the scan output signal line (scan line KS_A).

Also, a fourth key scan output signal line (scan line KS_D) is provided so as to be arranged next to the third key scan output signal line (scan line KS_C), and the fourth key scan output is output by being pressed. Key switches (D_SW1, D_SW2, D_SW3, D_SW4, D_SW5, D_SW6) for electrically connecting the signal line (scan line KS_D) and each key return input signal line (KR1, KR2, KR3, KR4, KR5, KR6) I am trying to provide it.
When these key switches electrically connected to the fourth key scan output signal line (scan line KS_D) are collectively called, they are called a fourth key switch group.

  Then, the key switches (C_SW1, C_SW2, C_SW3, C_SW4, C_SW5, C_SW6) of the third key switch group, the third key scan output signal line (scan line KS_C), and the key return input signal line (KR1, KR2) , KR3, KR4, KR5, KR6), the wiring in which the third signal control resistors (RC1, RC3, RC5) are inserted and the wiring in which the third signal control resistors are not inserted are alternately arranged. Has been provided.

Further, the key switches (C_SW1, C_SW2, C_SW3, C_SW4, C_SW5, C_SW6) of the third key switch group, the third key scan output signal line (scan line KS_C), and the key return input signal lines (KR1, KR2, KR3) , KR4, KR5, KR6), the key return input in which the key switch (C_SW2, C_SW4, C_SW6) of the third key switch group is connected to the wiring L connecting the wiring L to the third signal control resistor The key switch (D_SW2, D_SW4, D_SW6) of the fourth key switch group corresponding to the signal line (KR2, KR4, KR6), the fourth key scan output signal line (scan line KS_D), and the key return input signal line (KR2) , KR4, KR6) to the wiring L connecting the fourth signal control. Resistance (RD2, RD4, RD6) is inserted wiring is so provided.
By doing so, as shown in FIG. 50, it becomes possible to avoid the detection failure shown in FIG.

  By the way, in the case of the arrangement of the signal control resistors shown in FIG. 50, when the three key switches as shown in FIG. 51 are simultaneously pressed, the normal route has the third signal control resistor (RC1), and the wraparound route. However, when these signal control resistors have the same resistance value, detection failure occurs.

In order to avoid such a case, the third signal control resistors (RC1, RC3, RC5) are connected to the first signal control resistors (RA1, RA3, RA5) and the second signal control resistors (RB2, RB4). , RB6) and a different resistance value.
Similarly, for the fourth signal control resistors (RD2, RD4, RD5), the first signal control resistors (RA1, RA3, RA5), the second signal control resistors (RB2, RB4, RB6) and the third signal control resistors ( RC1, RC3, RC5) and different resistance values.

  As shown in FIG. 52, among the third key switch group (C_SW1, C_SW2, C_SW3, C_SW4, C_SW5, C_SW6) and the fourth key switch group (D_SW1, D_SW2, D_SW3, D_SW4, D_SW5, D_SW6) Two key switches (C_SW4, D_SW4) connected to the same key return input signal line (KR4) and another key return input signal line (KR2) not adjacent to the same key return input signal line (KR4) One key switch (A_SW2, B_SW2, C_SW2, D_SW2) connected to a key scan output signal line (scan line KS_C, scan line KS_D) to which the two previous key switches (C_SW4, D_SW4) are connected And the other key switch (C_ One of the key switches (C_SW2) of W2 and D_SW2) and a normal route that passes only through the other key switch (D_SW2) have one fourth signal control on the wraparound route. Since there is a resistor (RD4) and only one fourth signal control resistor (RD2) is present in the normal route, the resistance of the entire wraparound route and the resistance of the normal route are the same. As a result, detection becomes impossible.

  In this example, there is only one fourth signal control resistor for both the sneak route and the normal route. For example, when C_SW3, D_SW3, and D_SW5 are simultaneously pressed, the third key scan is performed. Only one third signal control resistor exists in each of the sneak route (route via C_SW3 → D_SW3 → D_SW5) and the normal route (C_SW5) when scanning the output signal line (scan line KS_C). It will cause disability.

  In such a unique part, the third signal control resistor and the second signal control resistor located on the wraparound route and the normal route so that the resistance value of the entire wraparound route and the resistance value of the entire normal route are different from each other. The resistance value of the 4-signal control resistor may be selected.

As described above, as described in detail based on the embodiment, by arranging the external resistors (signal control resistors) as described above, it is possible to avoid detection failure when a plurality of key switches are simultaneously pressed. At the same time, the number of signal control resistors required can be reduced to almost half the number of key switches.
Therefore, an increase in mounting space can be significantly suppressed while using a normal switch and an external resistor that can be reduced in cost.
Further, since the number of types of signal control resistors (signal control resistors having different resistance values) necessary for avoiding the undetectability may be significantly reduced, it is easy to reduce the cost from this point.

As mentioned above, although preferred embodiment of this invention was explained in full detail, it cannot be overemphasized that the technical scope of this invention is not limited to the range as described in the said embodiment.
For example, in the mode shown in FIG. 50, a third signal control resistor (RC1, RC3, RC5) is provided at the key switches C_SW1, C_SW3, C_SW5 of the third key switch group, and the fourth key switch group. Of these, the fourth signal control resistors (RD2, RD4, RD6) are provided at the key switches D_SW2, D_SW4, D_SW6, but this relationship may be reversed.

  That is, the third signal control resistors (RC2, RC4, RC6) are provided at the key switches C_SW2, C_SW4, C_SW6 of the third key switch group, and the key switches D_SW1, D_SW3 of the fourth key switch group are provided. , D_SW5 may be provided with fourth signal control resistors (RD1, RD3, RD5).

  Further, in the second embodiment, the case where the number of key scan output signal lines is expanded to four has been described. However, the fourth key scan output signal line (scan line KS_D) is omitted, and only three scan output signal lines are provided. It is good also as the state of.

  As described above, it is obvious to those skilled in the art that the present invention is not limited to the above-described embodiment, and various changes or improvements can be made. It is apparent from the scope of the claims that the embodiments can be included in the technical scope of the present invention.

  DESCRIPTION OF SYMBOLS 10 ... Key matrix circuit, 11 ... Key matrix part, 12 ... Control part, KS_A, KS_B, KS_C, KS_D ... Scan line (1st-4th key scan output signal line), KR1-KR6 ... Return line (key return input) Signal line), A_SW1, A_SW2, A_SW3, A_SW4, A_SW5, A_SW6 ... key switches (first key switch group), B_SW1, B_SW2, B_SW3, B_SW4, B_SW5, B_SW6 ... key switches (second key switch group), C_SW1, C_SW2, C_SW3, C_SW4, C_SW5, C_SW6 ... key switches (third key switch group), D_SW1, D_SW2, D_SW3, D_SW4, D_SW5, D_SW6 ... key switches (fourth key switch group), RA1, RA , RA3, RA4, RA5, RA6, RB2, RB3, RB4, RB5, RB6, RC1, RC3, RC5, RD2, RD4, RD5... Signal control resistor (first to fourth signal control resistors), P. ... Wiring (wiring that connects the key scan signal line or key return signal line to the switch)

Claims (4)

A key matrix circuit,
A first key scan output signal line;
A second key scan output signal line;
A plurality of key return input signal lines to which a power supply voltage is applied via a pull-up resistor;
A plurality of key switches which are a first key switch group for electrically connecting the first key scan signal line and each of the key return signal lines;
A plurality of key switches which are a second key switch group for electrically connecting the second key scan signal line and each of the key return signal lines;
On the first key scan signal line, a plurality of first connection points respectively connected to the first key scan signal line and a plurality of key switches as a first key switch group;
On the second key scan signal line, a plurality of second connection points respectively connected to the second key scan signal line and a plurality of key switches that are a second key switch group,
When the position between the adjacent first connection points is a first position and the position between the adjacent second connection points is a second position, the same key return input signal line is connected via the key switch. A signal control resistor is provided at one of the first position and the second position, and the resistance value of the first signal control resistor provided at the plurality of first positions and the plurality of second positions are provided. A key matrix circuit characterized in that a resistance value of a second signal control resistor provided at a position is different. Furthermore, a third key scan output signal line is arranged in addition to the first key scan output signal line and the second key scan output signal line,
A plurality of key switches which are a third key switch group for electrically connecting the third key scan signal line and each of the key return signal lines;
A plurality of third connection points on the third key scan signal line, to which a plurality of key switches that are a third key switch group are respectively connected to the third key scan signal line;
When the position between the adjacent third connection points is the third position, every third signal control resistor is provided in the third position, and the resistance value of the third signal control resistor is: The key matrix circuit according to claim 1, wherein a resistance value of the first signal control resistor is different from a resistance value of the second signal control resistor. In addition to the first key scan output signal line, the second key scan output signal line, and the third key scan output signal line, a fourth key scan output signal line is disposed,
A plurality of key switches which are a fourth key switch group for electrically connecting the fourth key scan signal line and each of the key return signal lines;
A plurality of fourth connection points on the fourth key scan signal line, to which a plurality of key switches that are a fourth key switch group are respectively connected to the fourth key scan signal line;
When no signal control resistor is provided at the third position connected to the same key return input signal line via the key switch when the position between the adjacent fourth connection points is the fourth position. A signal control resistor is provided at the fourth position, and a resistance value of the fourth signal control resistor is a resistance value of the first signal control resistor, a resistance value of the second signal control resistor, and a resistance of the third resistor. 3. The key matrix circuit according to claim 2, wherein the key matrix circuit is different from any of the values. Of the third key switch group and the fourth key switch group, two key switches connected to the same key return input signal line and another key return input signal not adjacent to the same key return input signal line A sneak route via one of the key switches connected to the line and one of the other key switches connected to the key scan output signal line to which the two key switches are connected, And, in the normal route that passes only through the other key switch, the resistance value on the wraparound route and the normal route are such that the resistance value of the entire wraparound route is different from the resistance value of the entire normal route. The resistance values of the third signal control resistor and the fourth signal control resistor located above are selected. Key matrix circuit according to.

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